ams AS3953A-BWLM 14443 high speed passive tag interface Datasheet

A S3 9 5 3
1 44 4 3 H i g h S p e e d P a s s i v e Ta g I n te r fa c e
1 General Description
The AS3953 supports ISO 14443A up to Level-4, meaning a
contactless smart card or an NFC forum compatible tag (Tag Type 4)
can be built. Having a NFC Forum compatible tag interface allows
the AS3953 to be used in an application where a standard NFC
enabled phone is used as a PCD.
The AS3953 NFC interface IC (NFiC) delivers low cost, ultra low
power NFC forum functionality to multiple different applications. The
AS3953 is a analog front-end with integrated 14443A data framing
and SPI interface. It is designed to create a fast data link between an
ISO 14443A reader device (PCD) and a microcontroller. The AS3953
is Passively powered meaning that it can be supplied from the PCD
magnetic field, eliminating the need of a continual external supply.
This makes the AS3953 perfect for wireless communication to a lowpower battery powered device.
2 Key Features
ISO 14443A compliant to
NFCIP-1
Level-4
target at 106 kb/s
1k bit EEPROM (928 bits of user memory)
The AS3953 is used with an appropriate antenna coil connected to
the terminals LC1 and LC2, and behaves as a normal passive ISO
144443A tag (PICC). After the anti-collision protocol is passed, the
PCD sends a Wake-up command, which wakes up the
microcontroller by sending an interrupt. From this point onwards, the
AS3953 serves as a data link between the microcontroller and the
PCD. AS3953 can also operate as NFCIP-1 target at 106 kb/s.
Configurable wake-up interrupt (after
tag is selected or using
proprietary command)
Powered from external magnetic field
with the possibility to
draw up to 5mA
7 byte UID
User configurable regulated voltage extracted from external
The AS3953 includes an onboard EEPROM that can be accessed
either from the PCD or from the microcontroller via the SPI interface.
This built-in flexibility makes it ideal for two types of applications:
magnetic field
Bit rates from 106 Kbps till 848 Kbps
Integrated resonant capacitor
Where personalization data is programmed by the PCD (even in
case the SPI side is not powered) and it is later read by
microcontroller through SPI interface.
Integrated buffer capacitor
4-wire Serial Peripheral Interface (SPI)
Where log data is stored periodically by the microcontroller
and
can then be read by the PCD even when the microcontroller is
not powered.
A regulated power supply voltage extracted from the PCD field is
also available on a pin and can be used as power supply for external
circuitry. For example, an external microcontroller and a sensor
could be powered from the PCD field combined with pass through
data rates up to 848Kbps, which means the AS3953 is ideal for
contactless passive programming of MCU systems. The AS3953 can
also operate as a stand-alone ISO 14443A tag.
with 32 byte FIFO
Wide
SPI power supply range (1.65V to 3.6V)
Wide
temperature range: -40ºC to 85ºC
Available as WLCSP 10-bumps (Future delivery options: 10-pin
MLPD (3x3mm) and Gold bumped dies)
3 Applications
The device is ideal for applications like Passive wake-up,
Multipurpose HF interface to a controller, Low power or passive
programming, Ultra Low Power Data Logger, RFID Programmable
configuration EEPROM, ISO 14443A smart card, NFC Forum Tag
Type 4, and Bluetooth and Wi-Fi pairing.
Figure 1. AS3953 Block Diagram
VP_REG
VP_INT
AS3953
Power
Manager
VP_SPI
VDD
LC1
IRQ
AFE
LC2
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Logic
POR
EEPROM
Level
Shifters
SPI
VSS
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AS3953
Datasheet - C o n t e n t s
Contents
1 General Description ..................................................................................................................................................................
1
2 Key Features.............................................................................................................................................................................
1
3 Applications...............................................................................................................................................................................
1
4 Pin Assignments .......................................................................................................................................................................
4
4.1 Pin Descriptions....................................................................................................................................................................................
5
5 Absolute Maximum Ratings ......................................................................................................................................................
6
6 Electrical Characteristics...........................................................................................................................................................
7
6.1 Operating Conditions............................................................................................................................................................................
7
6.2 DC/AC Characteristics for Digital Inputs and Outputs..........................................................................................................................
7
6.3 Electrical Specification..........................................................................................................................................................................
8
7 Detailed Description..................................................................................................................................................................
9
7.1 Circuit ...................................................................................................................................................................................................
9
7.2 PICC AFE.............................................................................................................................................................................................
9
7.3 Power Manager ..................................................................................................................................................................................
11
7.4 ISO 14443A Framing Mode................................................................................................................................................................
11
7.5 ISO 14443A Level-4 Protocol Mode...................................................................................................................................................
12
7.5.1 Coding of UID ............................................................................................................................................................................ 12
7.5.2 Coding of ATQA, SAK and ATS ................................................................................................................................................ 13
7.6 Proprietary Commands.......................................................................................................................................................................
15
7.6.1 Passing of Block Data to Controller ........................................................................................................................................... 17
7.6.2 Use of CID ................................................................................................................................................................................. 17
7.7 ISO 14443A Level-3 Protocol Mode...................................................................................................................................................
17
7.8 Transparent Mode ..............................................................................................................................................................................
18
7.9 EEPROM............................................................................................................................................................................................
18
7.9.1
7.9.2
7.9.3
7.9.4
7.9.5
7.9.6
UID Word ...................................................................................................................................................................................
Fabrication Data Word...............................................................................................................................................................
Configuration Word....................................................................................................................................................................
OTP Words ...............................................................................................................................................................................
Write Lock Word ........................................................................................................................................................................
Read Lock Word ........................................................................................................................................................................
8 Application Information ...........................................................................................................................................................
18
18
19
21
21
21
22
8.1 SPI Interface.......................................................................................................................................................................................
8.1.1 Writing of Data to Addressable Registers (Register Write Mode)..............................................................................................
8.1.2 Reading of Data from Addressable Registers (Register Read Mode) .......................................................................................
8.1.3 Writing and Reading of EEPROM Through SPI ........................................................................................................................
8.1.4 Loading Transmitting Data into FIFO.........................................................................................................................................
8.1.5 Reading Received Data from FIFO ...........................................................................................................................................
8.1.6 Direct Command Mode..............................................................................................................................................................
8.1.7 SPI Timing .................................................................................................................................................................................
8.1.8 Interrupt Interface ......................................................................................................................................................................
8.1.9 FIFO Water Level and FIFO Status Register.............................................................................................................................
8.1.10 ISO 14443A Frame Data in FIFO ............................................................................................................................................
8.2 Direct Commands...............................................................................................................................................................................
22
23
24
24
25
25
26
26
28
28
29
29
8.2.1 Set Default ................................................................................................................................................................................. 29
8.2.2 Clear .......................................................................................................................................................................................... 29
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AS3953
Datasheet - C o n t e n t s
8.2.3 Transmit..................................................................................................................................................................................... 29
8.2.4 Go2halt ...................................................................................................................................................................................... 29
8.3 Registers ............................................................................................................................................................................................
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Overview of Registers................................................................................................................................................................
IO Definition Register.................................................................................................................................................................
Mode Definition Registers..........................................................................................................................................................
Display Registers.......................................................................................................................................................................
Interrupt Register and Associated Registers .............................................................................................................................
Definition of Number of Transmitted Bytes ................................................................................................................................
30
30
30
31
32
33
36
9 Package Drawings and Markings ...........................................................................................................................................
37
10 Ordering Information.............................................................................................................................................................
41
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AS3953
Datasheet - P i n A s s i g n m e n t s
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
GND
VP_SPI
1
VP_REG
2
LC1
3
LC2
VSS
10
IRQ
9
MISO
8
MOSI
4
7
SCLK
5
6
/SS
AS3953
MLPD
(Top view)
/SS
IRQ
A1
MOSI
MISO
A2
A3
LC2
LC1
B2
B3
SCLK
B1
VSS
AS3953
WL-CSP
(Top view)
10
9
8
7
6
IRQ
MISO
MOSI
SCLK
/SS
C1
A4
VP_REG
B4
VP_SPI
C4
AS3953
TEST
Gold bumped die
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3
4
VSS
2
LC2
VP_REG
1
LC1
VP_SPI
0
(Bottom view)
5
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AS3953
Datasheet - P i n A s s i g n m e n t s
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Number
MLPD
WL-CSP
Gold Bumped
Die
Pin Name
Pin Type
-
-
0
TEST
Internal use
No connection
1
C4
1
VP_SPI
Supply pad
Positive supply of SPI interface
2
B4
2
VP_REG
Analog output
3
B3
3
LC1
4
B2
4
LC2
5
C1
5
VSS
6
A1
6
/SS
7
B1
7
SCLK
8
A2
8
MOSI
9
A3
9
MISO
Digital output / tristate
Serial Peripheral Interface data output
10
A4
10
IRQ
Digital output
Interrupt request output (active high)
11
-
-
Exposed Pad
Supply
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Description
Regulator output
Analog I/O
Connection to tag coil
Supply pad
Ground, die substrate potential
Serial Peripheral Interface enable (active low)
Digital input
Serial Peripheral Interface clock
Serial Peripheral Interface data input
Revision 1.0
Exposed pad to be connected to ground (optional)
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AS3953
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 7 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Comments
Electrical Parameters
VDD
DC supply voltage
-0.5
5
V
VIN
Input pin voltage except LC1 and LC2
-0.5
5
V
Input pin voltage pins LC1 and LC2
-0.5
6.5
V
100
mA
100
mA
Norm: Jedec 78
kV
Norm: MIL 883 E method 3015
(Human Body Model)
Peak current induced on pins
LC1 and LC2
Iscr
Input current (latchup immunity)
-100
Electrostatic Discharge
ESD
Electrostatic discharge
±2
Temperature Ranges and Storage Conditions
Tstrg
Tbody
Storage temperature
-55
125
Package body temperature
Humidity non-condensing
5
Moisture Sensitivity Level for MLPD
3
Moisture Sensitivity Level for WL-CSP
1
tstrg_DOF
Storage time for DOF/dies or wafers on foil
3
Tstrg_DOF
Storage temperature for DOF/dies or
wafers on foil
RHopen_DOF
Relative humidity for DOF/dies or wafers on
foil in open package
RHUnopen_DOF
Relative humidity for DOF/dies or wafers on
foil in closed package
MSL
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18
40
ºC
260
ºC
85
%
months
Norm: IPC/JEDEC J-STD-020
The reflow peak soldering temperature
(body temperature) is specified
according IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity
Classification for Non-hermetic Solid
State Surface Mount Devices”.
The lead finish for Pb-free leaded
packages is “Matte Tin” (100% Sn)
Refer to indicated date of packing
24
ºC
15
%
Opened package
60
%
Unopened package
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AS3953
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
All in this specification defined tolerances for external components need to be assured over the whole operation conditions range and also over
lifetime.
6.1 Operating Conditions
Symbol
Parameter
Ilim
Limiter current
VVP_SPI
TAMB
Min
Typ
Max
Units
Note
30
mA
Till this current limiter clamps
VLC1-LC2 to 5.0V
1.65
3.6
V
When logic powered from RFID
interface
1.8
3.6
V
When logic powered from VP_SPI
interface
-40
85
ºC
Max
Units
SPI power supply
Ambient temperature
6.2 DC/AC Characteristics for Digital Inputs and Outputs
CMOS Inputs. Valid for input pins /SS, MOSI, SCLK
Symbol
Parameter
Min
Typ
Note
VIH
High level input voltage
0.7 * VP_SPI
VIL
Low level input voltage
0.3 * VP_SPI
V
ILEAK
Input leakage current
1
µA
Max
Units
Note
V
ISOURCE = 1mA
VP_SPI = 3V
V
CMOS Outputs. Valid for output pins MISO, IRQ
Symbol
Parameter
Min
VOH
High level output voltage
0.9 * VP_SPI
VOL
Low level output voltage
0.1 * VP_SPI
V
CL
Capacitive load
50
pF
RO
Output Resistance
200
400
Ω
RPD
Pull-down resistance pad MOSI
10
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Typ
Revision 1.0
kΩ
Pull-down can be enabled while
MISO output is in tristate. The
activation is controlled by register
setting
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AS3953
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.3 Electrical Specification
VP_SPI = 3.0 V, Temperature 25ºC unless noted otherwise
Symbol
Parameter
Min
Typ
ISB_SPI
Standby consumption on VP_SPI
100
VLIM
Limiter voltage
5.2
Max
5.8
Units
Note
nA
@ 25ºC
V
ILC = 30mA (DC)
µA
Internal supply current measured in
test mode on VREC, 13.56 MHz
alternative pulses with amplitude
2Vpp, negative peak at VSS, forced to
LC1 and LC2
V
Set to 1.8V in EEPROM Configuration
word
IS
Supply current
VVP_REG
Regulated supply voltage
VHF_PON
HF_PON threshold (rising VREG)
2.3
V
VPOR_HY
HF_PON hysteresis
0.8
V
VMOD
Modulator ON voltage drop
250
1.65
1.8
2.01
1.2
V
2.6
Resonance capacitor for die
25.2
28
30.8
Resonance capacitor for MLPD package
38.2
31.3
34.4
Resonance capacitor for WL-CSP package
27
30
33
EEEN
EEPROM endurance
100 000
cycles
EERET
EEPROM retention
10
years
CR
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pF
Guaranteed by design only
ILC = 1mA
ILC = 30mA
Measured at 10MHz, 3.0Vpp (2.5Vpp)
Guaranteed by design
@ 125ºC
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AS3953
Datasheet - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
Figure 3. System Block Diagram
ISO 14443A
Reader
SPI
AS3953
Microcontroller
7.1 Circuit
The AS3953 is composed of ISO 14443A PICC Analog Front-end (PICC AFE), the ISO 14443A PICC Logic (PICC Logic), EEPROM, SPI
Interface, Level Shifters and Power Supply Manager Block (Power Manager).
The PICC AFE is connected to an external tag coil, which forms together with integrated resonant capacitor an LC tank with a resonance at the
external electromagnetic field frequency of 13.56 MHz. The PICC AFE has a built in rectifier and regulators. Output of internal regulator is called
VP_INT. It is used to supply the PICC AFE and usually also the LOGIC and EEPROM (through Power Supply Manager). Output of external
regulator VP_REG is available on a pin to supply some external circuitry.
Power Manager is controlling power supply of Logic and EEPROM. The two blocks can be supplied either from VP_INT or from VP_SPI (SPI
power supply). In order to save current on VP_SPI, VP_INT is used as power supply whenever it is available. VP_SPI is only used when some
activity is started over the SPI and the VP_REG is too low to be used as a power supply.
The PICC Logic is responsible for PICC-to-PCD communication up to the Level-4 (block transmission) of ISO 14443A. This means that anticollision and other low-level functionality are implemented there.
The SPI Interface logic contains a 32 byte FIFO for block transmission data which is exchanged on Level-4 of ISO 14443A communication. It
also contains some control and display registers.
The EEPROM is used to store the UID, the housekeeping data (configuration and control bits) and user data. It can be accessed from both sides
(RFID and SPI).
7.2 PICC AFE
Figure 4 depicts main PICC AFE building blocks.
The PICC AFE is connected to external tag coil, which together with the integrated resonant capacitor forms an LC tank with resonance at
external electromagnetic field frequency (13.56 MHz). Figure 4 depicts the main PICC AFE building blocks.
Rectifier: Extracts DC power supply from AC voltage induced on coil terminals.
Limiter: Limits the maximum voltage on coil terminals to protect PICC AFE from destruction. At voltages that exceed limiter voltage it starts to
absorb current (acts as some sort of shunt regulator).
Modulator Switch: Is used for communication PICC-to-PCD. When switched on, it will draw current from coil terminals. This mechanism is
called load modulation. Variation of current in the modulator switch (ON and OFF state) is seen as modulation by the PCD.
Demodulator: Is used for communication PICC-to-PCD. It detects AM modulation of the PCD magnetic field. The demodulator is designed to
accept modulation according to ISO 14443A; all standard bit rates from 106 kb/s to 848 kb/s are supported. The modulation for bit rate 106 kb/s
is 100%, whereas for other bit rates it may be less.
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AS3953
Datasheet - D e t a i l e d D e s c r i p t i o n
Clock Extractor: The clock extractor extracts a digital clock signal from the PCD carrier field frequency which is used as clock signal by logic
blocks.
HF_PON: Observes rectified regulated voltage VREC. When the supply voltage is sufficiently high it enables operation of the PICC AFE and
the digital tag logic. A buffer capacitor and HF_PON hysteresis guarantees that there is no reset during reader (PCD) modulation.
Internal Regulator: Provides regulated voltage VP_INT to the PICC AFE and in most cases also to EEPROM and logic blocks. Typical
regulated voltage VP_INT is 2.0V. A buffer capacitor is also integrated.
External Regulator: Provides regulated voltage on external pin VP_REG where it can be used to supply some external circuitry. The
regulated voltage and output resistance can be adjusted using EEPROM settings (see Table 6). Appropriate external buffer capacitor is needed
in case VP_REG is used in the application. The current to be provided depends on reader field strength, antenna size and Q factor, but it is
limited to maximum 5mA.
Bias: Provides bias currents and reference voltages to PICC AFE analog blocks.
Figure 4. PICC AFE Block Diagram
VP_REG
Rectifier
Limiter
VREC
VP_INT
External
Regulator
Internal
Regulator
LC1
Modulator
Switch
BIAS
HF
PON
ISO 14443 A
LOGIC
LC2
Demodulator
AS3953
Clock
Extractor
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AS3953
Datasheet - D e t a i l e d D e s c r i p t i o n
7.3 Power Manager
Power manager is controlling the positive supply voltage of the PICC Logic, EEPROM and SPI Interface (VDD). Its inputs are VP_INT (rectified
and regulated supply extracted from PCD field) and the VP_SPI (SPI power supply from external).
In standby mode, when the AS3953 is not in a PCD field (condition is that rectified supply voltage is below HF_PON threshold) and the SPI is not
active (/SS is high) the VDD supply is disconnected not to consume on VP_SPI. The only consumption on VP_SPI is leakage of level shifters
and SPI pins.
When the AS3953 is placed in a PCD field the VDD is connected to VP_INT. This happens once the VP_INT level is above the HF_PON
threshold.
VP_SPI is connected to VDD only when the AS3953 is not in the PCD field (rectified supply voltage is below HF_PON threshold) and the SPI
interface is activated by pulling /SS signal low. The switch to VP_SPI is controlled by /SS signal. The deactivation is delayed by 0.7ms min., thus
the switch stays on in case the time between successive SPI activations shorter. During EEPROM writing, which is activated over the SPI, the
switch is also active.
At activation of the switch the time between the falling edge of /SS signal and rising edge of SCLK has to be at least 50µs to allow charging of
internal VDD buffer capacitor and expiration of POR signal. Please note that the only SPI operations, which are allowed in this mode, are reading
and writing of the EEPROM and registers.
Figure 5. Power Manager Concept
VP_INT
PON
VDD
/SS
EEPROM
WRITE
DELAY
VP_SPI
7.4 ISO 14443A Framing Mode
When Framing mode is selected the PICC logic performs receive and transmit framing according to the selected ISO 14443A bit rate.
During reception it recognizes the SOF, EOF and data bits, performs parity and CRC check, organizes the received data in bytes and places
them in the FIFO.
During transmit, it operates inversely, it takes bytes from FIFO, generates parity and CRC bits, adds SOF and EOF and performs data encoding.
Default bit rate in the Framing mode is fc/128 (~106 kb/s). Higher data rates may be configured by controller by writing the Bit Rate Definition
Register.
In order to respect the PCD-to-PICC frame delay according to ISO14443-3 at data rate fc/128 bit the PICC logic synchronizes the response to
the beginning of the next response window, but not earlier than window with n=9.
In this mode the EEPROM can be accessed via SPI when the RF field is active.
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AS3953
Datasheet - D e t a i l e d D e s c r i p t i o n
7.5 ISO 14443A Level-4 Protocol Mode
When Level-4 Protocol mode is selected the PICC Logic autonomously execute complete ISO 14443A Level-3 communication and certain
commands of Level-4. This also includes the anti-collision sequence during which the AS3953 UID number is read by the PCD (7 bytes UID is
supported), the AS3953 is brought in the selected state (ISO14443-4) in which data exchange between the AS3953 and the PCD can start. On
this level also a reading and writing of the AS3953 EEPROM is possible.
In case the configuration bit irq_l4 is set an interrupt is automatically sent to controller once the PICC Logic enters in ACTIVE(*) state (after
sending SAK on Cascade Level 2).
Support of ISO 14443A Level-4.
ISO 14443A-4 commands RATS, PPS and DESELECT are implemented in the PICC Logic. RATS and PPS define communication parameters,
which are going to be used in the following data exchange by using the block transmission protocol. The advantage of implementing PPS that
defines the bit rate used for communication, is that all bit rate issues are handled by the PICC Logic. The MCU gets the information about the
actual receive and transmit bit rate by reading a dedicated display register. It has to be fast enough to serve receive and transmit at the maximum
bit rate.
Execution of the block transmission protocol is left to the controller. In case of receiving the block data from the PCD the PICC Logic provides
support by detecting and removing start bit, stop bit, parity bits and CRC. Parity bits and CRC are also checked. When the block data is sent to
the PCD the PICC Logic calculates and inserts start bit, parity bits, CRC and stop bit.
DESELECT puts the PICC Logic in HALT state. An interrupt is sent to controller upon reception of DESELECT command to inform it that PCD
stopped the Level-4 communication.
Additionally to supporting the ISO14443-4 transmitting protocol the PICC Logic accepts also proprietary commands. Proprietary commands are
identified by setting the two MSB bits of first transmitted byte to ‘01’ (This combination is not used by ISO 14443A Level-4 protocol). The
following custom commands are implemented:
Wake-up:
Read
Sends a wake-up interrupt to controller
EEPROM: Reads data from EEPROM
Write EEPROM:
Writes data to EEPROM
Support of ISO 14443A Optional Features.
CID
is supported
NAD is not supported
Historical bytes are not supported
Power
7.5.1
level indication is not supported
Coding of UID
Anti-collision procedure is based on Unique Identification Number (UID). The AS3953 supports double UID size (7 bytes). First three bytes of
UID are hard-wired inputs to the PICC Logic (uid<23:0>). Last 4 bytes of UID are stored in EEPROM UID word.
First Byte of UID (uid0).
First byte of UID is according to [ISO3] ISO/IEC 7816-6 IC Manufacturer ID. It is coded on bits uid<7:0>. ams IC Manufacturer ID is 3F(hex).
Second Byte of UID (uid1).
Second byte of UID – uid<15:8> is reserved for ams chip type (IC Type). Every ams RFID tag IC has its own chip type attributed. Therefore PCD
which has read the RFID tag UID knows to which tag IC it is talking.
The AS3953 IC type is 10(hex).
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AS3953
Datasheet - D e t a i l e d D e s c r i p t i o n
Third Byte of UID (uid2).
Third byte of UID – uid<23:16> is set to 00(hex). Table below defines the coding of the first three bytes of UID.
UID Byte
uid0
uid1
uid2
FL Signal Name
uid<7:0>
uid<15:8>
uid<23:16>
Value (hex)
3F
10
00
The last 4 bytes of UID are read from EEPROM (UID word). Table below defines the last four bytes of UID.
UID Byte
uid3
uid4
uid5
uid6
7.5.2
UID Word Bits
b7-b0
b15-b8
b23-b16
b31-b24
Coding of ATQA, SAK and ATS
Several bits of responses ATQA, SAK and ATS are defined as “don’t care” in the ISO 14443A standard. Some others are defined by optional
choices in standard protocol. This section defines how these bits are set by the AS3953.
ATQA.
ATQA is response to REQA and WUPA commands. Table below defines the ATQA coding.
b16
0
b15
0
b14
0
b13
0
b12
0
b11
0
b10
0
b9
0
b8
b7
0
1
UID size
b6
0
b5
0
b4
b3
b2
0
1
0
Bit frame anti-collision
b1
0
Bits b16 to b13 are RFU bits which must be set to ‘0’.
Bits b12 to b9 are proprietary coding and are set to ‘0’.
Bits b8 and b7 indicate double size UID.
Bit b6 is ‘RFU’ bit and is set to ‘0’.
For bit frame anti-collision, the code 00100 is chosen.
SAK.
SAK is response to SELECT command. AS3953 UID has double size, which defines SAK responses for Cascade Level 1 and Cascade Level 2.
Cascade Level 1:
According to ISO 14443-3, all bits except b3 are “don’t care” for Cascade Level 1. Table below defines Cascade Level 1
coding.
b8
MSB
0
b7
b6
b5
b4
b3
b2
0
0
0
0
1
0
Cascade Level
b1
LSB
0
Description
Cascade bit set: UID not complete
2: According to ISO 14443-3 all bits except b6 and b3 are “don’t care” for Cascade Level 2.
If configuration bit16 [nl4] is set to logic ‘0’ (default state), the SAK on Cascade Level 2 reports that tag is compliant to level4 (see table below).
b8
MSB
b7
b6
b5
b4
b3
b2
b1
LSB
Description
0
0
1
0
0
0
0
0
UID complete, tag is compliant to
ISO/IEC14443-4
If configuration bit16 [nl4] is set to logic ‘1’, the SAK on Cascade Level 2 reports that tag is NOT compliant to Level-4 (see table below).
b8
MSB
b7
b6
b5
b4
b3
b2
b1
LSB
Description
0
0
0
0
0
0
0
0
UID complete, tag is NOT compliant
to ISO/IEC14443-4
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If configuration bit15 [nfc] is set to logic ‘1’, the SAK on Cascade Level 2 reports that tag is NFC passive target (see table below).
b8
MSB
b7
b6
b5
b4
b3
b2
b1
LSB
Description
0
1
0
0
0
0
0
0
UID complete, tag is compliant to
NFCIP-1 transport protocol
ATS.
ATS is response to ISO 14443-4 command RATS. The content of the ATS is used to inform the PCD about PICC capability (like the maximum
frame size, support of higher bit rates, etc.)
Several response fields of ATS are stored in EEPROM configuration word. The AS3953 ATS is composed of following 5 bytes according to
[ISO4]: TL, T0, TA(1), TB(1) and TC(1).
TL: This is the length
b8
MSB
0
T0:
byte. Since ATS is composed of 5 bytes, its content is 0x05. Table below defines the coding of the TL byte.
b7
b6
b5
b4
b3
b2
0
0
0
0
1
0
b1
LSB
1
Description
Coding of ATS byte TL
This is the format byte. Table below defines the coding of the T0 byte.
b8
MSB
0
b7
b6
b5
b4
b3
1
TC(1)
1
TB(1)
1
TA(1)
fsci<3>
fsci<2>
b2
fsci<1>
b1
LSB
fsci<0>
Description
Coding of ATS byte T0
FCSI
Bit b8 is set to ‘0’.
Bits b7 to b5 indicate presence of bytes TA(1), TB(1) and TC(1) and hence are all set to ‘1’.
Bits b4 to b1 are called FCSI and codes FCS. The FCS is maximum size of a frame defined by PICC. It is defined by configuration bits fsci<3:0>.
TA(1):
This codes the bit rate capability of PICC. Supported higher bit rates of AS3953 are 212, 424 and 848 kb/s. However in specific
applications, it is advised to report lower capability to PCD (for example, due to the usage of slow controller or low power application). Due
to this reason the TA(1) response is configurable using configuration bits.
b8
MSB
dr_sdr
b7
b6
b5
dr_picc_8 dr_picc_4 dr_picc_2
DS (PICC to PCD)
b4
0
b3
b2
b1
LSB
dr_pcd_8 dr_pcd_4 dr_pcd_2
DR (PCD to PICC)
Description
Coding of ATS byte TA(1)
Bit b8 set to ‘0’ codes possibility of having different data rates for each direction.
TB(1): The interface
byte TB(1) conveys information to define the frame waiting time and the start-up frame guard time. The interface byte
TB(1) consists of two parts:
- The most significant half-byte b8 to b5 is called FWI and codes frame waiting time (FWT).
- The least significant half byte b4 to b1 is called SFGI and codes a multiplier value used to define the SFGT. The SFGT defines a specific
guard time needed by the PICC before it is ready to receive the next frame after it has sent the ATS. SFGI is coded in the range from 0 to
14. The value of ‘0’ indicates ‘No SFGT needed’.
The SFGT bits are fixed to default value which is 0x0, while the FWI bits are defined by configuration bits fwi<3:0>. Table below defines the
coding of the TB(1) byte.
b8
MSB
fwi<3>
b7
fwi<2>
FWI
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b6
b5
b4
b3
fwi<1>
fwi<0>
0
0
b2
0
b1
LSB
0
Description
Coding of ATS byte TB(1)
SFGI
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TC(1): The interface
byte TC(1) specifies a parameter of the protocol. The interface byte TC(1) consists of two parts:
- The most significant bits b8 to b3 are set to 000000, all other values are ‘RFU’.
- The bits b2 and b1 define which optional fields in the prologue field are supported by the PICC. The PCD is allowed to skip fields that are
supported by the PICC. Bit b2 indicates support of CID and b1 indicates support of NAD. The AS3953 value is ‘10’ indicating “CID
supported” and “NAD not supported”.
Table below defines the coding of the TC(1) byte.
b8
MSB
0
b7
b6
b5
b4
b3
b2
0
0
0
0
0
1
CID
b1
LSB
0
NAD
Description
Coding of ATS byte TC(1)
7.6 Proprietary Commands
Proprietary commands have the same format as blocks defined in ISO 14443-4 with the difference that optional NAD field is abandoned since
NAD is not supported by the AS3953. The same format is used for commands sent by PCD and AS3953 responses. Table below defines the
coding of the Proprietary commands.
Prologue Field
PCB
[CID]
1 byte
1 byte
Information Field
INF
Epilogue Field
EDC
2 bytes
Prologue field consists of the mandatory Protocol Control Byte and an optional Card Identifier Byte. Card identifier byte is according to ISO
14443-4 definition. Epilogue field contains CRC over transmitted block.
Prologue Field for Proprietary Commands.
Table below defines the coding of Prologue field for Proprietary commands.
Bit
b8
b7
b6
b5
b4
b3
b2
b1
Value
0
1
0
1
Function
01 indicates proprietary command
Shall be set to this value, other values are ‘RFU’
CID following if bit is set to ‘1’
1
0
1
Shall be set to this value, other values are ‘RFU’
The following proprietary commands are implemented:
Wake-up:
Read
Sends a wake-up interrupt to controller
EEPROM: Reads data from EEPROM
Write EEPROM:
Writes data to EEPROM
Wake-up Command.
Information field of Wake-up command consists of one byte only (see table below). The AS3953 echoes back the same information field.
01h
1byte
Table below defines the coding of the AS3953 reply INF to Wake-up command.
01h
1byte
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Word Address Byte.
Both proprietary commands related to EEPROM (Read and Write) use Word Address byte to define the address of EEPROM word that is
accessed. Seven MSB bits of the Address Byte are used to define the address, while the last bit is “don’t care”.
Note: The valid range for the Word Address byte is from 0000 000xb to 0011 111xb (EEPROM words from 00h to 1Fh).
Read EEPROM.
The Read EEPROM command is used to read data from the EEPROM. The request information field contains the following three bytes –
- Command code byte (02h)
- Address of the first word to be read
- Number of words to be read
Table below defines coding of Read EEPROM command information field.
Address of first word to be read Number of words (≤ 8) to be read
1byte
1byte
02h
1byte
If the request is normally processed, the reply information field contains the status word 90h followed by the data. In case of error, the information
field only contains the error status byte. The following rules apply:
In case the number
of words to be read is higher than 8, first eight words are read.
In case the read protected word
(its read lock bit is set) is accessed, an all ‘0’ data is sent out.
In case the reading starts at valid address and the
number of words to read is such that the reading would be done beyond the EEPROM
addressing space, all ‘0’ data is returned for non-existing addresses.
In case the reading starts at non-existing address,
error information field is returned.
Table below defines the coding of the AS3953 reply information field to Read EEPROM command, if command is normally processed.
90h
1byte
Data
4 to 32 bytes
Table below defines the coding of the AS3953 reply information field to Read EEPROM command, in case of an error.
Information Field
61h
Comment
Error (no diagnostic)
Write EEPROM.
The Write EEPROM command is used to write one EEPROM word (32 bits). The request information field contains 6 bytes –
- Command code byte (04h)
- Address of the word to be written
- Four bytes (32 bits) of data to be written
Table below defines coding of Write EEPROM command information field.
04h
1 byte
Address of word to be written
1 byte
Data
4 bytes
The AS3953 reply contains one byte informing whether the writing of EEPROM was executed or whether there was an error. Prior to actual
programming of data in EEPROM, the control logic checks whether there is enough power available. This is done by performing so called power
check during which a dummy EEPROM programming is started. If the power check fails, EEPROM programming is not performed and an error
code is sent. The EEPROM programming is a time consuming operation. Therefore, if the EEPROM programming is executed, the AS3953 reply
comes after 8ms typical. Table below defines the coding of the AS3953 reply to Write EEPROM command.
Information Field
90h
61h
62h
64h
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Comment
Writing is normally processed
Writing is not done due to coding error
(error in parity, CRC, nonexistent address…)
Writing is not done since the word is locked
Writing is not done due to power check fail
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7.6.1
Passing of Block Data to Controller
After the PICC Logic has passed the anti-collision procedure and replied with SAK on Cascade Level 2 it passes in ACTIVE(*) state. On this level
it expects that blocks received from the PCD have the format according to ISO 14443A-4. The ISO 144443A Logic recognizes the command by
observing the first received byte. Based on content of this byte command is either processed by the AS3953 or the complete block data is put in
the FIFO for further processing by the controller. The table below displays the decision criteria.
Table 3. First byte of the ISO 14443-4 PCD Block
First Byte
Comment
Action of PICC Logic
1110 0000
RATS
Replies with ATS
1110 not(0000)
1
Block is put in FIFO
1101 xxxx
PPS
1100 x 010
DESELECT
Replies and go to Halt
1100 x not(010)
(see footnote 2)
Block is put in FIFO
Replies with PPS response (second character is CID)
1111 xxxx
WTX, S(PARAMETERS), RFU
01xx xxxx
Proprietary command
00xx xxxx
I-block
10xx xxxx
R-block
2
1
Block is put in FIFO since controller needs it to implement chaining
Proprietary command is processed
Block is put in FIFO
1. RATS and PPS are only processed by the AS3953 logic in case they are sent according to the ISO 14443-4 specification (RATS is first
command sent after entry in ACTIVE(*) state, optionally followed by PPS). In case RATS or PPS are sent once the AS3953 logic is in
PROTOCOL state the information received is saved into FIFO and not acted upon.
2. Compatible with old and new S(PARAMETERS) definition: Old: 1100 x000 is S(PARAMETERS) block according to the ISO 14443-4/
AM2. New: 1111 x000 is S(PARAMETERS) block according to the modification SC17/WG8.
As shown in Table 3, the block data is put in the FIFO whenever the two MSB bits are 00 or 10 and also in the case when the four MSB bits are
1111. Therefore the implemented communication between the PCD and a tag implemented by the AS3953 and a controller does not need to
follow the Block transmission protocol defined in the ISO 14443-4.
7.6.2
Use of CID
As mentioned above the AS3953 decides depending on content of the first byte of received message to either execute received message as a
command or to put it in the FIFO. The second byte of the message comprises a CID number which is attributed by PCD. PCD will use CID
number in case more PICCs are brought to Level-4 of communication at the same time.
CID is only checked for messages (commands) that are executed by the AS3953. In case CID does not match such a command is rejected (no
action is taken).
Messages that are based on first byte are put in FIFO and are not filtered by CID. It is left to controller to check for the CID and decide whether
or not to reply (CID number is stored in the RATS Register).
7.7 ISO 14443A Level-3 Protocol Mode
Level-3 Protocol mode is intended for implementation of custom protocols for which coding on Level-4 of ISO 14443A communication according
to Table 3 is not appropriate. In this mode Level-2 and Level-3 behavior of the PICC logic is identical to ISO 14443A Level-4 Protocol mode,
while on Level-4 all received data blocks are put in FIFO.
In case the configuration bit irq_l4 is set an interrupt is automatically sent to controller once the PICC Logic enters in ACTIVE(*) state (after
sending SAK on Cascade Level 2).
In this mode the EEPROM can be accessed via SPI when the RF field is active.
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7.8 Transparent Mode
In the Transparent Mode the AS3953 logic is bypassed, AFE input and output signals are directly available on SPI interface pins when /SS signal
is high.
Modulator
switch is controlled by pin MOSI (high is modulator on)
Clock extractor output is sent to pin MISO
Demodulator output is sent to pin IRQ
When /SS signal is low the SPI interface pins resume its normal functionality.
In this mode the EEPROM can be accessed via SPI when the RF field is active.
7.9 EEPROM
The AS3953 contains an EEPROM block which can be accessed from both RFID and SPI interface. EEPROM contains 1024 bits (128 bytes)
organized in 32 words of 32 bits. Words in EEPROM are number from 0 to 31(1F[hex]). Bits in a word are numbered from 0 to 31.
Most of the EEPROM is used to store user data (27 words – 864 bits), five words are used to store some housekeeping information (part of the
AS3953 UID, configuration bits which define the AS3953 operating options, lock bits, which control the possibility to write EEPROM words).
Table 4. EEPROM Organization
Word Address [hex]
Content
Access Properties
0
UID
RO
1
Fabrication Data
RO
2
Configuration Word
RW
3
Write Lock Word
OTP
4
Read Lock Word
OTP
5
:
:
:
:
:
:
1F
User Data
RW
Access properties:
RO: Read only, writing to this word is not possible
RW: Reading and writing to this word is possible, writing is disabled once the lock bit is set
OTP: One time programmable. A bit of this word once set to ‘1’ cannot be set back to ‘0’.
7.9.1
UID Word
The UID word contains four LSB bytes of 7 byte UID which is used during anti-collision and selection process. Every IC is programmed by a
unique number during fabrication process at ams. For details on UID, please refer to Coding of UID on page 12.
7.9.2
Fabrication Data Word
This word stores some IC manufacturer data which is programmed and locked during fabrication process at ams.
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7.9.3
Configuration Word
The Configuration word is used to define the AS3953 operating options. It is delivered by ams with default setting.
Table 5. Configuration Word (Bits 31 to 16)
Configuration Bit
Name
Default
Function
b31
fsci<3>
0
b30
fsci<2>
0
b29
fsci<1>
1
b28
fsci<0>
0
b27
fwi<3>
0
b26
fwi<2>
1
b25
fwi<1>
1
b24
fwi<0>
0
b23
dr_sdr
0
1: Only the same bit rate for both directions supported (TA(1) of ATS)
b22
dr_picc_8
0
1: DR=8 PICC-to-PCD supported (848kb/s) (TA(1) of ATS)
b21
dr_picc_4
0
1: DR=4 PICC-to-PCD supported (424kb/s) (TA(1) of ATS)
b20
dr_picc_2
0
1: DR=2 PICC-to-PCD supported (212kb/s) (TA(1) of ATS)
b19
dr_pcd_8
0
1: DR=8 PCD-to-PICC supported (848kb/s) (TA(1) of ATS)
b18
dr_pcd_4
0
1: DR=4 PCD-to-PICC supported (424kb/s) (TA(1) of ATS)
b17
dr_pcd_2
0
1: DR=2 PCD-to-PICC supported (212kb/s) (TA(1) of ATS)
b16
nl4
0
1: SAK on Cascade Level 2 reports that tag is not ISO 14443-4 compatible
b15
nfc
0
1: SAK on Cascade Level 2 reports that tag is NFC passive target
FSCI. Default value (2h) codes maximum size of frame accepted by PICC to 32
bytes which is the size of the FIFO. Please note that the AS3953 can support
larger frame sizes in case FIFO is read during the receiving.
FWI (default value (6h) defines frame waiting time of ~19.3ms)
Notes:
1. Configuration bits b31 to b15 define AS3953 response to SAK and ATS command in ISO 14443A Protocol modes, while bits b14 to b0
actually change performance.
2. Incase both nl4 and nfc are set, the nl4 setting prevails.
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Table 6. Configuration Word (Bits 14 to 0)
Configuration Bit
Name
b14
irq_pu
Default
0
1: Send a power-up IRQ (after power-up initialization is finished)
b13
irq_l4
0
1: Send an IRQ at entry in ACTIVE(*) state (after sending SAK on Cascade
Level 2) (see note 2)
b12
mod_1
0
b11
mod_0
0
b10
rxncrc
0
1: Rx – CRC is not checked, CRC part of message is also put in FIFO
(see note 3)
b9
rxbs
0
1: Rx – Bit stream mode, received bits are put in FIFO (no parity and CRC
check) (see note 3)
b8
txncrc
0
1: Tx – Do not generate CRC (see note 3)
b7
txbs
0
1: Tx – Bit stream mode, bits put in FIFO are sent without parity and CRC
generation (see note 3)
b6
fdel<1>
0
b5
fdel<0>
0
b4
vreg<1>
0
b3
vreg<0>
0
b2
rreg<1>
0
b1
rreg<0>
0
b0
dr8
0
Function
00: ISO 14443A Level-4 Protocol mode
01: ISO 14443A Level-3 Protocol mode
10: Framing mode
11: Transparent mode
PCD-to-PICC delay adjustment (see note 4)
00: 1.8V
01: 2.0V
00: disabled
01: 100Ω
10: 2.7V
11: 3.3V
10: 50Ω
11: 25Ω
External Regulated voltage (VP_REG) setting
External Regulator enable and output
resistance setting
Reserved for internal use
Notes:
1. Configuration bits b31 to b15 define AS3953 response to SAK and ATS command in ISO 14443A Protocol mode, while bits b14 to b0
actually change performance.
2. Applicable in ISO 14443A Level-3 and Level-4 Protocol modes.
3. Applicable in ISO 14443A Level-3 Protocol mode and Framing mode, in Protocol mode applicable for frames which are put in FIFO.
4. Configuration bits fdel<1:0> are used to adjust frame delay time PCD-to-PICC. Delays caused by reader and tag resonant tanks and
AFE processing are compensated by PICC logic.Table below defines PCD-to-PICC frame delay compensation using fdel bits.
fdel<1:0>
00
01
10
11
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delay [ns]
442.5
295.0
147.5
590.0
delay [number of 13.56 MHz periods]
6
4
2
8
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7.9.4
OTP Words
Write and Read Lock Words are OTP (One Time Programmable). This means that once they are set to ‘1’, they cannot be reset back to ‘0’. Since
setting of OTP bits is an irreversible operation, it is strongly recommended to perform it in controlled environment.
7.9.5
Write Lock Word
The Write Lock Word contains write lock bits. Each EEPROM word has a corresponding lock bit in the Write Lock Word. Once a certain lock bit
is set to ‘1’, the content of corresponding word cannot be modified any more (it becomes read only), EEPROM write commands issued either
through PICC interface or through SPI interface are rejected. The lock bit of a certain number protects the word with the same number (e.g. b5 of
lock word protects word 5). Since lock bits are OTP they cannot be reset back to ‘0’ once they are set to ‘1’.Therefore once a certain word is
locked it cannot be unlocked any more. The lock bits for page 0 is “don’t care” since word 0 is always read only. Please note that setting lock bit
b2 locks the Lock Word itself, therefore once this bit is set the lock configuration cannot be modified any more.
7.9.6
Read Lock Word
The Read Lock Word contains read lock bits. Each EEPROM word has a corresponding lock bit in the Read Lock Word. Once a certain lock bit
is set to ‘1’, the content of corresponding word cannot be read through PICC interface, it can only be read through SPI interface. The lock bit of a
certain number protects the word with the same number (e.g. b5 of lock word protects word 5). Since lock bits are OTP they cannot be reset back
to ‘0’ once they are set to ‘1’. Therefore once a certain word is locked it cannot be unlocked any more. The lock bits for pages 0 to 4 are “don’t
care”; these pages can be read through PICC interface even in case their corresponding lock bits are set.
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8 Application Information
8.1 SPI Interface
Communication between the AS3953 and controller is done through a 4-wire Serial Peripheral Interface (SPI) and additional interrupt signal. The
AS3953 is an SPI slave device; it requests controller attention by sending an interrupt (IRQ pin).
Table 7. SPI and Interrupt Signals
Name
Signal
Signal Level
Description
/SS
Digital input with pull-up
CMOS
SPI enable (active low)
MOSI
Digital input
CMOS
Serial data input
MISO
Digital output with tristate
CMOS
Serial data output
SCLK
Digital input
CMOS
Clock for serial communication
IRQ
Digital output
CMOS
Interrupt output pin
While signal /SS is high the SPI interface is in reset, while it is low the SPI interface is enabled. It is recommended to keep signal /SS high
whenever the SPI interface is not in use. MOSI is sampled at the falling edge of SCLK. All communication is done in blocks of 8 bits (bytes). First
three bits of first byte transmitted after high to low transition of /SS define SPI operation mode. MSB bit is always transmitted first (valid for
address and data). Read and Write modes support address auto incrementing, which means that in case after the address and first data byte
some additional data bytes are sent (read), they are written to (read from) addresses incremented by ‘1’.
SPI interface supports the following modes:
Read
and write of the SPI Interface internal registers
Read
and write of the EEPROM
Read
and write of the FIFO
Sending direct commands
Please note that the only SPI operations, which are allowed when logic and EEPROM are supplied from VP_SPI, are reading and writing of
EEPROM and registers (see also Power Manager on page 11).
Table 8. SPI Modes
MODE Pattern (communication bits)
MODE
MODE
Trailer
MODE Related Data
M2
M1
M0
C4
C3
C2
C1
C0
Register Write
0
0
0
A4
A3
A2
A1
A0
Data byte (or more bytes in case of auto
incrementing)
Register Read
0
0
1
A4
A3
A2
A1
A0
Data byte (or more bytes in case of auto
incrementing)
EEPROM Write
0
1
0
0
0
0
0
0
Word Address byte
4 bytes of word
data
EEPROM Read
0
1
1
1
1
1
1
1
4 bytes of word
data (or multiple
Word Address byte words in case of
auto incrementing
FIFO Load
1
0
0
0
0
0
0
0
One or more bytes of FIFO data
FIFO Read
1
0
1
1
1
1
1
1
One or more bytes of FIFO data
COMMAND
Mode
1
1
C5
C4
C3
C2
C1
C0
MISO output is usually in tristate, it is only driven when output data is available. Due to this the MOSI and the MISO can be externally shorted to
create a bidirectional signal.
During the time the MISO output is in tristate, it is possible to switch on a 10 kΩ pull-down by activating option bits miso_pd1 and miso_pd2 in IO
Configuration Register.
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Figure 6. Signal to Controller
Separate SPI Input and Output Signals to Controller
MOSI
MOSI
MOSI
µC
AS3953
AS3953
MISO
MISO
8.1.1
Bi-directional Data IO Signal to Controller
µC
I/O
MISO
Writing of Data to Addressable Registers (Register Write Mode)
Following figures show cases of writing a single byte and writing multiple bytes with auto-incrementing address. After the SPI operation mode
bits, the address of register to be written is provided. Then one or more data bytes are transferred from the SPI, always from the MSB to the LSB.
The data byte is written in register on falling edge of its last clock. In case the communication is terminated by putting /SS high before a packet of
8 bits composing one byte is sent, writing of this register is not performed. In case the register on the defined address does not exist or it is a
read only register no write is performed.
Note: When the AS3953 is powered via vp_SPI and not via field; the registers and EEPROM can be readout. When CS is set to low, after
50us of the falling edge, the Registers and the EEPROM can be readout. Nevertheless, if there is no activity for 1ms, there is a timeout
and the logic goes to sleep, hence losing the values in the registers. (EEPROM values are retained).
Figure 7. Writing of a Single Register
/SS
SCLK
MOSI
X
0
0
Three leading
bits indicate
Mode
0
A4
A3
A2
SCLK rising
edge Data is
transfered from
µC
A1
A0
D7
D6
D5
D4
SCLK falling
edge Data is
sampled
D3
D2
D1
X
D0
/SS rising
edge signals
end of WRITE
Mode
Data is moved to
Address
A4-A0
Figure 8. Writing of Register Data with Auto-incrementing Address
/SS
SCLK
MOSI
X
0 0 0
A A A A A D D D D D D D D D D D D D D D D D D
4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
Three leading
bits indicate
Mode
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Data is moved
to Address
<A4-A0>
Data is moved to
Address
<A4-A0> + 1
Revision 1.0
D D D D D D D D D D
1 0 7 6 5 4 3 2 1 0
Data is moved to
Address
<A4-A0> + (n-1)
Data is moved to
Address
<A4-A0> + n
X
/SS raising edge
signals end of
WRITE Mode
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Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.1.2
Reading of Data from Addressable Registers (Register Read Mode)
After the SPI operation mode bits the address of register to be read has to be provided from the MSB to the LSB. Then one or more data bytes
are transferred to MISO output, always from the MSB to the LSB. As in case of the write mode also the read mode supports auto-incrementing
address.
MOSI is sampled at the falling edge of SCLK (like shown in the following diagrams); data to be read from the AS3953 internal register is driven to
MISO pin on rising edge of SCLK and is sampled by the master at the falling edge of SCLK.
In case the register on defined address does not exist all ‘0’ data is sent to MISO.
In the following figure example for reading of single byte is given.
Figure 9. Reading of a Single Register
/SS
SCLK
MOSI
X
0
0
1
MISO
A3
A2
A1
X
A0
D
7
X
Three leading
bits indicate
Mode
8.1.3
A4
SCLK rising
edge Data is
transfered
from µC
SCLK falling
edge Data is
sampled
D
6
SCLK rising
edge Data is
moved from
Address
<A4-A0>
D
5
D
4
D
3
D
2
D
1
D
0
SCLK falling
edge Data is
transfered to
µC
X
/SS rising
edge signals
end of READ
Mode
Writing and Reading of EEPROM Through SPI
EEPROM data can be read and written also through SPI interface. Due to possible conflict with RFID interface trying to access the EEPROM in
ISO 14443A - level4 mode, access is granted to SPI only in case the PICC AFE is not active.
In all other modes defined in Mode Definition Registers on page 31, the EEPROM can be accessed via SPI when the RF field is active.
Activity of the PICC AFE can be checked by observing hf_pon bit of RFID Status Display Register. In case PICC AFE is activated while the
EEPROM writing or reading operation is going on, this operation is interrupted, and l_ee_spi IRQ is sent.
Word Address Byte. Both EEPROM modes (Read and Write) use Word Address byte to define the address of EEPROM word which is
accessed. 7 MSB bits of the Address Byte are used to define the address; while the last bit is “don’t care” (utilized to synchronize EEPROM
access).
Note: The valid range for the Word Address byte is from 0000 000xb to 0011 111xb (EEPROM words from 00h to 1Fh).
Table below defines the EEPROM Word Address byte.
EEPROM Word Address
B7
WA6
B6
WA5
B5
WA4
B4
WA3
B3
WA2
B2
WA1
B1
WA0
B0
x
EEPROM Write. In order to program an EEPROM word six bytes have to be sent (mode byte, word address byte and 4 bytes of word data, all
of them MSB first)). Actual programming of EEPROM is started with rising edge of /SS signal which terminated the EEPROM Write command.
During EEPROM programming the controller is not allowed to start another SPI activity. Controller is informed about the end of EEPROM
programming by sending an interrupt (an interrupt flag is set in the Auxiliary Interrupt Register). I_eew flag is set in case EEPROM
programming is normally finished; in case of an error (writing to write protected word, writing to non-existent address) an error flag (I_er_eew) is
set. Typical EEPROM programing time for one word is 8ms.
Note: Word data is sent MSB first which is opposite to RFID EEPROM programming where LSB is sent first.
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Datasheet - A p p l i c a t i o n I n f o r m a t i o n
EEPROM Read. In order to read data from EEPROM first a mode byte is sent, followed by the word address byte (MSB first). Then one or
more words of data with address auto incrementing (packets of 4 bytes) are transferred to MISO output, always from the MSB to the LSB. MOSI
is sampled at the falling edge of SCLK; data to be read from the AS3953 EEPROM is driven to MISO pin on rising edge of SCLK and is sampled
by the master at the falling edge of SCLK. In case the word on defined address does not exist all ‘0’ data is sent to MISO.
Please note that SCLK frequency should not exceed 1MHz during EEPROM Read (limited by EEPROM read access time).
Figure 10. Reading of EEPROM Page
/SS
SCLK
MOSI
X
0 1 1 1 1
1
MISO
1 1
W W W W W W W
A A A A A A A x
6 5 4 3 2 1 0
X
B B B B B B B B B B
3 3 2 2 2 2 2 2 2 2
1 0 9 8 7 6 5 4 3 2
X
B B B B B B B B B B
9 8 7 6 5 4 3 2 1 0
X
LSB Byte from
Address
<WA6-WA0>
MSB Byte from
Address
<WA6-WA0>
1µs min
8.1.4
X
Loading Transmitting Data into FIFO
Loading the transmitting data into the FIFO is similar to writing data into an addressable registers. Difference is that in case of loading more bytes
all bytes go to the FIFO. The command mode code 10 indicates FIFO operations. In case of loading transmitting data into FIFO all bits <C5 –
C0> are set to ‘0’. Then a bit-stream, the data to be sent (1 to 32 bytes), can be transferred.
Figure 11 shows how to load the Transmitting data into the FIFO.
Figure 11. Loading of FIFO
/SS
SCLK
MOSI
X
1
0
10 pattern
indicates FIFO
mode
8.1.5
0
0
0
SCLK rising
edge Data is
transfered
from µC
0
0
SCLK falling
edge Data is
sampled
1 to 32
bytes
0
Start of
payload Data
X
/SS rising edge
signals end of
COMMAND Mode
Reading Received Data from FIFO
Reading received data from the FIFO is similar to reading data from an addressable registers. Difference is that in case of reading more bytes
they all come from the FIFO. The command mode code 10 indicates FIFO operations. In case of reading the received data from the FIFO all bits
<C5 – C0> are set to ‘1’. On the following SCLK rising edges the data from FIFO appears as in case of read data from addressable registers. In
case the command is terminated by putting /SS high before a packet of 8 bits composing one byte is read that particular byte is considered read.
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8.1.6
Direct Command Mode
Direct Command Mode has no arguments, so a single byte is sent. SPI operation mode bits 11 indicate Direct Command Mode. The following six
bits define command code, sent MSB to the LSB. The command is executed on falling edge of last clock.
Figure 12. Sending of a Direct Command
/SS
SCLK
MOSI
X
1
1
C5
C3
SCLK rising
edge Data is
transfered from
µC
Two leading
ONE indicate
COMMAND
Mode
8.1.7
C4
C2
C1
C0
X
/SS rising edge signals
start of command
execution
SCLK falling
edge Data is
sampled
SPI Timing
Table 9. Timing Parameters
Symbol
Parameter
Min
Typ
Max
Units
Note
TSCLK=TSCLKL+TSCLKH, during EEPROM
read the SCLK period has to be increased
to 1µs (this limitation is imposed by
EEPROM read access time)
General Timing (VDD = VDD_IO = VDD_D = 3.3V, Temperature 25°C)
TSCLK
SCLK period
200
ns
TSCLKL
SCLK low
80
ns
TSCLKH
SCLK high
80
ns
TSSH
SPI reset (/SS high)
50
ns
TNCSL
/SS falling to SCLK rising
25
ns
first SCLK pulse
TNCSH
SCLK falling to /SS rising
80
ns
last SCLK pulse
TDIS
Data in setup time
10
ns
TDIH
Data in hold time
10
ns
Read Timing (VDD = VDD_IO = VDD_D = 3.3V, Temperature 25°C, CLOAD ≤ 50pF)
TDOD
Data out delay
20
ns
TDOHZ
Data out to high impedance delay
20
ns
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Figure 13. SPI General Timing
/SS
...
t NCSL
t SCLKH
tSCLKL
t NCSH
SCLK
...
tDIS
MOSI
tDIH
DATAI
...
DATAI
DATAI
...
MISO
Figure 14. SPI Read Timing
/SS
...
SCLK
...
MOSI
...
DATAI
MISO
DATAO
t DOD
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...
DATAO
tDOHZ
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8.1.8
Interrupt Interface
There are two interrupt registers implemented in the AS3953 (Main Interrupt Register and Auxiliary Interrupt Register). Main Interrupt
Register contains information about seven interrupt sources, while one bit references to interrupt sources detailed in Auxiliary Interrupt
Register.
When an interrupt condition is met the source of interrupt bit is set in the Main Interrupt Register and the IRQ pin transitions to high.
The controller then reads the Main Interrupt Register to distinguish between different interrupt sources. In case the bit l_aux is pointing to the
Auxiliary Interrupt Register, this register also needs to be read. After an interrupt register (main or auxiliary) is read its content is reset to ‘0’.
Exception to this rule is the bit pointing to auxiliary register. This bit is only cleared when the auxiliary interrupt register is read. IRQ pin transitions
to high after the interrupt bit(s) which caused its transition to high has been read. Please note that there may be more than one interrupt register
bit set in case the controller did not immediately read the Interrupt registers after the IRQ signal is set and another event causing interrupt
occurred.
8.1.9
FIFO Water Level and FIFO Status Register
The AS3953 contains a 32 byte FIFO. In case of transmitting the Control logic shifts data which was previously loaded by the external controller
to the Framing Block and further to the Transmitter. During reception, the demodulated data is stored in the FIFO and the external controller can
download received data.
Transmit and receive capability of the AS3953 is not limited by of the FIFO size due to a FIFO water level interrupt system. During transmission
an interrupt is sent (interrupt due to FIFO water level in the Main Interrupt Register) when the content of data in the FIFO which still need to be
sent is lower than the FIFO water level for transmit. The external controller can now add more data in the FIFO. The same stands for receive
mode. In case the number of received bytes increases over the FIFO water level for receive an interrupt is sent to inform the external controller
that data has to be downloaded from FIFO.
The external controller has to serve the FIFO faster than data is transmitted or received. A general rule is that the SCLK frequency has to be at
least double than the actual data rate in receive or transmit.
FIFO water level is set to ¾ of FIFO for reception and to ¼ of FIFO for transmission. This means that in case of getting an interrupt during
reception there are already 24 bytes in the FIFO, which have to be read out to liberate space for following data bytes. Same stands for
transmission, water level interrupt is sent when there are 8 bytes left in FIFO, therefore up to 24 additional bytes can be loaded.
During FIFO operation (FIFO read or FIFO load) the water level detection system is blocked to avoid spurious water level interrupts (these might
occur when for example number of bytes has increased above water level during loading and immediately after that dropped again below water
level due to Tx process which runs in parallel). Due to this the FIFO loading/reading rate has to be higher than Tx / Rx bit rate, once FIFO
loading/reading is finished the /SS pin has to be pulled to VDD (logic remains in FIFO load/read mode as long as /SS remains low).
In case loading/reading of FIFO is not much faster than Tx / Rx processes low the following two cases have to be considered:
FIFO underflow IRQ is not blocked, in case
loading in FIFO is slower than transmission process the FIFO underflow IRQ is produced.
In case of slow FIFO loading it is possible
that the content of FIFO is increased above water level but it is below when FIFO loading is finished. In such case a water level IRQ is issued after termination of FIFO loading. Same stands for FIFO reading.
In case of slow FIFO loading it is possible that the content of FIFO stays below water level during complete FIFO loading operation. In such
case water level IRQ is not issued after termination of FIFO loading. Same stands for FIFO reading.
In case it is known that the receive data frame is smaller than the FIFO size the water level interrupt does not have to be served. In such case the
water level interrupt can be masked.
After data is received the external controller needs to know how long the receive data string was before downloading data from the FIFO: This
information is available in the FIFO Status Register 1 and FIFO Status Register 2 which display number of bytes in the FIFO which were not
read out.
The FIFO Status Register 2 additionally contains two bits which indicate that the FIFO was not correctly served during reception or transmission
process (FIFO overflow and FIFO underflow).
FIFO overflow is set when too much data is written in FIFO. In case this bit is set during reception the external controller did not react on time on
water level IRQ and more than 32 bytes were written in the FIFO. The received data is corrupted in such a case. During transmission this means
that controller has written more data than FIFO size. The data to be transmitted is corrupted.
FIFO underflow is set when data was read from empty FIFO. In case this bit is set during reception the external controller read more data than
was actually received. During transmission this means that controller has failed to provide the quantity of data defined in number of transmitted
bytes registers on time.
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8.1.10 ISO 14443A Frame Data in FIFO
Data in ISO 14443A frames is organized in bytes; each byte is terminated by parity bit. Data bits in a byte are numbered from b1 to b8 where b1
is LSB bit, LSB is sent first.
Data sent over SPI is also organized in bytes, bits in a byte are marked D0 to D7, where D0 is LSB bit, MSB is sent first.
During receive the framing engine checks the parity bit and removes it from data frame, only the data bytes are put in FIFO. During transmission
the process is inversed, only the data bytes are put in FIFO, while the framing engine adds the parity bits.
The ISO 14443A data bits b1 to b8 are mapped to FIFO data bits D0 to D7, which means that the order of receiving/transmitting bits in a byte is
inversed (the ISO 14443A bytes are sent LSB first while the SPI bytes are sent MSB first).
The only exceptions to this rule are the Rx and Tx bit stream modes. In these modes the meaning of byte is lost. In order to simplify processing
the order of bits is the same on ISO 14443A and FIFO side.
This means that during reception with bit rxbs set the first received bit is also the first bit read out of FIFO. In case the last FIFO byte is not
complete the bits which are not part of received data are padded with ‘0’.
The same stands for transmission with bit txbs set: the first bit written in FIFO is also the first bit sent.
8.2 Direct Commands
Table 10. List of Direct commands
Command Byte Value
[hex]
Command
Comments
C2, C3
Set Default
Puts the AS3953 in default state
C4, C5
Clear
Stops all activities and clears FIFO
C8
Transmit
Starts a transmit sequence
D0
Go2halt
Puts PICC logic in HALT state
8.2.1
Set Default
This direct command puts the AS3953 in the same state as power-up initialization. All registers are initialized to the default state.
8.2.2
Clear
This direct command stops all current activities (transmission or reception) and clears FIFO.
8.2.3
Transmit
This direct command transmits the data stored in the FIFO. In Protocol modes it is only accepted on Level-4 of communication. Before triggering
transmission using Transmit command direct command Clear has to be sent, followed by definition of number of transmitted bytes and writing
data to be transmitted in FIFO.
Execution of this direct command is only enabled when the AS3953 antenna coil is in a PCD field (VP_INT is above HF_PON threshold).
8.2.4
Go2halt
Puts PICC logic in HALT state.
Execution of this direct command is only enabled when the AS3953 antenna coil is in a PCD field (VP_INT is above HF_PON threshold) and
PICC Logic is in one of the two ISO 14443A Protocol modes.
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8.3 Registers
The 6-bit register addresses below are defined in the hexadecimal notation. The possible address range is from 00h to 3Fh.
There are two types of registers implemented in the AS3953: configuration registers and display registers. The configuration registers are used
to configure the AS3953. They can be written and read through the SPI (RW). The display registers are read only (RO); they contain information
about the AS3953 internal state, which can be accessed through the SPI.
8.3.1
Overview of Registers
Table 11. List of the SPI Interface Internal Registers
8.3.2
Address
[hex]
Content
Type
00
IO Configuration Register
RW
01
Mode Definition Register
RW
02
Bit Rate Definition Register
RW
04
RFID Status Display Register
RO
05
RATS Register
RO
08
Mask Main Interrupt Register
RW
09
Mask Auxiliary Interrupt Register
RW
0A
Main Interrupt Register
RO
0B
Auxiliary Interrupt Register
RO
0C
FIFO Status Register 1
RO
0D
FIFO Status Register 2
RO
10
Number of Transmitted Bytes Register 1
RW
11
Number of Transmitted Bytes Register 2
RW
IO Definition Register
IO Configuration Register.
Address# 00h : IO Configuration
Bit
Name
Type: RW
Default
7
miso_pd2
x
6
miso_pd1
x
Function
Comments
1: Pull-down on MISO, when \SS is low
and MISO is not driven by the AS3953
1: Pull-down on MISO when \SS is high
5
RFU
4
RFU
3
RFU
2
RFU
1
RFU
0
RFU
Note: This register is directly supplied by VP_SPI. Its initial state is unknown.
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8.3.3
Mode Definition Registers
Mode Definition Register.
Address# 01h : Mode Definition
Bit
Type: RW
Name
Default
Function
7
RFU
6
RFU
5
r_mod_1
see note
4
r_mod_2
see note
3
r_rxncrc
see note
2
r_rxbs
see note
1
r_txncrc
see note
0
r_txbs
see note
Comments
00: ISO 14443A Level-4 Protocol mode
01: ISO 14443A Level-3 Protocol mode
10: Framing mode
11: Transparent mode
ISO mode in case of register control;
If ISO 14443A Protocol mode is selected
through registers, logic is forced in Level-4
mode.
1: Rx – CRC is not checked, CRC part of
message is also put in FIFO
1: Rx – Bit stream mode, received bits are Applicable in ISO 14443A Level-3 Protocol
put in FIFO (no parity and CRC check)
mode and Framing mode. In Protocol mode,
applicable for frames which are put in FIFO.
1: Tx – Do not generate CRC
1: Tx – Bit stream mode, bits put in FIFO
are sent without parity and CRC generation
Note: Default value is loaded from EEPROM configuration word bits b12 to b7 during power-up initialization.
Bit Rate Definition Register.
Address# 02h : Bit Rate Definition
Type: RW
Bit
Name
Default
7
tx_rate3
0
6
tx_rate2
0
5
tx_rate1
0
4
tx_rate0
0
3
rx_rate3
0
2
rx_rate2
0
1
rx_rate1
0
0
rx_rate0
0
Function
Comments
Bit rate for Tx
For coding see table below
Bit rate for Rx
For coding see table below
Note: Default setting is set at power-up and after Set Default command. In ISO 14443A Level-4 Protocol mode, this value is rewritten after
receiving PPS command.
Table below defines the coding of the Bit Rate
Rate3
Rate2
Rate1
Rate0
Bit Rate [kbps]
0
0
0
0
fc/128 (~106)
0
0
0
0
0
0
0
1
1
1
0
1
fc/64 (~212)
fc/32 (~424)
fc/16 (~848)
Comments
Other combinations RFU
Note: In case a bit rate which is not supported is selected, the Tx / Rx operation is disabled.
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8.3.4
Display Registers
RFID Status Display Register.
Address# 04h : RFID Status Display
Bit
Type: R
Name
7
hf_pon
6
state<2>
5
state<1>
4
state<0>
Function
Comments
1: PICC AFE is active
AFE Power-on signal
000: POWER OFF
001: IDLE
010: READY 011 – ACTIVE
101: HALT
110: READYX
111: ACTIVEX
100: L4
PICC Logic state
3
RFU
2
RFU
1
RFU
0
RFU
Notes:
1. The information read from this register can be false during reception (the logic state change during reception and the readout of status
can be done just at the moment when the status is changing).
2. The RFID Status Display Register is not a real register. By reading this register, controller has access to specific RFID logic internal
signals in order to observe its internal state.
RATS Register.
Address# 05h : RATS
Type: R
Bit
Name
7
fsdi3
6
fsdi2
5
fsdi1
4
fsdi0
3
cid3
2
cid2
1
cid1
0
cid0
Function
Comments
RATS FSDI bits
Displays maximum frame size that PCD can
handle (set by PCD in RATS command)
RATS CID bits
Displays attributed CID number (set by PCD
in RATS command)
Notes:
1. At power-up and after Set Default, content of this register is set to ‘0’.
2. The RATS Register is used only in ISO 14443A-4 Protocol mode. It contains information sent by PCD in RATS command. The register
informs the controller about maximum frame size that the PCD can handle and the attributed CID number.
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8.3.5
Interrupt Register and Associated Registers
Mask Main Interrupt Register.
Address# 08h : Mask Main Interrupt
Bit
Name
Type: RW
Default
Function
Comments
7
M_pu
1
Mask power-up IRQ
This bit is set to ‘0’ during power-up
initialization in case EEPROM configuration
bit irq_pu is set to ‘1’
6
M_wu_l4
1
Mask wake-up IRQ at entry in ACTIVE(*)
state
This bit is set to ‘0’ during power-up
initialization in case EEPROM configuration
bit irq_l4 is set to ‘1’
5
M_wu
0
Mask wake-up IRQ triggered by sending
Wake-up command
4
M_rxs
0
Mask IRQ due to start of receive
3
M_rxe
0
Mask IRQ due to end of receive
2
M_txe
0
Mask IRQ due to end of transmission
1
M_wl
0
Mask IRQ due to FIFO water level
0
RFU
0
Note: Default setting is set at power-up and after Set Default command.
Mask Auxiliary Interrupt Register.
Address# 09h : Mask Auxiliary Interrupt
Bit
Default
Function
M_des
0
Mask IRQ due to reception of DESELECT
command
6
M_er_fr
0
Mask Framing error IRQ
5
M_er_par
0
Mask Parity error IRQ
4
M_er_crc
0
Mask CRC error IRQ
3
M_er_fifo
0
Mask FIFO error IRQ
2
M_eew
0
Mask IRQ due to successful termination of
EEPROM programming
1
M_er_eew
0
Mask error during EEPROM programming
IRQ
0
M_ee_spi
0
Mask IRQ due to interruption of EEPROM
access due to PICC interface activation
7
Name
Type: RW
Comments
Note: Default setting is set at power-up and after Set Default command.
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Main Interrupt Register.
Address# 0Ah : Main Interrupt
Bit
Type: R
Name
Function
Comments
7
I_pu
6
I_wu_l4
Power-up IRQ
5
I_wu
Wake-up IRQ triggered by sending Wake-up
command
4
I_rxs
IRQ due to start of receive
Applicable when receive frame is put in FIFO
3
I_rxe
IRQ due to end of receive
Applicable when receive frame is put in FIFO
2
I_txe
IRQ due to end of transmission
Applicable when data from FIFO is sent
During receive informing that FIFO is almost
full and has to be read out.
During transmit informing that FIFO is almost
empty and that additional data has to be send
Wake-up IRQ at entry in ACTIVE(*) state
1
I_wl
IRQ due to FIFO water level
0
I_aux
IRQ due to event displayed in the Auxiliary
Interrupt Register
Notes:
1. At power-up and after Set Default command, content of this register is set to ‘0’.
2. After Main Interrupt Register is read, with the exception of bit0, the register content is set to ‘0’. The bit0 is set to ‘0’ only after the
corresponding interrupt register is read.
Auxiliary Interrupt Register.
Address# 0Bh : Auxiliary Interrupt
Bit
Name
7
I_des
Type: R
Function
Comments
IRQ due to reception of DESELECT command
6
I_er_fr
5
I_er_par
Parity error
Framing error
4
I_er_crc
CRC error
In case of parity or/and CRC error the receive
data is still put in FIFO, error IRQ is
additionally send.
3
I_er_fifo
FIFO error (overflow/underflow)
See FIFO Status Register 2
2
I_eew
IRQ due to successful termination of EEPROM
programming
In case EEPROM write command was sent
through SPI
1
I_er_eew
Error during EEPROM programming (writing to write In case EEPROM write command was sent
protected word, writing to nonexistent address)
through SPI
0
I_ee_spi
IRQ due to interruption of EEPROM access due to
PICC interface activation
Notes:
1. At power-up and after Set Default command content of this register is set to 0.
2. After Auxiliary Interrupt Register has been read its content is set to 0.
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AS3953
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
FIFO Status Register 1.
Address# 0Ch : FIFO Status 1
Bit
Type: R
Name
Function
7
RFU
6
RFU
5
fifo_b5
4
fifo_b4
3
fifo_b3
2
fifo_b2
1
fifo_b1
0
fifo_b0
Number of data bytes (binary coded) in the FIFO
which were not read out
Comments
Valid range is from 000000 to 100000
000000 means that there are no data bytes to
be read out
Note: At power-up and after direct commands Set Default and Clear content of this register is set to 0.
FIFO Status Register 2.
Address# 0Dh : FIFO Status 2
Bit
Type: R
Name
Function
Comments
RFU
7
Set when more bytes than the actual content
of FIFO are read
6
fifo_unf
FIFO underflow
5
fifo_ovr
FIFO overflow
4
fifo_ncp
Last FIFO byte is not complete
3
fifo_lb2
2
fifo_lb1
1
fifo_lb0
0
np_lb
Number of bits in last FIFO byte in case it was not
complete (fifo_npc=1)
MSB bits valid
Parity bit is missing in last byte
This is a framing error
Note: At power-up and after direct commands Set Default and Clear content of this register is set to 0
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AS3953
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.3.6
Definition of Number of Transmitted Bytes
Number of Transmitted Bytes Register 1.
Address# 10h : Number of Transmitted Bytes 1
Bit
Name
Default
7
RFU
6
RFU
5
RFU
4
ntx9
0
3
ntx8
0
2
ntx7
0
1
ntx6
0
0
ntx5
0
Type: RW
Function
Number of full bytes to be
transmitted in one command, MSB
bits
Comments
Maximum supported number of bytes is 1023
Note: Default setting is set at power-up and after Set Default command.
Number of Transmitted Bytes Register 2.
Address# 11h : Number of Transmitted Bytes 2
Bit
Name
Default
7
ntx4
0
6
ntx3
0
5
ntx2
0
4
ntx1
0
3
ntx0
0
2
nbtx2
1
nbtx1
0
nbtx0
Type: RW
Function
Comments
Number of full bytes to be transmitted
Maximum supported number of bytes is 1023
in one command, LSB bits
Number of bits in the split byte
000 means that all bytes all full
Applicable in
- Level-3 Protocol mode in case configuration
bit txbs is set (bit stream Tx)
- Framing mode
Note: Default setting is set at power-up and after Set Default command.
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AS3953
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
9 Package Drawings and Markings
The device is available in a MLPD (3x3x0.9mm) 10-pin, WL-CSP 10-bumps package. Gold bumped dies are also available.
Figure 15. MLPD (3x3x0.9mm) 10-pin Package Diagram
AS39
53A
XXXX
Notes:
1.
2.
3.
4.
5.
Dimensions and tolerancing conform to ASME Y14.5M-1994.
All dimensions are in millimeters. Angles are in degrees.
Coplanarity applies to the exposed heat slug as well as the terminal.
Radius on terminal is optional.
N is the total number of terminals.
Symbol
A
A1
A3
L
b
D
E
e
D2
E2
aaa
bbb
ccc
ddd
eee
N
Min
0.80
0
0.30
0.18
2.23
1.49
-
Nom
0.90
0.02
0.20 REF
0.40
0.25
3.00 BSC
3.00 BSC
0.50 BSC
2.38
1.64
0.15
0.10
0.10
0.05
0.08
10
Max
1.00
0.05
0.50
0.30
2.48
1.74
-
Marking: XXXX - Encoded Date Code.
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AS3953
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Figure 16. WL-CSP 10-bumps Package Diagram
Notes:
1. ccc Coplanarity
2. All dimensions are in µm
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AS3953
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Figure 17. Gold Bumped Dies 11-pins
Table 12. Specification for Gold Bumps
Item
Min
Backgrinded Wafer Height (excl bimp height)
Max
100
Unit
µm
Bump Height
13
17
µm
Height Coplanarity for within Wafer
<
4
µm
Height Coplanarity for within Die
<
2
µm
Surface roughness
<=
3
µm
Hardness
35
65
Hv
Shear Force
8
>=
mg/µm
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AS3953
Datasheet - D e l i v e r y F r a m e D r a w i n g
10 Delivery Frame Drawing
Figure 18. Delivery Frame drawing for ‘8” cut DIEs on Foil in 12” Frame’ (see Ordering Information (page 41))
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AS3953
Datasheet - O r d e r i n g I n f o r m a t i o n
11 Ordering Information
The devices are available as standard products shown in table below.
Table 13. Ordering Information
Ordering Code
Type
Marking
Delivery Form
AS3953A-BWLT
AS3953A-BWLM
Wafer level chip scale
AS3953A
Tape & Reel
Wafer level chip scale
AS3953A
Mini Reels
Sorted wafer
NA
Wafer Box
Sorted wafer with gold bumps
NA
Foil
1
MPLD Package
AS3953A
Tape & Reel
1
MPLD Package
AS3953A
Mini Reels
AS3953A-BSWB
1
AS3953A-BSWF-Au
AS3953A-BDFT
AS3953A-BDFM
1
1. Future delivery options.
Note: All products are RoHS compliant and ams green.
Buy our products or get free samples online at www.ams.com/ICdirect
Technical Support is available at www.ams.com/Technical-Support
For further information and requests, please contact us at [email protected]
or find your local distributor at www.ams.com/distributor
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AS3953
Datasheet - C o p y r i g h t s
Copyrights
Copyright © 1997-2013, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights
reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the
copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal
commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability
applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing
by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third
party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other
services.
Contact Information
Headquarters
ams AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel
Fax
: +43 (0) 3136 500 0
: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.ams.com/contact
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