ALSC AS4LC4M16S0-75TC 3.3v 4mx16 and 8mx8 cmos synchronous dram Datasheet

Advance information
AS4LC8M8S0
AS4LC4M16S0
®
3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
Features
• PC100/133 compliant
• Organization
- 2,097,152 words × 8 bits × 4 banks (8M×8)
- 1,048,576 words × 16 bits × 4 banks (4M×16)
• Fully synchronous
- All signals referenced to positive edge of clock
• Four internal banks controlled by BA0/BA1 (bank select)
• High speed
- 133/125/100 MHz
- 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time
• Low power consumption
- Standby: 7.2 mW max, CMOS I/O
• 4096 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh
• Automatic and direct precharge
• Burst read, single write operation
• Can assert random column address in every cycle
• LVTTL compatible I/O
• 3.3V power supply
• JEDEC standard package, pinout and function
- 400 mil, 54-pin TSOP II
• Read/write data masking
• Programmable burst length (1/2/4/8/full page)
• Programmable burst sequence (sequential/interleaved)
• Programmable CAS latency (2/3)
Pin arrangement
Pin designation
NC
DQ1
VSSQ
NC
DQ2
VCCQ
NC
DQ3
VSSQ
NC
VCC
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54-pin TSOP
VCC
DQ0
VCCQ
4LC4M16S0
AS4LC4M16S0
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VCCQ
NC
DQ5
VSSQ
NC
DQ4
VCCQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Pin(s)
Description
DQM (8M×8)
UDQM/LDQM (4M×16)
Output disable/write mask
A0 to A11
Address inputs
BA0, BA1
Bank select inputs
DQ0 to DQ7 (8M×8)
DQ0 to DQ15 (4M×16)
Input/output
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
CS
Chip select
VCC, VCCQ
Power (3.3V ± 0.3V)
VSS, VSSQ
Ground
CLK
Clock input
CKE
Clock enable
AS4LC4M16S0
Selection guide
Symbol
-75 (PC133)
-8
-10F (PC100)
-10 (PC100)
Unit
fmax
133
125
100
100
MHz
CL = 2
tAC
–
–
6
–
ns
CL = 3
tAC
5.4
6
–
6
ns
Minimum setup time
tS
1.5
2
2
2
ns
Minimum hold time
tH
0.8
1.0
1.0
1.0
ns
Minimum RAS to CAS delay
tRCD
3
3
2
3
cycles
Minimum RAS precharge time
tRP
3
3
2
3
cycles
3/3/3
3/3/3
2/2/2
3/3/3
Bus frequency
Minimum clock access time
Remarks: (CL/tRCD/tRP)
7/5/00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS4LC4M16S0
AS4LC16M4S0
®
Functional description
The AS4LC8M8S0 and AS4LC4M16S0 are high-performance 64-megabit CMOS Synchronous Dynamic Random Access
Memory (SDRAM) devices organized as 2,097,152 words × 8 bits × 4 banks, and 1,048,576 words × 16 bits × 4 banks,
respectively. Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the
rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data without selecting a
new column address.
The four internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving
operations. This provides a significant advantage over asynchronous EDO and fast page mode devices.
This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length
and type (sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency
improves maximum frequency of operation. This feature enables flexible performance optimization for a variety of
applications.
DRAM commands and functions are decoded from control inputs. Basic commands are as follows:
• Deactivate all banks
• Select row; activate bank
• Mode register set
• Deactivate bank
• Deselect; power down
• CBR refresh
• Select column; write
• Select column; read
• Auto precharge with read/write • Self-refresh
The 64 Mb DRAM devices are available in 400-mil plastic TSOP II packages and have 54 pins in each configuration. Both
devices operate with a power supply of 3.3V ± 0.3V. Multiple power and ground pins are provided for low switching noise
and EMI. Inputs and outputs are LVTTL-compatible.
Logic block diagram
CLK
Clock generator
A[11:0]
Row
address
buffer
RAS
CAS
WE
Control logic
CS
Command decoder
Mode register
Refresh
counter
Column
address
buffer
Burst
counter
Bank A† 1M×16
(4096×256×16)
Bank B† 1M×16
(4096×256×16)
Bank C† 1M×16
(4096×256×16)
Bank D† 1M×16
(4096×256×16)
Sense amplifier
Column decoder and
latch circuit
Data control circuit
DQM‡
Input and output buffer
Bank select
Latch circuit
BA0, BA1
Row decoder
CKE
DQ
† For AS4LC8M8S0, Banks A-D will read 8M×8 (4096×512×8).
‡For AS4LC4M16S0, DQM will be UDQM and LDQM.
2
ALLIANCE SEMICONDUCTOR
7/5/00
AS4LC8M8S0
AS4LC4M16S0
®
Pin descriptions
Pin
Name
Description
CLK
System clock
All operations synchronized to rising edge of CLK. It also increments
the burst counters.
CKE
Clock enable
Controls CLK input. If CKE is high, the next CLK rising edge is valid.
If CKE is low, the internal clock is suspended from the next clock
cycle and the burst address and output states are frozen. Pulling CKE
low has the following effects:
all banks idle: Precharge power down and Self refresh.
row active in any bank: Active power down.
burst/access in progress: Clock suspend.
When in Power down or Self refresh mode, CKE becomes
asynchronous until exiting the mode.
CS
Chip select
Enables or disables device operation by masking or enabling all inputs
except CLK, CKE, UDQM/LDQM (×16), DQM (×8).
A0~A11
Address
Row and column addresses are multiplexed. Row address: A0~A11.
Column address (8M×8): A0~A8. Column address (4M ×16):
A0~A7.
BA0, BA1
Bank select
Memory cell array is organized in 4 banks. BA0 and BA1 select which
internal bank will be active during activate, read, write, and
precharge operations.
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
×8: DQM
×16: UDQM/LDQM
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
7/5/00
Enables row access and precharge operation. When RAS is low, row
address is latched at the rising edge of CLK.
Enables column access. When CAS is low, starting column address for
the burst access operation is latched at the rising edge of the CLK.
Enables write operation and row precharge operation.
Controls I/O buffers. When DQM is high, output buffers are disabled
during a read operation and input data is masked during a write
operation. DQM latency is 2 clocks for Read and 0 clocks for Write.
Output disable/ write
For ×16, LDQM controls lower byte (DQ0–7) and UDQM controls
mask
upper byte (DQ8–15). For ×8, only one DQM controls the 8 DQs.
UDQM and LDQM are considered same state when referenced as
DQM.
Data input/output
Data inputs/outputs are multiplexed. Data bus for 8M×8 is
DQ0~DQ7 only.
Power supply/ground Power and ground for core logic and input buffers.
Data output power/
ground
Power and ground for data output buffers.
ALLIANCE SEMICONDUCTOR
3
AS4LC4M16S0
AS4LC16M4S0
®
Commands
Command
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM
BA0/
BA1
A10
A9–A0
Mode register set
H*
H
L
L
L
L
X
Auto refresh
H
H
L
L
L
H
X
–
Entry
Self
refresh Exit
H
L
L
L
L
H
X
–
L
H
L
H
H
H
X
–
H
X
X
X
X
–
–
H
H
L
L
H
H
X
V
row address
H
H
L
H
L
H
X
V
H
H
L
H
L
L
X
V
H
H
L
H
H
L
X
H
H
L
L
H
L
X
Clock suspend or Entry
active power down
Exit
H
L
H
X
X
X
L
V
V
V
L
H
X
X
X
X
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
X
X
X
Register
Refresh
Bank activate
Read
Write
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
Burst stop
Precharge
Selected bank
All banks
Precharge power
down mode
Exit
DQM
Write enable/output
enable
Write inhibit/Output
High-Z
No operation command
1
L
H
H
H
H
X
Op code
DQ
Note
X
1,2
–
X
L
H
L
H
3
–
X
–
3
3
3
X
column
address
X
column
address
Valid
X
4
4,5
4
4,5
Active
6
X
X
4
V
L
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
H
H
X
X
X
X
L
H
H
H
X
OP = operation code.
A0~A11 and BA0~BA1 program keys.
MRS can be issued only when all banks are precharged. A new command can be issued 1 clock cycle after MRS.
Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic.
Auto/self refresh can only be issued after all banks are precharged.
BA0~BA1: bank select addresses.
If A10/AP is High at row precharge, BA0 and BA1 are ignored and all banks are selected.
During read, write, row active, and prechage:
If BA0 and BA1 are Low, Bank A is selected.
If BA0 = Low and BA1 = High, Bank B is selected.
If BA0 = High and BA1 = Low, Bank C is selected.
If BA0 and BA1 are High, Bank D is selected.
A new read/write command to the same bank cannot be issued during a burst read/write with auto precharge.
A new row active command can be issued after t(t RP/tCK + BL +) cycles.
Burst stop command valid at every burst length.
DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0).
Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2).
2
3
4
5
6
7
4
ALLIANCE SEMICONDUCTOR
7/5/00
AS4LC8M8S0
AS4LC4M16S0
®
Mode register fields
Register programmed with MRS
Address
A11~A10
Function
RFU
†
A9
WBL
A8
A7
A6
TM
A5
A4
A3
CAS latency
A2
BT
A1
A0
Burst length
† RFU = 0 during MRS cycle.
Write burst length
Burst type
A9
Length
A3
Type
0
Programmed
burst length
0
Sequential
1
Interleaved
1
Single burst
Test mode
A8
A7
Type
0
0
Mode register set
0
1
Reserved
1
0
Reserved
1
1
Reserved
CAS latency
Burst length
A6
A5
A4
Latency
A2
A1
A0
BT = 0
BT = 1
0
0
0
Reserved
0
0
0
1
1
0
0
1
Reserved
0
0
1
2
2
0
1
0
2
0
1
0
4
4
0
1
1
3
0
1
1
8
8
1
X
X
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full page
Reserved
7/5/00
ALLIANCE SEMICONDUCTOR
5
AS4LC4M16S0
AS4LC16M4S0
®
Recommended operating conditions
Parameter
Symbol
Min
Max
Unit
VCC,VCCQ
3.0
3.6
V
GND
0.0
0.0
V
VIH
2.0
VCC + 0.3
V
VIL
–0.3†
0.8
V
VOH
2.4
–
V
VOL
–
0.4
V
IL
–5
+5
uA
Output leakage current
DQs are disabled
0V ≤ VOUT ≤ VCCQ
IOZ
–5
+5
uA
Ambient operating temperature
TA
0
70
°C
Supply voltage
Input voltage
Output voltage‡
Input leakage current
Any input 0V ≤ VIN ≤ VCC
† V min = –1.5V for pulse widths less than 5 ns.
IL
‡I
OH = –2mA, and I OL = 2mA.
Recommended operating conditions apply throughout this document unless otherwise specified.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Input voltage
VIN,VOUT
–1.0
+4.6
V
Power supply voltage
VCC,VCCQ
–1.0
+4.6
V
TSTG
–55
+150
°C
PD
–
1
W
IOUT
–
50
mA
Storage temperature (plastic)
Power dissipation
Short circuit output current
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
Parameter
Symbol
Min
Max
Unit
Notes
Input capacitance: CLK
Ci1
2.5
4
pF
1, 2, 3
Input capacitance: All other input-only
pins
Ci2
2.5
5
pF
1, 2, 4
Input/output capacitance
CI/O
4.0
6.5
pF
1, 2, 5
Notes
1 This parameter is sampled. VCC = VCCQ = 3.3V; f = 1MHz; TA = 23° C; pin under test biased at 1.4V.
2 Max value is specified for –10, –10F, and –8.
3 For –75 part, Max = 3.5 pF.
4 For –75 part, Max = 3.8 pF.
5 For –75 part, Max = 6.0 pF.
6
ALLIANCE SEMICONDUCTOR
7/5/00
AS4LC8M8S0
AS4LC4M16S0
®
IDD specifications and conditions
(0° C ≤ TA ≤ 70° C, VDD, VDDQ = +3.3V ± 0.3V)
Max
Parameter
Symbol
–75
–8
–10F/10
Units
Notes
Operating current: active mode; burst = 2; READ or WRITE;
tRC = tRC(min); CAS latency = 3
IDD1
115
95
95
mA
4, 5
Standby current: power-down mode; all banks idle;
CKE = low
IDD2
2
2
2
mA
4,5
Standby current: active mode; CKE = high; CS# = high; all
banks active after tRCD met; no accesses in progress
IDD3
45
35
35
mA
4, 5
Operating current: burst mode; continuous burst; READ or
WRITE; all banks active; CAS latency = 3
IDD4
140
130
120
mA
4,5
tRFC = tRFC(min);
CL = 3
IDD5
210
210
190
mA
4, 5
tRFC = 15.625ms;
CL = 3
IDD6
50
50
40
mA
4,5
IDD7
1
1
1
mA
4,5
Auto refresh current: CKE = high;
CS# = high
Self-refresh current: CKE ≤ 0.2V
Notes
1 IDD specifications are tested after proper initialization of the device.
2 IDD is dependent on output loading and clock cycle time. Values are specified with minimum cycle time and outputs open.
3 IDD tests have VIL = 0V and V IH = 3V.
4 IDD current will decrease at lower CAS latencies. This is because the lower the latency, the lower the clock cycle time.
5 Address transitions average one transition every two clock cycles.
7/5/00
ALLIANCE SEMICONDUCTOR
7
AS4LC4M16S0
AS4LC16M4S0
®
AC parameters common to all waveforms
Sym
-75
CAS
latency Min Max
Parameter
-8
-10F
-10
Min
Max
Min
Max
Min
Max
Unit Notes
tRRD Row active to row active delay
15
–
20
–
20
–
20
–
ns
1
tRCD RAS to CAS delay time
20
–
20
–
20
–
30
–
ns
1
tRP
20
–
20
–
20
–
30
–
ns
1
tRAS Row active
44
–
50
–
50
–
60
–
ns
1
tRC Row cycle time
66
–
70
–
70
–
90
–
ns
1
1
–
1
–
1
–
1
–
CLK
2
tRDL Last data in to row precharge
2
–
2
–
2
–
2
–
CLK
2
tBDL Last data in to burst stop
1
–
1
–
1
–
1
–
CLK
2
1
–
1
–
1
–
1
–
CLK
3
3
7.5
–
8
–
10
–
10
–
2
10
–
10
–
15
–
15
–
3
5.4
–
6
–
6
–
6
–
2
6
–
6
–
6
–
6
–
3
2.7
–
3
–
3
–
3
–
2
3
–
3
–
3
–
3
–
tCH CLK high pulse width
2.5
–
3
–
3
–
3
–
ns
6
tCL CLK low pulse width
2.5
–
3
–
3
–
3
–
ns
6
tAS Add setup time
1.5
–
2
–
2
–
2
–
ns
6
tAH Add hold time
0.8
–
1
–
1
–
1
–
ns
6
1
–
1
–
1
–
1
–
ns
5
3
–
6
–
7
–
7
–
7
2
–
6
–
7
–
7
–
7
tCKH CKE hold time
0.8
–
1
–
1
–
1
–
ns
tCKS CKE setup time
1.5
–
2
–
2
–
2
–
ns
tCDL
tCCD
Row precharge
Last data in to new column
address delay
Column address to column
address delay
tCK CLK cycle time
tAC CLK to valid output delay @ 50pF
tOH Output data hold time @ 50 pF
tSLZ CLK to output in low Z
tSHZ CLK to output in high Z
ns
ns
ns
CS, RAS, CAS, WE, DQM hold
time
0.8
–
1
–
1
–
1
–
ns
tCMS
CS, RAS, CAS, WE, DQM setup
time
1.5
–
2
–
2
–
2
–
ns
tDH Data in hold time
0.8
–
1
–
1
–
1
–
ns
tDS Data in setup time
1.5
–
2
–
2
–
2
–
ns
ALLIANCE SEMICONDUCTOR
4
4,5,7
4,5,7
4,5,7
4,5,7
ns
tCMH
8
4
7/5/00
AS4LC8M8S0
AS4LC4M16S0
®
AC parameters common to all waveforms (continued)
-75
CAS
latency Min Max
Sym
Parameter
tDQD
DQM to input data delay
tDQM DQM to data mast during writes
-8
-10 F
-10
Min
Max
Min
Max
Min
Max
Unit
1
–
1
–
1
–
1
–
CLK
0
–
0
–
0
–
0
–
CLK
Notes
tDQZ
DQM to data high Z during
reads
2
–
2
–
2
–
2
–
CLK
tDWD
Write command to input data
delay
0
–
0
–
0
–
0
–
CLK
tDAL
Data-in to active command
5
–
5
–
5
–
5
–
CLK
tMRD
Load mode register to active/
refresh command
1
–
1
–
1
–
1
–
CLK
tROH
Data-out high Z from
precharge/burst stop command
3
3
–
3
–
3
–
3
–
CLK
4
2
2
–
2
–
2
–
2
–
CLK
4
tCKED
CKE to CLOCK disable or powerdown entry mode
1
–
1
–
1
–
1
–
CLK
tPED
CKE to clock enable or powerdown exit mode
1
–
1
–
1
–
1
–
CLK
Notes
1 Minimum clock cycles = (Minimum time / clock cycle time) rounded up.
2 Minimum delay required to complete write.
3 Column address change allowed every cycle.
4 Parameters dependent on CAS latency.
5 If clock rising time > 1ns, (tr/2-0.5)ns should be added to parameter.
6 If (tr and tf) > 1ns, [(tr+tf)/2-1]ns should be added to parameter.
7 Outputs measured at 1.5V with 50pF load only without resistive termination.
Burst sequence
(BL = 4)
Initial address
A1
0
0
1
1
A0
0
1
0
1
Sequential
1
2
2
3
3
0
0
1
0
1
2
3
Interleave
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
Burst sequence
A2
0
0
0
0
1
1
1
1
7/5/00
Initial address
A1
0
0
1
1
0
0
1
1
(BL = 8)
A0
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
Sequential
3
4
4
5
5
6
6
7
7
0
0
1
1
2
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
ALLIANCE SEMICONDUCTOR
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
Interleave
3
4
2
5
1
6
0
7
7
0
6
1
5
2
4
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
9
AS4LC4M16S0
AS4LC16M4S0
®
Device operation
Command
Pin settings
The following sequence must be performed prior to normal
operation.
1. Apply power, start clock, and assert CKE and DQM high. All other
signals are NOP.
2. After power-up, pause for a minimum of 200µs.
CKE/DQM = high; all others NOP.
3. Precharge both banks.
4. Perform Mode Register Set command to initialize mode register.
5. Perform a minimum of 8 auto refresh cycles to stabilize internal
circuitry.
(Steps 4 and 5 may be interchanged.)
Power up
Mode register set
Device deselect and no
operation
Bank activation
The mode register stores the user selected opcode for the SDRAM
operating modes. The CAS latency, burst length, burst type, test mode
and other vendor specific functions are selected/programmed during
CS = RAS = CAS = WE = low;
the Mode Register Set command cycle. The default setting of the
A0~A11 = opcode
mode register is not defined after power-up. The power-up and mode
register set cycle must be executed prior to normal SDRAM operation.
Refer to the Mode Register Set table and timing for details.
CS = high
The SDRAM performs a “no operation” (NOP) when RAS, CAS, and
WE = high. Since the NOP performs no operation, it may be used as
a wait state in performing normal SDRAM functions. The SDRAM is
deselected when CS is high. CS high disables the command decoder
such that RAS, CAS, WE and address inputs are ignored. Device
deselection is also considered a NOP.
The SDRAM is configured with four internal banks. Use the Bank
CS = RAS = low; CAS = WE =
Activate command to select a row in one of the idle banks. Initiate
high; A0~A10 = row address;
a read or write operation after tRCD(min) from the time of bank
BA0~BA1 = bank select
activation.
Burst read
CS = CAS = A10 = low; RAS =
WE = high; BA0~BA1 = bank
select, A0~A8 = column
address; (A9 = don’t care for
8M×8; A8,A9 = don’t care for
4M×16)
Use the Burst Read command to access a consecutive burst of data
from an active row in an active bank. Burst read can be initiated on
any column address of an active row. The burst length, sequence and
latency are determined by the mode register setting. The first output
data appears after the CAS latency from the read command. The
output goes into a high impedance state at the end of the burst
(BL = 1,2,4,8) unless a new burst read is initiated to form a gapless
output data stream. Terminate the burst with a burst stop command,
precharge command to the same bank or another burst read/write.
Burst write
CS = CAS = WE = A10 = low;
RAS = high; A0~A9 = column
address; (A9 = don’t care for
8M×8; A8,A9 = don’t care for
4M×16)
Use the Burst Write command to write data into the SDRAM on
consecutive clock cycles to adjacent column addresses. The burst
length and addressing mode is determined by the mode register
opcode. Input the initial write address in the same clock cycle as the
Burst Write command. Terminate the burst with a burst stop
command, precharge command to the same bank or another burst
read/write.
UDQM/LDQM (×16),
DQM (×8) operation
10
Description
Use DQM to mask input and output data on a cycle-by-cycle basis. It
disables the output buffers in a read operation and masks input data in
a write operation. The output data is invalid 2 clocks after DQM
assertion (2 clock latency). Input data is masked on the same clock as
DQM assertion (0 clock latency).
ALLIANCE SEMICONDUCTOR
7/5/00
®
AS4LC8M8S0
AS4LC4M16S0
Device operation (continued)
Command
Pin Settings
Description
CS = WE = low; RAS = Use burst stop to terminate burst operation. This command may be used
Burst stop
to terminate all legal burst lengths.
CAS = high
The Bank Precharge command precharges the bank specified by BA0 and
CS = A10 = RAS = WE =
BA1. The precharged bank is switched from active to idle state and is
low; CAS = high; A11 =
Bank precharge
ready to be activated again. Assert the precharge command after
bank select; A0~A9 =
tRAS(min) of the bank activate command in the specified bank. The
don’t care
precharge operation requires a time of tRP(min) to complete.
CS = RAS = WE = low;
The Precharge All command precharges all four banks simultaneously.
CAS = A10 = high;
Precharge all
BA0~BA1 = bank select; All four banks are switched to the idle state on precharge completion.
A0~A9 = don’t care
CS = CAS = WE (write) = During auto precharge, the SDRAM adjusts internal timing to satisfy
low; RAS = WE (read) = tRAS(min) and tRP for the programmed CAS latency and burst length.
A10 = high; BA0~BA1 = Couple the auto precharge with a burst read/write operation by
bank select; A0~A9 = asserting A10 to a high state at the same time the burst read/write
Auto precharge
column address; (A9 = commands are issued. At auto precharge completion, the specified bank
don’t care for 2M×8; is switched from active to idle state. Note that no new commands to the
A8,A9 = don’t care for bank can be issued until the specified bank achieves the idle state. Auto
1M×16)
precharge doesn’t work with full-page burst.
When CKE is low, the internal clock is frozen or suspended from the
next clock cycle and the state of the output and burst address are frozen.
Clock suspend/power
If all banks are idle and CKE goes low, the SDRAM enters power down
CKE = low
down mode entry
mode at the next clock cycle. When in power down mode, no input
commands are acknowledged as long as CKE remains low. To exit power
down mode, raise CKE high before the rising edge of CLK.
Resume internal clock operation by asserting CKE high before the rising
Clock suspend/power
CKE = high
edge of CLK. Subsequent commands can be issued one clock cycle after
down mode exit
the end of the Exit command.
SDRAM storage cells must be refreshed every 64ms to maintain data
integrity. Use the Auto Refresh command to refresh all rows in all banks
of the SDRAM. The row address is provided by an internal counter
which increments automatically. Auto refresh can only be asserted when
CS = RAS = CAS = low;
all four banks are idle and the device is not in the power down mode.
WE = CKE = high;
Auto refresh
The time required to complete the auto refresh operation is tRC(min).
A0~A11 = don’t care
Use NOPs in the interim until the auto refresh operation is complete.
This is the most common refresh mode. It is typically performed once
every 15.6us or in a burst of 4096 auto refresh cycles every 64ms. All
four banks will be in the idle state after this operation.
Self refresh is another mode for refreshing SDRAM cells. In this mode,
refresh address and timing are provided internally. Self refresh entry is
allowed only when all four banks are idle. The internal clock and all
CS = RAS = CAS = CKE = input buffers with the exception of CKE are disabled in this mode. Exit
low; WE = high; A0~A11 self refresh by restarting the external clock and then asserting CKE high.
Self refresh
= don’t care
NOP’s must follow for a time of tRC(min) for the SDRAM to reach the
idle state where normal operation is allowed. If burst auto refresh is used
in normal operation, burst 4096 auto refresh cycles immediately after
exiting self refresh.
7/5/00
ALLIANCE SEMICONDUCTOR
11
AS4LC4M16S0
AS4LC16M4S0
®
Mode register set command waveform
CLK
CMD
PRE
ACT
MRS
tRP
tRSC(min)
MRS can be issued only when both banks are idle.
Precharge waveforms
Precharge can be asserted after tRAS (min). The selected bank will enter the idle state after tRP.. The earliest assertion of the
precharge command without losing any burst data is show below.
(normal write; BL = 4)
CLK
CMD
WE
DQ
D0
PRE
D1
D2
D3
(normal read; BL = 4)
CLK
CMD
Read data
PRE
DQ(CL2)
Q0
DQ(CL3)
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Auto precharge waveforms
A10 controls the selection of auto precharge during the read or write command cycle.
(write with auto precharge; BL = 4)
CLK
CMD
WE
DQ
D0
D1
D2
D3
Auto precharge starts*
(read with auto precharge; BL = 4)
CLK
CMD
Read data
DQ(CL2)
DQ(CL3)
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Auto precharge starts*
* The row active command of the precharge bank can be issued after t from this point. At burst read/write with auto precharge, CAS interrupt of the same
RP
bank is illegal; other bank is described below.
12
ALLIANCE SEMICONDUCTOR
7/5/00
AS4LC8M8S0
AS4LC4M16S0
®
Concurrent Auto-P Waveforms
According to Intel™’s specification, auto-p burst interruption is allowed by another burst provided that the interrupting burst
is in a different bank than the ongoing burst.
(A) RD-P interrupted by RD in another bank (CL = 3, BL = 4)
CLK
RD
(B)
RD-P
(A)
CMD
DQ
A0
A1
B0
B1
B2
B3
Bank A Precharge Starts *
(B) RD-P interrupted by WR in another bank (CL = 2, BL = 8)
CLK
RD-P
(A)
CMD
WR
(B)
DQM
DQ
QA1
QA0
DN(B0)
D(B1)
D(B2)
D(B7)
Bank A Precharge Starts *
(C) WR-P interrupted by RD in another bank (CL = 2, BL = 4)
CLK
CMD
DQ
WRP
(A)
D(A0)
RD
(B)
D(A1)
QB0
QB1
QB2
QB3
Bank A Precharge Starts *
* The row active command of the precharge bank can be issued after t RP from this point.
7/5/00
ALLIANCE SEMICONDUCTOR
13
AS4LC4M16S0
AS4LC16M4S0
®
(D) WR-P Interrupted by WR in another bank (CL = 3, BL = 4)
CLK
WRP
(A)
CMD
WR
(B)
DA1
DA0
DQ
DA2
DB0
DB2
DB 1
DB3
Bank A Precharge Starts *
* The row active command of the precharged bank can be issued after t from this point.
RP
Clock suspension read waveforms
(BL = 8)
CLK external
CLK internal
CKE
DQM
DQ
Q1
Q2
Q3
Q4
OPEN
Q6
OPEN
CLK external
CLK internal
CKE
DQM
DQ
Q1
Q2
Q3
Q4
Q6
OPEN
CLK external
CLK internal
CKE
DQM
DQ
14
Q1
Q2
Q3
Q4
ALLIANCE SEMICONDUCTOR
Q5
Q6
7/5/00
AS4LC8M8S0
AS4LC4M16S0
®
Clock suspension write waveforms
(BL = 8)
CLK external
CLK internal
CKE
DQM
DQ
D1
D2
D3
D6
D5
DQM Mask
CKE Mask
CLK external
CLK internal
CKE
DQM
DQ
D1
D2
D3
DQM Mask
D5
D6
D5
D6
CKE Mask
CLK external
CLK internal
CKE
DQM
DQ
D1
D2
D3
D4
Read/write interrupt timing
read interrupted by read (CL = 2, BL = 4)
CLK
CMD
ADD
Read data
Read data
A
B
DQ (CL2)
DQ (CL3)
QA0
tCCD
QB0
QA 0
QB 1
QB 0
QB2
QB 3
QB1
QB2
QB3
tCCD = CAS to CAS delay (= 1 CLK)
7/5/00
ALLIANCE SEMICONDUCTOR
15
AS4LC4M16S0
AS4LC16M4S0
®
write interrupted by write (BL = 4)
CLK
CMD
tCCD
Write data Write data
ADD
A0
DQ
DA0
B0
tCDL
DB 0
DB 1
DB 2
DB3
tCCD = CAS to CAS delay (= 1 CLK)
tCDL = last address in to new column addres delay (= 1 CLK)
write interrupted by read (CL = 2, BL = 4)
CLK
CMD
ADD
tCCD
Write data Read data
A
DQ (CL2)
DA0
DQ (CL3)
DA0
B
QB0
QB 1
QB 2
QB3
QB0
QB 1
QB2
QB 3
tCDL
tCCD = CAS to CAS delay (= 1 CLK)
tCDL = last address in to new column addres delay (= 1 CLK)
read interrupted by write (CL = 3, BL = 4)
CLK
CMD
Read data
Write data*
DQM
DQ
D0
Q0
D1
D2
D3
* To prevent bus contention, maintain a gap between data in and data out.
Burst termination
Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted
during the read cycle, burst read data is terminated and the data bus goes to High Z after CAS latency. When Burst Stop is
asserted during the write cycle, burst write data is terminated and the databus goes to High Z simultaneously.
Burst stop command waveform, read cycle
(BL = 8)
CLK
CMD
DQ (CL = 2)
DQ (CL = 3)
16
Read data
Burst stop
Q0
Q1
Q2
Q0
Q1
ALLIANCE SEMICONDUCTOR
Q2
7/5/00
AS4LC8M8S0
AS4LC4M16S0
®
write cycle
CLK
CMD
Write data
DQ
(CL = 2,3)
Burst stop
Q1
Q0
Q2
Q3
Precharge command
A Precharge command can be used to interrupt burst read/write operation during the read cycle. During RD, burst read is
terminated and o/p goes to High Z after CAS latency. The same bank can be activated after tRP . During write, burst write
operation is terminated immediately. Data written two cycles prior to the precharge command will be correctly stored. Set
DQM high one cycle before Precharge command and hold it high until Precharge command to mask and avoid writing invalid
data.
read cycle (CL = 2)
CLK
CMD
Read data
PRE
DQ
Q1
Q0
ACT
Q2
Q3
tRP
read cycle (CL = 3)
CLK
CMD
Read data
PRE
DQ
Q0
ACT
Q1
Q2
Q3
write cycle (BL = 8)
CLK
CMD
DQ
Write data
D0
PRE
D1
D2
D3
Masked
Q4
ACT
tRP
DQM
7/5/00
ALLIANCE SEMICONDUCTOR
17
AS4LC4M16S0
AS4LC16M4S0
®
Auto refresh waveform
CLK
tRC
tRP
tRC
CS
RAS
CAS
WE
BA0/BA1
Banks
A10 †
A0–A9
DQM
CKE
DQ
Precharge all banks Auto refresh
Auto refresh
Auto refresh
† If A10 = High, then BA0/BA1 = don’t care; if A10 = low, then BA0/BA1 = bank select.
Self refresh waveform
CLK
CS
RAS
CAS
WE
BA0/BA1
A10
RAa
RAa
A0–A9,A11
DQM
CKE
DQ
Precharge all banks
Self refresh entry
18
tRC
Self refresh cycle
Self refresh exit
ALLIANCE SEMICONDUCTOR
Arbitrary cycle
7/5/00
AS4LC8M8S0
AS4LC4M16S0
®
Power down mode waveform
CLK
CS
RAS
CAS
WE
BA0/BA1
A10
RAa
A0–A9,A11
RAa
RAa
CAa
RAa
CAx
DQM
CKE
DQ
Active standby
Bank activate
Precharge standby
NOP
Power down mode
Power down mode entry
NOP
Power down mode
Power down mode exit
Power down mode entry
Bank activate
Power down mode exit
Enter power down mode by pulling CKE low.
All input/output buffers (except CKE buffer are turned off in power down mode.
When CKE goes high, command input must be equal to no operation at next CLK rising edge.
Read/write waveform
(BL = 8, CL = 3)
CLK
tRAS
CS
tRP
RAS
CAS
WE
BA0/BA1
A10
A0-A9,A11
tRP
RAb
RAa
RAa
CAa
RAb
CAb
DQM
CKE
tRP
DQ
Bank activate
Read
Aa 0
Aa 1
Aa 2
Aa 3
Aa 4
Aa 5
Ab0
Ab1
Q
Q
Q
Q
Q
Q
D
D
Write
7/5/00
ALLIANCE SEMICONDUCTOR
Ab 2
Ab 3
Ab 4
Ab 5
D
D
D
D
Bank activate
Precharge
19
AS4LC4M16S0
AS4LC16M4S0
®
Burst read/single write waveform
(BL = 4, CL = 3)
CLK
CS
RAS
CAS
WE
BA0/BA1
A10
RAa
A0–A9,A11
RAa
CAr
CAb
CAa
CAd
DQM
CKE
DQ
Activate
Read
Aa0
Aa1
Aa2
Aa3
Q
Q
Q
Q
Aa4
Aa5
Single
Write
D
Ad0
Ad1
Q
Q
Ad2
Ad3
Q
Q
Read
D
Interleaved bank read waveform
(BL = 4, CL = 3)
CLK
tCCD
tCCD
tCCD
CS
tRAS
tRP
RAS
CAS
WE
BA0/BA1 †
Bank
Bank Bank
tRCD
A10
RAa
A0–A9, A11
RAa
Bank
Bank
Bank
Bank
CBa
CAb
CAc
CBb
Bank
Bank
tRCD
RBa
CAa
RBa
DQM
CKE
DQ
Bank A
Bank B
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QAb0 QAb1 QAb2 QAc0 QAc1 QAc2 QBb0 QB b1 QB b2 QBb3
Active
Read
Read
Read
Precharge
Read
Precharge
† BA0 and BA1 together determine which bank undergoes operations.
20
ALLIANCE SEMICONDUCTOR
7/5/00
AS4LC8M8S0
AS4LC4M16S0
®
Interleaved bank read waveform
(BL = 4, CL = 3, Autoprecharge)
CLK
CS
tRC
tRC
tRC
RAS
tRAS
tRC
tRP
tRAS
tRAS
CAS
tRAS
tRP
tRAS
tRP
WE
BA0/BA1 †
Bank
Bank Bank
A0–A9, A11
RAa
A10
RAa
Bank
Bank
tRCD
Bank
tRCD
RAb
CAa
Bank
Bank
Bank
tRCD
tRCD
RAd
RAc
RAc
CBb
RAb
RAe
RAd
CBc
RAe
CBd
DQM
CKE
tRRD
tRRD
DQ
tRRD
QAa0 QAa1 QAa2 QAa3
Bank A
Bank B
Active
Read
Active
Read
AP
Active
tRRD
QB b0 QBb1 QBb2 QB b3
QAa0 QAa1 QAa2 QAa3
QBb0 QBb1 QBb2
AP
Read
AP
Active
Active
Read
†BA0 and BA1 together determine which bank undergoes operations. AP = internal precharge begins.
Interleaved bank read waveform
(BL = 8, CL = 3)
CLK
CS
tRC
tRC
tRC
RAS
tRAS
tRP
tRP
tRAS
tRAS
tRP
CAS
WE
BA0/BA1†
A10
A0–A9, A11
Bank
Bank Bank
tRCD
Bank
tRCD
Bank
tRCD
RAc
RBb
CAa
Bank
Bank
RB b
RAa
RAa
Bank
Bank
CBb
RAc
CAc
DQM
CKE
DQ
Bank A
Bank B
QAa0 QAa1
QAa2 QAa3 QAa4 QAa5 QA a6 QB b0 QBb1
Precharge
Active Read
Precharge
Active
Active
Read
QBb4
QB b5 QB b6 QBb7
QAc0
QAc1
Read
Precharge
†BA0 and BA1 together determine which bank undergoes operations.
7/5/00
ALLIANCE SEMICONDUCTOR
21
AS4LC4M16S0
AS4LC16M4S0
®
Interleaved bank read waveform
(BL = 8, CL = 3, Autoprecharge)
CLK
tRC
CS
tRC
RAS
tRP
tRAS
tRAS
tRAS
tRP
CAS
WE
BA0/BA1†
Bank
Bank
Bank
tRCD
A10
A0–A9, A11
Bank
RAa
tRCD
RBb
RAa
Bank
Bank
tRCD
CAa
RAc
RBb
RAc
CAb
CAc
DQM
CKE
DQ
QAa0 QAa1 QAa2
QAa3 QAa4 QAa5 QAa6 QAa7 QBb0 QBb1
tRRD
Bank A Active
Bank B
Read
AP
Read
Active
tRRD
QBb4
Read
Active
QB b5 QBb6
QAc0
QAc0
AP
† BA0 and BA1 together determine which bank undergoes operations. AP = internal precharge begins.
Interleaved bank write waveform
(BL = 8)
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
CAS
tRCD
tRCD
tRCD
WE
BA0/BA1†
A10
A0-A9,A11
Bank
Bank
Bank
RAa
RAa
Bank
Bank
RBb
CAa
Bank
RAc
RBb
CAb
RAc
CAc
DBb4 DBb5
DBb6 DBb7 DAc0
DQM
CKE
DQ
Bank A Active
Bank B
DAa0
Write
DAa1
DAa4
DAa5
Active
DAa6 DAa7
DBb0
Write
DB b1 DB b2
DBb3
Precharge
Active
DAc1
DAc2
Write Precharge
† BA0 and BA1 together determine which bank undergoes operations.
22
ALLIANCE SEMICONDUCTOR
7/5/00
AS4LC8M8S0
AS4LC4M16S0
®
Interleaved bank write waveform
(BL = 8, Autoprecharge)
CLK
CS
tRC
RAS
tRAS
tRP
tRAS
tRAS
CAS
WE
tRCD
BA0/BA1†
A10
A0-A9.A11
Bank
tRCD
Bank
Bank
RAa
RAa
tRCD
Bank
Bank
Bank
RB b
RAc
RBb
CAa
RAc
CAb
CAc
DQM
CKE
DQ
Bank A Active
Bank B
DAa0
DAa1
DAa4 DAa5 DAa6 DAa7
Write
Active
DBb0 DBb1 DBb2 DBb3
AP Bank A
Write
DBb4
DBb5 DB b6 DBb7 DA c0 DAc1
Active
DAc2
Write
AP Bank B
† BA0 and BA1 together determine which bank undergoes operations. AP = internal precharge begins
7/5/00
ALLIANCE SEMICONDUCTOR
23
AS4LC4M16S0
AS4LC16M4S0
®
Package dimensions
c
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
54-pin TSOP II
54-pin TSOP II
E He
Min
(mm)
Max
(mm)
A
–
1.2
A1
0.05
–
A2
0.95
1.05
b
0.30
0.45
c
0.12
0.21
D
22.12
22.32
E
10.03
10.29
e
0.80 (typical)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
D
l
A2
A
A1
b
He
11.56
11.96
l
0.40
0.60
0–5°
e
AC test conditions
- Input reference levels of VIH = 2.0V and VIL = 0.8V
- Output reference levels = 1.4V
- Input rise and fall times: 2 ns
+1.4V
DOUT
50W
Z0 = 50W
CLOAD = 50 pF
Figure A: Equivalent output load
Ordering information
Part
–75
–8
–10
–10F
TSOP II, 400 mil, 54-pin
AS4LC8M8S0-75TC
AS4LC8M8S0-8TC
AS4LC8M8S0-10TC
AS4LC8M8S0-10FTC
TSOP II, 400 mil, 54-pin
AS4LC4M16S0-75TC
AS4LC4M16S0-8TC
AS4LC4M16S0-10TC
AS4LC4M16S0-10FTC
Part numbering system
AS4
LC
XXXS0
–XX
T
C
DRAM prefix
LC = 3.3V CMOS
Device number for
synchronous DRAM
1/frequency
Package (device dependent):
TSOP II 400 mil, 54 pin
Commercial temperature
range, 0° C to 70 ° C
24
ALLIANCE SEMICONDUCTOR
7/5/00