high performance needs great design. Datasheet: AS5510 Linear Hall Sensor with I²C Output Please be patient while we update our brand image as austriamicrosystems and TAOS are now ams. www.ams.com AS5510 Linear Hall Sensor with I²C Output 1 General Description 2 Key Features The AS5510 is a linear Hall sensor with 10 bit resolution and I²C interface. It can measure absolute position of lateral movement of a simple 2-pole magnet. Depending on the magnet size, a lateral stroke of 0.5~2mm can be measured with air gaps around 1.0mm. To conserve power, the AS5510 may be switched to a power down state when it is not used.It is available in a WLCSP package and qualified for an ambient temperature range from -30°C to +85°C. Figure 1. Linear Position Sensor with AS5510 + Magnet 10bit resolution I²C Interface Power down mode Programmable sensitivity 3 Applications The AS5510 is ideal for: Position sensing Magnet N Servo drive feedback Camera lens control S Closed loop position control. AS5510 PCB Figure 2. Block Diagram Front End Offset Compensation Buffer & Filter DSP I2C Factory Gain Trim Test www.ams.com/AS5510 Power down Biasing & Reference ADC 10 bit SDA Revision 0.1 SCL ADR VDD VSS 1 - 18 AS5510 Datasheet - C o n t e n t s Contents 1 General Description .................................................................................................................................................................. 1 2 Key Features............................................................................................................................................................................. 1 3 Applications............................................................................................................................................................................... 1 4 Pin Assignments ....................................................................................................................................................................... 3 4.1 Pin Descriptions.................................................................................................................................................................................... 3 5 Absolute Maximum Ratings ...................................................................................................................................................... 4 6 Electrical Characteristics........................................................................................................................................................... 5 6.1 DC Characteristics for Digital Inputs and Outputs ................................................................................................................................ 5 6.1.1 CMOS Input: ADR ....................................................................................................................................................................... 5 6.1.2 CMOS I²C: SDA, SCL.................................................................................................................................................................. 5 6.2 Electrical and Magnetic Specifications ................................................................................................................................................. 6 7 Detailed Description.................................................................................................................................................................. 7 7.1 Typical Application................................................................................................................................................................................ 7 7.2 I²C Interface.......................................................................................................................................................................................... 7 7.2.1 I²C Interface Data ........................................................................................................................................................................ 8 7.3 I²C Modes ............................................................................................................................................................................................. 9 7.4 SDA, SCL Input Filters ....................................................................................................................................................................... 12 7.5 Register Map and Description ............................................................................................................................................................ 12 8 Package Drawings and Markings ........................................................................................................................................... 14 8.1 Chip Scale Package 1.4 x 1.1mm ...................................................................................................................................................... 14 8.2 Package Dimensions.......................................................................................................................................................................... 14 8.3 Recommended Footprint .................................................................................................................................................................... 9 Ordering Information............................................................................................................................................................... www.ams.com/AS5510 Revision 0.1 15 17 2 - 18 AS5510 Datasheet - P i n A s s i g n m e n t s 4 Pin Assignments Figure 3. Pin Configuration of AS5510 (Top view) Pin A1 indicator 1 2 3 A VSS ADR VDD B SDA SCL Test Note: The AS5510 is available in a 6-pin Chip Scale Package with a ball pitch of 400μm. 4.1 Pin Descriptions Table 1. Pin Description Pin Name Pin Number Pin Type VSS A1 Supply pin Negative supply pin, analog and digital ground ADR A2 Digital input I²C address selection pin Connect to either VSS (56h) or VDD (57h) VDD A3 Supply pin Positive supply pin. A capacitor of 100nF should be connected to this pin and VSS SDA B1 SCL B2 Digital input Test B3 Digital input/output www.ams.com/AS5510 Description Digital input / Digital output I²C data I/O, 20mA driving capability open drain I²C clock Test pin, must be connected to VSS during operation Revision 0.1 3 - 18 AS5510 Datasheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Min Max Units DC supply voltage at pin VDD -0.3 5 V Input pin voltage -0.3 VDD +0.3 V Input current (latchup immunity) -100 100 mA Norm: JEDEC 78 ±2 kV Norm: MIL 883 E method 3015 +125 °C Electrostatic discharge Storage temperature -55 Body temperature (Lead-free package) TBody Humidity non-condensing 5 Moisture Sensitive Level www.ams.com/AS5510 +260 °C 85 % Comments The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ JEDEC J-STD-020“Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. Represents a max. floor life time of unlimited 1 Revision 0.1 4 - 18 AS5510 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics Table 3. Operating Conditions Symbol Parameter VDD Supply voltage at pin VDD Isupp Supply current Ipd Power down current Tamb Ambient temperature Conditions Min Typ Max Units 2.5 3 3.6 V @ 25°C ambient temperature 3.5 mA 25 μA -30 85 °C 6.1 DC Characteristics for Digital Inputs and Outputs 6.1.1 CMOS Input: ADR Table 4. Electrical Characteristics ADR Input Symbol Parameter VIH High level input voltage VIL ILEAK Conditions Min Typ Max Units 0.7 * VDD VDD V Low level input voltage 0 0.3 * VDD V Input leakage current -1 1 μA Max Units Note: Operating conditions: Tamb = -30°C to +85°C, VDD = 2.5V to 3.6V (3V operation) unless otherwise noted. 6.1.2 CMOS I²C: SDA, SCL Table 5. Electrical Characteristics I²C Symbol Parameter Conditions Min Typ VIL LOW-level input voltage -0.5 0.3 * VDD V VIH HIGH-level input voltage 0.7 * VDD VDD +0.5V V Vhys Hysteresis of Schmitt Trigger inputs VDD > 2.5V VOL LOW-level output voltage (open-drain or open-collector) at 3mA sink current VDD > 2.5V IOL LOW-level output current VOL = 0.4V tof Output fall time from VIHmax to VILmax 120 1 ns tSP Pulse width of spikes that must be suppressed by the input filter 50 2 ns Ii Input current at each I/O pin +10 3 μA CB Total capacitive load for each bus line 550 pF CI/O I/O capacitance (SDA, SCL) 10 pF 0.05 * VDD V 0.4V 20 -10 4 V mA 1. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used this has to be considered for bus timing. 2. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns. 3. I/O pins of Fast-mode and Fast-mode plus devices must not obstruct the SDA and SCL lines if VDD is switched off. 4. Special purpose devices such as multiplexers and switches may exceed this capacitance due to the fact that they connect multiple paths together. Note: Operating conditions: Tamb = -30°C to +85°C, VDD = 2.5V to 3.6V (3V operation) unless otherwise noted. www.ams.com/AS5510 Revision 0.1 5 - 18 AS5510 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.2 Electrical and Magnetic Specifications Table 6. Electrical and Magnetic Specifications Symbol Parameter RES Resolution Conditions Default Setting Bin Magnetic Input Range Offsetinp Input related offset Linearity error tPwrUp Typ ±50 mT ±25 mT ±12.5 mT ±18.75 mT This time is needed for the first power-up of the device until the offset compensation is finished; Includes readout of the PPROM fuses Time after switching from powerdown mode into active mode until the offset compensation is finished 4 Power-on time Units bit 2 3 Max 10 1 Initial Power up time from cold start tPwrOn Configurable via I²C or factory trimming option Min 0.45 mT 3 % 1.5 ms μs 250 Fast Mode (default setting) fS ADC sampling frequency tdelay System propagation delay Noiseinp Input related noise 5 After offset compensation finished Equivalent to 8 * rms 50 KHz 20 μs 0.8 mTpp 12.5 KHz 50 μs 0.5 mTpp Slow mode (I²C command option) fS ADC sampling frequency tdelay System propagation delay Noiseinp Input related noise 5 After offset compensation finished Equivalent to 8 * rms 1. Offsetinp = 0.35mT residual offset + 0.1mT earth magnetic field. 2. Linearity error= adc – out ( maxB ) – adc – out ( zeroB ) lin – error = 1 – ------------------------------------------------------------------------------------------------------------- × 100 2 × adc out maxB -------------- – adc – out ( zeroB ) – 2 3. This time is needed for the first power-up of the device until the offset compensation is finished; Includes readout of the PPROM fuses; It depends on the sensitivity setting. 4. Time after switching from power-down mode into active mode until the offset compensation is finished. 5. Input related Noise (NoiseInp) is the repeatability of the measurement. www.ams.com/AS5510 Revision 0.1 6 - 18 AS5510 Datasheet - D e t a i l e d D e s c r i p t i o n 7 Detailed Description 7.1 Typical Application Figure 4. Typical Application VDD = 2.5 ~ 3.6V VDD AS5510 #1 VDD 2.7 ~ 10k VSS 100nF SCL Microcontroller SCL SDA SDA I²C interface I²C ADDR = 56h ADR Test VDD VDD VSS AS5510 #2 100nF SCL SDA I²C ADDR = 57h ADR VDD Test 7.2 I²C Interface The AS5510 includes an I²C slave according to the NXP specification UM10204. 7-bit slave address 101011x, the last address bit x is set by the ADR pin (0 or 1) Random/Sequential Read Byte/Page Write Fast-mode plus with 20mA SDA drive strength Internal hold time of 120ns for SDA signal is included (Start/Stop detection) Not implemented: 10-bit Slave Address Clock Stretching General Call Address General Call – Software Reset Read of Device ID www.ams.com/AS5510 Revision 0.1 7 - 18 AS5510 Datasheet - D e t a i l e d D e s c r i p t i o n The communication from the AS5510 includes: Reading the magnetic field strength in 10-bit data Reading the status bits Note: The I²C address of the chip is selected by hardware (pin ADR). Depending on the state of this pin, the I²C address is either Pin ADR = LOW I²C address = 1010110b(56h) Pin ADR = HIGH I²C address = 1010111b(57h) 7.2.1 I²C Interface Data Table 7. I²C Timings Symbol Parameter Conditions Min fSCLK SCL clock frequency tBUF Bus free time; time between STOP and START condition 0.5 μs tHD.STA Hold time; (repeated) START 1 condition 0.26 μs tLOW LOW period of SCL clock 0.5 μs tHIGH HIGH period of SCL clock 0.26 μs tSU.STA Setup time for a repeated START condition 0.26 μs tHD.DAT Data hold time tSU.DAT Data setup time tR Rise time of SDA and SCL signals 120 ns tF 4 Fall time of SDA and SCL signals 120 ns tSU.STO Setup time for STOP condition 2 Typ Max Units 1 MHz 0.45 3 50 0.26 μs ns μs 1. After this time the first clock is generated 2. A device must internally provide a hold time of at least 120ns (Fast-mode Plus) for the SDA signal (referred to the VIHmin of the SCL) to bridge the undefined region of the falling edge of SCL. 3. A fast-mode device can be used in standard-mode system, but the requirement tSU.DAT = 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRmax + TSU.DAT = 1000 + 250 = 1250ns before the SCL line is released. 4. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used this has to be considered for bus timing. Note: Operating conditions Tamb = -30 to +85°C, VDD=2.5 to 3.6V (3V operation) unless otherwise noted. www.ams.com/AS5510 Revision 0.1 8 - 18 AS5510 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 5. I²C Timing Diagram SDA tbuf tLOW tR tHD.STA tF SCL tSU.DAT tHD.STA Stop Start tHD.DAT tHIGH tSU.STA tSU.STO Repeated Start 7.3 I²C Modes The AS5510 supports the I²C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions must control the bus. The AS5510 operates as a slave on the I²C bus. Within the bus specifications a standard mode (100 kHz maximum clock rate) a fast mode (400 kHz maximum clock rate) and fast mode plus (1MHz maximum clock rate) are defined. The AS5510 works in all three modes. Connections to the bus are made through the open-drain I/O lines SDA and the input SCL. Clock stretching is not included. The following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as start or stop signals. Accordingly, the following bus conditions have been defined: Bus Not Busy. Both data and clock lines remain HIGH. Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data Valid. The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge. Each receiving device, when addressed, is obliged to generate an acknowledge bit after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of READ access to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. www.ams.com/AS5510 Revision 0.1 9 - 18 AS5510 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 6. Data Read (Write Pointer, Then Read) - Slave Receive and Transmit Slave Address SDA Repeated if more Bytes are transferred MSB SCL 1 2 ... 6 LSB R/W ACK 7 8 9 Start Condition ACK 1 ... 7 8 9 Stop Condition or Repeated Start Condition Depending upon the state of the R/W bit, two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address, followed by R/W = 0. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. If the slave does not understand the command or data it sends a “not acknowledge”. Data is transferred with the most significant bit (MSB) first. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. The AS5510 can operate in the following two modes: Slave Receiver Mode (Write Mode). Serial data and clock are received through SDA and SCL. Each byte is followed by an acknowledge bit (or by a not acknowledge depending on the address-pointer pointing to a valid position). START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (see Figure 7). The slave address byte is the first byte received after the START condition. The slave address byte contains the 7-bit AS5510 address. The 7-bit slave address is followed by the direction bit (R/W), which, for a write, is 0. After receiving and decoding the slave address byte the device outputs an acknowledge on the SDA. After the AS5510 acknowledges the slave address + write bit, the master transmits a register address to the AS5510. This sets the address pointer on the AS5510. If the address is a valid readable address the AS5510 answers by sending an acknowledge. If the address-pointer points to an invalid position a “not acknowledge” is sent. The master may then transmit zero or more bytes of data. In case of the address pointer pointing to an invalid address the received data are not stored. The address pointer will increment after each byte transferred independent from the address being valid. If the address-pointer reaches a valid position again, the AS5510 answers with an acknowledge and stores the data. The master generates a STOP condition to terminate the data write. www.ams.com/AS5510 Revision 0.1 10 - 18 AS5510 Datasheet - D e t a i l e d D e s c r i p t i o n <Slave address> <RW> Figure 7. Data Write - Slave Receiver Mode 1010110 0 S <Word address (n)> A XXXXXXXX S – Start A – Acknowledge (ACK) P – Stop <Data(n)> A <Data(n+1)> XXXXXXXX A <Data(n+X)> XXXXXXXX A XXXXXXXX NA P Data transferred: X+1 Bytes + Acknowledge Slave Transmitter Mode (Read Mode). The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the AS5510 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 8 and Figure 9). The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit AS5510 address. The 7-bit slave address is followed by the direction bit (R/W), which, for a read, is 1. After receiving and decoding the slave address byte the device outputs an acknowledge on the SDA line. The AS5510 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The AS5510 must receive a “not acknowledge” to end a read. S <Slave address> <RW> Figure 8. Data Read (from Current Pointer Location) - Slave Transmitter Mode 1010110 1 <Data(n)> A S – Start A – Acknowledge (ACK) NA – Not Acknowledge (NACK) P – Stop www.ams.com/AS5510 XXXXXXXX <Data(n+1)> A XXXXXXXX <Data(n+2)> A XXXXXXXX <Data(n+X)> A XXXXXXXX NA P Data transferred: X+1 Bytes + Acknowledge Note: Last data byte is followed by NACK Revision 0.1 11 - 18 AS5510 Datasheet - D e t a i l e d D e s c r i p t i o n <Slave address> 1010110 0 <W ord Address (n)> A XXXXXXXX S – Start SA – Repeated Start A – Acknowledge (ACK) NA – Not Acknowledge (NACK) P – Stop A <Slave Address> <RW> S <RW> Figure 9. Data Read (Write Pointer, Then Read) - Slave Receive and Transmit 1010110 1 Sr <Data(n)> A <Data(n+1)> XXXXXXXX A <Data(n+X)> XXXXXXXX A XXXXXXXX NA P Data transferred : X+1 Bytes + Acknowledge Note: Last data byte is followed by NACK Automatic increment of address pointer. The AS5510 slave automatically increments the address pointer after each byte transferred. The increase of the address pointer is independent from the address being valid or not. Invalid Addresses. If the user sets the address pointer to an invalid address, the address byte is not acknowledged. Nevertheless a read or write cycle is possible. The address pointer is increased after each byte. Reading. When reading from a wrong address, the AS5510 slave returns all zero. The address pointer is increased after each byte. Sequential read over the whole address range is possible including address overflow. Write. A write to a wrong address is not acknowledged by the AS5510 slave, although the address pointer is increased. When the address pointer points to a valid address again, a successful write accessed is acknowledged. Page write over the whole address range is possible including address overflow. 7.4 SDA, SCL Input Filters Input filters for SDA and SCL inputs are included to suppress noise spikes of less than 50ns. Furthermore the SDA line is delayed by 120ns to provide an internal hold time for Start/Stop detection to bridge the undefined region of the falling edge of SCL. The delay needs to be smaller than tHD.STA 260ns. For Standard-mode and Fast-mode an internal hold time of 300ns is required, which is not covered by the AS5510 slave. 7.5 Register Map and Description Table 8. Register Map Register Address 00h Bit 7 6 5 4 3 2 1 0 Access Type D7 D6 D5 D4 D3 D2 D1 D0 R OCF Parity (even) D9 D8 R PD(0) R/W Offs1 Offs0 R/W Offs9 Offs8 R/W 01h Fast(0) Polarity(0) Slow mode (1) 02h 03h Offs7 Offs6 Offs5 Offs4 Offs3 04h Offs2 05h 06h Reserved for factory testing R/W 07h 0Bh www.ams.com/AS5510 Sens 1 Revision 0.1 Sens 0 R/W 12 - 18 AS5510 Datasheet - D e t a i l e d D e s c r i p t i o n Table 9. Register Description Description Register Address Name 00h, 01h D9 to D0 01h Parity Even parity bit calculated from D9 to D0 01h OCF Offset compensation loop status 0 = Offset compensation loop in use 1 = Offset compensation loop has finished 02h PD Power down mode 0 = Normal operation (Default) 1 = Power Down mode. 02h Polarity 02h Fast / Slow mode 03h, 04h Offs9 to Offs0 05h, 06h, 07h Test 0Bh www.ams.com/AS5510 Sensitivity 10 Bit ADC output value that corresponds to the magnetic field input Output signal polarity 0 = Normal polarity (Default) 1 = Reversed polarity (reversed magnet) 0 = Fast mode (Default) 1 = Slow mode. Enables averaging of the output values (reduced noise, better repeatability slower sampling frequency. See Section 6.2 10 Bit value of the offset compensation. This register is factory trimmed These registers are reserved for factory testing Sensitivity setting 0h = Input range ±50mT Sensitivity = 97.66µT/LSB (Default) 1h = Input range ±25mT Sensitivity = 48.83µT/LSB 2h = Input range ±12.5mT Sensitivity = 24.41µT/LSB 3h = Input range ±18.75mT Sensitivity = 36.62µT/LSB Revision 0.1 13 - 18 AS5510 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 8 Package Drawings and Markings 8.1 Chip Scale Package 1.4 x 1.1mm Figure 10. 6-Pin WL-CSP 1.4 x 1.1mm XXXX 8.2 Package Dimensions Figure 11. Package Dimensions Top View Side View Device number Bottom View Notes: 1. ccc Coplanarity 2. All dimensions in μm www.ams.com/AS5510 Revision 0.1 14 - 18 AS5510 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 8.3 Recommended Footprint Figure 12. Recommended Footprint X x0 x1 x1 Symbol X x0 x1 Y y0 y1 D x0 y0 D y1 Y y0 www.ams.com/AS5510 Revision 0.1 Package Dimensions Typ 1460 330 400 1100 350 400 270 Unit μm 15 - 18 AS5510 Datasheet - R e v i s i o n H i s t o r y Revision History Revision Date Owner Description 0.1 27 Jan, 2012 rph Initial revision Note: Typos may not be explicitly mentioned under revision history. www.ams.com/AS5510 Revision 0.1 16 - 18 AS5510 Datasheet - O r d e r i n g I n f o r m a t i o n 9 Ordering Information The devices are available as the standard products shown in Table 10. Table 10. Ordering Information Model Description Delivery Form Package AS5510 DWLT Linear Hall Sensor Tape & Reel 6pin WL-CSP 1.4 x 1.1mm D......Temperature Range: -30°C to +85°C WL...Package: WL-CSP Wafer Level - Chip Scale Package T......Delivery Form: Tape & Reel Note: All products are RoHS compliant and ams green. Buy our products or get free samples online at www.ams.com/ICdirect Technical Support is available at www.ams.com/Technical-Support For further information and requests, email us at [email protected] (or) find your local distributor at www.ams.com/distributor www.ams.com/AS5510 Revision 0.1 17 - 18 AS5510 Datasheet - C o p y r i g h t s Copyrights Copyright © 1997-2012, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. 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Contact Information Headquarters ams AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel Fax : +43 (0) 3136 500 0 : +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.ams.com/contact www.ams.com/AS5510 Revision 0.1 18 - 18