ALSC AS7C32096A-15TIN 3.3v 256k x 8 cmos sram Datasheet

February 2005
Preliminary Information
AS7C32096A
®
3.3V 256K × 8 CMOS SRAM
Features
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
• Industrial and commercial temperature
• Organization: 262,144 words × 8 bits
• Center power and ground pins
• High speed
- 44-pin TSOP 2
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• Low power consumption: ACTIVE
- 650 mW / max @ 10 ns
• Low power consumption: STANDBY
- 28.8 mW / max CMOS
Pin arrangements
Logic block diagram
44-pin TSOP 2
NC
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
VCC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
NC
NC
VCC
GND
262,144 × 8
Array
(2,097,152)
I/O1
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Row decoder
Input buffer
I/O8
Control
Circuit
WE
OE
CE
A10
A11
A12
A13
A14
A15
A16
A17
Column decoder
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A17
A16
A15
A14
OE
I/O8
I/O7
GND
VCC
I/O6
I/O5
A13
A12
A11
A10
NC
NC
NC
NC
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
2/24/05, v. 1.0
Industrial
Commercial
–10
10
4
180
170
8
Alliance Semiconductor
–12
12
5
160
150
8
–15
15
6
140
130
8
–20
20
7
110
100
8
Unit
ns
ns
mA
mA
mA
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
AS7C32096A
®
Functional description
The AS7C32096A is a high-performance CMOS 2,097,152-bit Static Random Access Memory (SRAM) device organized as
262,144 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 4/5/6/7 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory
systems.
When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in
CMOS standby mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written
on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins
only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3V supply voltage. This device is available as
per industry standard 44-pin TSOP 2 package.
Absolute maximum ratings
Parameter
Voltage on VCC relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature with VCC applied
DC current into output (low)
Symbol
Vt1
Vt2
PD
Tstg
Tbias
IOUT
Min
–0.5
–0.5
–
–65
–55
–
Max
+5.0
VCC +0.5
1.0
+150
+125
20
Unit
V
V
W
°C
°C
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
Data
High Z
High Z
DOUT
DIN
Mode
Standby (ISB, ISB1)
Output disable (ICC)
Read (ICC)
Write (ICC)
Key: X = Don’t care, L = Low, H = High
2/24/05, v. 1.0
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P. 2 of 9
AS7C32096A
®
Recommended operating condition
Parameter
Symbol
VCC(10/12/15/20)
VIH**
VIL*
TA
TA
Supply voltage
Input voltage
commercial
industrial
Ambient operating
temperature
Min
3.0
2.0
–0.5
0
–40
Nominal
3.3
–
–
–
–
Max
3.6
VCC + 0.5
0.8
70
85
Unit
V
V
V
°C
°C
* V min = –1.0V for pulse width less than 5ns.
** IL
VIH max = VCC + 2.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)1
Parameter
Input leakage
current
Symbol
|ILI|
Output leakage
current
|ILO|
Operating power
supply current
ICC
Standby power
supply current
Output voltage
–10
–12
–15
–20
Min Max Min Max Min Max Min Max Unit
Test conditions
–
1
–
1
–
1
–
1
µA
–
1
–
1
–
1
–
1
µA
Industrial
–
180
–
160
–
140
–
110
mA
Commercial
-
170
-
150
-
130
-
100
mA
VCC = Max, VIN = GND to VCC
VCC = Max, CE = VIH
VOUT= GND to VCC
VCC = Max, CE ≤ VIL
f = fMax, IOUT = 0mA
ISB
VCC = Max, CE ≥ VIH, f = fMax
–
60
–
60
–
60
–
60
mA
ISB1
VCC = Max,
CE ≥ VCC – 0.2V,
VIN ≤ 0.2V or VIN ≥ VCC – 0.2V,
f=0
–
8
–
8
–
8
–
8
mA
VOL
IOL = 8 mA, VCC = Min
–
0.4
–
0.4
–
0.4
–
0.4
V
VOH
IOH = –4 mA, VCC = Min
2.4
–
2.4
–
2.4
–
2.4
–
V
Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)4
Signals
Test conditions
Max
Unit
Input capacitance
Parameter
CIN
A, CE, WE, OE
VIN = 0V
5
pF
I/O capacitance
CI/O
I/O
VIN = VOUT = 0V
7
pF
2/24/05, v. 1.0
Symbol
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AS7C32096A
®
Read cycle (over the operating range)2,8
Parameter
–10
Max
Min
–12
Max
Min
–15
Max
Min
–20
Max
Symbol
Min
Unit Notes
Read cycle time
tRC
10
–
12
–
15
–
20
–
ns
Address access time
tAA
–
10
–
12
–
15
–
20
ns
2
Chip enable (CE) access time
tACE
–
10
–
12
–
15
–
20
ns
2
Output enable (OE) access time
tOE
–
4
–
5
–
6
–
7
ns
Output hold from address change
tOH
3
–
3
–
3
–
3
–
ns
4
CE Low to output in low Z
tCLZ
3
–
3
–
3
–
3
–
ns
3,4
CE High to output in high Z
tCHZ
–
5
–
6
–
7
–
9
ns
3,4
OE Low to output in low Z
tOLZ
0
–
0
–
0
–
0
–
ns
3,4
OE High to output in high Z
tOHZ
–
5
–
6
–
7
–
9
ns
3,4
Power up time
tPU
0
–
0
–
0
–
0
–
ns
3,4
Power down time
tPD
–
10
–
12
–
15
–
20
ns
3,4
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)2,5,6,8
tRC
Address
tAA
tOH
DOUT
Data valid
Read waveform 2 (CE, OE controlled)2,5,7,8
tRC1
CE
tOE
OE
tOLZ
tOHZ
tACE
tCHZ
DOUT
Data valid
tCLZ
Supply
current
2/24/05, v. 1.0
tPU
tPD
50%
50%
Alliance Semiconductor
ICC
ISB
P. 4 of 9
AS7C32096A
®
Write cycle (over the operating range)9
–10
Symbol Min
Max
Parameter
–12
Min
Max
–15
Min
Max
–20
Min
Max
Unit Notes
Write cycle time
tWC
10
–
12
–
15
–
20
–
ns
Chip enable (CE) to write end
tCW
7
–
8
–
10
–
12
–
ns
Address setup to write end
tAW
7
–
8
–
10
–
12
–
ns
Address setup time
tAS
0
–
0
–
0
–
0
–
ns
Write pulse width (OE = high)
tWP1
7
–
8
–
10
–
12
–
ns
Write pulse width (OE = low
tWP2
10
–
12
–
15
–
20
–
ns
Address hold from end of write
tAH
0
–
0
–
0
–
0
–
ns
Write recovery time
tWR
0
–
0
–
0
–
0
–
ns
Data valid to write end
tDW
5
–
6
–
7
–
9
–
ns
Data hold time
tDH
0
–
0
–
0
–
0
–
ns
3,4
Write enable to output in high Z
tWZ
0
5
0
6
0
7
0
9
ns
3,4
Output active from write end
tOW
3
–
3
–
3
–
3
–
ns
3,4
Write waveform 1 (WE controlled)9
tWC
tWR
tAH
tAW
Address
tWP
WE
tAS
tDW
DIN
tDH
Data valid
tWZ
tOW
DOUT
2/24/05, v. 1.0
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P. 5 of 9
AS7C32096A
®
Write waveform 2 (CE controlled)9
tWC
tWR
tAH
tAW
Address
tAS
tCW
CE
tWP
WE
tWZ
DIN
tDW
tDH
Data valid
DOUT
AC test conditions
-
Output load: see Figure B.
Input pulse level: GND to 3.0V. See Figures A and B.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
DOUT
+3.3V
320Ω
+3.0V
GND
90%
10%
90%
10%
2 ns
Figure A: Input pulse
DOUT
350Ω
C10
Thevenin equivalent:
168Ω
+1.728V
GND
Figure B: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
For test conditions, see AC Test Conditions.
tCLZ and tCHZ are specified with CL = 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CE and OE are LOW for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
C=30pF, except on High Z and Low Z parameters, where C=5pF.
2/24/05, v. 1.0
Alliance Semiconductor
P. 6 of 9
AS7C32096A
®
Package dimensions
c
44434241403938 37 36 35 34333231 30 29 28 27262524 23
E1 E
44-pin TSOP 2
1 2 3 4 5 6 7 8 9 10 111213 14 15 16 17 1819 20 21 22
d
A2
A
A1
2/24/05, v. 1.0
b
L
0–5°
e
Alliance Semiconductor
A
A1
A2
b
c
d
E1
E
e
L
44-pin TSOP 2
Min(mm) Max(mm)
1.2
0.05
0.15
0.95
1.05
0.30
0.45
0.21
0.12
18.31
18.52
10.06
10.26
11.68
11.94
0.80 (typical)
0.40
0.60
P. 7 of 9
AS7C32096A
®
Ordering codes
Package
Temperature
Commercial
TSOP 2
Industrial
10 ns
AS7C32096A-10TC
AS7C32096A-10TI
12 ns
AS7C32096A-12TC
AS7C32096A-12TI
15 ns
AS7C32096A-15TC
AS7C32096A-15TI
20 ns
AS7C32096A-20TC
AS7C32096A-20TI
Note: Add suffix ‘N’ to the above part number for Lead Free Parts. (Ex: AS7C32096A - 10TIN)
Part numbering system
AS7C
X
2096A
–XX
Voltage:
SRAM
Device
Access time
prefix 3 - 3.3V CMOS number
2/24/05, v. 1.0
T
Package:
T: TSOP 2
Alliance Semiconductor
X
X
Temperature ranges:
C: Commercial, 0°C to 70°C N=Lead Free Parts
I: Industrial, –40°C to 85°C
P. 8 of 9
AS7C32096A
®
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
Copyright © Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: AS7C32096A
Document Version: v. 1.0
www.alsc.com
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changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
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