ALSC AS7C33512PFS18A-166TQI 3.3v 512k x 18 pipeline burst synchronous sram Datasheet

November 2004
AS7C33512PFS18A
®
3.3V 512K × 18 pipeline burst synchronous SRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Organization: 524,288 words × 18 bits
Fast clock speeds to 166 MHz
Fast clock to data access: 3.5/4.0 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous register-to-register operation
Single-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate VDDQ
30 mW typical standby power in power down mode
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CS
CLR
19
A[18:0]
Burst logic
Q
D
CS Address
register
19
512K × 18
Memory
array
17 19
CLK
18
18
GWE
BWb
D DQb
BWE
CLK
D DQa Q
Q
Byte Write
registers
BWa
2
Byte Write
registers
CLK
CE0
CE1
CE2
D
Enable
register
OE
Q
CE
CLK
ZZ
Power
down
Input
registers
Output
registers
CLK
CLK
D Enable Q
delay
register
CLK
18
OE
DQ[a,b]
Selection guide
–166
–133
Units
6
7.5
ns
Maximum clock frequency
166
133
MHz
Maximum clock access time
3.5
4
ns
Maximum operating current
475
425
mA
Maximum standby current
130
100
mA
Maximum CMOS standby current (DC)
30
30
mA
Minimum cycle time
11/30/04; v.2.2
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C33512PFS18A
®
8 Mb Synchronous SRAM products list1,2
Org
512KX18
Part Number
AS7C33512PFS18A
Mode
PL-SCD
Speed
166/133 MHz
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
AS7C33256PFS32A
AS7C33256PFS36A
AS7C33512PFD18A
AS7C33256PFD32A
AS7C33256PFD36A
AS7C33512FT18A
AS7C33256FT32A
AS7C33256FT36A
AS7C33512NTD18A
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
FT
FT
NTD-PL
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
166/133 MHz
256KX32
256KX36
512KX18
256KX32
256KX36
AS7C33256NTD32A
AS7C33256NTD36A
AS7C33512NTF18A
AS7C33256NTF32A
AS7C33256NTF36A
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
NTD1-PL
NTD-FT
:
:
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
Pipelined Burst Synchronous SRAM with NTDTM
Flow-through Burst Synchronous SRAM with NTDTM
1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners.
11/30/04; v.2.2
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AS7C33512PFS18A
®
TQFP 14 × 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSSQ
NC
DQpa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
NC
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
NC
NC
VSSQ
VDDQ
NC
NC
NC
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
A
A
A
A
A
A
A
A
VDDQ
VSSQ
NC
NC
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
NC
VDD
NC
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQpb
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
Pin arrangement
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AS7C33512PFS18A
®
Functional description
The AS7C33512PFS18A is a high performance CMOS 8-Mbit Synchronous Static Random Access Memory (SRAM) device organized as
524,288 words × 18 bits and incorporate a pipeline for highest frequency on any given technology.
Timing for this device is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP,
and PowerPC™1-based systems in computing, datacom, instrumentation, and telecommunications systems.
Fast cycle times of 6/7.5 ns with clock access times (tCD) of 3.5/4.0 ns enable 166 and 133 MHz bus frequencies. Three chip enable inputs
permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor
address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and
driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on
all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address
strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium®
count sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented
internally to the next burst address if BWn and ADV are sampled LOW. This device operates in single-cycle deselect feature during
read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are
as follows:
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
• Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C33512PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are
available in a 100-pin 14×20 mm TQFP packaging.
.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
Test conditions
Max
Unit
CIN*
CI/O*
VIN = 0V
5
pF
VIN = VOUT = 0V
7
pF
*
Guaranteed not tested
TQFP thermal resistance
Description
Thermal resistance
(junction to ambient)1
Thermal resistance
(junction to top of case)1
Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
Symbol
Typical
Units
1–layer
θJA
40
°C/W
4–layer
θJA
22
°C/W
θJC
8
°C/W
1 This parameter is sampled.
1. PowerPC™ is a trademark International Business Machines Corporation
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AS7C33512PFS18A
®
Signal descriptions
Signal
I/O
Properties
Description
CLK
I
CLOCK
A,A0,A1
I
SYNC
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
DQ[a,b]
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0
I
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
CE1, CE2
I
SYNC
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
ADSP
I
SYNC
Address strobe (processor). Asserted LOW to load a new address or to enter standby mode.
ADSC
I
SYNC
Address strobe (controller). Asserted LOW to load a new address or to enter standby mode.
ADV
I
SYNC
Burst advance. Asserted LOW to continue burst read/write.
GWE
I
SYNC
Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE and BW[a,b]
control write enable.
BWE
I
SYNC
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs.
BW[a,b]
I
SYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a,b] are inactive, the cycle is a read cycle.
OE
I
ASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
LBO
I
STATIC
Selects Burst mode. When tied to VDD or left floating, device follows Interleaved Burst
order. When driven Low, device follows linear Burst order. This signal is internally pulled
High.
ZZ
I
ASYNC
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC
-
-
Clock. All inputs except OE, ZZ, LBO are synchronous to this clock.
No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
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AS7C33512PFS18A
®
Write enable truth table (per byte)
Function
Write All Bytes
Write Byte a
Write Byte b
Read
GWE
BWE
BWa
BWb
L
H
H
H
H
H
X
L
L
L
H
L
X
L
L
H
X
H
X
L
H
L
X
H
Key: X = don’t care, L = low, H = high, n = a, b; BWE, BWn = internal write signal.
Asynchronous Truth Table
Operation
Snooze mode
Read
Write
Deselected
ZZ
H
L
L
L
L
OE
X
L
H
X
X
I/O Status
High-Z
Dout
High-Z
Din, High-Z
High-Z
Burst sequence table
Interleaved burst address (LBO = 1)
A1 A0
A1 A0
A1 A0
Starting Address
First Increment
Second Increment
Third Increment
11/30/04; v.2.2
00
01
10
11
01
00
11
10
10
11
00
01
Linear burst address (LBO = 0)
A1 A0
A1 A0
A1 A0
A1 A0
11
10
01
00
Starting Address
First Increment
Second Increment
Third Increment
Alliance Semiconductor
00
01
10
11
01
10
11
10
10
11
00
01
A1 A0
11
00
01
10
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AS7C33512PFS18A
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Synchronous truth table[4]
CE01
CE1
CE2
ADSP
ADSC
H
L
L
L
L
L
L
L
L
X
X
X
X
H
H
H
H
L
X
H
X
H
X
L
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
H
H
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
L
H
L
H
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
L
X
L
X
L
X
X
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
ADV WRITE[2]
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
X
L
L
H
H
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
OE
Address accessed
CLK
Operation
DQ
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
NA
NA
NA
NA
NA
External
External
External
External
Next
Next
Current
Current
Next
Next
Current
Current
External
Next
Next
Current
Current
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Deselect
Deselect
Deselect
Deselect
Deselect
Begin read
Begin read
Begin read
Begin read
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
D3
D
D
D
D
1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa or BWb) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE,
GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time
4 ZZ pin is always Low.
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AS7C33512PFS18A
®
Absolute maximum ratings1
Parameter
Symbol
Min
Max
Unit
VDD, VDDQ
–0.5
+4.6
V
Input voltage relative to GND (input pins)
VIN
–0.5
VDD + 0.5
V
Input voltage relative to GND (I/O pins)
VIN
–0.5
VDDQ + 0.5
V
Power dissipation
PD
–
1.8
W
DC output current
IOUT
–
50
mA
Storage temperature (plastic)
Tstg
–65
+150
°C
Temperature under bias
Tbias
–65
+135
°C
Power supply voltage relative to GND
1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
VDDQ
Vss
Min
3.135
3.135
0
Nominal
3.3
3.3
0
Max
3.465
3.465
0
Unit
V
V
V
Min
3.135
2.375
0
Nominal
3.3
2.5
0
Max
3.465
2.625
0
Unit
V
V
V
Recommended operating conditions at 2.5V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
11/30/04; v.2.2
Symbol
VDD
VDDQ
Vss
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AS7C33512PFS18A
®
DC electrical characteristics for 3.3V I/O operation
Parameter
Input leakage current1
Output leakage current
Sym
|ILI|
|ILO|
Input high (logic 1) voltage
VIH
Input low (logic 0) voltage
VIL
Output high voltage
Output low voltage
VOH
VOL
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Address and control pins
I/O pins
IOH = –4 mA, VDDQ = 3.135V
IOL = 8 mA, VDDQ = 3.465V
Min
-2
-2
2*
2*
-0.3**
-0.5**
2.4
–
Max
2
2
VDD+0.3
VDDQ+0.3
0.8
0.8
–
0.4
Unit
µA
µA
V
V
V
V
1 LBO and ZZ pins and the have an internal pull-up or pull-down, and input leakage = ±10 µA.
DC electrical characteristics for 2.5V I/O operation
Parameter
Input leakage current
Output leakage current
Sym
|ILI|
|ILO|
Input high (logic 1) voltage
VIH
Input low (logic 0) voltage
VIL
Output high voltage
Output low voltage
VOH
VOL
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Address and control pins
I/O pins
IOH = –4 mA, VDDQ = 2.375V
IOL = 8 mA, VDDQ = 2.625V
*V max < VDD +1.5V for pulse width less than 0.2
IH
**V min = -1.5 for pulse width less than 0.2 X t
IL
CYC
Min
-2
-2
1.7*
1.7*
-0.3**
-0.3**
1.7
–
Max
2
2
VDD+0.3
VDDQ+0.3
0.7
0.7
–
0.7
Unit
µA
µA
V
V
V
V
V
V
X tCYC
IDD operating conditions and maximum limits
Parameter
Operating power supply
current1
Sym
ICC
ISB
Standby power supply
current
ISB1
ISB2
Conditions
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax,
IOUT = 0 mA, ZZ < VIL
All VIN ≤ 0.2V or > VDD – 0.2V, Deselected,
f = fMax, ZZ < VIL
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
Deselected, f = fMax, ZZ ≥ VDD – 0.2V,
all VIN ≤ VIL or ≥ VIH
-166
-133
Unit
475
425
mA
130
100
30
30
30
30
mA
1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
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AS7C33512PFS18A
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Timing characteristics for 3.3 V I/O operation
–166
Parameter
–133
Notes1
Symbol
Min
Max
Min
Max
Unit
Clock frequency
fMax
–
166
–
133
MHz
Cycle time
tCYC
6
–
7.5
–
ns
Clock access time
tCD
-
3.5
-
4.0
ns
Output enable low to data valid
tOE
–
3.5
–
4.0
ns
Clock high to output low Z
tLZC
0
–
0
–
ns
2,3,4
Data output invalid from clock high
tOH
1.5
–
1.5
–
ns
2
Output enable low to output low Z
tLZOE
0
–
0
–
ns
2,3,4
Output enable high to output high Z
tHZOE
–
3.5
–
4.0
ns
2,3,4
Clock high to output high Z
tHZC
–
3.5
–
4.0
ns
2,3,4
tOHOE
0
–
0
–
ns
Clock high pulse width
tCH
2.4
–
2.5
–
ns
5
Clock low pulse width
tCL
2.3
–
2.5
–
ns
5
Address setup to clock high
tAS
1.5
–
1.5
–
ns
6
Data setup to clock high
tDS
1.5
–
1.5
–
ns
6
Write setup to clock high
tWS
1.5
–
1.5
–
ns
6,7
Chip select setup to clock high
tCSS
1.5
–
1.5
–
ns
6,8
Address hold from clock high
tAH
0.5
–
0.5
–
ns
6
Data hold from clock high
tDH
0.5
–
0.5
–
ns
6
Write hold from clock high
tWH
0.5
–
0.5
–
ns
6,7
Chip select hold from clock high
tCSH
0.5
–
0.5
–
ns
6,8
ADV setup to clock high
tADVS
1.5
–
1.5
–
ns
6
ADSP setup to clock high
tADSPS
1.5
–
1.5
–
ns
6
ADSC setup to clock high
tADSCS
1.5
–
1.5
–
ns
6
ADV hold from clock high
tADVH
0.5
–
0.5
–
ns
6
ADSP hold from clock high
tADSPH
0.5
–
0.5
–
ns
6
ADSC hold from clock high
tADSCH
0.5
–
0.5
–
ns
6
Output enable high to invalid output
1 See “Notes” on page 17
11/30/04; v.2.2
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Timing characteristics for 2.5V I/O operation
–166
Parameter
–133
Notes1
Symbol
Min
Max
Min
Max
Unit
Clock frequency
fMax
–
166
–
133
MHz
Cycle time
tCYC
6
–
7.5
–
ns
Clock access time
tCD
-
4.0
-
4.5
ns
Output enable LOW to data valid
tOE
–
3.5
–
4.0
ns
Clock HIGH to output Low Z
tLZC
0
–
0
–
ns
2,3,4
Data output invalid from clock HIGH
tOH
1.5
–
1.5
–
ns
2
Output enable LOW to output Low Z
tLZOE
0
–
0
–
ns
2,3,4
Output enable HIGH to output High Z
tHZOE
–
3.5
–
4.0
ns
2,3,4
Clock HIGH to output High Z
tHZC
–
3.5
–
4.0
ns
2,3,4
tOHOE
0
–
0
–
ns
Clock
HIGH pulse width
.
tCH
2.4
–
2.5
–
ns
5
.
Clock
LOW pulse width
tCL
2.3
–
2.5
–
ns
5
Address setup to clock HIGH
tAS
1.7
–
1.7
–
ns
6
Data setup to clock HIGH
tDS
1.7
–
1.7
–
ns
6
Write setup to clock HIGH
tWS
1.7
–
1.7
–
ns
6,7
Chip select setup to clock HIGH
tCSS
1.7
–
1.7
–
ns
6,8
Address hold from clock HIGH
tAH
0.7
–
0.7
–
ns
6
Data hold from clock HIGH
tDH
0.7
–
0.7
–
ns
6
Write hold from clock HIGH
tWH
0.7
–
0.7
–
ns
6,7
Chip select hold from clock HIGH
tCSH
0.7
–
0.7
–
ns
6,8
ADV setup to clock HIGH
tADVS
1.7
–
1.7
–
ns
6
ADSP setup to clock HIGH
tADSPS
1.7
–
1.7
–
ns
6
ADSC setup to clock HIGH
tADSCS
1.7
–
1.7
–
ns
6
ADV hold from clock HIGH
tADVH
0.7
–
0.7
–
ns
6
ADSP hold from clock HIGH
tADSPH
0.7
–
0.7
–
ns
6
ADSC hold from clock HIGH
tADSCH
0.7
–
0.7
–
ns
6
Output enable HIGH to invalid output
1 See “Notes on page 17.
Snooze Mode Electrical Characteristics
Description
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
11/30/04; v.2.2
Conditions
Symbol
ZZ > VIH
ISB2
tPDS
tPUS
tZZI
tRZZI
Alliance Semiconductor
Min
Max
Units
30
mA
cycle
cycle
cycle
2
2
2
0
11 of 20
AS7C33512PFS18A
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Key to switching waveforms
Rising input
Falling input
don’t care
Undefined
Timing waveform of read cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
LOAD NEW ADDRESS
tAH
tAS
A1
Address
A2
tWS
A3
tWH
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
ADV inserts wait states
OE
tOE
tHZOE
tLZOE
Dout
Q(A1)
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
tCD
tHZC
tOH
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Burst
Burst
Read
Suspend
Burst
Burst
Burst
Burst
Read
Read
Q(A3)
Read
Read
Read
Read
Read
Q(A 2Ý01) Q(A 2Ý10) Q(A 2Ý10) Q(A 2Ý11)
Q(A 3Ý01) Q(A 3Ý10) Q(A 3Ý11)
DSEL
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
11/30/04; v.2.2
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AS7C33512PFS18A
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Timing waveform of write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
ADSC LOADS NEW ADDRESS
tAS
tAH
A1
Address
A3
A2
tWS
tWH
tADVS
tADVH
tDS
tDH
BWE
BW[a:b]
tCSS
tCSH
CE0, CE2
CE1
ADV SUSPENDS BURST
ADV
OE
Din
D(A1)
Read
Q(A1)
Suspend
Write
D(A1)
D(A2)
Read
Q(A2)
D(A2Ý01)
Suspend
Write
D(A 2)
D(A2Ý01)
D(A2Ý10)
D(A2Ý11)
D(A3)
ADV
ADV
ADV
Suspend
Burst
Burst
Burst
Write
Write
Write
D(A 2Ý01) Write
D(A 2Ý01)
D(A 2Ý10) D(A 2Ý11)
D(A3Ý01)
Write
D(A 3)
D(A3Ý10)
Burst
Write
D(A 3Ý01)
ADV
Burst
Write
D(A 3Ý10)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
11/30/04; v.2.2
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AS7C33512PFS18A
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Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
tCYC
tCL
tCH
CLK
tADSPH
tADSPS
ADSP
tAH
tAS
A2
A1
Address
A3
tWH
tWS
GWE
CE0, CE2
CE1
tADVH
tADVS
ADV
OE
tDS tDH
Din
D(A2)
tOE
tCD
tLZC
Dout
DSEL
Read
Q(A1)
tHZOE
Q(A1)
Suspend
Read
Q(A1)
tOH
tLZOE
Q(A3)
Read
Q(A2)
Suspend
Write
D(A 2)
Read
Q(A3)
ADV
Burst
Read
Q(A 3Ý01)
Q(A3Ý01)
ADV
Burst
Read
Q(A 3Ý10)
Q(A3Ý10)
Q(A3Ý11)
ADV
Burst
Read
Q(A 3Ý11)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
11/30/04; v.2.2
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AS7C33512PFS18A
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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
tCYC
tCL
tCH
CLK
tADSCS
tADSCH
ADSC
tAS
A1
ADDRESS
A3
A2
A5
A4
A7
A6
tWS
tAH
A8
A9
tWH
GWE
tCSS
tCSH
CE0,CE2
CE1
ADV
OE
tOE
Q(A1)
Dout
tLZOE
tHZOE
tLZOE
Q(A2)
Q(A3)
Q(A8)
Q(A4)
D(A5)
READ
Q(A1)
11/30/04; v.2.2
READ
Q(A2)
READ
Q(A3)
READ
Q(A4)
Q(A9)
tDH
tDS
Din
tOH
D(A6)
D(A7)
WRITE WRITE WRITE
D(A6) D(A7)
D(A5)
Alliance Semiconductor
READ
Q(A8)
READ
Q(A9)
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AS7C33512PFS18A
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Timing waveform of power down cycle
tCH
tCYC
tCL
CLK
tADSPS
tADSPS
ADSP
ADSC
A2
A1
ADDRESS
tWH
tWS
GWE
tCSS
tCSH
CE0,CE2
CE1
ADV
OE
tOE
Din
tLZOE
tHZOE
D(A2)
D(A2(Ý01))
tHZC
Dout
Q(A1)
tPUS
tPDS
ZZ Recovery Cycle
ZZ
Normal Operation Mode
ZZ Setup Cycle
tZZI
tRZZI
Isupply
ISB2
READ SUSPEND
Q(A1) READ
Q(A1)
11/30/04; v.2.2
Sleep
State
Alliance Semiconductor
READ SUSPEND CONQ(A2) WRITE TINUE
D(A2) WRITE
D(A2 Ý01)
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AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
• Input and output timing reference levels: 1.5V.
+3.0V
90%
10%
GND
90%
10%
Figure A: Input waveform
DOUT
Z0 = 50Ω
50Ω
VL = 1.5V
for 3.3V I/O;
30 pF* = V
DDQ/2
for 2.5V I/O
Figure B: Output load (A)
DOUT
353Ω / 1538Ω
319Ω / 1667Ω
5 pF*
GND *including scope
and jig capacitance
Figure C: Output load (B)
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage.
5) tCH measured HIGH above VIH and tCL measured as LOW below VIL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to GWE, BWE, BW[a,b].
8) Chip select refers to CE0, CE1, CE2.
11/30/04; v.2.2
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AS7C33512PFS18A
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Package Dimensions
100-pin quad flat pack (TQFP)
Hd
TQFP
Min
Max
A1
A2
b
c
D
E
e
Hd
He
L
L1
α
0.05
0.15
1.35
1.45
0.22
0.38
0.09
0.20
13.90
14.10
19.90
20.10
D
b
α
e
He E
0.65 nominal
15.90
16.10
21.90
22.10
0.45
0.75
c
L1
L
A1 A2
1.00 nominal
0°
7°
Dimensions in millimeters
11/30/04; v.2.2
Alliance Semiconductor
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AS7C33512PFS18A
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Ordering information
Package
–166 MHz
–133 MHz
TQFP x18
AS7C33512PFS18A-166TQC
AS7C33512PFS18A-133TQC
TQFP x18
AS7C33512PFS18A-166TQI
AS7C33512PFS18A-133TQI
Note: Add suffix ‘N’ with the above part number for Lead Free Parts (Ex. AS7C33512PFS18A-166TQCN)
Part numbering guide
AS7C
33
512
PF
S
18
A
–XXX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
11
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33=3.3V
3.Organization: 512=512K
4.Pipelined mode
5.Deselect: S=Single cycle deselect
6.Organization: 18=x18
7.Production version: A=first production version
8. Clock speed (MHz)
9. Package type: TQ=TQFP
10. Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C)
11. N = Lead free part
11/30/04; v.2.2
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AS7C33512PFS18A
®
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C33512PFS18A
Document Version: v.2.2
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