AUSTIN AS8E32K32

AUSTIN SEMICONDUCTOR, INC.
AS8E32K32
32K x 32 EEPROM
EEPROM
AVAILABLE AS MILITARY
SPECIFICATIONS
•
•
PIN ASSIGNMENT (Top View)
66 Lead PGA
SMD 5962-94614: AS8E32K32
MIL-STD-883
FEATURES
•
•
•
•
•
•
Access times of 90, 120, 150 ns
Built in decoupling caps for low noise
operation
Organized as 32K x 32; User configurable
as 64K x 16 or 128K x 8
Operation with single 5 volt supply
Low power CMOS
TTL Compatible Inputs and Outputs
OPTIONS
•
•
MARKINGS
Timing
90 ns
120 ns
150 ns
68 Lead CQFP
-9
-12
-15
Package
Ceramic Quad Flatpack
Pin Grid Array
Q
P
No. 705
No. 805
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8E32K32 is a 1 Megabit
EEPROM Modules organized as 32K x 32 bit. User configurable to
64K x16 or 128Kx 8. The module achieves high speed access, low
power consumption and high reliability by employing advanced
CMOS memory technology.
The military grade product is manufactured in compliance to
the SMD and MIL-STD 883, making the AS8E32K32 ideally suited
for military or space applications.
The module is offered in a 1.090 sq inch ceramic pin grid array
substrate. This package design provides the optimum space saving
solution for boards that accept through hole packaging.
The module is also offered as a 68 lead 0.990 sq. inch ceramic
quad flatpack. It has a max. height of 0.200 inch. This package
design is targeted for those applications which require low profile
SMT Packaging.
CE4
M3
WE4
32K x 8
CE3
WE3
M2
I/O 24 - I/O 31
32K x 8
CE2
WE2
DEVICE IDENTIFICATION
M1
I/O 16 - I/O 23
32K x 8
An extra 64 bytes of EEPROM memory is available on each die
for user identification. By raising A9 to 12 V +/- 0.5V and using
address locations 7FC0H to 7FFFH the bytes may be written to
or read from in the same manner as the regular memory array.
CE1
WE1
OE
A0 - 14
M0
I/O 8 - I/O 23
32K x 8
I/O 0 - I/O 7
AS8E32K32
REV. 1.5 9/99
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Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS8E32K32
32K x 32 EEPROM
DEVICE OPERATION
The 32Kx 32 EEPROM memory soultion is an electricaly erasable and programmable memory module that is accessed like a
Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte-page register to
allow writing of up to 64 bytes of data simultaneously. During a write cycle, the address and 1 to 64 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically
write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end
of a write cycle has been detected a new access for a read or write can begin.
READ
data will be read. Reading the toggle bit may begin at any time
during the write cycle.
The memory module is accessed like a Static RAM. When
CE\ and OE\ are low and WE\ is High, the data stored at the
memory location determined by the address pins is asserted on
the outputs. The module can be read as a 32 bit, 16 bit or 8 bit
device. The outputs are put in the high impedance state when
either CE\ or OE\ is high. This dual-line control gives designers
flexibility in preventing bus contention in their system.
DATA PROTECTION
If precautions are not taken, inadvertent writes may occur
during transitions of the host power supply. The E2 module has
incorporated both hardware and software features that will
protect the memory against inadvertent writes.
BYTE WRITE
A low pulse on the WE\ or CE\ input with CE\ or WE\ low
(respectively) and OE\ high initiates a write cycle. The address is
latched on the falling edge of CE\ or WE\, whichever occurs last.
The data is latched by the first rising edge of CE\ or WE\. Once a
BWDW (byte, word or double word) write has been started it
HARDWARE PROTECTION
Hardware features protect against inadvertent writes to the
module in the following ways: (a) VCC sense - if VCC is below
3.8 V (typical) the write function is inhibited; (b) VCC power-on
delay - once VCC has reached 3.8 V the device will automatically
time out 5 ms (typical) before allowing a write; (c) write inhibit holding any one of OE\ low, CE\ high or WE\ high inhibits write
cycles; (d) noise filter - pulses of less than 15 ns (typical) on the
WE\ or CE\ inputs will not initiate a write cycle.
will automatically time itself to completion.
PAGE WRITE
The page write operation of the 32K x 32 EEPROM allows
1 to 64 BWDWs of data to be written into the device during a
single internal programming period. Each new BWDW must be
written within 150-µs (tBLC) of the previous BWDW. If the
tBLC limit is exceeded the device will cease accepting data and
commence the internal programming operation. For each WE
high to low transition during the page write operation, A6-A14
must be the same.
The A0-A5 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any order
and may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary
cycling of other bytes within the page does not occur.
SOFTWARE DATA PROTECTION
A software controlled data protection feature has been
implemented on the memory module. When enabled, the
software data protection (SDP), will prevent inadvertent writes.
The SDP feature may be enabled or disabled by the user and is
shipped with SDP disabled.
SDP is enabled by the host system issuing a series of thre e
write commands; three specific bytes of data are written to three
specific addresses (refer to Software Data Protection Algorithm).
After writing the three byte command sequence and after tWC
the entire module will be protected from inadvertent write
operations. It should be noted, that once protected the host may
still perform a byte of page write to the module. This is done by
preceding the data to be written by the same three byte command
sequence used to enable SDP.
Once set, SDP will remain active unless the disable
command sequence is issued. Power transitions do not disable
SDP and SDP will protect the 32K x 32 EEPROM module during
power-up and Power-down conditions. All command sequences
must conform to the page write timing specifications. The data
in the enable and disable command sequences is not written to the
device and the memory addresses used in the sequence may be
written with data in either a byte of page write operation.
After setting SDP, any attempt to write to the device
without the three byte command sequence will start the internal
write timers. No data will be written to the device; however, for
the duration of tWC, read operations will effectively be polling
operations.
DATA POLLING
this memory module features DATA Polling to indicate the
end of a write cycle. During a byte or page write cycle an
attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write
cycle has been completed, true data is valid on all outputs, and
the next write cycle may begin. DATA Polling may begin at
anytime during the write cycle.
TOGGLE BIT
In addition to DATA Polling the module provides another
method for determining the end of a write cycle. During the write
operation, successive attempts to read data from the device will
result in I/O6 of the accessed die toggling between one and zero.
Once the write has completed, I/O6 will stop toggling and valid
AS8E32K32
REV. 1.5 9/99
2
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss
Vcc ..........................................................................-.6V to +6.5V
Storage Temperature ........................................-65°C to +150°C
Short Circuit Output Current (per I/O)….........................20mA
Voltage on any Pin Relative to Vss..............-.5V to Vcc+1 mA
Junction Temperature**..................................................+150°C
Thermal Resistance junction to case (θJC):
Package Type Q...........................................11.3° C/W
Package Type P..............................................2.8° C/W
AS8E32K32
32K x 32 EEPROM
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
** Maximum junction temperature depends upon package
type, cycle time, loading, ambient temperature and airflow,
and humidity.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55°C ≤ T
A
≤ 125°C; Vcc = 5V ±10%)
DESCRIPTION
Input High (Logic 1) Voltage
CONDITIONS
SYMBOL
VIH
VIL
Input Low (Logic 0) Voltage
Input Leakage Current
Input Leakage Current
0V ≤ VIN ≤ VCC
ILI
WE\, CE\
Output Leakage Current
MIN
2
MAX
VCC+.3
UNITS
V
NOTES
1
-0.5
0.8
V
1, 2
-10
10
µA
-10
10
µA
10
µA
ILO
-10
Output High Voltage
Output(s) disabled
0V ≤ VOUT ≤ VCC
IOH = -.4 mA
VOH
2.4
Output Low Voltage
IOL = 2.1mA
VOL
VCC
Supply Voltage
4.5
V
1
0.45
V
1
5.5
V
1
DESCRIPTION
Power Supply
CONDITIONS
CE\ ≤ VIL; VCC = MAX
SYMBOL
-90
MAX
-120
Current: Operating
f = 5 MHz
OUTPUTS OPEN
CE\ ≥ VIH; All Other Inputs
ICC
340
340
340
mA
≤VIL or ≥ VIH; VCC = MAX
f = 5 MHz
CE\ ≥ VCC -0.2V; VCC = MAX
ISBT1
12
12
12
mA
VIL ≤ VSS +0.2V or
ISBC1
1.3
1.3
1.3
mA
Power Supply
Current: Standby
-150
UNITS NOTES
VIH ≥ VCC -0.2V; f = 0 Hz
AS8E32K32
REV. 1.5 9/99
3
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
C APAC ITANC E TABLE
AS8E32K32
32K x 32 EEPROM
(1)
VIN = 0V, f = 1MHz, TA =25ºC
S y m b o l P a ra m e te r
Ma x im u m
U n its
N o te s
C ADD
A0-A14 C apacti ance
24
pF
4, 14
C OE
OE\ C apacti ance
24
pF
4, 14
C WE, C CE WE\ and C E\ C apacti ance
6
pF
4, 14
12
pF
4, 14
I/O 0 - I/O 31 C apacti ance
C IO
1. This parameter is guaranteed but not tesed
TRUTH TABLE
MODE
Read
CE\
VIL
OE\
VIL
WE\
VIH
I/O
DOUT
Write (2)
VIL
VIH
VIL
DIN
Standby/Write
VIH
X (1)
High Z
Write Inhibit
X
Write Inhibit
X
X
VIL
X
VIH
Output Disable
X
VIH
X
X
High Z
AC TEST CONDITIONS
Test Specifications
IOL
Input pulse levels....................................VSS to 3V
Input rise and fall times.......................................5ns
Input timing reference levels.............................1.5V
Output reference levels.....................................1.5V
Output load................................See Figures 1 and 2
Current Source
Device
Under
Test
-
+
Vz = 1.5V
(Bipolar
Supply)
+
Ceff = 50pf
Current Source
IOH
Notes:
Vz is programable from -2V to + 7V.
IOL and IOH programmable from 0 to 16 mA.
Vz is typically the midpoint of VOH and VOL.
IOL and IOH are adjusted to simulate a typical resistive load
circuit.
AS8E32K32
REV. 1.5 9/99
4
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS8E32K32
32K x 32 EEPROM
AC READ CHARACTERISTICS
(-55°C ≤ T A ≤ 125°C; VCC = 5V ±10%)
-90
-120
-150
Symbol
Parameter
tRC
Read Cycle Time
tACC
Address to Output Delay
90
120
150
ns
tACS
Min
Max
90
Min
Max
120
Min
Max
150
Units
ns
CE\ Access Time
90
120
150
ns
tCE
(1)
CE\ to Output Delay
90
120
150
ns
tOE
(2)
OE\ to Output Delay
50
60
70
ns
tDF
(3,4)
CE\ or OE\ to Output High-Z
Output Hold from OE\, CE\ or
Address, whichever occurs first
50
60
70
ns
tOH
0
0
0
ns
A.C. Read Waveforms(1,2,3)
tRC
ADDRESS
ADDRESS VALID
tCE
tDF
CE/
tOE
tOH
OE\
tACC
DQ
OUTPUT VALID
Notes:
1. CE\ may be delayed to tACC-tCE after the address transition without inpact on tACC.
2. OE\ may be delayed to tCE-tOE after the falling edge of CE\ without inpact on tCE or by tACC-tOE after an address change
without inpact on tACC.
3. tDF is specified from OE\ or CE\ whichever occurs first (CL = 5pF).
AS8E32K32
REV. 1.5 9/99
5
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS8E32K32
32K x 32 EEPROM
AC WRITE CHARACTERISTICS
(-55°C ≤ T A ≤ 125°C; VCC = 5V ±10%)
-90
Min
-120
Max
Min
-150
Symbol
Parameter
twc
Write Cycle Time
tAS
Address, OE\ Set-Up time
0
0
0
tAH
Address, Hold time
50
50
50
ns
tCS
Chip Select Set-up Time
0
0
0
ns
tCH
Chip Select Hold Time
0
0
0
ns
tWP
Write Pulse Width (WE\ or CE\)
100
100
100
ns
tDS
Data Set-up Time
50
50
50
ns
tDH
Data Hold Time
0
0
0
ns
tOEH
OE\ Hold time
0
0
0
ns
tOES
OE\ Set-up time
0
0
0
ns
tWPH
Write Pulse Width High
50
50
10
Max
Min
10
50
Max
Unit
10
ms
ns
ns
WRITE CYCLE NO 1.
(Chip Enable Controlled)
tOES
tOEH
OE\
tWC
tAH
tAS
ADDRESS
ADDRESS VALID
tCS
tCH
WE\
tWP
tWPH
CE\
tDS
tDH
DQ
AS8E32K32
REV. 1.5 9/99
DATA VALID
6
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS8E32K32
32K x 32 EEPROM
WRITE CYCLE NO 2.
(Write Enable Controlled)
tOES
tOEH
OE\
tAH
tAS
ADDRESS
tCS
tCH
CE\
tWP
tWPH
WE\
tDS
tDH
DQ
AS8E32K32
REV. 1.5 9/99
DATA VALID
7
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS8E32K32
32K x 32 EEPROM
PAGE MODE CHARACTERISTICS
(-55°C ≤ T A ≤ 125°C; VCC = 5V ±10%)
-90
Symbol Parameter
Min
-120
Max
Min
-150
Max
Min
Max
Unit
0
ms
twc
Write Cycle Time
tWP
Write Pulse Width (WE\ or CE\)
100
100
100
ns
tDS
Data Set-up Time
50
50
50
ns
tDH
Data Hold Time
0
tBLC
Byte Load Cycle Time
tWPH
Write Pulse Width High
0
0
0
150
50
0
150
150
50
50
ns
µs
ns
Page Mode Write Waveforms(1,2)
OE
CE\
tWP
tWPH
tBLC
WE\
tAH
tAS
A0 - A16
VA
VA
VA
VA
VA
VA
VA
tDH
tDS
DATA
Notes:
AS8E32K32
REV. 1.5 9/99
1.
2.
3.
4.
tWC
VD
VD
VD
VD
BYTE 0
BYTE 1
BYTE 2
BYTE 3
VD
VD
BYTE 126
VD
VD
BYTE127
A7 through A16 must specify the page address during each high to low transition of WE\ (or CE\).
OE\ must be high only when WE\ and CE\ are both low.
VD - Valid Data
VA - Valid Address
8
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
Software Data Protection Disable Algorithm(1)
Software Data Protection Enable Algorithm(1)
Load Data AA
to
Address 5555
Load Data AA
to
Address 5555
Load Data 55
to
Address 2AAA
Load Data A0
to
Address 5555
Load Data 55
to
Address 2AAA
Load Data 80
to
Address 5555
Writes Enabled(2)
Load Data XX
to
Any Address(4)
Load Last Byte
to
Last Address
AS8E32K32
32K x 32 EEPROM
Load Data AA
to
Address 5555
Load Data 20
to
Address 5555
Enter Data
Protect State
Exit Data Protect
State(3)
Load Data XX
to
Any Address(4)
Load Last Byte
to
Last Address
Notes:
1. Data Format: I/O 7 - I/O 0, I/O 15 - I/O 8, I/O 23 - I/O 16, and I/O 31 - I/O 24, (Hex)
2. Write Protect state will be active at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of period even if no other data is loaded.
4. 1 to 64 bytes of data are loaded.
5. A0-A12 of the selected I/O bytes must conform to the addressing sequence for the first three bytes as shown above.
6. After the command sequence has been issued and a page write operation follows, the page address inputs (A5-A14) of the selected I/O
bytes must be the same for each high to low transition of WE\ (or CE\).
7. OE Must be high only when WE\ and CE\ are both low.
AS8E32K32
REV. 1.5 9/99
9
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS8E32K32
32K x 32 EEPROM
Data Polling Characteristics(1)
Symbol
Parameter
Min
Max
Units
tDH
Data Hold Time
10
ns
tOEH
OE\ Hold Time
10
ns
(2)
tOE
OE\ to Output Delay
tWR
Write Recovery Time
100
ns
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See A.C. Read Characteristics.
Data Polling Waveforms
tOEH
WE\
CE\
tDH
OE\
tOE
tWR
I/O 7
A0 - A17
VA
VA
VA
VA
VA
VA
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE\ Hold Time
tOE
tOEPH
ICC
OE\ to Output Delay
Min
Max
10
ns
10
(2)
ns
100
OE\ High Pulse
Write Recovery Time
Units
ns
150
ns
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See A.C. Read Characteristics.
Toggle Bit Waveforms(1,2,3)
WE\
CE\
tOEH
OE\
tDH
tOE
HIGH Z
tWR
I/O 6
Notes:
AS8E32K32
REV. 1.5 9/99
1. Toggling either OE or CE or Both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
10
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS8E32K32
32K x 32 EEPROM
MECHANICAL DEFINITION
AS8E32K32
(ASI Case #705, Package Designator Q)
AS8E32K32
REV. 1.5 9/99
11
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN SEMICONDUCTOR, INC.
AS8E32K32
32K x 32 EEPROM
MECHANICAL DEFINITION
AS8E32K32
(ASI Case #805, Package Designator P)
AS8E32K32
REV. 1.5 9/99
12
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.