Austin AS8F128K32Q1-70/Q 128k x 32 flash flash memory array Datasheet

FLASH
AS8F128K32
Austin Semiconductor, Inc.
128K x 32 FLASH
PIN ASSIGNMENT
(Top View)
FLASH MEMORY ARRAY
68 Lead CQFP (Q & Q1)
•
•
NC
A0
A1
A2
A3
A4
A5
CS3\
GND
CS4\
WE1\
A6
A7
A8
A9
A10
Vcc
AVAILABLE AS MILITARY
SPECIFICATIONS
SMD 5962-94716
MIL-STD-883
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
FEATURES
Fast Access Times: 60, 70, 90, 120 and 150ns
Operation with single 5V (±10%)
Compatible with JEDEC EEPROM command set
Any Combination of Sectors can be Erased
Supports Full Chip Erase
Embedded Erase and Program Algorithms
TTL Compatible Inputs and CMOS Outputs
Hardware Data Protection
Data\ Polling and Toggle Bits
Low Power consumption
Individual Byte Read/ Write Control
10,000 Program/Erase Cycles
OPTIONS
•
•
controls the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program command
sequence. This invokes the Embedded Program algorithm—an internal
algorithm that automatically times the program pulse widths and
verifies proper cell margin.
Device erasure occurs by executing the erase command sequence.
This invokes the Embedded Erase algorithm—an internal algorithm
that automatically preprograms the array (if it is not already
programmed) before executing the erase operation. During erase, the
device automatically times the erase pulse widths and verifies proper
cell margin.
The host system can detect whether a program or erase operation
is complete by reading the I/O7 (Data\ Polling) and I/O6 (toggle)
status bits. After a program or erase cycle has been completed, the
device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased
and reprogrammed without affecting the data contents of other
sectors. The device is erased when shipped from the factory.
The hardware data protection measures include a low VCC
detector automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both
program and erase operations in any combination of the sectors of
memory, and is implemented using standard EPROM programmers.
The system can place the device into the standby mode. Power
consumption is greatly reduced in this mode.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The bytes are
programmed one byte at a time using the EPROM programming
mechanism of hot electron injection.
MARKINGS
Timing
60ns
70ns
90ns
120ns
150ns
Package
Ceramic Quad Flat pack
Ceramic Quad Flat pack
Vcc
A11
A12
A13
A14
A15
A16
CS1\
OE
CS2\
NC
WE2\
WE3\
WE4\
NC
NC
NC
•
•
•
•
•
•
•
•
•
•
•
•
-60
-70
-90
-120
-150
Q
Q1
No. 703
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8F128K32 is a 4 Megabit
CMOS FLASH Memory Module organized as 128K x 32 bits. The
AS8F128K32 achieves high speed access (60 to 150 ns), low power
consumption and high reliability by employing advanced CMOS
memory technology.
The device is designed to be programmed in-system with the
standard system 5.0V VCC supply. A 12.0V VPP is not required for
program or erase operation. The device can also be programmed or
erased in standard EPROM programmers. To eliminate bus
contention the device has seperate chip enbaled (CEx\), write enable
(WEx\) and output enable (OE) controls.
The device requires only a single 5.0 volt power supply for both
read and write functions. Internally generated and regulated voltages
are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC
single-power-supply Flash standard. Commands are written to the
command register using standard microprocessor write timings.
Register contents serve as input to an internal state machine that
AS8F128K32
Rev. 2.0 5/03
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FLASH
AS8F128K32
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
PIN
A0 - A16
I/O0 - I/O31
CEx\
OE\
WEx\
DESCRIPTION
Addresses
Input/Output
Chip Enable
Output Enable
Write Enable
VCC
5.0V Power Supply
Device Ground
No Connect
GND
NC
LOGIC SYMBOL
x = 1, 2, 3 or 4
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
FLASH
AS8F128K32
Austin Semiconductor, Inc.
DEVICE BUS OPERATIONS
for read access until the command register contents are altered.
See “Reading Array Data” for more information. Refer to
the AC Read Operations table for timing specifications and to
the Read Operations Timings diagram for the timing waveforms.
ICC1 in the DC Characteristics table represents the active
current specification for reading array data.
NOTE: All device/algorithm descriptions contained in this data
sheet reference each individual die.
This section describes the requirements and use of the
device bus operations, which are initiated through the internal
command register. The command register itself does not
occupy any addressable memory location. The register is
composed of latches that store the commands, along with the
address and data information needed to execute the command.
The contents of the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of the
device. The appropriate device bus operations table lists the
inputs and control levels required, and the resulting output.
The following subsections describe each of these operations
in further detail.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of memory),
the system must drive WEx\ and CEx\ to VIL, and OE\ to VIH.
An erase operation can erase one sector, multiple sectors,
or the entire device. The Sector Address Tables indicate the
address space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select a
sector. See the “Command Definitions” section for details on
erasing a sector or the entire chip.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O31–I/O0. Standard read
cycle timings apply in this mode. Refer to the “Autoselect Mode”
and “Autoselect Command Sequence” sections for more
information. ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The “AC
Characteristics” section contains timing specification tables
and timing diagrams for write operations.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CEx\ and OE\ pins to VIL. CEx\ is the power control and
selects the device. OE\ is the output control and gates array
data to the output pins. WEx\ should remain at VIH.
The internal state machine is set for reading array data
upon device power-up. This ensures that no spurious
alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce valid
data on the device data outputs. The device remains enabled
TABLE 1: Device Bus Operations1
CEx\
OE\
WEx\
ADRESSES
(A16:A0)
I/O0 - I/O31
Read
L
L
H
AIN
DOUT
Write
L
H
L
AIN
DIN
VCC ± 0.5V
X
X
X
High-Z
Output Disable
L
H
H
X
High-Z
Hardware Reset
X
X
X
X
High-Z
Temporary Sector Unprotect
X
X
X
AIN
DIN
OPERATION
Standby
LEGEND:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out
NOTES:
1. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection/
Unprotection” section.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
FLASH
AS8F128K32
Austin Semiconductor, Inc.
Program and Erase Operation Status
Autoselect Mode
During an erase or program operation, the system may check
the status of the operation by reading the status bits on I/O31–
I/O0. Standard read cycle timings and ICC read specifications
apply. Refer to “Write Operation Status” for more information,
and to each AC Characteristics section in the appropriate data
sheet for timing diagrams.
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O31–I/O0. This mode is primarily
intended for programming equipment to automatically match a
device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed
in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (11.5 V to 12.5 V) on address pin A9. Address pins
A6, A1, and A0 must be as shown in Autoselect Codes (High
Voltage Method) table. In addition, when verifying sector
protection, the sector address must appear on the appropriate
highest order address bits. Refer to the corresponding Sector
Address Tables. The Command Definitions table shows the
remaining address bits that are don’t care. When all necessary
bits have been set as required, the programming equipment
may then read the corresponding identifier code on I/O31–
I/O0.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command register, as
shown in the Command Definitions table. This method does
not require VID. See “Command Definitions” for details on
using the autoselect mode.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE\ input.
The device enters the CMOS standby mode when the CEx\
pin is held at VCC ± 0.5 V. (Note that this is a more restricted
voltage range than VIH.) The device enters the TTL standby
mode when CEx\ is held at VIH. The device requires the
standard access time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is completed.
ICC3 in the DC Characteristics tables represents the standby
current specification.
Output Disable Mode
When the OE\ input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
TABLE 2: Sector Addresses Table (Each Byte)
SECTOR
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
AS8F128K32
Rev. 2.0 5/03
A16
0
0
0
0
1
1
1
1
A15
0
0
1
1
0
0
1
1
A14
0
1
0
1
0
1
0
1
ADDRESS RANGE
00000h - 03FFFh
04000h - 07FFFh
08000h - 0BFFFh
0C000h - 0FFFFh
10000h - 13FFFh
14000h - 17FFFh
18000h - 1BFFFh
1C000h - 1FFFFh
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
FLASH
AS8F128K32
Austin Semiconductor, Inc.
Sector Protection/Unprotection
Low VCC Write Inhibit
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and erase
operations in previously protected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure requires a high
voltage (VID) on address pin A9 and the control pins.
The device is shipped with all sectors unprotected. It is
possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
When VCC is less than VLKO, the device does not accept
any write cycles. This protects data during VCC power-up and
power-down. The command register and all internal program/
erase circuits are disabled, and the device resets. Subsequent
writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent
unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE\, CEx\ or
WEx\ do not initiate a write cycle.
Hardware Data Protection
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table). In
addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up and power-down transitions, or from system
noise.
Logical Inhibit
Write cycles are inhibited by holding any one of OE\ = VIL,
CEx\ = VIH or WEx\ = VIH. To initiate a write cycle, CEx\ and
WEx\ must be a logical zero while OE\ is a logical one.
Power-Up Write Inhibit
If WEx\ = CEx\ = VIL and OE\ = VIH during power up, the device
does not accept commands on the rising edge of WEx\. The
internal state machine is automatical ly reset to reading array
data on power-up.
TABLE 3: Autoselect Codes (High Voltage Method)
CEx\
OE\
WEx\
A16
to
A14
Manufacturer ID: AMD
L
L
H
X
X
VID
X
L
X
L
L
I/O0 to I/O7
I/O8 to I/O15
I/O16 to I/O23
I/O24 to I/O31
01h
Device ID: AM29F010B
L
L
H
X
X
VID
X
L
X
L
H
20h
L
L
H
SA
X
VID
X
L
X
H
L
DESCRIPTION
A13
to
A10
A9
A8 to
A6
A7
A5
to
A2
A1
A0
01h (protected)
Sector Protection Verification
00h
(unprotected)
LEGEND:
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
FLASH
Austin Semiconductor, Inc.
AS8F128K32
COMMAND DEFINITIONS
Autoselect Command Sequence
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device to
reading array data.
All addresses are latched on the falling edge of WEx\ or
CEx\, whichever happens later. All data is latched on the rising
edge of WEx\ or CEx\, whichever happens first. Refer to the
appropriate timing diagrams in the “AC Characteristics”
section.
The autoselect command sequence allows the host
system to access the manufacturer and devices codes, and
determine whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing
two unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h or retrieves the
manufacturer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address (SA) and
the address 02h in returns 01h if that sector is protected, or 00h
if it is unprotected. Refer to the Sector Address tables for valid
sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
The device is also ready to read array data after completing an
Embedded Program or Embedded Erase algorithm.
The system must issue the reset command to re-enable the
device for reading array data if I/O5* goes high, or while in the
autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information. The
Read Operations table provides the read parameters, and Read
Operation Timings diagram shows the timing diagram.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The program
address and data are written next, which in turn initiate the
Embedded Program algorithm. The system is not required to
provide further controls or timings. The device automatically
provides internally generated program pulses and verify the
programmed cell margin. The Command Definitions take shows
the address and data requirements for the byte program
command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are no
longer latched. The system can determine the status of the
program operation by using I/O7or I/O6. See “Write Operation
Status” for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a “0”
back to a “1”. Attempting to do so may halt the operation and
set I/O5* to “1”, or cause the Data\ Polling algorithm to indicate
the operation was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.
Reset Command
Writing the reset command to the device resets the device
to reading array data. Address bits are don’t care for this
command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing begins.
This resets the device to reading array data. Once erasure
begins, however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data. Once
programming begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to return
to reading array data.
If I/O5* goes high during a program or erase operation,
writing the reset command returns the device to reading array
data.
*NOTE:
applies to every 8th byte (i.e. I/O5, I/O13, I/O21, I/O29)
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
FLASH
Austin Semiconductor, Inc.
AS8F128K32
additional sector erase commands can be assumed to be less
than 50 ms, the system need not monitor I/O3*. Any command
during the time-out period resets the device to reading array
data. The system must rewrite the command sequence and any
additional sector addresses and commands.
The system can monitor I/O3* to determine if the sector
erase timer has timed out. (See the “I/O3*: Sector Erase Timer”
section.) The time-out begins from the rising edge of the final
WE# pulse in the command sequence.
Once the sector erase operation has begun, all other
commands are ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7 or I/O6. Refer to “Write Operation
Status” for information on these status bits.
Figure 2 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations tables in the “AC
Characteristics” section for parameters, and to the Sector Erase
Operations Timing diagram for timing waveforms.
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which in
turn invokes the Embedded Erase algorithm. The device does
not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored.
The system can determine the status of the erase
operation by using I/O7 or I/O6. See “Write Operation Status”
for information on these status bits. When the Embedded Erase
algorithm is complete, the device returns to reading array data
and addresses are no longer latched.
Figure 2 illustrates the algorithm for the erase operation.
See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector Erase
Operation Timings for timing waveforms.
FIGURE 1: Program Operation
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the
sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not required
to provide any controls or timings during these operations.
After the command sequence is written, a sector erase timeout of 50 ms begins. During the time-out period, additional
sector addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any sequence,
and the number of sectors may be from one sector to all sectors.
The time between these additional cycles must be less than
50 ms, otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended that
processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after
the last Sector Erase command is written. If the time between
*NOTE:
NOTE:
See the appropriate Command Definitions table for program
command sequence.
applies to every 8th byte (i.e. I/O3, I/O11, I/O19, I/O27)
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
FLASH
AS8F128K32
Austin Semiconductor, Inc.
COMMAND SEQUENCE
CYCLES
TABLE 4: Command Definitions (Applies to each device8)
1
4
Read
Reset
5
6
Autoselect
Manufacturer ID
Device ID
7
Sector Protect Verify
Program
Chip Erase
Sector Erase
2,3
FIRST
SECOND
Addr Data8 Addr Data8
1
RA
RD
3
4
4
555
555
555
555
AA
AA
AA
4
4
6
6
555
555
555
555
AA
AA
AA
AA
2AA
2AA
2AA
2AA
55
55
55
55
2AA
2AA
2AA
2AA
55
55
55
BUS CYCLES
FIFTH
SIXTH
THIRD
FOURTH
Addr Data8 Addr Data8 Addr Data8 Addr Data8
555
555
555
555
555
555
555
555
F0
90
90
90
A0
80
80
XX00
XX01
(SA)
X02
PA
555
555
1
20
00
01
PD
AA
AA
2AA
2AA
55
55
555
SA
10
30
NOTES:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all command bus cycles are write operations.
4. No unlock or command cycles required when reading array data.
5. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high (while the device is
providing status data).
6. The fourth cycle of the autoselect command sequence is a read operation.
7. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.
8. Data shown for each respective byte I/O31-I/O24, I/O25-I/O16, I/O15-I/O8, I/O7-I/O0.
FIGURE 2: Erase Operation
LEGEND:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WEx\ or CEx\ pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WEx\ or CEx\ pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased.
Address bits A16–A14 uniquely select any sector.
NOTE:
1. See the appropriate Command Definitions table for program command sequence.
2. See "I/O3: Sector Erase Timer" for more information.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
FLASH
AS8F128K32
Austin Semiconductor, Inc.
WRITE OPERATION STATUS
FIGURE 3: Data\ Polling Algorithm
The device provides several bits to determine the status of
a write operation: I/O3, I/O5, I/O6, and I/O7. Table 5 and the
following subsections describe the functions of these bits.
I/O7 and I/O6 each offer a method for determining whether a
program or erase operation is complete or in progress. These
three bits are discussed first.
I/O7: Data\ Polling
The Data\ Polling bit, I/O7*, indicates to the host system
whether an Embedded Algorithm is in progress or completed.
Data\ Polling is valid after the rising edge of the final WEx\
pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device
outputs on I/O7* the complement of the datum programmed to
I/O7*. When the Embedded Program algorithm is complete, the
device outputs the datum programmed to I/O7*. The system
must provide the program address to read valid status
information on I/O7*. If a program address falls within a
protected sector, Data\ Polling on I/O7* is active for
approximately 2 ms, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data\ Polling
produces a “0” on I/O7*. When the Embedded Erase algorithm
is complete, Data\ Polling produces a “1” on I/O7*. This is
analogous to the complement/true datum output described for
the Embedded Program algorithm: the erase function changes
all the bits in a sector to “1”; prior to this, the device outputs
the “complement,” or “0.” The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O7*.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data\ Polling on I/O7* is
active for approximately 100 ms, then the device returns to
reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
When the system detects I/O7* has changed from the
complement to true data, it can read valid data at I/O7– I/O0 on
the following read cycles. This is because I/O7* may change
asynchronously with I/O0–I/O6 while Output Enable (OE\) is
asserted low. The Data\ Polling Timings (During Embedded
Algorithms) figure in the “AC Characteristics” section
illustrates this. Table 5 shows the outputs for Data\ Polling on
I/O7*. Figure 3 shows the Data\ Polling algorithm.
*
*
*
NOTES:
1. VA = Valid address for programming. During a sector erase operation,
a valid address is an address within any sector selected for erasure. During
chip erase, a valid address is any non-protected sector address.
2. I/O7 should be rechecked even if I/O5 = “1” because I/O7 may change
simultaneously with I/O5.
*NOTE: applies to every 8th byte.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
FLASH
AS8F128K32
Austin Semiconductor, Inc.
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete. Toggle
Bit I may be read at any address, and is valid after the rising
edge of the final WEx\ pulse in the command sequence (prior to
the program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address cause I/O6 to
toggle. (The system may use either OE\ or CEx\ to control the
read cycles.) When the operation is complete, I/O6 stops
toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles or approximately
100 ms, then returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm erases
the unprotected sectors, and ignores the selected sectors that
are protected.
If a program address falls within a protected sector, I/O6
toggles for approximately 2 ms after the program command
sequence is written, then returns to reading array data.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O6. Refer to Figure 4 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the “AC
Characteristics” section for the timing diagram.
I/O5 through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the system
must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 4).
FIGURE 4: Toggle Bit Algorithm
Reading Toggle Bit I/O6
Refer to Figure 4 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must
read I/O7–I/O0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and store
the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O7–I/O0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again whether
the toggle bit is toggling, since the toggle bit may have stopped
toggling just as I/O5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the program
or erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and I/O5 has not gone
high. The system may continue to monitor the toggle bit and
*NOTE: applies to every 8th byte.
AS8F128K32
Rev. 2.0 5/03
*
NOTES:
1. Read toggle bit twice to determine whether or not it is toggling. See
text.
2. Recheck toggle bit because it may stop toggling as I/O5 changes to “1”.
See text.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
FLASH
AS8F128K32
Austin Semiconductor, Inc.
I/O5: Exceeded Timing Limits
the chip erase command.) If additional sectors are selected for
erasure, the entire timeout also applies after each additional
sector erase command. When the time-out is complete, I/O3*
switches from “0” to “1.” The system may ignore I/O3* if the
system can guarantee that the time between additional sector
erase commands will always be less than 50 ms. See also the
“Sector Erase Command Sequence” section.
After the sector erase command sequence is written, the
system should read the status on I/O7* (Data\ Polling) or I/O6
(Toggle Bit I) to ensure the device has accepted the command
sequence, and then read I/O3. If I/O3 is “1”, the internally
controlled erase cycle has begun; all further commands are
ignored until the erase operation is complete. If I/O3 is “0”, the
device will accept additional sector erase commands. To
ensure the command has been accepted, the system software
should check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted. Table 5 shows the outputs for I/O3.
I/O5* indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5* produces a “1.” This is a failure condition
that indicates the program or erase cycle was not successfully
completed.
The I/O5* failure condition may appear if the system tries
to program a “1” to a location that is previously programmed to
“0.” Only an erase operation can change a “0” back to a “1.”
Under this condition, the device halts the operation, and when
the operation has exceeded the timing limits, I/O5* produces a
“1.” Under both these conditions, the system must issue the
reset command to return the device to reading array data.
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read I/O3* to determine whether or not an erase
operation has begun. (The sector erase timer does not apply to
TABLE 5: Write Operation Status
OPERATION
Embedded Program Algorithm
Embedded Erase Algorithm
NOTES: *applies to every 8th byte
I/O71,*
I/O7\
0
I/O52,*
0
0
I/O6*
Toggle
Toggle
I/O3*
N/A
1
1. I/O7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “I/O5: Exceeded
Timing Limits” for more information.
ABSOLUTE MAXIMUM RATINGS*
1
Voltage with respect to Ground, VCC .........................-2.0V to +7.0V
Voltage with respect to Ground, A9 2..........................-2.0V to +14V
Voltage with respect to Ground, All other pins 1......-2.0V to +7.0V
Short-circuit output current.....................................................200mA
Ambient Temperature with power Applied...............-55°C to 125°C
Storage temperature range..........................................-65°C to 150°C
NOTES:
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
1. Minimum DC voltage on input or I/O pin is –0.5 V. During voltage transitions, inputs may overshoot VSS to –2.0 V for periods of up to 20 ns. See
Figure 5. Maximum DC on input and I/O pins is VCC + 0.5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods
up to 20 ns. See Figure 6.
2. Minimum DC input voltage on A9 pin is –0.5V. During voltage transitions, A9 pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See
Figure 5. Maximum DC input voltage on A9 is +12.5 V which may overshoot to 14V for periods up to 20 ns.
3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
FIGURE 5: Maximum Negative Overshoot
AS8F128K32
Rev. 2.0 5/03
FIGURE 6: Maximum Positive Overshoot
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
FLASH
Austin Semiconductor, Inc.
AS8F128K32
DC CHARACTERISTICS
SYM
CONDITION
MAX
UNIT
Input Load Current
ILI
VIN = VSS to VCC, VCC = VCCMax
±10
µA
A9 Input Load Current
ILIT
VCC = VCCMax, A9 = 12.5V
200
µA
Output Leakage Current
PARAMETER
MIN
ILO
VOUT = VSS to VCC, VCC = VCCMax
±10
µA
1
ICC1
CEx\ = VIL, OE\ = VIH, VCC = VCCMax, f = 5MHz
140
mA
2,3
ICC2
CEx\ = VIL, OE\ = VIH, VCC = VCCMax, f = 5MHz
200
mA
TTL/NMOS
ICC3
VCC = VCCMax, CEx\ and OE\ = VIH, f = 5MHz
6.5
mA
CMOS
ICC3
VCC = VCCMax, CEx\ = VCC ± 0.3V, OE\ = VIH
2
mA
VCC Active Current
VCC Active Current
VCC Standby Current
Input Low Voltage
VIL
-0.5
0.8
V
Input High Voltage
VIH
2.0
VCC + 0.5
V
Voltage for Autoselect and Temporary
Sector Unprotect
VID
VCC = 5.0V
11.5
12.5
V
Output Low Voltage
VOL
IOL = 12mA, VCC = VCCMin
0.45
V
VOH
IOH = -2.5mA, VCC = VCCMin
2.4
V
VOH1
IOH = -2.5mA, VCC = VCCMin
0.85 VCC
V
VOH2
IOH = -100µA, VCC = VCCMin
VCC -0.4
V
TTL/NMOS
Output High Voltage
CMOS
Low VCC Lock-out Voltage
VLKO
3.2
4.2
V
NOTES:
1. The ICC current listed is typically less than 8 mA/MHz, with OE\ at VIH.
2. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.
3. Not 100% tested.
FIGURE 7: Test Setup
TABLE 6: Test Specifications
CONDITION
Output Load
Output Load Capacitiance, CL
(Including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
Input timing measurement
reference levels
Output timing measurement
reference levels
NOTE:
ALL SPEEDS
UNIT
1 TTL Gate
50
pF
5
0.0 - 0.3
ns
V
1.5
V
1.5
V
Diodes are IN3064 or equivalent.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
FLASH
AS8F128K32
Austin Semiconductor, Inc.
AC CHARACTERISTICS
SYMBOL
JEDEC Standard
PARAMETER
Read-Only Operations
1
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
tACC
Chip Enable to Output Delay
tELQV
Output Enable to Output Delay
1,2
Chip Enable to Output High Z
1,2
Output Enable to Output High Z
Output Enable Hold Time
ns
Max 60 70 90 120 150
ns
tCE
Max 60 70 90 120 150
ns
tGLQV
tOE
Max 30 35 40
50
55
ns
tEHQZ
tDF
Max 20 20 25
30
35
ns
tGHQZ
tDF
Max 20 20 25
30
35
ns
tOEH
Min
-60 -70 -90 -120 -150 UNIT
60 70 90 120 150
1
Output Hold Time From Addresses
CEx\ or OE\, Whichever Comes First
Erase and Program Operations
TEST SETUP
CEx\ = VIL
OE\ = VIL
Read
Toggle and
Data Polling
Min
0
ns
Min
10
ns
tAXQX
tOH
Min
0
ns
tAVAV
tWC
Min
60 70 90 120 150
ns
Address Setup Time
tAVWL
tAS
Min
0
ns
Address Hold Time
tWLAX
tAH
Min
45 45 45
50
50
ns
Data Setup Time
tDVWH
tDS
Min
30 30 45
50
50
ns
Data Hold Time
tWHDX
tDH
Min
0
ns
Read Recover Time Before Write
(OE\ High to WEx\ Low)
tGHWL
tGHWL
Min
0
ns
CEx\ Setup Time
tELWL
tCS
Min
0
ns
CEx\ Hold Time
tWHEH
tCH
Min
0
ns
Write Pulse Width
tWLWH
tWP
Min
30 35 45
Write Pulse Width High
tWHWL
tWPH
Min
20
ns
tWHWH1
tWHWH1
TYP
14
µs
tWHWH2
tWHWH2
TYP
1.0
sec
Min
50
µs
Write Cycle Time
1
4
Byte Programming Operation
4
Sector Erase Operation
VCC Setup Time
1
tVCS
50
50
ns
NOTES:
1.
2.
3.
4.
Not 100% tested.
Output Driver Disable Time.
See Figure 7 and Table 6 for test specifications.
See the “Erase and Programming Performance” section for more information.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
FLASH
Austin Semiconductor, Inc.
AS8F128K32
FIGURE 8: Read Operations Timings
FIGURE 9: Program Operations Timings
NOTE:
PA = program address, PD = program data, DOUT is the true data at the program address.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
14
FLASH
Austin Semiconductor, Inc.
AS8F128K32
FIGURE 10: Chip/Sector Erase Operations Timings
2AAh
NOTE:
SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
FIGURE 11: Data\ Polling Timings (During Embedded Algorithms)
NOTES:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
*applies
AS8F128K32
Rev. 2.0 5/03
to every 8th byte.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
FLASH
Austin Semiconductor, Inc.
AS8F128K32
FIGURE 12: Toggle Bit Timings (During Embedded Algorithms)
NOTES:
VA = Valid address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
*applies to every 8th byte.
AC CHARACTERISTICS: Erase and Program Operations, Alternate CEx\
Controlled Writes
SYMBOL
JEDEC Standard DESCRIPTION -60 -70 -90 -120 -150 UNIT
PARAMETER
1
tAVAV
tWC
Min
60 70 90 120 150
ns
Address Setup Time
tAVEL
tAS
Min
0
ns
Address Hold Time
tELAX
tAH
Min
45 45 45
50
50
ns
Data Setup Time
tDVEH
tDS
Min
30 30 45
50
50
ns
Data Hold Time
tEHDX
tDH
Min
0
ns
tOES
Min
0
ns
Write Cycle Time
1
Output Enable Setup Time
Read Recover Time Before Write
tGHEL
tGHEL
Min
0
ns
WEx\ Setup Time
tEHWH
tWS
Min
0
ns
WEx\ Hold Time
tEHWH
tWH
Min
0
ns
CEx\ Pulse Width
tELEH
tCP
Min
30 35 45
CEx\ Pulse Width High
tEHEL
tCPH
Min
20
ns
2
tWHWH1
tWHWH1
TYP
14
µs
2
tWHWH2
tWHWH2
TYP
1.0
sec
Byte Programming Operation
Chip/Sector Erase Operation
50
50
ns
NOTES:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
FLASH
Austin Semiconductor, Inc.
AS8F128K32
FIGURE 13: Alternate CEx\ Controlled Write Operation Timings
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
NOTES:
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7\ = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER
TYP
Chip/Sector Erase Time
Byte Programming Time
Chip Programming Time
3
1.0
14
1.8
1
2
MAX
UNIT
15
1000
12.5
sec
µs
sec
COMMENTS
Excludes 00h programming prior to erasure
4
Excludes system-level overhead5
NOTES:
1. Typical program and erase times assume the following conditions: 25° C, 5.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for -45, -55 PDIP), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster
than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set I/O5 = 1. See
the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1 for further
information on command definitions.
6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17
FLASH
AS8F128K32
Austin Semiconductor, Inc.
CAPACITANCE
PARAMETER
SYMBOL CONDITIONS
MAX
UNIT
CIN
VIN = 0
50
pF
CSx\ & WEx\ Capacitance
COUT
VOUT = 0
20
pF
I/O0 - I/O31 Capacitance
CIN2
VIN = 0
20
pF
A0 - A16 Capacitance
NOTES:
1. Sampled, not 100% tested.
2. Test conditions TA = 25° C, f = 1.0 MHz.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
18
FLASH
AS8F128K32
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #703 (Package Designator Q)
SMD 5962-94716, Case Outline N
D2
D1
DETAIL A
D
R
1o - 7o
b
L1
e
SEE DETAIL A
c
A2
A
E
SYMBOL
A
A2
b
c
D
D1
D2
E
e
R
L1
SMD SPECIFICATIONS
MIN
MAX
0.123
0.160
0.005
0.025
0.013
0.017
0.009
0.012
0.800 BSC
0.870
0.890
0.980
1.000
0.936
0.956
0.050 BSC
0.010 BSC
0.035
0.045
*All measurements are in inches.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
19
FLASH
Austin Semiconductor, Inc.
AS8F128K32
MECHANICAL DEFINITIONS*
ASI Case (Package Designator Q1)
SMD 5962-94716, Case Outline A
SYMBOL
A
A1
b
B
c
D/E
D1/E1
D2/E2
e
L
R
SMD SPECIFICATIONS
MIN
MAX
--0.200
0.054
--0.013
0.017
0.010 TYP
0.009
0.012
0.980
1.000
0.870
0.890
0.800 BSC
0.050 BSC
0.035
0.045
0.010 TYP
*All measurements are in inches.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
20
FLASH
AS8F128K32
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS8F128K32Q-70/XT
Device Number
AS8F128K32
AS8F128K32
AS8F128K32
AS8F128K32
AS8F128K32
Package
Type
Q
Q
Q
Q
Q
Speed
ns
-60
-70
-90
-120
-150
Process
/*
/*
/*
/*
/*
EXAMPLE: AS8F128K32Q1-120/883C
Device Number
AS8F128K32
AS8F128K32
AS8F128K32
AS8F128K32
AS8F128K32
Package
Type
Q1
Q1
Q1
Q1
Q1
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing
Q = Full QML Processing
AS8F128K32
Rev. 2.0 5/03
Speed
ns
-60
-70
-90
-120
-150
Process
/*
/*
/*
/*
/*
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
21
FLASH
Austin Semiconductor, Inc.
AS8F128K32
ASI TO DSCC PART NUMBER*
CROSS REFERENCE
ASI Package Designator Q
ASI Part #
SMD Part #
AS8F128K32Q-150/Q
AS8F128K32Q-120/Q
AS8F128K32Q-90/Q
AS8F128K32Q-70/Q
AS8F128K32Q-60/Q
5962-9471601HNX
5962-9471602HNX
5962-9471603HNX
5962-9471604HNX
5962-9471605HNX
ASI Package Designator Q1
ASI Part #
SMD Part #
AS8F128K32Q1-150/Q
AS8F128K32Q1-120/Q
AS8F128K32Q1-90/Q
AS8F128K32Q1-70/Q
AS8F128K32Q1-60/Q
5962-9471601HAX
5962-9471602HAX
5962-9471603HAX
5962-9471604HAX
5962-9471605HAX
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
AS8F128K32
Rev. 2.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
22