ASM2I2313ANZ June 2005 rev 0.4 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Functional Description Features One input to 13 Output Buffer/Driver The ASM2I2313ANZ is a 3.3V buffer designed to distribute Supports up to three SDRAM DIMMs high-speed clocks in desktop PC applications. The part has One additional outputs for feedback 13 outputs, 12 of which can be used to drive up to three Serial interface for output control SDRAM DIMMs, and the remaining can be used for Low skew outputs external feedback to a PLL. The device operates at 3.3V Up to 133MHz operation and outputs can run up to 133MHz, thus making it Multiple VDD and VSS pins for noise reduction compatible Low EMI outputs ASM2I2313ANZ can be used in conjunction with the clock 28 pin SOIC (300-mil) Package synthesizer for a complete Pentium II motherboard 3.3V operation solution. The ASM2I2313ANZ also includes a serial with Pentium®*II processors. The interface, which can enable or disable each output clock. On power-up, all output clocks are enabled. *Pentium is a registered trademark of Intel Corporation. Block Diagram BUF_IN SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDATA Serial Interface Decoding SDRAM4 SDRAM5 SDRAM6 SCLOCK SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. ASM2I2313ANZ June 2005 rev 0.4 Pin Configuration 28 Pin SOIC Package -- Top View VDD 1 28 VDD SDRAM0 2 27 SDRAM11 SDRAM1 3 26 SDRAM10 VSS 4 25 VSS VDD 5 24 VDD SDRAM2 6 23 SDRAM9 SDRAM3 7 22 SDRAM8 VSS 8 21 VSS BUF_IN 9 20 VDD SDRAM4 10 19 SDRAM7 SDRAM5 11 18 SDRAM6 SDRAM12 12 17 VSS VDDIICC 13 16 VSSIIC SDATA 14 15 SCLK ASM2I2313ANZ Pin Description Pins Name Type Description 1, 5, 20, 24, 28 VDD P 3.3V Digital Voltage supply 4, 8, 17, 21, 25 VSS P Ground 13 VDDIIC P 3.3V Serial Interface voltage supply 16 VSSIIC P Ground for serial interface 9 BUF_IN I Input clock .5V Tolerant 14 SDATA I/O Serial data input, internal pull-up to VDD .5V Tolerant 15 SCLK I Serial clock input, internal pull-up to VDD .5V Tolerant 2, 3, 6, 7, 10, 11, 12, 18, 19, 22, 23, 26, 27 SDRAM [0-12] O SDRAM Clock Outputs 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 2 of 13 ASM2I2313ANZ June 2005 rev 0.4 Serial Configuration Map Byte 1: SDRAM Active/Inactive Register • The Serial bits will be read by the clock driver in the (1 = Enable, 0 = Disable), Default = Enable following order: Bit Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Pin # Description Bit 7 27 SDRAM11 (Active/Inactive) Bit 6 26 SDRAM10 (Active/Inactive) • Reserved bits should be programmed to “0” or ”1”. Bit 5 23 SDRAM9 (Active/Inactive) • Serial interface address for the ASM2I2313ANZ is: Bit 4 22 SDRAM8 (Active/Inactive) Bit 3 -- Reserved Bit 2 -- Reserved Bit 1 19 SDRAM7 (Active/Inactive) Byte 0: SDRAM Active/Inactive Register Bit 0 18 SDRAM6 (Active/Inactive) (1 = Enable, 0 = Disable), Default = Enable Byte 2: SDRAM Active/Inactive Register Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 ---- Bit Pin # Description Bit 7 11 SDRAM5 (Active/Inactive) Bit 6 10 SDRAM4 (Active/Inactive) Bit 5 -- Reserved Bit 4 -- Reserved Bit 3 7 SDRAM3 (Active/Inactive) Bit 2 6 SDRAM2 (Active/Inactive) Bit 1 3 SDRAM1 (Active/Inactive) Bit 0 2 SDRAM0 (Active/Inactive) (1 = Enable, 0 = Disable), Default = Enable Bit Pin # Description Bit 7 -- Reserved Bit 6 12 SDRAM12 (Active/Inactive) Bit 5 -- Reserved Bit 4 -- Reserved Bit 3 -- Reserved Bit 2 -- Reserved Bit 1 -- Reserved Bit 0 -- Reserved Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value of all the bits is high after chip is powered up. IIC Byte Flow Byte Description 1 IIC Address 2 Command (dummy value, ignored) 3 Byte Count (dummy value, ignored) 4 IIC Data Byte 0 5 IIC Data Byte 1 6 IIC Data Byte 2 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 3 of 13 ASM2I2313ANZ June 2005 rev 0.4 Absolute Maximum Ratings Symbol Parameter VDD Supply Voltage to Ground Potential VIN DC Input Voltage (Except BUF_IN) VBUFIN DC Input Voltage (BUF_IN) Rating –0.5 to +7.0 –0.5 to VDD + 0.5 –0.5 to +7.0 Unit V V V TSTG Storage Temperature –65 to +150 °C TJ Junction Temperature 150 °C 2 KV TDV Static Discharge Voltage (As per JEDEC STD 22- A114-B) Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions1 Parameter Description Min Max Unit 3.135 3.465 V VDD Supply Voltage TA Operating Temperature (Ambient Temperature) 0 70 °C CL Load Capacitance 20 30 pF CIN Input Capacitance - 7 pF tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 mS Note: 1. Electrical parameters are guaranteed under the operating conditions specified. 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 4 of 13 ASM2I2313ANZ June 2005 rev 0.4 Electrical Characteristics Parameter VIL Description Test Conditions Input LOW Voltage Except serial interface pins VILIIC Input LOW Voltage For serial interface pins only VIH Input HIGH Voltage VOL Output LOW Voltage1 1 VOH Output HIGH Voltage ICC Quiescent Supply Current IOZ High Impedance Output Current IOFF Off-State Current (for SCL ,SDATA) ∆ICC Change in Supply Current Ii Input Leakage 1 IDD Supply Current IDD Supply Current1 IDD Supply Current 1 IDD Supply Current 1 IDD Supply Current1 IDD Supply Current 1 IDDS Supply Current IOL= 25 mA IOH = -36 mA VDD= 3.465V, Vi = VDD or GND, IO =0 Min Typ Max Unit - 0.8 V - 0.7 V 2.0 - V - 0.4 V 2.4 - V 100 µA ±10 µA 50 µA 500 µA +5 µA 266 mA 360 mA - 200 mA - 290 mA - 150 mA - 185 mA - 500 µA 50 VDD= 3.465V, Vi = VDD or GND VDD= 0V, Vi = 0V or 5.5V VDD= 3.135V to 3.465V One Input at VDD-0.6, All other Inputs at VDD or GND VDD= 3.465V or GND (Applicable to all Input Pins) Unloaded outputs,133MHz Loaded outputs, 30pF,133MHz Unloaded outputs, 100MHz Loaded outputs, 30pF,100MHz Unloaded outputs, 66.67MHz Loaded outputs, 30pF,66.67MHz BUF_IN=VDD or VSS All other inputs at VDD -5 Note: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production. 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 5 of 13 ASM2I2313ANZ June 2005 rev 0.4 Switching Characteristics1 Parameter Name Fin Maximum Operating Frequency tD t3 t4 t5 t6 t7 tPLZ, tPHZ tPZL, tPZH tr tf 2,3 Duty cycle Test Conditions = t2 ÷ t1 Min Typ Max Unit - - 133 MHz 45.0 50.0 55.0 % Measured between 0.4V and 2.4V 1 2 4 V/nS Measured between 2.4V and 0.4V 1 2 4 V/nS 150 225 pS Measured at 1.5V 3 Rising Edge Rate 3 Falling Edge Rate 3 Output to Output Skew All outputs equally loaded 3 Input edge greater than 1 V/nS 1 2.7 3.5 nS 3 Input edge greater than 1 V/nS 1 2.7 3.5 nS Input edge greater than 1 V/nS 1 3 5 nS Input edge greater than 1 V/nS 1 3 5 nS CL = 10pF 6 SDRAM Buffer LH Prop. Delay SDRAM Buffer HL Prop. Delay 3 SDRAM Buffer Enable Delay 3 SDRAM Buffer Disable Delay Rise Time for SDATA (Refer Test Circuit for IIC) Refer figure no.3 Fall Time for SDATA (Refer Test Circuit for IIC) Refer figure no.3 CL = 400pF 250 CL = 10pF 20 CL = 400pF 250 Note: 1. All parameters specified with loaded outputs. 2. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/nS 3. Parameter is guaranteed by design and characterization. Not 100% tested in production. Test Circuit for SDRAM Enable and Disable Times S1 2 * VDD Open VSS VDD 500Ω VI VO PULSE GENERATOR D.U.T RT TEST t6/t7 tPLZ/tPZL tPHZ/tPZH CL 500Ω S1 Open 2* VDD VSS Figure 1. Load circuit for Switching times 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 6 of 13 nS nS ASM2I2313ANZ June 2005 rev 0.4 SDRAM Enable and Disable Times VM = 1.5V VX = VOL +0.3V VY = VOH -0.3V VOH and VOL are the typical Output Voltage drop that occur with the output load VI VDD VM OE INPUT GND tPZL tPLZ VDD OUTPUT LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VDD OUTPUT HIGH-to-OFF OFF-to-HIGH tPZH VY VM VSS Outputs enabled Outputs enabled Outputs disabled Figure 2. 3-State Enable and Disable times Test Circuit for IIC Rise and Fall Times VO = 3.3V RL = 1kΩ DUT CL = 10pF or CL = 400pF GND Figure 3. Test Circuit for IIC 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 7 of 13 ASM2I2313ANZ June 2005 rev 0.4 Switching Waveforms Duty Cycle Timing t1 t2 1.5 V 1.5 V 1.5 V All Outputs Rise/Fall Time 2.4 V 0.4 V OUTPUT 3.3 V 2.4 V 0.4 V 0V t3 t4 Output - Output Skew 1.5 V OUTPUT 1.5 V OUTPUT t5 SDRAM Buffer LH and HL Propagation Delay INPUT OUTPUT t6 t7 Test Circuit VDD 0.1 µ F OUTPUTS CLK Out CLOAD GND 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 8 of 13 ASM2I2313ANZ June 2005 rev 0.4 Application Information Clock traces must be terminated with either series or parallel termination, as is normally done. Application Circuit Rs CPUCLK BUF_IN Rs SDRAM (0.12) SDATA SDATA SCLK SCLK SDRAM(0.12) Ct 3.3V VDD VSS Cd = 0.1 µ F ASM2I2313ANZ 28-Pin SOIC Cd = DECOUPLING CAPACITORS Ct = OPTIONAL EMI-REDUCING CAPACITORS Rs = SERIES TERMINATING RESISTORS Summary • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value • The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic of 0.1 µF. In some cases, smaller value capacitors may be required. impedance of the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7pF to 22pF. • A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. • If a Ferrite Bead is used, a 10µF–22µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 9 of 13 ASM2I2313ANZ June 2005 rev 0.4 IIC Serial Interface Information The information in this section assumes familiarity with IIC programming. How to program ASM2I2313ANZ through IIC: • Master (host) sends a start bit. • Master (host) sends the write address D3 (H). • ASM2I2313ANZ device will acknowledge. • Master (host) sends the Command Byte. • ASM2I2313ANZ device will acknowledge the Command Byte. • Master (host) sends a Byte count • ASM2I2313ANZ device will acknowledge the Byte count. • Master (host) sends the Byte 0 • ASM2I2313ANZ device will acknowledge Byte 0 • Master (host) sends the Byte 1 • ASM2I2313ANZ device will acknowledge Byte 1 • Master (host) sends the Byte 2 • ASM2I2313ANZ device will acknowledge Byte 2 • Master (host) sends a Stop bit. Controller (Host) ASM2I2313ANZ (slave/receiver) Start Bit Slave Address D3(H) ACK Command Byte ACK Byte count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Stop Bit 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 10 of 13 ASM2I2313ANZ June 2005 rev 0.4 Package Information 28L SOIC Package(300 mil) Dimensions Symbol Inches Min Max Millimeters Min Max A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 A2 0.088 0.094 2.25 2.40 D 0.697 0.712 17.70 18.10 h 0.010 0.029 0.25 0.75 E 0.291 0.299 7.40 7.60 H 0.394 0.419 10.00 10.65 R1 0.003 …. 0.08 ….. b 0.013 0.022 0.33 0.56 b1 0.013 0.020 0.33 0.51 c 0.009 0.015 0.23 0.38 c1 0.009 0.013 0.23 0.33 L 0.016 0.050 0.40 1.27 e θ 0.050 BSC 0° 1.27 BSC 8° 0° 8° 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 11 of 13 ASM2I2313ANZ June 2005 rev 0.4 Ordering Information Marking Ordering Code Package Type Operating Range ASM2I2313ANZ-28-ST 2I2313ANZ 28 Pin SOIC, Tube Industrial ASM2I2313ANZ-28-SR 2I2313ANZ 28 Pin SOIC, Tape and Reel Industrial ASM2I2313AGNZ-28-ST 2I2313AGNZ 28 Pin SOIC, Tube, Green Industrial ASM2I2313AGNZ-28-SR 2I2313AGNZ 28 Pin SOIC, Tape and Reel, Green Industrial Device Ordering Information A S M 2 I 2 3 1 3 A N Z G - 2 8 - S R R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 13 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs Notice: The information in this document is subject to change without notice. 12 of 13 ASM2I2313ANZ June 2005 rev 0.4 Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM22313ANZ Document Version: 0.4 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2004 Alliance Semiconductor Corporation. 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