ALSC ASM2I2318ANZ 18 output, 3.3v sdram buffer for desktop pcs with 3 dimm Datasheet

ASM2I2318ANZ
June 2005
rev 0.3
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Functional Description
Features
ƒ
One input to 18 output Buffer/Driver
The ASM2I2318ANZ is a 3.3V buffer designed to distribute
ƒ
Supports up to four SDRAM DIMMs
high-speed clocks in PC applications. The part has 18
ƒ
Two additional outputs for feedback
outputs, 16 of which can be used to drive up to four
ƒ
Serial interface for individual output control
SDRAM DIMMs, and the remaining can be used for
ƒ
Low skew outputs (< 250 pS)
external feedback to a PLL. The device operates at 3.3V
ƒ
Up to 133 MHz operation
and outputs can run up to 133MHz, thus making it
ƒ
Dedicated OE pin for testing
compatible
ƒ
Space-saving 48 Pin SSOP package
ASM2I2318ANZ can be used in conjunction with the clock
ƒ
3.3V operation
synthesizer for a complete Pentium II motherboard
with
Pentium
II®*
processors.
The
solution. The ASM2I2318ANZ also includes a serial
interface which can enable or disable each output clock.
On power-up, all output clocks are enabled (internal pull
up). A separate Output Enable pin facilitates testing on
ATE.
*Pentium is a registered trademark of Intel Corporation.
Block Diagram
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDATA
SDRAM9
Serial Interface
Decoding
SCLOCK
SDRAM10
SDRAM11
SDRAM12
SDRAM13
SDRAM14
SDRAM15
SDRAM16
SDRAM17
OE
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
ASM2I2318ANZ
June 2005
rev 0.3
Pin Configuration
48-Pin SSOP Package -- Top View
NC 1
48 NC
NC 2
VDD 3
47 NC
46 VDD
SDRAM0 4
SDRAM1 5
VSS 6
VDD 7
45 SDRAM15
44 SDRAM14
43 VSS
SDRAM2 8
41 SDRAM13
SDRAM3 9
VSS 10
BUF_IN 11
VDD 12
40 SDRAM12
39 VSS
42
VDD
38 OE
37 VDD
ASM2I2318ANZ
SDRAM4 13
36 SDRAM11
SDRAM5 14
VSS 15
VDD 16
35 SDRAM10
SDRAM6 17
32 SDRAM9
SDRAM7 18
VSS 19
VDD 20
31 SDRAM8
34 VSS
33 VDD
30 VSS
29 VDD
28 SDRAM17
SDRAM16 21
VSS 22
27 VSS
26 VSSIIC
VDDIIC 23
25 SCLOCK
SDATA 24
Pin Description
Pins
3, 7, 12, 16, 20,
29, 33, 37, 42, 46
6, 10, 15, 19, 22,
27, 30, 34, 39, 43
23
Name
Type
Description
VDD
P
3.3V Digital voltage supply
VSS
P
Ground
VDDIIC
P
Serial interface voltage supply
26
VSSIIC
P
Ground for serial interface
11
BUF_IN
I
Input clock. 5V tolerant
38
OE
I
Output Enable (active HIGH), Three-state outputs when low1
24
SDATA
25
I/O
Serial data input1. 5V tolerant
SCLK
I
Serial clock input1. 5V tolerant
4, 5, 8, 9
SDRAM [0–3]
O
SDRAM byte 0 clock outputs
13, 14, 17, 18
SDRAM [4–7]
O
SDRAM byte 1 clock outputs
31, 32, 35, 36
SDRAM [8–11]
O
SDRAM byte 2 clock outputs
40, 41, 44, 45
SDRAM [12–15]
O
SDRAM byte 3 clock outputs
21, 28
SDRAM [16–17]
O
SDRAM clock outputs usable for feedback
NC
1, 2, 47, 48
-
Reserved for future modifications, do not connect in system
Note: 1. Internal pull-up resistor to VDD (value > 100 KOhms)
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
2 of 13
ASM2I2318ANZ
June 2005
rev 0.3
Device Functionality
OE
Byte 1: SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enable
SDRAM [0-17]
0
Hi-Z
1
1 x BUF_IN
Bit
Pin #
Description
Bit 7
45
SDRAM15 (Active/Inactive)
Bit 6
44
SDRAM14 (Active/Inactive)
Serial Configuration Map
Bit 5
41
SDRAM13 (Active/Inactive)
• The Serial bits will be read by the clock driver in the
Bit 4
40
SDRAM12 (Active/Inactive)
Bit 3
36
SDRAM11 (Active/Inactive)
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Bit 2
35
SDRAM10 (Active/Inactive)
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Bit 1
32
SDRAM9 (Active/Inactive)
Bit 0
31
SDRAM8 (Active/Inactive)
following order:
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved bits should be programmed to “0” or ”1”.
• Serial interface address for the ASM2I2318ANZ is:
Byte 2: SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enable
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
----
Bit
Pin #
Description
Bit 7
28
SDRAM17 (Active/Inactive)
Bit 6
21
SDRAM16 (Active/Inactive)
Bit 5
--
Reserved
Bit 4
--
Reserved
Description
Bit 3
--
Reserved
Byte 0:SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enable
Bit
Pin #
Bit 7
18
SDRAM7 (Active/Inactive)
Bit 2
--
Reserved
Bit 6
17
SDRAM6 (Active/Inactive)
Bit 1
--
Reserved
Bit 5
14
SDRAM5 (Active/Inactive)
Bit 0
--
Reserved
Bit 4
13
SDRAM4 (Active/Inactive)
Bit 3
9
SDRAM3 (Active/Inactive)
Bit 2
8
SDRAM2 (Active/Inactive)
Bit 1
5
SDRAM1 (Active/Inactive)
Bit 0
4
SDRAM0 (Active/Inactive)
Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value
of all the bits is high after chip is powered up.
IIC Byte Flow
Byte
Description
1
IIC Address
2
Command (dummy value, ignored)
3
Byte Count (dummy value, ignored)
4
IIC Data Byte 0
5
IIC Data Byte 1
6
IIC Data Byte 2
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
3 of 13
ASM2I2318ANZ
June 2005
rev 0.3
Absolute Maximum Ratings
Symbol
Parameter
VDD
Supply Voltage to Ground Potential
VIN
DC Input Voltage (Except BUF_IN)
VBUFIN
DC Input Voltage (BUF_IN)
Rating
–0.5 to +7.0
–0.5 to VDD + 0.5
–0.5 to +7.0
Unit
V
V
V
TSTG
Storage Temperature
–65 to +150
°C
TJ
Junction Temperature
150
°C
2
KV
TDV
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions1
Parameter
VDD VDDIIC
Description
Supply Voltage
Min
Max
Unit
3.135
3.465
V
TA
Operating Temperature (Ambient Temperature)
0
70
°C
CL
Load Capacitance
20
30
pF
7
pF
50
mS
CIN
Input Capacitance
tPU
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
0.05
Note: 1. Electrical parameters are guaranteed under the operating conditions specified.
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
4 of 13
ASM2I2318ANZ
June 2005
rev 0.3
Electrical Characteristics
(Test condition: All parameters values are valid within the Operating range, unless otherwise stated)
Parameter
VIL
VILiic
VIH
VOL
VOH
ICC
IOZ
IOFF
∆ICC
Ii
Description
Input LOW Voltage
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage1
Output HIGH Voltage1
Quiescent Supply Current
High Impedance Output
Current
Off-State Current
(for SCL ,SDATA)
Change in Supply Current
Input Leakage
1
IDD
IDD
IDD
IDD
IDD
IDD
Supply Current
Supply Current1
Supply Current1
Supply Current1
Supply Current1
Supply Current1
IDDS
Supply Current
Test Conditions
Min
Typ
For all pins except serial interface pins
For serial pins only
Max
Unit
0.8
0.7
100
V
V
V
V
V
µA
±10
µA
50
µA
500
µA
+5
µA
150
400
110
300
80
200
mA
mA
mA
mA
mA
mA
500
µA
2.0
IOL= 25 mA
IOH = –36 mA
VDD= 3.465V, Vi = VDD or GND, IO =0
0.4
2.4
50
VDD= 3.465V, Vi = VDD or GND
VDD= 0V, Vi = 0V or 5.5V
VDD= 3.135V to 3.465V
One Input at VDD-0.6, All other Inputs
at VDD or GND
VDD= 3.465V or GND
(Applicable to all Input Pins)
Unloaded outputs, 133 MHz
Loaded outputs, 30pF,133 MHz
Unloaded outputs, 100 MHz
Loaded outputs, 30pF, 100 MHz
Unloaded outputs, 66.67 MHz
Loaded outputs, 30pF, 66.67 MHz
BUF_IN=VDD or VSS,
all other inputs at VDD
-5
Note: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production.
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
5 of 13
ASM2I2318ANZ
June 2005
rev 0.3
Switching Characteristics1
Parameter
Name
Fin
Maximum Operating Frequency
2,3
Test Conditions
tD
Duty cycle
t3
Rising Edge Rate3
t4
Falling Edge Rate3
t5
Output to Output Skew3
t6
t7
= t2 ÷ t1
Measured at 1.5V
Measured between 0.4V and
2.4V
Measured between 2.4V and
0.4V
All outputs equally loaded
Min
Typ
Max
Unit
-
-
133
MHz
45.0
50.0
55.0
%
1
2
4
V/nS
1
2
4
V/nS
150
225
pS
3
Input edge greater than 1 V/nS
1
2.7
3.5
nS
3
Input edge greater than 1 V/nS
1
2.7
3.5
nS
SDRAM Buffer LH Prop. Delay
SDRAM Buffer HL Prop. Delay
3
tPLZ, tPHZ
SDRAM Buffer Enable Delay
Input edge greater than 1 V/nS
1
3
5
nS
tPZL, tPZH
SDRAM Buffer Disable Delay3
Rise Time for SDATA
(Refer Test Circuit for IIC)
Refer figure no.3
Fall Time for SDATA
(Refer Test Circuit for IIC)
Refer figure no.3
Input edge greater than 1 V/nS
1
3
5
nS
CL = 10pF
6
tr
tf
CL = 400pF
250
CL = 10pF
20
CL = 400pF
250
nS
nS
Note: 1. All parameters specified with loaded outputs.
2. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/nS
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Test Circuit for SDRAM Enable and Disable Times
S1
2 * VDD
Open
VSS
VDD
500Ω
VI
VO
PULSE
GENERATOR
D.U.T
RT
TEST
t6/t7
tPLZ/tPZL
tPHZ/tPZH
CL
500Ω
S1
Open
2* VDD
VSS
Figure 1. Load circuit for Switching times
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
6 of 13
ASM2I2318ANZ
June 2005
rev 0.3
SDRAM Enable and Disable Times
VM = 1.5V
VX = VOL +0.3V
VY = VOH -0.3V
VOH and VOL are the typical Output Voltage drop that occur with the output load
VI
VDD
VM
OE INPUT
GND
tPZL
tPLZ
VDD
OUTPUT
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
VDD
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
tPZH
VY
VM
VSS
Outputs
enabled
Outputs
enabled
Outputs
disabled
Figure 2. 3-State Enable and Disable times
Test Circuit for IIC Rise and Fall Times
VO = 3.3V
RL = 1kΩ
DUT
CL = 10pF or
CL = 400pF
GND
Figure 3. Test Circuit for IIC
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
7 of 13
ASM2I2318ANZ
June 2005
rev 0.3
Switching Waveforms
Duty Cycle Timing
t1
t2
1.5 V
1.5 V
1.5 V
All Outputs Rise/Fall Time
2.4 V
0.4 V
OUTPUT
3.3 V
2.4 V
0.4 V
t3
0V
t4
Output - Output Skew
1.5 V
OUTPUT
1.5 V
OUTPUT
t5
SDRAM Buffer LH and HL Propagation Delay
INPUT
OUTPUT
t6
t7
Test Circuit
VDD
0.1 µ F
OUTPUTS
CLK Out
CLOAD
GND
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
8 of 13
ASM2I2318ANZ
June 2005
rev 0.3
Application Circuit
+3.3V
Rs
CPUCLK
VDD
BUF_IN
0.1ụF
VDDiic
0.1ụF
SDRAM(0:17)
SDATA
SCLK
VDDiic
Rs
SDRAM(0:17)
Ct
VSS
ASM2I2318ANZ
48-Pin SSOP
Rs = Series termination resistor
Ct = Optional cap to reduce EMI
Summary
•
Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of
•
The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic
0.1µF. In some cases, smaller value capacitors may be required.
impedance of the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating
resistor.
Rseries > Rtrace – Rout
•
Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating
resistor as is physically possible. Typical values of these capacitors range from 4.7pF to 22pF.
•
A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead
offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions.
•
If a Ferrite Bead is used, a 10µF–22µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This
capacitor prevents power supply droop during current surges.
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
9 of 13
ASM2I2318ANZ
June 2005
rev 0.3
IIC Serial Interface Information
The information in this section assumes familiarity with IIC programming.
How to program ASM2I2318ANZ through IIC:
•
Master (host) sends a start bit.
•
Master (host) sends the write address D3 (H).
•
ASM2I2318ANZ device will acknowledge.
•
Master (host) sends the Command Byte.
•
ASM2I2318ANZ device will acknowledge the Command Byte.
•
Master (host) sends a Byte count
•
ASM2I2318ANZ device will acknowledge the Byte count.
•
Master (host) sends the Byte 0
•
ASM2I2318ANZ device will acknowledge Byte 0
•
Master (host) sends the Byte 1
•
ASM2I2318ANZ device will acknowledge Byte 1
•
Master (host) sends the Byte 2
•
ASM2I2318ANZ device will acknowledge Byte 2
•
Master (host) sends a Stop bit.
Controller (Host)
ASM2I2318ANZ
(slave/receiver)
Start Bit
Slave Address D3(H)
ACK
Command Byte
ACK
Byte count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Stop Bit
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
10 of 13
ASM2I2318ANZ
June 2005
rev 0.3
Package Information
48L SSOP Package (300 mil)
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
0.095
0.110
2.413
2.794
A1
0.008
0.016
0.203
0.406
B
0.008
0.012
0.203
0.305
C
0.005
0.009
0.127
0.228
D
0.620
0.630
15.75
16.002
E
0.291
0.299
7.39
7.59
H
0.395
0.420
10.033
10.67
L
0.020
0.040
0.508
1.016
e
α
0.025 BSC
0°
0.635 BSC
8°
0°
8°
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
11 of 13
ASM2I2318ANZ
June 2005
rev 0.3
Ordering Information
Ordering Code
Marking
Package Type
Operating Range
ASM2I2318ANZ-48-AT
2I2318ANZ
48 Pin SSOP, Tube
Industrial
ASM2I2318ANZ-48-AR
2I2318ANZ
48 Pin SSOP, Tape and Reel
Industrial
ASM2I2318AGNZ-48-AT
2I2318AGNZ
48 Pin SSOP, Tube, Green
Industrial
ASM2I2318AGNZ-48-AR
2I2318AGNZ
48 Pin SSOP, Tape and Reel, Green
Industrial
Device Ordering Information
A S M 2 I 2 3 1 8 A N Z G - 4 8 - A R
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
12 of 13
ASM2I2318ANZ
June 2005
rev 0.3
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM2I2318ANZ
Document Version: 0.3
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).
All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any
other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
18 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
13 of 13
Similar pages