ALSC ASM2I99456G-32-ER 3.3v/2.5v lvcmos clock fanout buffer Datasheet

ASM2I99456
June 2005
rev 0.2
3.3V/2.5V LVCMOS Clock Fanout Buffer
Features
ƒ
Configurable
specified for the extended temperature range of –40 to
10
outputs
LVCMOS
Clock
distribution buffer
ƒ
Compatible to single, dual and mixed 3.3V/2.5V
85°C.
The ASM2I99456 is a full static design supporting clock
Voltage supply
frequencies up to 250 MHz. The signals are generated and
ƒ
Wide range output clock frequency up to
retimed on-chip to ensure minimal skew between the three
250MHz
output banks.
ƒ
Designed for mid-range to high-performance
telecom, networking and computer applications
ƒ
ƒ
Supports high-performance differential clocking
by 2.5V or 3.3V supporting mixed voltage applications. The
applications
FSELx pins choose between division of the input reference
Max. output skew of 200pS
frequency by one or two. The frequency divider can be set
(150pS within one bank)
individually for each of the three output banks. The
ƒ
Selectable output configurations per output bank
ƒ
Tristatable outputs
ƒ
32 LQFP and TQFP Packages
ƒ
Ambient Operating temperature range of
-40 to 85°C
ƒ
Each of the three output banks can be individually supplied
ASM2I99456 can be reset and the outputs are disabled by
deasserting the MR/OE pin (logic high state). Asserting
MR/OE will enable the outputs.
All control inputs accept LVCMOS signals while the outputs
Pin and Function compatible to MPC9456
provide LVCMOS compatible levels with the capability to
drive terminated 50Ω transmission lines. The clock input is
Functional Description
The ASM2I99456 is a 2.5V and 3.3V compatible 1:10 clock
distribution buffer designed for low-Voltage mid-range to
high-performance telecom, networking and computing
applications. Both 3.3V, 2.5V and dual supply voltages are
supported for mixed-voltage applications. The ASM2I99456
offers 10 low-skew outputs and a differential LVPECL clock
input. The outputs are configurable and support 1:1 and 1:2
low
voltage
PECL
compatible
for
differential
clock
distribution support. Please consult the ASM2I99446
specification for a full CMOS compatible device. For series
terminated transmission lines, each of the ASM2I99456
outputs can drive one or two traces giving the devices an
effective fanout of 1:20. The device is packaged in a
7x7 mm2 32-lead LQFP and TQFP Packages.
output to input frequency ratios. The ASM2I99456 is
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
ASM2I99456
June 2005
rev 0.2
Block Diagram
Bank A
PCLK
CLK
0
CLK÷ 2
1
25K
PCLK
QA0
QA1
VCC/2
QA2
25K
Bank B
QB0
0
QB1
1
QB2
FSELA
QC0
25K
Bank C
FSELB
QC1
0
25K
1
FSELC
QC2
25K
MR/OE
QC3
25K
ASM2I99456 Logic Diagram
GND
QB0
VCCB
QB1
GND
QB2
VCCB
VCCC
Pin Configuration
24
23
22
21
20
19
18
17
VCCB is internally connected to VCC
VCCA
25
16
QC3
QA2
26
15
GND
GND
27
14
QC2
QA1
28
13
VCCC
VCCA
29
12
QC1
QA0
30
11
GND
GND
31
10
QC0
MR/OE
32
ASM2I99456
2
3
4
5
6
7
8
NC
VCC
PECL_CLK
PCL_CLK
FSELA
FSELB
FSELC
GND
9
1
VCCC
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
2 of 14
ASM2I99456
June 2005
rev 0.2
Table 1. Pin Configuration
Pin Number
Pin
3
4
5,6,7
32
8,11,15,20,24,27,31
25,29
18,22
9,13, 17
2
30,28,26
I/O
Type
Function
PECL_CLK,
PECL_CLK
Input
LVPECL
Differential Clock reference
Low Voltage positive ECL input
FSELA, FSELB,
FSELC
Input
LVCMOS
Output bank divide select input
Input
LVCMOS
Internal reset and output tristate control
Supply
Negative Voltage supply output bank (GND)
Supply
Positive Voltage supply for output banks
Supply
Positive Voltage supply core (VCC)
Bank A Outputs
MR/OE
GND
VCCA,
VCCB1,
VCCC
VCC
QA0 - QA2
Output
LVCMOS
23,21,19
QB0 - QB2
Output
LVCMOS
Bank B Outputs
10,12,14,16
QC0 - QC3
Output
LVCMOS
Bank C Outputs
1
NC
-
-
No Connect
Note:1 VCCB is internally connected to VCC.
Table 2. Supported Single and Dual Supply Configurations
Supply voltage
configuration
VCC1
VCCA2
VCCB3
VCCC4
GND
3.3V
3.3V
3.3V
3.3V
0V
Mixed voltage supply
3.3V
3.3V or 2.5V
3.3V
3.3V or 2.5V
0V
2.5V
2.5V
2.5V
2.5V
2.5V
0V
3.3V
Note: 1 VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels
2 VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels
3 VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC.
4 VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels
Table 3. Function Table (Controls)
Control
FSELA
FSELB
FSELC
MR/OE
Default
0
0
0
0
fQA0:2 = fREF
fQB0:2 = fREF
fQC0:3 = fREF
0
Outputs enabled
1
fQA0:2 = fREF ÷2
fQB0:2 = fREF ÷2
fQC0:3 = fREF ÷2
Internal reset
Outputs disabled (tristate)
Table 4. Absolute Maximum Ratings1
Symbol
Characteristics
Min
Max
Unit
VCC
Supply Voltage
-0.3
4.6
V
VIN
DC Input Voltage
-0.3
VCC+0.3
V
DC Output Voltage
-0.3
VCC+0.3
V
DC Input Current
±20
mA
DC Output Current
±50
mA
125
°C
VOUT
IIN
IOUT
TS
Storage temperature
-40
Condition
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
3 of 14
ASM2I99456
June 2005
rev 0.2
Table 5. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
VTT
Output Termination Voltage
VCC ÷2
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
2000
V
LU
Latch–Up Immunity
200
mA
CPD
Power Dissipation Capacitance
10
pF
CIN
Input Capacitance
4.0
pF
Condition
V
Per output
Table 6. DC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, TA = –40 to +85°C)
Symbol
Characteristics
Min
VIH
VIL
Input high voltage
Input low voltage
VPP
Peak-to-peak input voltage
PCLK
250
Common Mode Range
PCLK
1.1
VCMR1
IIN
VOH
Input current
Typ
2.0
-0.3
2
Output High Voltage
Max
Unit
VCC + 0.3
0.8
V
Output Low Voltage
ZOUT
ICCQ4
Output impedance
Maximum Quiescent Supply Current
V
LVCMOS
LVCMOS
mV
LVPECL
VCC-0.6
V
200
µA
V
LVPECL
VIN=GND or
VIN=VCC
IOH=-24 mA3
0.55
0.30
V
V
IOL= 24mA2
IOL= 12mA
2.0
Ω
mA
2.4
VOL
Condition
14 - 17
All VCC Pins
Note: 1 VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input
swing lies within the VPP (DC) specification.
2 Input pull-up / pull-down resistors influence input current.
3 The ASM2I99456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to
a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
4 ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
4 of 14
ASM2I99456
June 2005
rev 0.2
Table 7. AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, TA = –40 to +85°C)1
Symbol
Characteristics
fref
Input Frequency
fMAX
Maximum Output
Frequency
VPP
Min
÷1 output
÷2 output
Peak-to-peak input voltage
PCLK
VCMR3
Common Mode Range
PCLK
tP, REF
Reference Input Pulse Width
tr, tf
tPLH
tPHL
tPLZ, HZ
PCLK Input Rise/Fall Time
tPZL, LZ
tsk(O)
tsk(PP)
Max
Unit
Condition
0
Typ
2502
0
0
2502
125
500
1000
MHz
MHz
MHz
mV
FSELx=0
FSELx=1
LVPECL
1.3
VCC-0.8
V
LVPECL
1.4
nS
1.04
Output Disable Time
10
nS
nS
nS
nS
Output Enable Time
Output-to-output Skew
10
nS
150
200
350
pS
pS
pS
2.25
nS
200
pS
53
55
%
%
DCREF = 50%
DCREF = 25%-75%
1.0
nS
0.55 to 2.4V
CCLK to any Q
CCLK to any Q
Propagation delay
2.2
2.2
2.8
2.8
4.45
4.2
Within one bank
Any output bank, same output divider
Any output, Any output divider
Device-to-device Skew
5
tSK(P)
Output pulse skew
DCQ
Output Duty Cycle
tr, tf
Output Rise/Fall Time
÷1 output
÷2 output
47
45
50
50
0.1
0.8 to 2.0V
Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT.
2 The ASM2I99456 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250 MHz.
3 VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input
swing lies within the VPP (AC) specification.
4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
5 Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
Table 8. DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, TA = –40 to +85°C)
Symbol
Characteristics
Min
VIH
VIL
Input high voltage
VPP
Peak-to-peak Input voltage
PCLK
Common Mode Range
PCLK
Input low voltage
VCMR1
VOH
Output High Voltage
VOL
Output Low Voltage
ZOUT
IIN
ICCQ
4
Typ
1.7
-0.3
Max
Unit
VCC + 0.3
0.7
V
V
mV
LVPECL
V
LVPECL
V
IOH=-24 mA 2
0.6
V
IOL= 15 mA
±200
µA
mA
250
1.1
VCC-0.7
1.8
2
Output impedance
17 - 20
Input current3
Maximum Quiescent Supply Current
Condition
LVCMOS
LVCMOS
Ω
2.0
VIN=GND or VIN=VCC
All VCC Pins
Note:1 VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input
swing lies within the VPP (DC) specification.
2 The ASM2I99456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
3 Input pull-up / pull-down resistors influence input current.
4 ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
5 of 14
ASM2I99456
June 2005
rev 0.2
Table 9. AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, TA = –40 to +85°C)1
Symbol
fref
fMAX
Characteristics
Input Frequency
÷1 output
÷2 output
Maximum Output Frequency
VPP
Min
0
Typ
0
0
Max
2502
Unit
MHz
Condition
2502
125
MHz
MHz
FSELx=0
FSELx=1
Peak-to-peak input voltage
PCLK
500
1000
mV
LVPECL
VCMR
Common Mode Range
PCLK
1.1
VCC-0.7
V
LVPECL
tP, REF
Reference Input Pulse Width
tr, tf
tPLH
tPHL
tPLZ, HZ
PCLK Input Rise/Fall Time
3
tPZL, LZ
tsk(O)
tsk(PP)
tSK(P)
1.4
nS
1.04
nS
5.6
5.5
nS
nS
Output Disable Time
10
nS
Output Enable Time
Output-to-output Skew
10
nS
150
200
350
pS
pS
pS
3.0
nS
200
pS
PCLK to any Q
PCLK to any Q
Propagation delay
2.6
2.6
Within one bank
Any output bank, same output divider
Any output, Any output divider
Device-to-device Skew
5
Output pulse skew
DCQ
Output Duty Cycle
tr, tf
Output Rise/Fall Time
÷1 or ÷2 output
45
50
0.1
0.7 to 1.7V
55
%
DCREF = 50%
1.0
nS
0.6 to 1.8V
Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT.
2 The ASM2I99456 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250 MHz.
3 VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input
swing lies within the VPP (AC) specification.
4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
5 Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
Table 10. AC Characteristics (VCC = 3.3V ± 5%, VCCA = VCCB = VCCC = 2.5V ± 5% or 3.3V ± 5%,TA = –40 to +85°C),1,2
Symbol
Characteristics
tsk(O)
Min
Typ
Max
Unit
Output-to-output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
150
250
350
pS
pS
pS
tsk(PP)
Device-to-device Skew
2.5
nS
tPLH,HL
PCLK to any Q
tSK(P)
Propagation delay
3
Output pulse skew
DCQ
Output Duty Cycle
÷1 or ÷2 output
Condition
See 3.3V table
45
50
250
pS
55
%
DCREF = 50%
Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT.
2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.
3 Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
6 of 14
ASM2I99456
June 2005
rev 0.2
Applications Information
parallel combination of the 36Ω series resistor plus the
output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
Driving Transmission Lines
The ASM2I99456 clock driver was designed to drive high
speed signals in a terminated transmission line
environment. To provide the optimum flexibility to the
user the output drivers were designed to exhibit the
lowest impedance possible. With an output impedance of
less than 20Ω the drivers can drive either parallel or
series terminated transmission lines. In most high
performance clock networks point-to-point distribution of
signals is the method of choice. In a point-to-point
scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a
50Ω resistance to VCC÷2.
ASM2I99456
OUTPUT BUFFER
14Ω
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0nS).
3.0
2.5
VOLTAGE (V)
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the ASM2I99456 clock driver. For the series
terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated
lines. Figure 1. “Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken
to its extreme the fanout of the ASM2I99456 clock driver
is effectively doubled due to its capability to drive multiple
lines.
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50Ω || 50Ω
RS = 36Ω || 36Ω
R0 = 14Ω
VL = 3.0 ( 25 ÷ (18+14+25)
= 1.31V
OutA
tD = 3.8956
OutB
tD = 3.9386
2.0
In
1.5
1.0
0.5
Z0=50Ω
RS=36Ω
0
2
4
6
8
10
12
14
TIME (nS)
ASM2I99456
OUTPUT BUFFER
Z0=50Ω
RS=36Ω
14Ω
RS=36Ω
Z0=50Ω
Figure 1. Single versus Dual Transmission Lines
The waveform plots in Figure 2. “Single versus Dual Line
Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both
cases the drive capability of the ASM2I99456 output
buffer is more than sufficient to drive 50Ω transmission
lines on the incident edge. Note from the delay
measurements in the simulations a delta of only 43pS
exists between the two differently loaded outputs. This
suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of
the ASM2I99456. The output waveform in Figure 2.
“Single versus Dual Line Termination Waveforms” shows
a step in the waveform, this step is caused by the
impedance mismatch seen looking into the driver. The
Figure 2. Single versus Dual Waveforms
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving
multiple lines the situation in Figure 3. “Optimized Dual
Line Termination” should be used. In this case the series
terminating resistors are reduced such that when the
parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
ASM2I99456
OUTPUT BUFFER
RS=22Ω
14Ω
RS=22Ω
Z0=50Ω
Z0=50Ω
14Ω + 22Ω || 22Ω = 50Ω || 50Ω
25Ω = 25Ω
Figure 3. Optimized Dual Line Termination
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
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ASM2I99456
June 2005
rev 0.2
ASM2I99456 DUT
Z0=50Ω
Z0=50Ω
Differential
Pulse Generator
Z=50Ω
RT=50Ω
RT=50Ω
VTT
VCC – 2V
Figure 4. PCLK ASM2I99456 AC Test Reference for VCC = 3.3V and VCC = 2.5V
PCLK
VCC = 3.3V VCC = 2.5V
2.4
PCLK
1.8V
0.55
VCMR
VPP
0.6V
VCC
tR
tF
VCC ÷2
QX
Figure 5. Output Transition Time Test Reference
tP(LH)
GND
tP(HL)
Figure 6. Propagation Delay (tPD) Test Reference
VCC
VCC
VCC ÷2
VCC ÷2
GND
GND
tP
VOH
VCC ÷2
T0
tSK(LH)
DC (tP ÷T0 Χ 100%)
tSK(HL)
The pin-to-pin skew is defined as the worst case
difference in propagation delay between any similar
delay path within a single device
The time from the output controlled edge to the
non-controlled edge, divided by the time output
controlled edge, expressed as a percentage.
Figure 8. Output-to- Output Skew tSK(O)
Figure 7. Output Duty Cycle (DC)
VCC = 3.3V VCC = 2.5V
tF
GND
2.4
1.8V
0.55
0.6V
tR
Figure 9. Output Transition Time Test Reference
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
8 of 14
ASM2I99456
June 2005
rev 0.2
Power Consumption of the ASM2I99456 and
Thermal Management
The ASM2I99456 AC specification is guaranteed for the
entire operating frequency range up to 250MHz. The
ASM2I99456 power consumption and the associated
long-term reliability may decrease the maximum
frequency limit, depending on operating conditions such
as clock frequency, supply voltage, output loading,
ambient temperature, vertical convection and thermal
conductivity of package and board. This section
describes the impact of these parameters on the junction
temperature and gives a guideline to estimate the
ASM2I99456 die junction temperature and the associated
device reliability.
Table 11. Die junction temperature and MTBF
Junction temperature (°C)
MTBF (Years)
100
20.4
110
9.1
120
4.2
130
2.0
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable
MTBF, the die junction temperature of the ASM2I99456
needs to be controlled and the thermal impedance of the
board/package should be optimized. The power
dissipated in the ASM2I99456
is represented in
equation 1.
Where ICCQ is the static current consumption of the
ASM2I99456, CPD is the power dissipation capacitance
per output, (Μ)ΣCL represents the external capacitive
output load, N is the number of active outputs (N is
always 12 in case of the ASM2I99456). The ASM2I99456
supports driving transmission lines to maintain high signal
integrity and tight timing parameters. Any transmission
line will hide the lumped capacitive load at the end of the
board trace, therefore, ΣCL is zero for controlled
transmission line systems and can be eliminated from
equation 1. Using parallel termination output termination
results in equation 2 for power dissipation.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, VOL, IOL, VOH and IOH are
a function of the output termination technique and DCQ is
the clock signal duty cycle. If transmission lines are used
ΣCL is zero in equation 2 and can be eliminated. In
general, the use of controlled transmission line
techniques eliminates the impact of the lumped capacitive
loads at the end lines and greatly reduces the power
dissipation of the device. Equation 3 describes the die
junction temperature TJ as a function of the power
consumption.
Where Rthja is the thermal impedance of the package
(junction to ambient) and TA is the ambient temperature.
According to Table 11, the junction temperature can be
used to estimate the long-term device reliability. Further,
combining equation 1 and equation 2 results in a
maximum operating frequency for the ASM2I99456 in a
series terminated transmission line system, equation 4.
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
9 of 14
ASM2I99456
June 2005
rev 0.2
TJ,MAX should be selected according to the MTBF
system requirements and Table 11. Rthja can be derived
from Table 12. The Rthja represent data based on 1S2P
boards, using 2S2P boards will result in a lower thermal
impedance than indicated below.
Table 12. Thermal package impedance of the
32LQFP
Convection,
LFPM
Still air
100 lfpm
200 lfpm
300 lfpm
400 lfpm
500 lfpm
Rthja (1P2S
board), °C/W
86
76
71
68
66
60
Rthja (2P2S
board), °C/W
61
56
54
53
52
49
If the calculated maximum frequency is below 350 MHz, it
becomes the upper clock speed limit for the given
application conditions. The following eight derating charts
describe the safe frequency operation range for the
ASM2I99456. The charts were calculated for a maximum
tolerable die junction temperature of 110°C (120°C),
corresponding to an estimated MTBF of 9.1 years
(4 years), a supply voltage of 3.3V and series terminated
transmission line or capacitive loading. Depending on a
given set of these operating conditions and the available
device convection a decision on the maximum operating
frequency can be made.
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
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Package Information
32-lead LQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0630
…
1.6
A1
0.0020
0.0059
0.05
0.15
A2
0.0531
0.0571
1.35
1.45
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.20
e
a
0.031 BASE
0°
7°
0.8 BASE
0°
7°
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
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rev 0.2
32-lead TQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0472
…
1.2
A1
0.0020
0.0059
0.05
0.15
A2
0.0374
0.0413
0.95
1.05
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.2
a
0°
7°
0°
7°
e
0.031 BASE
0.8 BASE
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
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rev 0.2
Ordering Information
Part Number
Marking
Package Type
Operating Range
ASM2I99456-32-LT
ASM2I99456L
32-pin LQFP, Tray
Industrial
ASM2I99456-32-LR
ASM2I99456L
32-pin LQFP –Tape and Reel
Industrial
ASM2I99456G-32-LT
ASM2I99456GL
32-pin LQFP, Tray, Green
Industrial
ASM2I99456G-32-LR
ASM2I99456GL
32-pin LQFP –Tape and Reel, Green
Industrial
ASM2I99456-32-ET
ASM2I99456E
32-pin TQFP, Tray
Industrial
ASM2I99456-32-ER
ASM2I99456E
32-pin TQFP –Tape and Reel
Industrial
ASM2I99456G-32-ET
ASM2I99456GE
32-pin TQFP, Tray, Green
Industrial
ASM2I99456G-32-ER
ASM2I99456GE
32-pin TQFP –Tape and Reel, Green
Industrial
Device Ordering Information
A S M 2 I 9 9 4 5 6 G - 3 2 - L R
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
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rev 0.2
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM2I99456
Document Version: 0.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
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assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
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