ALSC ASM3P2508SP-08ST Clock synthesizer and frequency generator with peak emi reduction Datasheet

ASM3P2508SP
February 2005
rev 0.4
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Features
The
ƒ
Dual PLL based Architecture
ƒ
Operates with a 3.3V ±0.3V supply.
ƒ
Generates an EMI optimized Spread Spectrum
uses
the
most
efficient
and
ASM3P2508SP modulates the output of a PLL in order to
“spread” the bandwidth of a synthesized clock, and more
importantly, decreases the peak amplitudes of its
PCI Clock output
harmonics. This results in a significantly lower system
Generates a high accuracy non Spread T1 clock of
ƒ
ASM3P2508SP
optimized modulation profile approved by the FCC.
EMI compared to the typical narrow band signal produced
±25ppm accuracy.
ƒ
Generates a non spread system reference clock
ƒ
Low power CMOS design.
ƒ
Input frequency: 25 MHz.
ƒ
Outputs:
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’ (SSCG).
In
Sys_ REF_CLK: 20 MHz
addition
to
the
SSCG
output,
ASM3P2508SP
generates two high accuracy clock signals -
T1 Clock: 25 MHz (±25 ppm)
T1 Clock @ 25.00MHz with +/- 25ppm stability, and a
PCI_CLK: 33.33MHz Spread Spectrum
20MHz Sys_ REF_CLK.
ƒ
Frequency deviation: -0.5% (Typ).
ƒ
Available in 8L SOIC Package.
Applications
The ASM3P2508SP is targeted towards Consumer,
Product Description
Industrial, Data and Telecommunications applications.
The ASM3P2508SP is a versatile Dual PLL based Clock
Synthesizer and Frequency Generator optimised and
Key Specifications
designed specifically for three clock frequencies. The
PCI_CLK
output
from
ASM3P2508SP
reduces
Description
Specification
electromagnetic interference (EMI) at the clock source,
Supply voltages
VDD = 3.3V ±0.3V
allowing system wide reduction of EMI of all clock
Input Frequency
25 MHz
dependent signals. ASM3P2508SP allows significant
Cycle-to-Cycle Jitter
175 pS ( Max)
system cost savings by reducing the number of circuit
Output Duty Cycle
45/55%
Output Rise and Fall Time
1.1 nS (Max)
SSC Modulation Rate
30KHz (Typ)
SSC Frequency Deviation
-0.5% (Typ)
board
layers,
ferrite
beads
&
shielding
that
are
traditionally required to pass EMI regulations.
Block Diagram
PWRDNB
T1_CLK
Input
Divider
VDD
PLL 1
Output
Divider
Sys_REF_CLK
XIN/CLKIN
Osc
XOUT
PLL 2
Output
Divider
PCI_CLK
Modulation
VSS
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
February 2005
ASM3P2508SP
rev 0.4
Pin Configuration
8
T1_CLK
7
VSS
VDD 3
6
PCI_CLK
Sys_REF_CLK 4
5
PWRDNB
XIN/CLKIN
1
XOUT 2
ASM3P2508SP
Pin Description
Pin#
Pin Name
Type
Description
1
XIN/CLKIN
I
Crystal connection or external reference frequency input. This pin has dual functions.
It can be connected either to an external crystal or an external reference clock.
2
XOUT
O
Crystal connection. If using an external reference, this pin must be left unconnected.
3
VDD
P
Power supply for the entire chip
4
Sys_REF_CLK
O
PLL 1 output System Reference Clock @ 20MHz
5
PWRDNB
I
Power-down control pin. Pull low to enable power-down mode. Connect to VDD if not
used. Power -down Mode shuts off all the Outputs.
6
PCI_CLK
O
PLL 2 Spread spectrum clock output @ 33.33MHz
7
VSS
P
Ground to entire chip. Connect to system ground
8
T1_CLK
O
Reference output T1 Clock @ 25MHz
Typical Modulation Profile
Absolute Maximum Ratings
Symbol
Parameter
VDD, VIN
TSTG
Rating
Unit
Voltage on any pin with respect to Ground
-0.5 to +7.0
V
Storage temperature
-65 to +125
°C
TA
Operating temperature
0 to 70
°C
Ts
Max. Soldering Temperature (10 sec)
260
°C
TJ
Junction Temperature
150
°C
TDV
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
2
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Notice: The information in this document is subject to change without notice.
2 of 7
February 2005
ASM3P2508SP
rev 0.4
DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated)
Symbol
Parameter
Min
Typ
Max
Unit
VIL
Input low voltage
VSS - 0.3
–
0.8
V
VIH
Input high voltage
2.0
–
VDD + 0.3
V
IIL
Input low current
–
–
-35
µA
IIH
Input high current
–
–
35
µA
IXOL
XOUT output low current (@0.4V, VDD=3.3V)
–
3
–
mA
IXOH
XOUT output high current (@2.5V, VDD=3.3V)
–
3
–
mA
VOL
Output low voltage (VDD = 3.3 V, IOL = 20 mA)
–
–
0.4
V
VOH
Output high voltage (VDD = 3.3 V, IOH = 20 mA)
2.5
–
–
V
IDD
–
–
10
µA
–
20
_
mA
VDD
Static supply current *
Dynamic supply current
(3.3V, 33.33MHz, 25MHz , 20MHz and 15pF loading)
Operating voltage
3.0
3.3
3.6
V
tON
Power-up time (first locked cycle after power up)**
–
–
5
mS
Clock output impedance
–
50
–
Ω
ICC
ZOUT
* PWRDNB pin is pulled low
** VDD and XIN/CLKIN input are stable, PWRDNB pin is made high from low.
AC Electrical Characteristics
Symbol
Min
Typ
Max
Unit
–
25
–
MHz
–
33.33
–
MHz
24.999375
25
25.000625
–
20
–
tLH*
Modulation Rate
Deviation
Output rise time (measured at 0.8V to 2.0V)
–
–
0.7
30
-0.5
0.9
–
–
1.0
KHz
%
nS
tHL*
Output fall time (measured at 2.0V to 0.8V)
0.6
0.8
1.0
nS
tJC
Jitter (cycle to cycle)
–
150
175
pS
tD
Output duty cycle
45
50
55
%
XIN
Parameter
Input frequency
PCI_CLK
Output frequency
T1_CLK
Sys_REF_CLK
PCI_CLK (SSCG)
MHz
* tLH and tHL are measured into a capacitive load of 15pF
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Notice: The information in this document is subject to change without notice.
3 of 7
February 2005
ASM3P2508SP
rev 0.4
Typical Crystal Oscillator Circuit
R1 = 510Ω
Crystal
C1 = 27 pF
C2 = 27 pF
Typical Crystal Specifications
Fundamental AT cut parallel resonant crystal
Nominal frequency
25 MHz
Frequency tolerance
± 25 ppm or better at 25°C
Operating temperature range
-25°C to +85°C
Storage temperature
-40°C to +85°C
Load capacitance
18pF
Shunt capacitance
7pF maximum
ESR
25 Ω
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Notice: The information in this document is subject to change without notice.
4 of 7
February 2005
ASM3P2508SP
rev 0.4
Package Information
8-lead (150-mil) SOIC Package
H
E
D
A2
A
C
A1
D
θ
e
L
B
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A1
0.004
0.010
0.10
0.25
A
0.053
0.069
1.35
1.75
A2
0.049
0.059
1.25
1.50
B
0.012
0.020
0.31
0.51
C
0.007
0.010
0.18
0.25
D
0.193 BSC
4.90 BSC
E
0.154 BSC
3.91 BSC
e
0.050 BSC
1.27 BSC
H
0.236 BSC
6.00 BSC
L
0.016
0.050
0.41
1.27
θ
0°
8°
0°
8°
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Notice: The information in this document is subject to change without notice.
5 of 7
February 2005
ASM3P2508SP
rev 0.4
Ordering Information
Part Number
Marking
ASM3P2508SP-08ST
3P2508SP
8-Pin SOIC, TUBE
Commercial
ASM3P2508SP-08SR
3P2508SP
8-Pin SOIC, TAPE & REEL
Commercial
ASM3P2508SPF-08ST
3P2508SPF
8-Pin SOIC, TUBE, Pb free
Commercial
ASM3P2508SPF-08SR
3P2508SPF
8-Pin SOIC, TAPE & REEL, Pb free
Commercial
ASM3I2508SP-08ST
3I2508SP
8-Pin SOIC, TUBE
Industrial
3I2508SP
8-Pin SOIC, TAPE & REEL
Industrial
ASM3I2508SPF-08ST
3I2508SPF
8-Pin SOIC, TUBE, Pb free
Industrial
ASM3I2508SPF-08SR
3I2508SPF
8-Pin SOIC, TAPE & REEL, Pb free
Industrial
ASM3I2508SP-08SR
Package Type
Temperature
Device Ordering Information
A S M 3 P 2 5 0 8 S P F - 0 8 T R
OR - TSOT23 -6, T/R
TT – TSSOP, TUBE
TR - TSSOP, T/R
VT – TVSOP, TUBE
VR – TVSOP, T/R
ST – SOIC, TUBE
AR - SSOP, T/R
AT – SSOP, TUBE
SR - SOIC, T/R
QR – QFN, T/R
QT - QFN, TRAY
BT - BGA, TRAY
BR – BGA, T/R
UR - SOT-23,T/R
DR - QSOP, T/R
DT – QSOP, TUBE
PIN COUNT
LEAD FREE PART
PART NUMBER
X = Automotive
I = Industrial P or n/c = Commercial
(-40C to +125C)
(-40C to +85C)
(0C to +70C)
1 – reserved
2- Non PLL based
3 – EMI Reduction
4 – DDR support products
5 – STD Zero Delay Buffer
6 – power management
7 – power management
8 – power management
9 – Hi performance
0 - reserved
Alliance Semiconductor Mixed Signal Product
Licensed under U.S Patent #s 5,488,627 and 5,631,921
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Notice: The information in this document is subject to change without notice.
6 of 7
February 2005
ASM3P2508SP
rev 0.4
Alliance Semiconductor Corporation
2595, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: ASM3P2508SP
Document Version: v0.4
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2004 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
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companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance
assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's
best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time,
without notice. If the product described herein is under development, significant changes to these specifications are possible.
The information in this product data sheet is intended to be general descriptive information for potential customers and users,
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Clock Synthesizer and Frequency Generator with Peak EMI reduction
Notice: The information in this document is subject to change without notice.
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