ON ASM3P622S00EG-16-TR Low frequency peak emi reduction ic Datasheet

ASM3P622S00B,
ASM3P622S00E
Product Preview
Low Frequency
TIMINGSAFEt Peak EMI
Reduction IC
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Description
ASM3P622S00B/E is a versatile, 3.3 V Zero−delay buffer designed
to distribute low frequency Timing−Safe clocks with Peak EMI
reduction. ASM3P622S00B is an eight−pin version, accepts one
reference input and drives out one low−skew Timing−Safe clock.
ASM3P622S00E accepts one reference input and drives out eight
low−skew Timing−Safe clocks.
ASM3P622S00B/E has an SS% that selects 2 different Deviation
and associated Input−Output Skew (TSKEW). Refer to Spread
Spectrum Control and Input−Output Skew table for details.
ASM3P622S00E has a CLKOUT for adjusting the Input−Output
clock delay, depending upon the value of capacitor connected at this
pin to GND.
ASM3P622S00B/E operates from a 3.3 V supply and is available in
two different packages, as shown in the ordering information table,
over commercial and Industrial temperature range.
Application
ASM3P622S00B/E is targeted for use in Displays and memory
interface systems.
TSSOP−8
T SUFFIX
CASE 948AL
SOIC−8
S SUFFIX
CASE 751BD
TSSOP−16
T SUFFIX
CASE 948AN
SOIC−16
S SUFFIX
CASE 751BG
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Features
• Low Frequency Clock Distribution with Timing−Safe Peak EMI
•
•
•
•
•
•
•
•
•
Reduction
Input Frequency Range: 4 MHz − 20 MHz
2 Different Spread Selection Options
Spread Spectrum can be Turned ON/OFF
External Input−Output Delay Control Option
Supply Voltage: 3.3 V ± 0.3 V
Commercial and Industrial Temperature Range
Packaging Information:
ASM3P622S00B: 8 pin SOIC, and TSSOP
ASM3P622S00E: 16 pin SOIC, and TSSOP
The First True Drop−in Solution
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. P2
1
Publication Order Number:
ASM3P622S00/D
ASM3P622S00B, ASM3P622S00E
DLY_CTRL
VDD
SS%
CLKOUT(s)*
(Timing−Safe)
CLKIN
PLL
SSON
*For ASM3P622S00E −
8 CLKOUTS
GND
Figure 1. General Block Diagram
Spread Spectrum Frequency Generation
Zero Delay and Skew Control
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the edge
rates also get faster. Analysis shows that a square wave is
composed of fundamental frequency and harmonics. The
fundamental frequency and harmonics generate the energy
peaks that become the source of EMI. Regulatory agencies
test electronic equipment by measuring the amount of peak
energy radiated from the equipment. In fact, the peak level
allowed decreases as the frequency increases. The standard
methods of reducing EMI are to use shielding, filtering,
multi−layer PCBs, etc. These methods are expensive.
Spread spectrum clocking reduces the peak energy by
reducing the Q factor of the clock. This is done by slowly
modulating the clock frequency. The ASM3P622S00B/E
uses the center modulation spread spectrum technique in
which the modulated output frequency varies above and
below the reference frequency with a specified modulation
rate. With center modulation, the average frequency is the
same as the unmodulated frequency and there is no
performance degradation.
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input−output delay.
For applications requiring zero input−output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero input−output
delay.
Timing−Safe Technology
Timing−Safe technology is the ability to modulate a clock
source with Spread Spectrum technology and maintain
synchronization with any associated data path.
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ASM3P622S00B, ASM3P622S00E
Pin Configuration for ASM3P622S00B
CLKIN
1
NC
2
8
NC
7
VDD
ASM3P622S00B
SS%
3
6
CLKOUT
GND
4
5
SSON
Table 1. PIN DESCRIPTION FOR ASM3P622S00B
1.
2.
3.
4.
Pin #
Pin Name
Type
1
CLKIN (Note 1)
I
Description
2
NC
3
SS% (Note 3)
I
Spread Spectrum Selection. Has an internal pull up resistor
4
GND
P
Ground
5
SSON (Note 3)
I
Spread Spectrum enable and disable option. When SSON is HIGH, the spread spectrum
is enabled and when LOW, it turns off the spread spectrum. Has an internal pull up resistor.
6
CLKOUT (Note 2)
O
Buffered clock output (Note 4)
7
VDD
P
3.3 V supply
8
NC
External reference Clock input , 5 V tolerant input
No Connect
No Connect
Weak pull down
Weak pull−down on all outputs
Weak pull−up on these Inputs
Buffered clock output is Timing−Safe
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ASM3P622S00B, ASM3P622S00E
Pin Configuration for ASM3P622S00E
CLKIN
1
16
CLKOUT
CLKOUT1
2
15
CLKOUT7
VDD
3
14
CLKOUT6
SS%
4
13
VDD
GND
5
12
GND
CLKOUT2
6
11
CLKOUT5
CLKOUT3
7
10
CLKOUT4
DLY_CTRL
8
9
SSON
ASM3P622S00E
Table 2. PIN DESCRIPTION FOR ASM3P622S00E
5.
6.
7.
8.
Pin #
Pin Name
Type
Description
1
CLKIN (Note 5)
I
External reference Clock input, 5 V tolerant input
2
CLKOUT1 (Note 6)
O
Buffered clock output (Note 8)
3
VDD
P
3.3 V supply
4
SS% (Note 7)
I
Spread Spectrum Selection. Refer to Spread Spectrum Control and
Input−Output Skew Table. Has an internal pull up resistor.
5
GND
P
Ground
6
CLKOUT2 (Note 6)
O
Buffered clock output (Note 8)
7
CLKOUT3 (Note 6)
O
Buffered clock output (Note 8)
8
DLY_CTRL
O
External Input−Output Delay control.
9
SSON (Note 7)
I
Spread Spectrum enable and disable option. When SSON is HIGH, the spread spectrum
is enabled and when LOW, it turns off the spread spectrum. Has an internal pull up resistor.
10
CLKOUT4 (Note 6)
O
Buffered clock output (Note 8)
11
CLKOUT5 (Note 6)
O
Buffered clock output (Note 8)
12
GND
P
Ground
13
VDD
P
3.3 V supply
14
CLKOUT6 (Note 6)
O
Buffered clock output (Note 8)
15
CLKOUT7 (Note 6)
O
Buffered clock output (Note 8)
16
CLKOUT (Note 6)
O
Buffered clock output (Note 8)
Weak pull down
Weak pull−down on all outputs
Weak pull−up on these Inputs
Buffered clock output is Timing−Safe
Table 3. SPREAD SPECTRUM CONTROL AND INPUT−OUTPUT SKEW TABLE
Device
Input Frequency
SS %
Deviation
Input−Output Skew (±TSKEW)
ASM3P622S00B/E
12 MHz
0
±0.25 %
0.0625 (Note 9)
1
±0.50 %
0.125 (Note 9)
9. TSKEW is measured in units of the Clock Period
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ASM3P622S00B, ASM3P622S00E
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDD
Supply Voltage to Ground Potential
VIN
DC Input Voltage (CLKIN)
TSTG
Storage temperature
Rating
Unit
−0.5 to +4.6
V
−0.5 to +7
V
−65 to +125
°C
Ts
Max. Soldering Temperature (10 sec)
260
°C
TJ
Junction Temperature
150
°C
2
KV
TDV
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. OPERATING CONDITIONS
Parameter
Min
Max
Unit
Supply Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
−40
+85
°C
CL
Load Capacitance
30
pF
CIN
Input Capacitance
7
pF
VDD
Description
Table 6. ELECTRICAL CHARACTERISTICS
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
0.8
V
VIL
Input LOW Voltage (Note 10)
VIH
Input HIGH Voltage (Note 10)
IIL
Input LOW Current
VIN = 0 V
50
mA
IIH
Input HIGH Current
VIN = VDD
100
mA
Output LOW Voltage (Note 11)
IOL = 8 mA
0.4
V
18
mA
VOL
2.0
VOH
Output HIGH Voltage (Note 11)
IOH = −8 mA
IDD
Supply Current
Unloaded outputs
Zo
Output Impedance
V
2.4
V
23
W
10. CLKIN input has a threshold voltage of VDD/2
11. Parameter is guaranteed by design and characterization. Not 100% tested in production
Table 7. SWITCHING CHARACTERISTICS FOR ASM3P622S00B/E
Parameter
Test Conditions
Input Frequency
Min
Typ
4
Max
Unit
20
MHz
20
MHz
60
%
Output Frequency
30 pF load
4
Duty Cycle = (t2 / t1) * 100 (Notes 12, 13)
Measured at VDD/2
40
Output Rise Time (Notes 12, 13)
Measured between 0.8 V and 2.0 V
2.5
nS
Output Fall Time (Notes 12, 13)
Measured between 2.0 V and 0.8 V
2.5
nS
Output−to−output skew (Notes 12, 13)
All outputs equally loaded with SSOFF
250
pS
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge (Note 13)
Measured at VDD/2 with SSOFF
±350
pS
Device−to−Device Skew (Note 13)
Measured at VDD/2 on the CLKOUT
pins of the device
700
pS
Cycle−to−Cycle Jitter
(Notes 12, 13)
Loaded outputs
< 8 MHz
±1.6
nS
> 8 MHz
±200
pS
PLL Lock Time (Note 13)
Stable power supply, valid clock
presented on CLKIN pin
1.0
mS
12. All parameters specified with 30 pF loaded outputs.
13. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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50
ASM3P622S00B, ASM3P622S00E
Switching Waveforms
t1
t2
VDD/2
VDD/2
VDD/2
OUTPUT
Figure 2. Duty Cycle Timing
2V
2V
OUTPUT
0.8 V
0.8 V
t3
t4
Figure 3. All Outputs Rise/Fall Time
VDD/2
OUTPUT
VDD/2
OUTPUT
t5
Figure 4. Output − Output Skew
VDD/2
INPUT
VDD/2
OUTPUT
t6
Figure 5. Input − Output Propagation Delay
VDD/2
CLKOUT, Device 1
VDD/2
CLKOUT, Device 2
t7
Figure 6. Device − Device Skew
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3.3 V
0V
ASM3P622S00B, ASM3P622S00E
Input
+3.3 V
Timing−Safe
Output
VDD
0.1 mF
TSKEW−
OUTPUT
+3.3 V
TSKEW+
LOAD
VDD
0.1 mF
One clock cycle
N=1
TSKEW represents input−output
skew when spread spectrum is ON
For example, TSKEW = ±0.125 for an Input
clock 12 MHz, translates in to
(1/12 MHz) * 0.125 = 10.41 nS
GND
Figure 8. Test Circuit
Figure 7. Input − Output Skew
Figure 9. Typical Example of Timing−Safe Waveform
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CLKOUT
ASM3P622S00B, ASM3P622S00E
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
A
E1
E
MAX
1.20
A1
0.05
A2
0.80
b
0.19
0.30
c
0.09
0.20
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
0.15
0.90
e
0.65 BSC
L
1.00 REF
L1
0.50
θ
0º
0.60
1.05
0.75
8º
e
TOP VIEW
D
A2
c
q1
A
A1
L1
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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ASM3P622S00B, ASM3P622S00E
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
MAX
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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ASM3P622S00B, ASM3P622S00E
PACKAGE DIMENSIONS
SOIC−16, 150 mils
CASE 751BG−01
ISSUE O
SYMBOL
E1
E
MIN
NOM
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
9.80
9.90
10.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
1.27 BSC
e
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
PIN#1 IDENTIFICATION
TOP VIEW
D
h
q
A
e
b
A1
c
L
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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ASM3P622S00B, ASM3P622S00E
PACKAGE DIMENSIONS
TSSOP16, 4.4x5
CASE 948AN−01
ISSUE O
b
SYMBOL
MIN
NOM
A
E1 E
MAX
1.10
A1
0.05
0.15
A2
0.85
0.95
b
0.19
0.30
c
0.13
0.20
D
4.90
5.10
E
6.30
6.50
E1
4.30
4.50
e
0.65 BSC
L
1.00 REF
L1
0.45
0.75
θ
0º
8º
e
PIN#1
IDENTIFICATION
TOP VIEW
D
A2
A
c
θ1
A1
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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L
ASM3P622S00B, ASM3P622S00E
Table 8. ORDERING INFORMATION
Part Number
Marking
Package Type
Temperature
ASM3P622S00BF−08−ST
3P622S00BF
8−pin 150−mil SOIC−TUBE, Pb Free
Commercial
ASM3I622S00BF−08−ST
3I622S00BF
8−pin 150−mil SOIC−TUBE, Pb Free
Industrial
ASM3P622S00BF−08−SR
3P622S00BF
8−pin 150−mil SOIC−TAPE & REEL, Pb Free
Commercial
ASM3I622S00BF−08−SR
3I622S00BF
8−pin 150−mil SOIC−TAPE & REEL, Pb Free
ASM3P622S00BF−08−TT
3P622S00BF
8−pin 4.4−mm TSSOP − TUBE, Pb Free
Commercial
Industrial
ASM3I622S00BF−08−TT
3I622S00BF
8−pin 4.4−mm TSSOP − TUBE, Pb Free
Industrial
ASM3P622S00BF−08−TR
3P622S00BF
8−pin 4.4−mm TSSOP − TAPE & REEL, Pb Free
Commercial
ASM3I622S00BF−08−TR
3I622S00BF
8−pin 4.4−mm TSSOP − TAPE & REEL, Pb Free
Industrial
ASM3P622S00EF−16−ST
3P622S00EF
16−pin 150−mil SOIC−TUBE, Pb Free
Commercial
ASM3I622S00EF−16−ST
3I622S00EF
16−pin 150−mil SOIC−TUBE, Pb Free
ASM3P622S00EF−16−SR
3P622S00EF
16−pin 150−mil SOIC−TAPE & REEL, Pb Free
Commercial
ASM3I622S00EF−16−SR
3I622S00EF
16−pin 150−mil SOIC−TAPE & REEL, Pb Free
Industrial
ASM3P622S00EF−16−TT
3P622S00EF
16−pin 4.4−mm TSSOP − TUBE, Pb Free
Commercial
ASM3I622S00EF−16−TT
3I622S00EF
16−pin 4.4−mm TSSOP − TUBE, Pb Free
Industrial
ASM3P622S00EF−16−TR
3P622S00EF
16−pin 4.4−mm TSSOP − TAPE & REEL, Pb Free
ASM3I622S00EF−16−TR
3I622S00EF
16−pin 4.4−mm TSSOP − TAPE & REEL, Pb Free
ASM3P622S00BG−08−ST
3P622S00BG
8−pin 150−mil SOIC−TUBE, Pb Free
Commercial
ASM3I622S00BG−08−ST
3I622S00BG
8−pin 150−mil SOIC−TUBE, Pb Free
Industrial
ASM3P622S00BG−08−SR
3P622S00BG
8−pin 150−mil SOIC−TAPE & REEL, Pb Free
Commercial
ASM3I622S00BG−08−SR
3I622S00BG
8−pin 150−mil SOIC−TAPE & REEL, Pb Free
Industrial
ASM3P622S00BG−08−TT
3P622S00BG
8−pin 4.4−mm TSSOP − TUBE, Pb Free
Commercial
ASM3I622S00BG−08−TT
3I622S00BG
8−pin 4.4−mm TSSOP − TUBE, Pb Free
Industrial
ASM3P622S00BG−08−TR
3P622S00BG
8−pin 4.4−mm TSSOP − TAPE & REEL, Pb Free
Commercial
ASM3I622S00BG−08−TR
3I622S00BG
8−pin 4.4−mm TSSOP − TAPE & REEL, Pb Free
Industrial
ASM3P622S00EG−16−ST
3P622S00EG
16−pin 150−mil SOIC−TUBE, Green
Commercial
ASM3I622S00EG−16−ST
3I622S00EG
16−pin 150−mil SOIC−TUBE, Green
Industrial
ASM3P622S00EG−16−SR
3P622S00EG
16−pin 150−mil SOIC−TAPE & REEL, Green
Commercial
ASM3I622S00EG−16−SR
3I622S00EG
16−pin 150−mil SOIC−TAPE & REEL, Green
Industrial
ASM3P622S00EG−16−TT
3P622S00EG
16−pin 4.4−mm TSSOP − TUBE, Green
Commercial
ASM3I622S00EG−16−TT
3I622S00EG
16−pin 4.4−mm TSSOP − TUBE, Green
Industrial
ASM3P622S00EG−16−TR
3P622S00EG
16−pin 4.4−mm TSSOP − TAPE & REEL, Green
Commercial
ASM3I622S00EG−16−TR
3I622S00EG
16−pin 4.4−mm TSSOP − TAPE & REEL, Green
Industrial
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Industrial
Commercial
Industrial
ASM3P622S00B, ASM3P622S00E
TIMING SAFE is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your local
Sales Representative
ASM3P622S00/D