PulseCore ASM3P622S00EG-16-TT Low frequency timing-safeâ ¢ peak emi reduction ic Datasheet

ASM3P622S00B/E
May 2008
rev 0.5
Low Frequency Timing-Safe™ Peak EMI reduction IC
one reference input and drives out eight low-skew Timing-
General Features
•
Safe™clocks.
Low Frequency Clock distribution with TimingSafe™ Peak EMI Reduction
ASM3P622S00B/E has an SS% that selects 2 different
Deviation and associated Input-Output Skew (TSKEW). Refer
•
Input frequency range: 4MHz - 20MHz
•
2 different Spread Selection option
•
Spread Spectrum can be turned ON/OFF
•
External Input-Output Delay Control option
•
ASM3P622S00E has a CLKOUT for adjusting the Input-
Supply Voltage: 3.3V±0.3V
•
Output clock delay, depending upon the value of capacitor
Commercial and Industrial temperature range
•
connected at this pin to GND.
Packaging Information:
•
Spread Spectrum Control and Input-Output Skew table
for details.
ASM3P622S00B: 8 pin SOIC, and TSSOP
ASM3P622S00B/E operates from a 3.3V supply and is
ASM3P622S00E:16 pin SOIC, and TSSOP
available in two different packages, as shown in the
The First True Drop-in Solution
ordering information table, over commercial and Industrial
temperature range.
Functional Description
Application
ASM3P622S00B/E is a versatile, 3.3V Zero-delay buffer
designed to distribute low frequency Timing-Safe™ clocks
ASM3P622S00B/E is targeted for use in Displays and
with Peak EMI reduction. ASM3P622S00B is an eight-pin
memory interface systems.
version, accepts one reference input and drives out one
low-skew Timing-Safe™ clock. ASM3P622S00E accepts
General Block Diagram
DLY_CTRL
CLKIN
VDD
SS%
PLL
CLKOUT(s)*
(Timing-Safe™)
*For
ASM3P622S00E 8 CLKOUTS
SSON
GND
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
ASM3P622S00B/E
May 2008
rev 0.5
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
PCBs etc. These methods are expensive. Spread
with a 50% duty cycle and as frequencies increase the
spectrum clocking reduces the peak energy by reducing
edge rates also get faster. Analysis shows that a square
the Q factor of the clock. This is done by slowly
wave is composed of fundamental frequency and
modulating the clock frequency. The ASM3P622S00B/E
harmonics. The fundamental frequency and harmonics
uses the center modulation spread spectrum technique in
generate the energy peaks that become the source of
which the modulated output frequency varies above and
EMI. Regulatory agencies test electronic equipment by
below
measuring the amount of peak energy radiated from the
modulation rate. With center modulation, the average
equipment. In fact, the peak level allowed decreases as
frequency is the same as the unmodulated frequency and
the frequency increases. The standard methods of
there is no performance degradation
the
reference
frequency
with
a
specified
reducing EMI are to use shielding, filtering, multi-layer
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
For applications requiring zero input-output delay, all
Delay between input and output. Since the CLKOUT pin
outputs, including CLKOUT, must be equally loaded.
is the internal feedback to the PLL, its relative loading can
Even if CLKOUT is not used, it must have a capacitive
adjust the input-output delay.
load equal to that on other outputs, for obtaining zeroinput-output delay.
Timing-Safe™ technology
Timing-Safe™ technology is the ability to modulate a
clock source with Spread Spectrum technology and
maintain synchronization with any associated data path.
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 15
ASM3P622S00B/E
May 2008
rev 0.5
Pin Configuration for ASM3P622S00B
CLKIN
1
NC
2
8
NC
7
VDD
SS% 3
6
CLKOUT
GND 4
5
SSON
ASM3P622S00B
Pin Description for ASM3P622S00B
Pin #
Pin Name
Type
1
CLKIN1
I
2
NC
Description
External reference Clock input , 5V tolerant input
No Connect
3
3
SS%
I
Spread Spectrum Selection. Has an internal pull up resistor
4
GND
P
Ground
5
SSON3
I
Spread Spectrum enable and disable option When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum. Has an internal
pull up resistor
6
CLKOUT
7
VDD
8
NC
2
O
Buffered clock output4
P
3.3V supply
No Connect
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 15
ASM3P622S00B/E
May 2008
rev 0.5
Pin Configuration for ASM3P622S00E
1
16
CLKOUT
CLKOUT1
2
15
CLKOUT7
VDD
3
14
CLKOUT6
SS%
4
13
VDD
CLKIN
ASM3P622S00E
GND
5
12
GND
CLKOUT2
6
11
CLKOUT5
CLKOUT3
7
10
CLKOUT4
DLY_CTRL 8
9
SSON
Pin Description for ASM3P622S00E
Pin #
1
Pin Name
1
CLKIN
Description
I
External reference Clock input, 5V tolerant input
2
CLKOUT1
O
Buffered clock output4
3
VDD
P
3.3V supply
4
2
Type
3
SS%
I
Spread Spectrum Selection. Refer Spread Spectrum Control and Input-Output Skew
Table. Has an internal pull up resistor
5
GND
P
Ground
6
2
CLKOUT2
O
Buffered clock output4
7
CLKOUT32
O
Buffered clock output4
8
DLY_CTRL
O
External Input-Output Delay control.
Spread Spectrum enable and disable option. When SSON is HIGH, the spread
9
3
SSON
I
spectrum is enabled and when LOW, it turns off the spread spectrum. Has an internal
pull up resistor
10
CLKOUT42
O
Buffered clock output4
11
CLKOUT52
O
Buffered clock output4
12
GND
P
Ground
13
VDD
P
3.3V supply
14
2
CLKOUT6
O
Buffered clock output4
15
CLKOUT72
O
Buffered clock output4
16
CLKOUT2
O
Buffered clock output4
Notes: 1.Weak pull down
2. Weak pull-down on all outputs
3. Weak pull-up on these Inputs
4. Buffered clock output is Timing-Safe™
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 15
ASM3P622S00B/E
May 2008
rev 0.5
Spread Spectrum Control and Input-Output Skew Table
Device
Input Frequency
ASM3P622S00B/E
12MHz
SS %
Deviation
Input-Output Skew (±TSKEW)
0
±0.25 %
0.0625
1
±0.50 %
0.125
Note: TSKEW is measured in units of the Clock Period
Absolute Maximum Ratings
Symbol
Parameter
VDD
Supply Voltage to Ground Potential
VIN
DC Input Voltage (CLKIN)
TSTG
Rating
Unit
-0.5 to +4.6
V
-0.5 to +7
-65 to +125
°C
Ts
Max. Soldering Temperature (10 sec)
Storage temperature
260
°C
TJ
Junction Temperature
150
°C
TDV
Static Discharge Voltage (As per JEDEC STD22- A114-B)
2
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions
Parameter
Min
Max
Unit
Supply Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
-40
+85
°C
CL
Load Capacitance
30
pF
CIN
Input Capacitance
7
pF
VDD
Description
Electrical Characteristics
Parameter
VIL
Description
Min
Typ
Input LOW Voltage
5
VIH
Input HIGH Voltage
IIL
Input LOW Current
IIH
Input HIGH Current
VOL
Test Conditions
5
Max
Unit
0.8
V
2.0
6
Output LOW Voltage
6
V
VIN = 0V
50
µA
VIN = VDD
100
µA
IOL = 8mA
0.4
V
VOH
Output HIGH Voltage
IOH = -8mA
IDD
Supply Current
Unloaded outputs
Zo
Output Impedance
2.4
V
18
23
mA
Ω
Note: 5. CLKIN input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
5 of 15
ASM3P622S00B/E
May 2008
rev 0.5
Switching Characteristics for ASM3P622S00B/E
Parameter
Test Conditions
Min
Max
Unit
4
20
MHz
30pF load
4
20
MHz
Measured at VDD/2
40
60
%
Measured between 0.8V and 2.0V
2.5
nS
Measured between 2.0V and 0.8V
2.5
nS
All outputs equally loaded with SSOFF
250
pS
Measured at VDD /2 with SSOFF
±350
pS
700
pS
< 8MHz
±1.6
nS
> 8MHz
±200
pS
1.0
mS
Input Frequency
Output Frequency
Duty Cycle
6,7
= (t2 / t1) * 100
Output Rise Time
Output Fall Time
7, 8
7, 8
7, 8
Output-to-output skew
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge
8
Typ
50
Measured at VDD/2 on the CLKOUT pins
Device-to-Device Skew 8
of the device
Cycle-to-Cycle Jitter 7, 8
Loaded outputs
Stable power supply, valid clock presented
PLL Lock Time 8
on CLKIN pin
Note: 7. All parameters specified with 30pF loaded outputs.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production
Switching Waveforms
Duty Cycle Timing
t1
t2
VDD/2
VDD/2
VDD/2
OUTPUT
All Outputs Rise/Fall Time
2V
2V
0.8V
3.3V
0.8V
OUTPUT
0V
t3
t4
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
6 of 15
ASM3P622S00B/E
May 2008
rev 0.5
Output - Output Skew
VDD/2
OUTPUT
VDD/2
OUTPUT
t5
Input - Output Propagation Delay
VDD/2
INPUT
VDD/2
OUTPUT
t6
Device - Device Skew
VDD/2
CLKOUT, Device 1
VDD/2
CLKOUT, Device 2
t7
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
7 of 15
ASM3P622S00B/E
May 2008
rev 0.5
Input-Output Skew
Test Circuit
Input
Timing-Safe™
Output
+3.3V
VDD
TSKEW -
TSKEW+
0.1uF
OUTPUT
+3.3V
Test Circuit
CLKOUT
LOAD
VDD
One clock cycle
N=1
TSKEW represents input-output skew
0.1uF
GND
when spread spectrum is ON
For example, TSKEW = ± 0.125 for an
Input clock12MHz, translates in to
(1/12MHz) * 0.125=10.41nS
A Typical example of Timing-Safe™ waveform
Input
Input
CLKOUT with SSOFF
Timing-Safe™ CLKOUT
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
8 of 15
ASM3P622S00B/E
May 2008
rev 0.5
Package Information
8-lead (150-mil) SOIC Package
H
E
D
A2
A
C
A1
D
θ
e
L
B
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A1
0.004
0.010
0.10
0.25
A
0.053
0.069
1.35
1.75
A2
0.049
0.059
1.25
1.50
B
0.012
0.020
0.31
0.51
C
0.007
0.010
0.18
0.25
D
0.193 BSC
4.90 BSC
E
0.154 BSC
3.91 BSC
e
0.050 BSC
1.27 BSC
H
0.236 BSC
6.00 BSC
L
0.016
0.050
0.41
1.27
θ
0°
8°
0°
8°
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
9 of 15
ASM3P622S00B/E
May 2008
rev 0.5
8-lead TSSOP (4.40-MM Body)
H
E
D
A2
A
C
θ
e
A1
L
B
Dimensions
Symbol
Inches
Min
Millimeters
Max
A
Min
Max
0.043
1.10
A1
0.002
0.006
0.05
0.15
A2
0.033
0.037
0.85
0.95
B
0.008
0.012
0.19
0.30
c
0.004
0.008
0.09
0.20
D
0.114
0.122
2.90
3.10
E
0.169
0.177
4.30
4.50
e
0.026 BSC
0.65 BSC
H
0.252 BSC
6.40 BSC
L
0.020
0.028
0.50
0.70
θ
0°
8°
0°
8°
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
10 of 15
ASM3P622S00B/E
May 2008
rev 0.5
16-lead (150 Mil) Molded SOIC Package
PIN 1 ID
1
8
H
E
9
16
D
h
Seating Plane
A2
D
A
e
C
θ
0.004
L
A1
B
Dimensions
Symbol
Inches
Millimeters
Min
Max
Min
Max
A
0.053
0.069
1.35
1.75
A1
0.004
0.010
0.10
0.25
A2
0.049
0.059
1.25
1.50
B
0.013
0.022
0.33
0.53
C
0.008
0.012
0.19
0.27
D
0.386
0.394
9.80
10.01
E
0.150
0.157
3.80
4.00
e
0.050 BSC
1.27 BSC
H
0.228
0.244
5.80
6.20
h
0.010
0.016
0.25
0.41
L
0.016
0.035
0.40
0.89
θ
0°
8°
0°
8°
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
11 of 15
ASM3P622S00B/E
May 2008
rev 0.5
16-lead TSSOP (4.40-MM Body)
1
8
PIN 1 ID
E
16
A
A2
e
B
A1
Seating Plane
C
θ
D
9
H
L
D
Dimensions
Symbol
Inches
Min
Millimeters
Max
A
Min
Max
0.043
1.20
A1
0.002
0.006
0.05
0.15
A2
0.031
0.041
0.80
1.05
B
0.007
0.012
0.19
0.30
C
0.004
0.008
0.09
0.20
D
0.193
0.201
4.90
5.10
E
0.169
0.177
4.30
4.50
e
0.026 BSC
0.65 BSC
H
0.252 BSC
6.40 BSC
L
0.020
0.030
0.50
0.75
θ
0°
8°
0°
8°
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
12 of 15
ASM3P622S00B/E
May 2008
rev 0.5
Ordering Code
Ordering Code
Marking
Package Type
Temperature
ASM3P622S00BF-08-ST
3P622S00BF
8-pin 150-mil SOIC-TUBE, Pb Free
Commercial
ASM3I622S00BF-08-ST
3I622S00BF
8-pin 150-mil SOIC-TUBE, Pb Free
Industrial
ASM3P622S00BF-08-SR
3P622S00BF
8-pin 150-mil SOIC-TAPE & REEL, Pb Free
Commercial
ASM3I622S00BF-08-SR
3I622S00BF
8-pin 150-mil SOIC-TAPE & REEL, Pb Free
Industrial
ASM3P622S00BF-08-TT
3P622S00BF
8-pin 4.4-mm TSSOP - TUBE, Pb Free
Commercial
ASM3I622S00BF-08-TT
3I622S00BF
8-pin 4.4-mm TSSOP - TUBE, Pb Free
Industrial
ASM3P622S00BF-08-TR
3P622S00BF
8-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free
Commercial
ASM3I622S00BF-08-TR
3I622S00BF
8-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free
Industrial
ASM3P622S00EF-16-ST
3P622S00EF
16-pin 150-mil SOIC-TUBE, Pb Free
Commercial
ASM3I622S00EF-16-ST
3I622S00EF
16-pin 150-mil SOIC-TUBE, Pb Free
Industrial
ASM3P622S00EF-16-SR
3P622S00EF
16-pin 150-mil SOIC-TAPE & REEL, Pb Free
Commercial
ASM3I622S00EF-16-SR
3I622S00EF
16-pin 150-mil SOIC-TAPE & REEL, Pb Free
Industrial
ASM3P622S00EF-16-TT
3P622S00EF
16-pin 4.4-mm TSSOP - TUBE, Pb Free
Commercial
ASM3I622S00EF-16-TT
3I622S00EF
16-pin 4.4-mm TSSOP - TUBE, Pb Free
Industrial
ASM3P622S00EF-16-TR
3P622S00EF
16-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free
Commercial
ASM3I622S00EF-16-TR
3I622S00EF
16-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free
Industrial
ASM3P622S00BG-08-ST
3P622S00BG
8-pin 150-mil SOIC-TUBE, Pb Free
Commercial
ASM3I622S00BG-08-ST
3I622S00BG
8-pin 150-mil SOIC-TUBE, Pb Free
Industrial
ASM3P622S00BG-08-SR
3P622S00BG
8-pin 150-mil SOIC-TAPE & REEL, Pb Free
Commercial
ASM3I622S00BG-08-SR
3I622S00BG
8-pin 150-mil SOIC-TAPE & REEL, Pb Free
Industrial
ASM3P622S00BG-08-TT
3P622S00BG
8-pin 4.4-mm TSSOP - TUBE, Pb Free
Commercial
ASM3I622S00BG-08-TT
3I622S00BG
8-pin 4.4-mm TSSOP - TUBE, Pb Free
Industrial
ASM3P622S00BG-08-TR
3P622S00BG
8-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free
Commercial
ASM3I622S00BG-08-TR
3I622S00BG
8-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free
Industrial
ASM3P622S00EG-16-ST
3P622S00EG
16-pin 150-mil SOIC-TUBE, Green
Commercial
ASM3I622S00EG-16-ST
3I622S00EG
16-pin 150-mil SOIC-TUBE, Green
Industrial
ASM3P622S00EG-16-SR
3P622S00EG
16-pin 150-mil SOIC-TAPE & REEL, Green
Commercial
ASM3I622S00EG-16-SR
3I622S00EG
16-pin 150-mil SOIC-TAPE & REEL, Green
Industrial
ASM3P622S00EG-16-TT
3P622S00EG
16-pin 4.4-mm TSSOP - TUBE, Green
Commercial
ASM3I622S00EG-16-TT
3I622S00EG
16-pin 4.4-mm TSSOP - TUBE, Green
Industrial
ASM3P622S00EG-16-TR
3P622S00EG
16-pin 4.4-mm TSSOP - TAPE & REEL, Green
Commercial
ASM3I622S00EG-16-TR
3I622S00EG
16-pin 4.4-mm TSSOP - TAPE & REEL, Green
Industrial
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
13 of 15
ASM3P622S00B/E
May 2008
rev 0.5
Device Ordering Information
A S M 3 P 6 2 2 S 0 0 B G - 0 8 - T R
R = Tape & Reel, T = Tube or Tray
O = TSOT23
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
J=TSOT26
C=TDFN (2X2) COL
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Clock Generator
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
14 of 15
ASM3P622S00B/E
May 2008
rev 0.5
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200
Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Copyright © PulseCore Semiconductor
All Rights Reserved
Preliminary Information
Part Number: ASM3P622S00B/E
Document Version: 0.5
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
Many PulseCore Semiconductor products are protected by issued patents or by applications for patent
© Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of
PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the
right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that
may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance.
PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive
information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and
disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to
fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s
Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to
PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights,
copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not
authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to
result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
15 of 15
Similar pages