ALSC ASM5I961CG-32-LT Low voltage zero delay buffer Datasheet

ASM5I961C
July 2005
rev 0.2
Low Voltage Zero Delay Buffer
Features
reference clock while the ASM5I961P offers an LVPECL
ƒ
Fully Integrated PLL
reference clock.
ƒ
Up to 200MHz I/O Frequency
When pulled high the OE pin will force all of the outputs
ƒ
LVCMOS Outputs
(except QFB) into a high impedance state. Because the OE
ƒ
Outputs Disable in High Impedance
pin does not affect the QFB output, down stream clocks
ƒ
LVCMOS Reference Clock Options
ƒ
LQFP and TQFP Packaging
The ASM5I961C is fully 2.5V or 3.3V compatible and
ƒ
±50pS Cycle–Cycle Jitter
requires no external loop filter components. All control
ƒ
150pS Output Skews
can be disabled without the internal PLL losing lock.
inputs accept LVCMOS compatible levels and the outputs
provide low impedance LVCMOS outputs capable of
Functional Description
driving terminated 50Ω transmission lines. For series
The ASM5I961C is a 2.5V or 3.3V compatible, 1:18 PLL
terminated lines the ASM5I961C can drive two lines per
based zero delay buffer. With output frequencies of up to
output giving the device an effective fanout of 1:36. The
200MHz, output skews of 150pS the device meets the
device is packaged in a 32 lead LQFP and TQFP
needs of the most demanding clock tree applications.
Packages.
The
ASM5I961
is
offered
with
two
different
input
configurations. The ASM5I961C offers an LVCMOS
Block Diagram
Q0
CCLK
50K
0
50-100 MHz
1
FB
FB_IN
Q1
PLL
Ref
100-200 MHz
Q2
Q3
50K
Q14
F_RANGE
50K
Q15
Q16
OE
50K
QFB
Figure 1. ASM5I961C Logic Diagram
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
ASM5I961C
July 2005
rev 0.2
Q11
Q10
Q9
GND
Q8
Q7
Q6
VCC
Pin Configuration
24 23 22 21 20 19 18 17
Q5
25
16
VCC
Q4
26
15
Q12
14
Q13
13
Q14
Q3
27
GND
28
ASM5I961C
Q16
VCC
32
9
QFB
1
2
3
4
5
6
7
8
VCC
10
FB_IN
31
OE
Q0
VCCA
Q15
F_RANGE
GND
11
NC
12
30
CCLK
29
Q1
GND
Q2
Figure 2. ASM5I961C 32-Lead Package Pinout (Top View)
Table 1: Pin Configuration
Pin #
Pin Name
I/O
Type
2
CCLK
Input
LVCMOS
7
FB_IN
Input
LVCMOS
4
F_RANGE
Input
LVCMOS
PLL reference clock signal
PLL feedback signal input, connect to a
QFB output
PLL frequency range select
Input
LVCMOS
Output enable/disable
Clock outputs
6
OE
31,30,29,27,26,25,23,22,21,
19,18,17,15,14,13,11,10
Q0 - Q16
Output
LVCMOS
9
QFB
Output
LVCMOS
1,12,20,28
GND
Supply
Ground
5
VCCA
Supply
VCC
8,16,24,32
VCC
Supply
VCC
3
NC
Function
PLL feedback signal output, connect to a
FB_IN
Negative power supply
PLL positive power supply (analog power
supply). The ASM5I961C requires an
external RC filter for the analog power
supply pin VCCA. Please see applications
section for details.
Positive power supply for I/O and core
Not connected
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
2 of 15
ASM5I961C
July 2005
rev 0.2
Table 2: FUNCTION TABLE
Control
Default
F_RANGE
0
OE
0
0
PLL high frequency range. ASM5I961C input
reference and output clock frequency range is
100 – 200MHz
1
PLL low frequency range. ASM5I961C input
reference and output clock frequency range is
50 – 100MHz
Outputs enabled
Outputs disabled (high–impedance state)
Table 3: ABSOLUTE MAXIMUM RATINGS1
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
3.6
V
VIN
DC Input Voltage
–0.3
VCC + 0.3
V
VOUT
DC Output Voltage
–0.3
VCC + 0.3
V
IIN
DC Input Current
±20
mA
IOUT
TS
DC Output Current
Storage Temperature Range
±50
125
mA
°C
–40
Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Table 4: DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = -40°C to +85°C)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
Input LOW Voltage
–0.3
0.8
V
LVCMOS
VOH
Output HIGH Voltage
2.4
V
IOH = –20mA1
VOL
Output LOW Voltage
V
IOL = 20mA1
ZOUT
Output Impedance
IIN
Input Current
0.55
14
20
Ω
±120
µA
CIN
Input Capacitance
4.0
CPD
Power Dissipation Capacitance
8.0
10
pF
pF
Per Output
ICCA
Maximum PLL Supply Current
2.0
5.0
mA
VCCA Pin
ICC
VTT
Maximum Quiescent Supply Current
Output Termination Voltage
TBD
mA
V
All VCC Pins
VCC÷2
Note: 1. The ASM5I961C is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to
a termination voltage of VTT. Alternatively, the device drives up two 50Ω series terminated transmission lines.
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 15
ASM5I961C
July 2005
rev 0.2
Table 5: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 40°C to +85°C)1
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
fref
Input Frequency
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
fmax
Maximum Output
Frequency
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
frefDC
Reference Input Duty Cycle
25
75
%
3.0
nS
0.8 to 2.0V
120
pS
PLL locked
90
150
pS
50
50
55
55
%
1.0
nS
10
nS
10
nS
15
pS
10
pS
15
10
nS
mS
tr, tf
TCLK Input Rise/Fall Time
t(∅)
Propagation Delay
(static phase offset)
tsk(O)
Output–to–Output Skew2
DCO
Output Duty Cycle
CCLK to FB_IN
F_RANGE = 0
F_RANGE = 1
tr, tf
Output Rise/Fall Time
tPLZ,HZ
Output Disable Time
–80
42
45
0.1
tPZL,LZ
Output Enable Time
tJIT(CC)
Cycle–to–Cycle Jitter
RMS (1σ)3
tJIT(PER)
Period Jitter
RMS (1σ)
tJIT(∅)
tlock
I/O Phase Jitter
RMS (1σ)
Maximum PLL Lock Time
7.0
0.55 to 2.4V
Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT.
2. See applications section for part–to–part skew calculation
3. See applications section for calculation for other confidence factors than 1σ
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 15
ASM5I961C
July 2005
rev 0.2
Table 6: DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
Input LOW Voltage
–0.3
0.7
V
LVCMOS
VOH
Output HIGH Voltage
1.8
V
IOH = –15mA1
VOL
Output LOW Voltage
V
IOL = 15mA1
ZOUT
Output Impedance
IIN
Input Current
0.6
18
CIN
Input Capacitance
4.0
CPD
Power Dissipation Capacitance
8.0
ICCA
Maximum PLL Supply Current
2.0
ICC
VTT
Maximum Quiescent Supply Current
Output Termination Voltage
26
Ω
±120
mA
pF
10
pF
5.0
mA
VCCA Pin
TBD
mA
V
All VCC Pins
VCC ÷2
Per Output
Note: 1.The ASM5I961C is capable of driving 50Ω  transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to
a termination voltage of VTT. Alternatively, the device drives up two 50Ω series terminated transmission lines.
Table 7: AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = 40°C to +85°C)1
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
fref
Input Frequency
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
fmax
Maximum Output
Frequency
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
frefDC
Reference Input Duty Cycle
25
75
%
3.0
nS
0.7 to 1.7V
120
pS
PLL locked
90
150
pS
50
50
60
55
%
1.0
nS
10
nS
tr, tf
TCLK Input Rise/Fall Time
t(∅)
Propagation Delay
(static phase offset)
tsk(O)
Output–to–Output Skew2
DCO
Output Duty Cycle
tr, tf
Output Rise/Fall Time
tPLZ,HZ
Output Disable Time
tPZL,LZ
Output Enable Time
tJIT(CC)
Cycle–to–Cycle Jitter
RMS (1σ)3
tJIT(PER)
Period Jitter
RMS (1σ)
tJIT(∅)
tlock
I/O Phase Jitter
RMS (1σ)
Maximum PLL Lock Time
CCLK to FB_IN
–80
F_RANGE = 0
F_RANGE = 1
40
45
0.1
7.0
10
nS
15
pS
10
pS
15
10
nS
mS
0.6 to 1.8V
Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT.
2 See applications section for part–to–part skew calculation
3 See applications section for calculation for other confidence factors than 1σ
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
5 of 15
ASM5I961C
July 2005
rev 0.2
APPLICATIONS INFORMATION
Power Supply Filtering
The ASM5I961C is a mixed analog/digital product and as
such it exhibits some sensitivity that would not
necessarily be seen on a fully digital product. Analog
circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
The ASM5I961C provides separate power supplies for
the output buffers (VCC) and the phase–locked loop
(VCCA) of the device. The purpose of this design
technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as
an evaluation board this level of isolation is sufficient.
However, in a digital system environment where it is more
difficult to minimize noise on the power supplies a second
level of isolation may be required. The simplest form of
isolation is a power supply filter on the VCCA pin for the
ASM5I961C.
Figure 3. illustrates a typical power supply filter scheme.
The ASM5I961C is most susceptible to noise with
spectral content in the 10KHz to 10MHz range. Therefore
the filter should be designed to target this range. The key
parameter that needs to be met in the final filter design is
the DC voltage drop that will be seen between the VCC
supply and the VCCA pin of the ASM5I961C. From the
data sheet the ICCA current (the current sourced through
the VCCA pin) is typically 2mA (5mA maximum), assuming
that a minimum of 2.375V (VCC = 3.3V or VCC = 2.5V)
must be maintained on the VCCA pin. The resistor RF
shown in Figure 3. must have a resistance of 270Ω
(VCC = 3.3V) or 5 to 15Ω (VCC = 2.5V) to meet the voltage
drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20KHz. As the
noise frequency crosses the series resonant point of an
individual capacitor it’s overall impedance begins to look
inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a
low impedance path to ground exists for frequencies well
above the bandwidth of the PLL.
Although the ASM5I961C has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still
may be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related
problems in most designs.
Driving Transmission Lines
The ASM5I961C clock driver was designed to drive high
speed signals in a terminated transmission line
environment. To provide the optimum flexibility to the
user the output drivers were designed to exhibit the
lowest impedance possible. With an output impedance of
less than 15Ω the drivers can drive either parallel or
series terminated transmission lines. In most high
performance clock networks point–to–point distribution of
signals is the method of choice. In a point–to–point
scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50Ω
resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line
can be driven by each output of the ASM5I961C clock
driver. For the series terminated case however there is no
DC current draw, thus the outputs can drive multiple
series terminated lines. Figure 4. illustrates an output
driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the
fanout of the ASM5I961C clock driver is effectively
doubled due to its capability to drive multiple lines.
ASM5I961C
OUTPUT BUFFER
IN
14Ω
RS=36Ω
ASM5I961C
OUTPUT BUFFER
IN
RS=36Ω
14Ω
RS=36Ω
Z0=50Ω
OUTA
Z0=50Ω
OUTB0
Z0=50Ω
OUTB1
Figure 4. Single versus Dual Transmission Lines
Figure 3. Power Supply Filter
The waveform plots of Figure 5. show the simulation
results of an output driving a single line vs two lines. In
both cases the drive capability of the ASM5I961C output
buffer is more than sufficient to drive 50Ω transmission
lines on the incident edge. Note from the delay
measurements in the simulations a delta of only 43pS
exists between the two differently loaded outputs. This
suggests that the dual line driving need not be used
exclusively to maintain the tight output–to–output skew of
the ASM5I961C. The output waveform in Figure 5. shows
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
6 of 15
ASM5I961C
July 2005
rev 0.2
a step in the waveform, this step is caused by the
impedance mismatch seen looking into the driver. The
parallel combination of the 36Ω series resistor plus the
output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50Ω || 50Ω
Rs = 36Ω || 36Ω
Ro = 14Ω
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.62V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0nS).
Using the ASM5I961C in zero-delay applications
Nested clock trees are typical applications for the
ASM5I961C. Designs using the ASM5I961C as LVCMOS
PLL fanout buffer with zero insertion delay will show
significantly lower clock skew than clock distributions
developed from CMOS fanout buffers. The external
feedback option of the ASM5I961C clock driver allows for
its use as a zero delay buffer. By using the QFB output as
a feedback to the PLL the propagation delay through the
device is virtually eliminated. The PLL aligns the
feedback clock output edge with the clock input reference
edge resulting a near zero delay through the device. The
maximum insertion delay of the device in zero-delay
applications is measured between the reference clock
input and any output. This effective delay consists of the
static phase offset, I/O jitter (phase or long-term jitter),
feedback path delay and the output-to-output skew error
relative to the feedback output.
Calculation of part-to-part skew
The ASM5I961C zero delay buffer supports applications
where critical clock signal timing can be maintained
across several devices. If the reference clock inputs of
two or more ASM5I961C are connected together, the
maximum overall timing uncertainty from the common
CCLK input to any output is:
tSK(PP) = t(ϕ) + tSK(O) + tPD, LINE(FB) + tJIT(ϕ) CF
This maximum timing uncertainty consist of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
Figure 5. Single versus Dual Waveforms
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving
multiple lines the situation in Figure 6. should be used. In
this case the series terminating resistors are reduced
such that when the parallel combination is added to the
output buffer impedance the line impedance is perfectly
matched.
ASM5I961C
OUTPUT BUFFER
IN
RS=22Ω
14Ω
RS=22Ω
Z0=50Ω
Z0=50Ω
Figure 7. ASM5I961C max. device-to-device skew
14Ω + 22Ω ║ 22Ω = 50Ω ║ 50Ω
25Ω = 25Ω
Figure 6. Optimized Dual Line Termination
Due to the statistical nature of I/O jitter a rms value (1σ) is
specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 8.
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
7 of 15
ASM5I961C
July 2005
rev 0.2
± 1σ
Probability of clock edge within the
distribution
0.68268948
± 2σ
0.95449988
term reliability may decrease the maximum frequency
limit, depending on operating conditions such as clock
frequency, supply voltage, output loading, ambient
temperature, vertical convection and thermal conductivity
of package and board. This section describes the impact
of these parameters on the junction temperature and
gives a guideline to estimate the ASM5I961C die junction
temperature and the associated device reliability.
± 3σ
0.99730007
Table 9: Die junction temperature and MTBF
± 4σ
0.99993663
± 5σ
0.99999943
± 6σ
0.99999999
Table 8: Confidence Factor CF
CF
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation
a I/O jitter confidence factor of 99.7% (± 3 σ) is assumed,
resulting in a worst case timing uncertainty from input to
any output of -275 pS to 315 pS relative to CCLK:
tSK(PP) = [–80pS...120pS] + [–150pS...150pS] +
[(15pS _ –3)...(15pS _ 3)] + tPD, LINE(FB)
tSK(PP) = [–275pS...315pS] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure
8. “Max. I/O Jitter versus frequency” can be used for a
more precise timing performance analysis.
Figure 8. Max. I/O Jitter versus frequency
Power Consumption of the ASM5I961C and Thermal
Management
The ASM5I961C AC specification is guaranteed for the
entire operating frequency range up to 200MHz. The
ASM5I961C power consumption and the associated long-
Junction temperature (°C)
MTBF (Years)
100
20.4
110
9.1
120
4.2
130
2.0
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable
MTBF, the die junction temperature of the ASM5I961C
needs to be controlled and the thermal impedance of the
board/package should be optimized. The power
dissipated in the ASM5I961C is represented in equation
1. Where ICCQ is the static current consumption of the
ASM5I961C, CPD is the power dissipation capacitance
per output, (M)ΣCL represents the external capacitive
output load, N is the number of active outputs (N is
always 27 in case of the ASM5I961C). The ASM5I961C
supports driving transmission lines to maintain high signal
integrity and tight timing parameters. Any transmission
line will hide the lumped capacitive load at the end of the
board trace, therefore, ΣCL is zero for controlled
transmission line systems and can be eliminated from
equation 1. Using parallel termination output termination
results in equation 2 for power dissipation. In equation 2,
P stands for the number of outputs with a parallel or
thevenin termination, VOL, IOL, VOH and IOH are a function
of the output termination technique and DCQ is the clock
signal duty cycle. If transmission lines are used ΣCL is
zero in equation 2 and can be eliminated. In general, the
use of controlled transmission line techniques eliminates
the impact of the lumped capacitive loads at the end lines
and greatly reduces the power dissipation of the device.
Equation 3 describes the die junction temperature TJ as a
function of the power consumption.
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
8 of 15
ASM5I961C
July 2005
rev 0.2
Where Rthja is the thermal impedance of the package
(junction to ambient) and TA is the ambient temperature.
According to Table 9, the junction temperature can be
used to estimate the long-term device reliability. Further,
combining equation 1 and equation 2 results in a
maximum operating frequency for the ASM5I961C in a
series terminated transmission line system.
Table 10: Thermal package impedance of the 32
LQFP
Convection, LFPM
Rthja (1P2S board), °C/W
Still air
80
100 lfpm
70
200 lfpm
61
300 lfpm
57
400 lfpm
56
500 lfpm
55
TJ,MAX should be selected according to the MTBF system
requirements and Table 9. Rthja can be derived from Table
10. The Rthja represent data based on 1S2P boards, using
2S2P boards will result in a lower thermal impedance
than indicated below. If the calculated maximum
frequency is below 200MHz, it becomes the upper clock
speed limit for the given application conditions. The
following two derating charts describe the safe frequency
operation range for the ASM5I961C. The charts were
calculated for a maximum tolerable die junction
temperature of 110°C, corresponding to an estimated
MTBF of 9.1 years, a supply voltage of 3.3V and series
terminated transmission line or capacitive loading.
Depending on a given set of these operating conditions
and the available device convection a decision on the
maximum operating frequency can be made. There are
no operating frequency limitations if a 2.5V power supply
or the system specifications allow for a MTBF of 4 years
(corresponding to a max. junction temperature of 120°C.
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
9 of 15
ASM5I961C
July 2005
rev 0.2
Figure 9. Maximum ASM5I961C frequency, VCC = 3.3V,
MTBF 9.1 years, driving series terminated transmission
Figure 10. Maximum ASM5I961C frequency,
VCC = 3.3V, MTBF 9.1 years,4pF load per line
Figure 11. TCLK ASM5I961C AC test reference for VCC = 3.3V and VCC =2.5V
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
10 of 15
ASM5I961C
July 2005
rev 0.2
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
11 of 15
ASM5I961C
July 2005
rev 0.2
Package Diagram
32-lead TQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0472
…
1.2
A1
0.0020
0.0059
0.05
0.15
A2
0.0374
0.0413
0.95
1.05
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.2
a
0°
7°
0°
7°
e
0.031 BASE
0.8 BASE
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
12 of 15
ASM5I961C
July 2005
rev 0.2
32-lead LQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0630
…
1.6
A1
0.0020
0.0059
0.05
0.15
A2
0.0531
0.0571
1.35
1.45
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.20
e
a
0.031 BASE
0°
7°
0.8 BASE
0°
7°
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
13 of 15
ASM5I961C
July 2005
rev 0.2
Ordering Information
Marking
Part Number
Package Type
Temperature
ASM5I961C-32-ET
ASM5I961C
32 pin TQFP
Industrial
ASM5I961C-32-LT
ASM5I961C
32 pin LQFP – Tape and Reel
Industrial
ASM5I961CG-32-ET
ASM5I961CG
32 pin TQFP, Green
Industrial
ASM5I961CG-32-LT
ASM5I961CG
32 pin LQFP – Tape and Reel, Green
Industrial
Device Ordering Information
A S M
5 I 9 6 1 C
F - 3 2 - L T
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
14 of 15
ASM5I961C
July 2005
rev 0.2
Alliance Semiconductor Corporation
2575 Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM5I961C
Document Version: 0.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).
All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any
other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
Low Voltage Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
15 of 15
Similar pages