ALSC ASM5P23S04A-2-08-SR 3.3 v spreadtrak zero delay buffer Datasheet

ASMP5P23S04A
August 2004
rev 2.0
3.3 V ‘SpreadTrak’ Zero Delay Buffer
Features

Zero input - output propagation delay,
adjustable by capacitive load on FBK input.

Multiple configurations - Refer “ASM5P23S04A
Configurations Table”.

Input frequency range: 10MHz to 133MHz

Multiple low-skew outputs.

Output-output skew less than 200 ps.

Device-device skew less than 500 ps.

Two banks of four outputs.

Less than 200 ps cycle-to-cycle jitter

Available in space saving, 8-pin 150-mil SOIC
packages.

3.3V operation.

Advanced 0.35µ CMOS technology.

Industrial temperature available.

‘SpreadTrak’
FBK pin, and can be obtained from one of the outputs. The
input-to-output propagation delay is guaranteed to be less
than 250ps, and the output-to-output skew is guaranteed to
be less than 200ps.
The ASM5P23S04A has two banks of two outputs each.
Multiple ASM5P23S04A devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
500ps.
The
ASM5P23S04A
configurations
(Refer
is
available
in
“ASM5P23S04A
two
different
Configurations
Table). The ASM5P23S04A-1 is the base part, where the
output frequencies equal the reference if there is no
counter in the feedback path. The ASM5P23S04A-1H is
the high-drive version of the -1 and the rise and fall times
on this device are much faster.
Functional Description
ASM5P23S04A is a versatile, 3.3V zero-delay buffer
The ASM5P23S04A-2 allows the user to obtain Ref, 1/2 X
designed
PC,
and 2X frequencies on each output bank. The exact
workstation, datacom, telecom and other high-performance
configuration and output frequencies depend on which
applications. It is available in a 8-pin package. The part has
output drives the feedback pin. The ASM5P23S04A-5H is a
an on-chip PLL which locks to an input clock presented on
high-drive version with REF/2 on both banks
to
distribute
high-speed
clocks
in
the REF pin. The PLL feedback is required to be driven to
Block Diagram
FBK
CLKA1
REF
PLL
CLKA2
/2
Extra Divider (-2)
CLKB1
CLKB2
Alliance Semiconductor
2575, Augustine Drive  Santa Clara, CA  Tel: 408.855.4900  Fax: 408.855.4999  www.alsc.com
Notice: The information in this document is subject to change without notice.
``
ASM5P23S04A
August 2004
rev 2.0
ASM5P23S04A Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
ASM5P23S04A-1
Bank A or Bank B
Reference
Reference
ASM5P23S04A-1H
Bank A or Bank B
Reference
Reference
ASM5P23S04A-2
Bank A
Reference
Reference /2
ASM5P23S04A-2
Bank B
2 X Reference
Reference
ASM5P23S04A-5H
Bank A or Bank B
Reference /2
Reference /2
‘SpreadTrak’
delay buffer is not designed to pass the Spread
Spectrum feature through, the result is a significant
Many systems being designed now utilize a
technology called Spread Frequency Timing
Generation. ASM3P23S04A is designed so as not
amount of tracking skew which may cause
problems in the systems requiring synchronization.
to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero
Zero Delay and Skew Control
For applications requiring zero input-output delay, all outputs must be equally loaded.
1500
REF-Input to CLKA/CLKB Delay (ps)
1000
500
0
-30
-25
-20
-15
-10
-5
5
0
10
15
20
25
30
-500
-1000
-1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins
3.3 ‘SpreadTrak’ Zero Delay Buffer
Notice:
of 13
The information in this document is subject to change without notice.
2
``
ASM5P23S04A
August 2004
rev 2.0
To close the feedback loop of the ASM5P23S04A,
the FBK pin can be driven from any of the four
available output pins. The output driving the FBK pin
will be driving a total load of 7 pF plus any additional
load that it drives. The relative loading of this output
(with respect to the remaining outputs) can adjust the
For applications requiring zero input-output delay, all
outputs including the one providing feedback should
be equally loaded. If input-output delay adjustments
are required, use the above graph to calculate
loading differences between the feedback output and
remaining outputs. For zero output-output skew, be
sure to load outputs equally.
input output delay. This is shown in the above graph.
Pin Configuration
REF
1
CLKA1
2
CLKA2
3
GND
4
ASM5P23S04A
8
FBK
7
VDD
6
CLKB2
5 CLKB1
Pin Description for ASM5P23S04A
Pin #
Pin Name
Description
1
REF1
2
CLKA12
Buffered clock output, bank A
3
CLKA22
Buffered clock output, bank A
4
GND
5
CLKB12
Buffered clock output, bank B
6
CLKB2 2
Buffered clock output, bank B
7
VDD
3.3V supply
8
FBK
PLL feedback input
Input reference frequency, 5V tolerant input
Ground
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3.3 ‘SpreadTrak’ Zero Delay Buffer
Notice:
of 13
The information in this document is subject to change without notice.
3
``
ASM5P23S04A
August 2004
rev 2.0
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
-0.5
+7.0
V
DC Input Voltage (Except REF)
-0.5
VDD + 0.5
V
DC Input Voltage (REF)
-0.5
7
V
Storage Temperature
-65
+150
°C
Max. Soldering Temperature (10 sec)
260
°C
Junction Temperature
150
°C
>2000
V
Static Discharge Voltage
(per MIL-STD-883, Method 3015)
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute
maximum
ratings for prolonged periods can affect device reliability.
Operating Conditions for ASM5P23S04A Commercial Temperature Devices
Parameter
Description
Min
Max
Unit
3.0
3.6
V
0
70
°C
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance, below 100 MHz
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
15
pF
CIN
Input Capacitance3
7
pF
Note: 3. Applies to both Ref Clock and FBK.
3.3 ‘SpreadTrak’ Zero Delay Buffer
Notice:
of 13
The information in this document is subject to change without notice.
4
``
ASM5P23S04A
August 2004
rev 2.0
Electrical Characteristics for ASM5P23S04A Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
0.8
V
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
50.0
µA
IIH
Input HIGH Current
VIN = VDD
100.0
µA
VOL
Output LOW Voltage 4
0.4
V
VOH
Output HIGH Voltage 4
2.0
IOL = 8mA (-1, -2)
IOH = 12mA (-1H, -5H)
IOL = -8mA (-1, -2)
IOH = -12mA (-1H, -5H)
2.4
Unloaded outputs 100MHz REF,
Select inputs at VDD or GND
IDD
Supply Current
V
Unloaded outputs, 66MHz REF
(-1, -2)
Unloaded outputs, 33MHz REF
(-1, -2)
V
TBD
TBD
TBD
mA
TBD
Note: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
5. REF Input Vth = ~ VDD/2
3.3 ‘SpreadTrak’ Zero Delay Buffer
Notice:
of 13
The information in this document is subject to change without notice.
5
``
ASM5P23S04A
August 2004
rev 2.0
Switching Characteristics for ASM5P23S04A Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
30-pF load, All devices
10
100
MHz
t1
Output Frequency
20-pF load, -1H, -5H devices
10
133.3
MHz
t1
Output Frequency
15-pF load, -1, -2 devices
10
133.3
MHz
4
Duty Cycle = (t2 / t1) * 100
(-1, -2, -1H, -5H)
Measured at 1.4V, FOUT = 66.66 MHz
30-pF load
40.0
50.0
60.0
%
Measured at 1.4V, FOUT = <50 MHz
15-pF load
45.0
50.0
55.0
%
Measured between 0.8V and 2.0V
30-pF load
2.20
ns
Measured between 0.8V and 2.0V
15-pF load
1.50
ns
Measured between 0.8V and 2.0V
30-pF load
1.50
ns
Measured between 2.0V and 0.8V
30-pF load
2.20
ns
Measured between 2.0V and 0.8V
15-pF load
1.50
ns
Measured between 2.0V and 0.8V
30-pF load
1.25
ns
4
All outputs equally loaded
200
Output-to-output skew
(-1H, -5H)
All outputs equally loaded
200
Output bank A -to- output bank B skew (-1, 5H)
All outputs equally loaded
200
Output bank A to output bank b skew (-2)
All outputs equally loaded
400
4
Duty Cycle = (t2 / t1) * 100
(-1, -2,-1H, -5H)
Output Rise Time
(-1, -2)
4
t3
Output Rise Time
(-1, -2)
4
t3
Output Rise Time
(-1H, -5H)
4
t3
Output Fall Time
(-1, -2)
4
t4
Output Fall Time
(-1, -2)
4
t4
Output Fall Time
(-1H, -5H)
4
t4
Output-to-output skew on same bank (-1, -2)
t5
t6
Delay, REF Rising Edge to FBK Rising Edge
3
t7
Device-to-Device Skew
t8
Output Slew Rate
tJ
tJ
tLOCK
4
Cycle-to-cycle jitter
(-1, -1H, -5H)
Cycle-to-cycle jitter
(-2,)
PLL Lock Time
Measured at VDD /2
0
±250
ps
Measured at VDD/2 on the FBK pins of the device
0
500
ps
Measured between 0.8V and 2.0V using
Test Circuit #2
4
ps
1
V/ns
Measured at 66.67 MHz, loaded outputs,
15 pF load
175
Measured at 66.67 MHz, loaded outputs,
30 pF load
200
Measured at 133.3 MHz, loaded outputs,
15 pF load
100
Measured at 66.67 MHz, loaded outputs, 30pF
load
400
Measured at 66.67 MHz, loaded outputs,
15 pF load
375
Stable power supply, valid clock presented on
REF and FBK pins
1.0
4
4
4
3.3 ‘SpreadTrak’ Zero Delay Buffer
Notice:
of 13
The information in this document is subject to change without notice.
ps
ps
ms
6
``
ASM5P23S04A
August 2004
rev 2.0
Operating Conditions for ASM5I23S04A Industrial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
Supply Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
-40
85
°C
CL
Load Capacitance, below 100 MHz
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
15
pF
CIN
Input Capacitance3
7
pF
Electrical Characteristics for ASM5I23S04A Industrial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
0.8
V
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
50.0
µA
IIH
Input HIGH Current
VIN = VDD
100.0
µA
VOL
Output LOW Voltage 4
0.4
V
VOH
Output HIGH Voltage 4
2.0
IOL = 8mA (-1, -2)
IOH = 12mA (-1H, -5H)
IOL = -8mA (-1, -2)
IOH = -12mA (-1H, -5H)
Unloaded outputs 100MHz REF,
Select inputs at VDD or GND
IDD
Supply Current
Unloaded outputs, 66MHz REF
(-1, -2)
Unloaded outputs, 33MHz REF
(-1, -2)
3.3 ‘SpreadTrak’ Zero Delay Buffer
Notice:
of 13
The information in this document is subject to change without notice.
V
2.4
V
TBD
TBD
TBD
mA
TBD
7
``
ASM5P23S04A
August 2004
rev 2.0
Switching Characteristics for ASM5I23S04A Industrial Temperature Devices
All parameters are specified with loaded outputs
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
30-pF load, All devices
10
100
MHz
t1
Output Frequency
20-pF load, -1H, -5H devices
10
133.3
MHz
t1
Output Frequency
15-pF load, -1 and -2 devices
10
133.3
MHz
4
Duty Cycle = (t2 / t1) * 100
(-1, -2, -1H, -5H)
Measured at 1.4V, FOUT = <66.66 MHz
30-pF load
40.0
50.0
60.0
%
Measured at 1.4V, FOUT = <50 MHz
15-pF load
45.0
50.0
55.0
%
Measured between 0.8V and 2.0V
30-pF load
2.50
ns
Measured between 0.8V and 2.0V
15-pF load
1.50
ns
Measured between 0.8V and 2.0V
30-pF load
1.50
ns
Measured between 2.0V and 0.8V
30-pF load
2.50
ns
Measured between 2.0V and 0.8V
15-pF load
1.50
ns
Measured between 2.0V and 0.8V
30-pF load
1.25
ns
All outputs equally loaded
200
Output-to-output skew
(-1H, -5H)
All outputs equally loaded
200
Output bank A -to- output bank B skew (-1, -5H)
All outputs equally loaded
200
Output bank A -to- output bank B skew (-2)
All outputs equally loaded
400
4
Duty Cycle = (t2 / t1) * 100
(-1, -2, -1H, -5H)
Output Rise Time
(-1, -2)
4
t3
Output Rise Time
(-1, -2)
4
t3
Output Rise Time
(-1H, -5H)
4
t3
Output Fall Time
(-1, -2)
4
t4
Output Fall Time
(-1, -2)
4
t4
Output Fall Time
(-1H, -5H)
4
t4
Output-to-output skew on same bank (-1, -2)
t5
t6
Delay, REF Rising Edge to FBK Rising Edge
t7
Device-to-Device Skew
t8
Output Slew Rate
tJ
tJ
tLOCK
4
Cycle-to-cycle jitter
(-2)
PLL Lock Time
4
ps
Measured at VDD /2
0
±250
ps
Measured at VDD/2 on the FBK pins of the device
0
500
ps
Measured between 0.8V and 2.0V using
Test Circuit #2
4
Cycle-to-cycle jitter
(-1, -1H, -5H)
4
1
V/ns
Measured at 66.67 MHz, loaded outputs,
15 pF load
180
Measured at 66.67 MHz, loaded outputs,
30 pF load
200
Measured at 133.3 MHz, loaded outputs,
15 pF load
100
Measured at 66.67 MHz, loaded outputs, 30pF load
400
Measured at 66.67 MHz, loaded outputs,
15 pF load
380
Stable power supply, valid clock presented on REF
and FBK pins
1.0
4
4
ps
ps
4
3.3 ‘SpreadTrak’ Zero Delay Buffer
Notice:
of 13
The information in this document is subject to change without notice.
ms
8
``
ASM5P23S04A
August 2004
rev 2.0
Switching Waveforms
Duty Cycle Timing
t1
t2
1.4 V
1.4 V
1.4 V
All Outputs Rise/Fall Time
2.0 V
OUTPUT
2.0 V
0.8 V
0.8 V
3.3 V
0V
t4
t3
Output - Output Skew
1.4 V
OUTPUT
1.4 V
OUTPUT
t5
Input - Output Propagation Delay
/2
V
DD
INPUT
V
/2
V
/2
DD
OUTPUT
t6
Device - Device Skew
V
/2
DD
FBK, Device 1
FBK, Device 2
DD
t7
3.3 ‘SpreadTrak’ Zero Delay Buffer
Notice:
of 13
The information in this document is subject to change without notice.
9
``
ASM5P23S04A
August 2004
rev 2.0
Test Circuits
Test Circuit #2
Test Circuit #1
V
V
DD
OUTPUTS
0.1 ÿF
1k 
DD
OUTPUTS
0.1 ÿF
1k
C
LOAD
V
0.1 ÿF
V
DD
GND
GND
0.1 ÿF
DD
GND
GND
For parameter 8t (output slew rate) on -1H devices
3.3 ‘SpreadTrak’ Zero Delay Buffer
10 of 13
Notice: The information in this document is subject to change without notice.
10 pF
``
ASM5P23S04A
August 2004
rev 2.0
Package Information: 8-lead (150 Mil) Molded SOIC
H
E
D
A
D
e
C

A1
L
B
Dimensions in inches
Symbol
Dimensions in
millimeters
Min
Max
Min
Max
A
0.053
0.069
1.35
1.75
A1
0.004
0.010
0.10
0.25
B
0.013
0.022
0.33
0.53
C
0.007
0.012
0.18
0.27
D
0.188
0.197
4.78
5.00
E
0.150
0.158
3.80
4.01
H
0.228
0.244
5.80
6.20
e
0.050 BSC
1.27 BSC
L
0.016
0.035
0.40
0.89

0°
8°
0°
8°
3.3 ‘SpreadTrak’ Zero Delay Buffer
11 of 13
Notice: The information in this document is subject to change without notice.
``
ASM5P23S04A
August 2004
rev 2.0
Ordering Information
Ordering Code
Package Type
Operating Range
ASM5P23S04A-1-08-SR
8-pin 150-mil SOIC-TAPE & REEL
Commercial
ASM5P23S04A-1-08-ST
8-pin 150-mil SOIC-TUBE
Commercial
ASM5I23S04A-1-08-SR
8-pin 150-mil SOIC-TAPE & REEL
Industrial
ASM5I23S04A-1-08-ST
8-pin 150-mil SOIC-TUBE
Industrial
ASM5P23S04A-1H-08-SR
8-pin 150-mil SOIC-TAPE & REEL
Commercial
ASM5P23S04A-1H-08-ST
8-pin 150-mil SOIC-TUBE
Commercial
ASM5I23S04A-1H-08-SR
8-pin 150-mil SOIC-TAPE & REEL
Industrial
ASM5I23S04A-1H-08-ST
8-pin 150-mil SOIC-TUBE
Industrial
ASM5P23S04A-2-08-SR
8-pin 150-mil SOIC-TAPE & REEL
Commercial
ASM5P23S04A-2-08-ST
8-pin 150-mil SOIC-TUBE
Commercial
ASM5I23S04A-2-08-SR
8-pin 150-mil SOIC-TAPE & REEL
Industrial
ASM5I23S04A-2-08-ST
8-pin 150-mil SOIC-TUBE
Industrial
ASM5P23S04A-5H-08-SR
8-pin 150-mil SOIC-TAPE & REEL
Commercial
ASM5P23S04A-5H-08-ST
8-pin 150-mil SOIC-TUBE
Commercial
ASM5I23S04A-5H-08-SR
8-pin 150-mil SOIC-TAPE & REEL
Industrial
ASM5I23S04A-5H-08-ST
8-pin 150-mil SOIC-TUBE
Industrial
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3 ‘SpreadTrak’ Zero Delay Buffer
12 of 13
Notice: The information in this document is subject to change without notice.
``
ASM5P23S04A
August 2004
rev 2.0
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM5P23S04A
Document Version: 2.0
8_30_2004
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).
All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any
other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
3.3 ‘SpreadTrak’ Zero Delay Buffer
13 of 13
Notice: The information in this document is subject to change without notice.
Similar pages