ATMEL AT27LV020A-12VU 2-megabit (256k x 8) low voltage otp eprom Datasheet

Features
• Fast Read Access Time – 120 ns, see AT27BV020 for Faster Speeds
• Dual Voltage Range Operation
•
•
•
•
•
•
•
•
•
•
– Low Voltage Power Supply Range, 3.0V to 3.6V
or Standard 5V ± 10% Supply Range
Compatible with JEDEC Standard AT27C020
Low Power CMOS Operation
– 20 µA Max (Less than 1 µA Typical) Standby for VCC = 3.6V
– 29 mW Max Active at 5 MHz for VCC = 3.6V
JEDEC Standard Packages
– 32-lead PLCC
– 32-lead TSOP
– 32-lead VSOP
High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Rapid Programming Algorithm – 100 µs/Byte (Typical)
Two-line Control
CMOS and TTL Compatible Inputs and Outputs
– JEDEC Standard for LVTTL
Integrated Product Identification Code
Industrial Temperature Range
Green (Pb/Halide-free) Packaging Option
2-Megabit
(256K x 8)
Low Voltage
OTP EPROM
AT27LV020A
1. Description
The AT27LV020A is a high-performance, low-power, low-voltage 2,097,152 bit onetime programmable read-only memory (OTP EPROM) organized as 256K by 8 bits. It
requires only one supply in the range of 3.0 to 3.6V in normal read mode operation,
making it ideal for fast, portable systems using battery power.
Atmel’s innovative design techniques provide fast speeds that rival 5V parts while
keeping the low power consumption of a 3V supply. At VCC = 3.0V, any byte can be
accessed in less than 120 ns. With a typical power dissipation of only 18 mW at 5 MHz
and VCC = 3.3V, the AT27LV020A consumes less than one fifth the power of a standard 5V EPROM. Standby mode supply current is typically less than 1 µA at 3.3V.
The AT27LV020A is available in industry-standard JEDEC approved one-time programmable (OTP) plastic PLCC, TSOP, and VSOP. All devices feature two-line
control (CE, OE) to give designers the flexibility to prevent bus contention.
The AT27LV020A operating with VCC at 3.0V produces TTL level outputs that are
compatible with standard TTL logic devices operating at VCC = 5.0V. The device is
also capable of standard 5-volt operation making it ideally suited for dual supply range
systems or card products that are pluggable in both 3-volt and 5-volt hosts.
Atmel's AT27LV020A has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program
the part and guarantees reliable programming. Programming time is typically only
100 µs/byte. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry standard programming
equipment to select the proper programming algorithms and voltages. The
AT27LV020A programs exactly the same way as a standard 5V AT27C020 and uses
the same programming equipment.
0549G–EPROM–12/07
2. Pin Configurations
2.1
Pin Name
Function
A0 - A17
Addresses
O0 - O7
Outputs
CE
Chip Enable
OE
Output Enable
PGM
Program Strobe
NC
No Connect
32-lead TSOP/VSOP (Type 1) Top View
A11
A9
A8
A13
A14
A17
PGM
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
O7
O6
O5
O4
O3
GND
02
01
O0
A0
A1
A2
A3
32-lead PLCC – Top View
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
A14
A13
A8
A9
A11
OE
A10
CE
O7
O1
O2
GND
O3
O4
O5
O6
A7
A6
A5
A4
A3
A2
A1
A0
O0
4
3
2
1
32
31
30
A12
A15
A16
VPP
VCC
PGM
A17
2.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
AT27LV020A
0549G–EPROM–12/07
AT27LV020A
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient
voltage excursions. Unless accommodated by the system design, these transients may exceed
datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency,
low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor
should be connected between the VCC and Ground terminals of the device, as close to the
device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards
with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected to the array.
4. Block Diagram
5. Absolute Maximum Ratings*
Temperature Under Bias................................. -40° C to +85° C
Storage Temperature .................................... -65° C to +125° C
Voltage on any Pin with
with Respect to Ground ..................................-2.0V to +7.0V(1)
Voltage on A9 with
Respect to Ground .......................................-2.0V to +14.0V(1)
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
VPP Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Notes:
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
VCC + 0.75V DC which may be exceeded if certain precautions are observed (consult application notes) and which may
overshoot to +7.0V for pulses of less than 20 ns.
3
0549G–EPROM–12/07
6. Operating Modes
Mode/Pin
CE
OE
PGM
Ai
VPP
VCC
Outputs
Read(2)
VIL
VIL
X(1)
Ai
X
VCC
DOUT
X
VIH
X
X
X
VCC
High Z
VIH
X
X
X
X
VCC
High Z
Output Disable
Standby
(2)
(2)
Rapid Program(3)
VIL
VIH
VIL
Ai
VPP
VCC
DIN
(3)
VIL
VIL
VIH
Ai
VPP
VCC
DOUT
(3)
VIH
X
X
X
VPP
VCC
High Z
X
VCC
Identification Code
PGM Verify
PGM Inhibit
(4)
Product Identification(3)(5)
Notes:
VIL
VIL
X
A9 = VH
A0 = VIH or VIL
A1 - A17 = VIL
1. X can be VIL or VIH.
2. Read, output disable, and standby modes require, 3.0V ≤VCC ≤3.6V, or 4.5V ≤VCC ≤5.5V.
3. Refer to Programming Characteristics. Programming modes require VCC = 6.5V.
4. VH = 12.0 ± 0.5V.
5. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled
low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
7. DC and AC Operating Conditions for Read Operation
AT27LV020A-12
Industrial Operating Temperature (Case)
-40° C - 85° C
3.0V to 3.6V
VCC Power Supply
4
5V ± 10%
AT27LV020A
0549G–EPROM–12/07
AT27LV020A
8. DC and Operating Characteristics for Read Operation
Symbol
Parameter
Condition
Min
Max
Units
VIN = 0V to VCC
±1
µA
VOUT = 0V to VCC
±5
µA
VPP = VCC
10
µA
ISB1 (CMOS), CE = VCC ± 0.3V
20
µA
ISB2 (TTL), CE = 2.0 to VCC + 0.5V
100
µA
8
mA
VCC = 3.0V to 3.6V
Input Load Current
ILI
ILO
IPP1
Output Leakage Current
(2)
(1)
Read/Standby Current
ISB
VCC Standby Current(1)
ICC
VCC Active Current
VIL
Input Low Voltage
-0.6
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.0 mA
0.4
V
VOH
Output High Voltage
IOH = -2.0 mA
f = 5 MHz, IOUT = 0 mA, CE = VIL
2.4
V
VCC = 4.5V to 5.5V
Input Load Current
ILI
ILO
IPP1
Output Leakage Current
(2)
(1)
Read/Standby Current
VIN = 0V to VCC
±1
µA
VOUT = 0V to VCC
±5
µA
VPP = VCC
10
µA
ISB1 (CMOS), CE = VCC ± 0.3V
100
µA
ISB2 (TTL), CE = 2.0 to VCC + 0.5V
1
mA
f = 5 MHz, IOUT = 0 mA, CE = VIL
25
mA
ISB
VCC Standby Current(1)
ICC
VCC Active Current
VIL
Input Low Voltage
-0.6
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1 mA
0.4
V
VOH
Output High Voltage
IOH = -400 µA
Notes:
2.4
V
1. VCC must be applied simultaneously with or before VPP, and removed simultaneously with or after VPP.
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sun of ICC and IPP.
5
0549G–EPROM–12/07
9. AC Characteristics for Read Operation
VCC = 3.0V to 3.6V and 4.5V to 5.5V
AT27LV020A-12
Symbol
Parameter
Condition
Address to Output Delay
tCE(2)
tOE(2)(3)
tDF(4)(5)
OE or CE High to Output Float, Whichever Occurred First
tOH
Output Hold from Address, CE or OE, Whichever Occurred First
tACC
(3)
Min
Max
Units
CE = OE = VIL
120
ns
CE to Output Delay
OE = VIL
120
ns
OE to Output Delay
CE = VIL
50
ns
40
ns
0
ns
10. AC Waveforms for Read Operation
Notes:
1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
6
AT27LV020A
0549G–EPROM–12/07
AT27LV020A
11. Input Test Waveform and Measurement Level
tR, tF < 20 ns (1% to 90%)
12. Output Test Load
Note:
CL = 1 pF including jig capacitance.
13. Pin Capacitance
f = 1 MHz, T = 25° C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
8
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
7
0549G–EPROM–12/07
14. Programming Waveforms(1)
Notes:
1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the AT27LV020A a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage
transients.
8
AT27LV020A
0549G–EPROM–12/07
AT27LV020A
15. DC Programming Characteristics
TA = 25 ± 5° C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
Symbol
Parameter
Test Conditions
ILI
Input Load Current
VIN = VIL, VIH
VIL
Input Low Level
VIH
Input High Level
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -400 µA
ICC2
VCC Supply Current (Program and Verify)
IPP2
VPP Supply Current
VID
A9 Product Identification Voltage
Min
Max
Units
±10
µA
-0.6
0.8
V
2.0
VCC + 0.5
V
0.4
V
2.4
V
CE = PGM = VIL
11.5
40
mA
20
mA
12.5
V
16. AC Programming Characteristics
TA = 25 ± 5° C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V
Limits
(1)
Min
Test Conditions
Max
Units
Symbol
Parameter
tAS
Address Setup Time
2
µs
tCES
CE Setup Time
2
µs
tOES
OE Setup Time
2
µs
tDS
Data Setup Time
2
µs
tAH
Address Hold Time
0
µs
tDH
Data Hold Time
2
µs
Input Rise and Fall Times
(10% to 90%) 20 ns
0.45V to 2.4V
OE High to Output Float Delay
tDFP
(3)
0
Input Timing Reference Level
0.8V to 2.0V
tVPS
VPP Setup Time
tVCS
VCC Setup Time
tPW
PGM Program Pulse Width(2)
tOE
Data Valid from OE
tPRT
VPP Pulse Rise Time During
Programming
Notes:
Input Pulse Levels
Output Timing Reference Level
0.8V to 2.0V
130
ns
2
µs
2
µs
95
105
µs
150
ns
50
ns
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven –
see timing diagram.
3. Program Pulse width tolerance is 100 µsec ± 5%.
17. Atmel’s AT27LV020A Integrated Product Identification Code(1)
Pins
A0
O7
O6
O5
O4
O3
O2
O1
O0
Hex
Data
Manufacturer
0
0
0
0
1
1
1
1
0
1E
Device Type
1
1
0
0
0
0
1
1
0
86
Codes
Note:
1. The AT27LV020A has the same Product Identification Code as the AT27C020. Both are programming compatible.
9
0549G–EPROM–12/07
18. Rapid Programming Algorithm
A 100 µs PGM pulse width is used to program. The address is set to the first location. VCC is
raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 100 µs
PGM pulse without verification. Then a verification/reprogramming loop is executed for each
address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are
applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been
applied, the part is considered failed. After the byte verifies properly, the next address is
selected until all have been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All bytes are
read again and compared with the original data to determine if the device passes or fails.
10
AT27LV020A
0549G–EPROM–12/07
AT27LV020A
19. Ordering Information
19.1
Standard Package
ICC (mA)
VCC = 3.6V
tACC
(ns)
Active
Standby
120
8
0.02
Note:
19.2
Package
32J
32T
32V(1)
Operation Range
Industrial
(-40° C to 85° C)
Not recommended for new designs. Use Green package option.
Green Package Option (Pb/Halide-free)
ICC (mA)
VCC = 3.6V
tACC
(ns)
Active
Standby
120
8
0.02
Note:
Ordering Code
AT27LV020A-12JI
AT27LV020A-12TI
AT27LV020A-12VI
Ordering Code
Package
AT27LV020A-12JU
AT27LV020A-12TU
AT27LV020A-12VU
32J
32T
32V(1)
Operation Range
Industrial
(-40° C to 85° C)
1. The 32-lead VSOP package is not recommended for new designs.
Package Type
32J
32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
32T
32-Lead, Plastic Thin Small Outline Package (TSOP)
32V
32-Lead, Plastic Thin Small Outline Package (VSOP)
11
0549G–EPROM–12/07
20. Packaging Information
20.1
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E1
E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
3.175
–
3.556
A1
1.524
–
2.413
A2
0.381
–
–
D
12.319
–
12.573
D1
11.354
–
11.506
D2
9.906
–
10.922
E
14.859
–
15.113
E1
13.894
–
14.046
E2
12.471
–
13.487
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
12
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
32J
B
AT27LV020A
0549G–EPROM–12/07
AT27LV020A
20.2
32T –TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
Note 2
E
7.90
8.00
8.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
32T
B
13
0549G–EPROM–12/07
20.3
32V –VSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
13.80
14.00
14.20
D1
12.30
12.40
12.50
Note 2
E
7.90
8.00
8.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
14
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP)
DRAWING NO.
REV.
32V
B
AT27LV020A
0549G–EPROM–12/07
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International
Atmel Corporation
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San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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0549G–EPROM–12/07
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