ATMEL AT49F8011T-90TC 8-megabit (512k x 16/ 1m x 8) 5-volt only flash memory Datasheet

Features
• 4.5V to 5.5V Read/Write
• Access Time - 70 ns
• Sector Erase Architecture
•
•
•
•
•
•
•
•
•
•
– Fourteen 32K Word (64K Byte) Sectors with Individual Write Lockout
– Two 16K Word (32K Byte) Sectors with Individual Write Lockout
– Two 8K Word (16K Byte) Sectors with Individual Write Lockout
– Four 4K Word (8K Byte) Sectors with Individual Write Lockout
Fast Word Program Time - 10 µs
Fast Sector Erase Time - 200 ms
Dual Plane Organization, Permitting Concurrent Read while Program/Erase
– Memory Plane A: Four 4K Word, Two 8K Word and Two 16K Word Sectors
– Memory Plane B: Fourteen 32K Word Sectors
Erase Suspend Capability
– Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
Low-power Operation
– 40 mA Active
– 10 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
RESET Input for Device Initialization
Sector Program Unlock Command
TSOP and CBGA Package Options
Top or Bottom Boot Block Configuration Available
Description
The AT49F8011(T) is a 5.0 volt 8-megabit Flash memory organized as 524,288 words
of 16 bits each or 1,048,576 bytes of 8 bits each. The x16 data appears on I/O0 I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 22 sectors for
erase operations. The device is offered in 48-pin TSOP and 48-ball CBGA packages.
The device has CE, and OE control signals to avoid any bus contention. This device
can be read or reprogrammed using a single 5.0V power supply, making it ideally
suited for in-system programming.
8-megabit
(512K x 16/
1M x 8)
5-volt Only
Flash Memory
AT49F8011
AT49F8011T
Not Recommended
for New Designs
Pin Configurations
Pin Name
Function
A0 - A18
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Reset
RDY/BUSY
READY/BUSY Output
I/O0 - I/O14
Data Inputs/Outputs
I/O15 (A-1)
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
BYTE
Selects Byte or Word Mode
NC
No Connect
DC
Don’t Connect
1264D–FLASH–5/03
1
TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RDY/BUSY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CBGA Top View
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
1
2
A3
3
4
5
6
A7 RDY/BUSY WE
A9
A13
A4
A17
NC
RESET
A8
A12
A2
A6
A18
NC
A10
A14
A1
A5
NC
NC
A11
A15
A0
I/O0
I/O2
I/O5
I/O7
A16
CE
I/O8
I/O10
I/O12
I/O14
BYTE
OE
I/O9
I/O11
VCC
I/O13
I/O15
/A-1
VSS
I/O1
I/O3
I/O4
I/O6
VSS
A
B
C
D
E
F
G
H
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector. Once the data protection for a given sector is enabled, the data in that
sector cannot be changed using input levels between ground and VCC.
The device is segmented into two memory planes. Reads from memory plane B may be performed even while program or erase functions are being executed in memory plane A and vice
versa. This operation allows improved system performance by not requiring the system to wait
for a program or erase operation to complete before a read is performed. To further increase
the flexibility of the device, it contains an Erase Suspend feature. This feature will put the
Erase on hold for any amount of time and let the user read data from or program data to any of
the remaining sectors within the same memory plane. There is no reason to suspend the
erase operation if the data to be read is in the other memory plane. The end of a program or
an Erase cycle is detected by the Ready/Busy pin, Data polling, or by the toggle bit.
A six byte command (bypass unlock) sequence to remove the requirement of entering the
three byte program sequence is offered to further improve programming time. After entering
the six byte code, only single pulses on the write control lines are required for writing into the
device. This mode (single pulse byte/word program) is exited by powering down the device, or
by pulsing the RESET pin low for a minimum of 50ns and then bringing it back to VCC. Erase
and Erase Suspend/Resume commands will not work while in this mode; if entered they will
result in data being programmed into the device. It is not recommended that the six byte code
reside in the software of the final product but only exist in external programming code.
The BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at logic “1”, the device is in word configuration, I/O0-I/O15 are
active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins
I/O0-I/O7 are active and controlled by CE and OE. The data I/O pins I/O8-I/O14 are tri-stated,
and the I/O15 pin is used as an input for the LSB (A-1) address function.
2
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
Block Diagram
I/O0 - I/O15/A-1
INPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
REGISTER
A0 - A18
OUTPUT
MULTIPLEXER
OUTPUT
BUFFER
CE
WE
OE
RESET
BYTE
COMMAND
REGISTER
ADDRESS
LATCH
DATA
COMPARATOR
Y-DECODER
Y-GATING
RDY/BUSY
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
VCC
GND
X-DECODER
PLANE B
SECTORS
PLANE A SECTORS
Device
Operation
READ: The AT49F8011(T) is accessed like an EPROM. When CE and OE are low and WE is
high, the data stored at the memory location determined by the address pins are asserted on
the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or
standby mode depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the Command Definitions table (I/O8 - I/O15 are don't care inputs for
the command codes). The command sequences are written by applying a low pulse on the
WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE. Standard microprocessor write timings are used. The address locations used in the
command sequences are not affected by entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high impedance
state. When a high level is reasserted on the RESET pin, the device returns to the Read or
Standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET pin any sector can be reprogrammed even if the sector lockout feature
has been enabled (see Sector Programming Lockout Override section).
3
1264D–FLASH–5/03
ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase commands.
CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is tEC.
If the sector lockout has been enabled, the Chip Erase will not erase the data in the sector that
has been locked; it will erase only the unprotected sectors. After the chip erase, the device will
return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 22 sectors that can be individually erased. The Sector Erase command is a six bus cycle operation.
The sector address is latched on the falling WE edge of the sixth cycle while the 30H data
input command is latched on the rising edge of WE. The sector erase starts after the rising
edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically
time to completion. The maximum time to erase a section is tSEC. When the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase
command). Once a sector has been protected, data in the protected sectors cannot be
changed unless the RESET pin is taken to 12V ± 0.5V. An attempt to erase a sector that has
been protected will result in the operation terminating in 2 µs.
BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the
internal device command register and is a 4-bus cycle operation. The device will automatically
generate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle
time. The DATA polling feature or the toggle bit feature may be used to indicate the end of a
program cycle.
SECTOR PROGRAMMING LOCKOUT: Each sector has a programming lockout feature. This
feature prevents programming of data in the designated sectors once the feature has been
enabled. These sectors can contain secure code that is used to bring up the system. Enabling
the lockout feature will allow the boot code to stay in the device while data in the rest of the
device is updated. This feature does not have to be activated; any sector’s usage as a write
protected region is optional to the user.
Once the feature is enabled, the data in the protected sectors can no longer be erased or programmed when input levels of 5.5V or less are used. Data in the remaining sectors can still be
changed through the regular programming method. To activate the lockout feature, a series of
six program commands to specific addresses with specific data must be performed. Please
refer to the Command Definitions table.
SECTOR LOCKOUT DETECTION: A software method is available to determine if programming of a sector is locked out. When the device is in the software product identification mode
(see Software product Identification Entry and Exit sections) a read from address location
00002H within a sector will show if programming the sector is locked out. If the data on I/O0 is
low, the sector can be programmed; if the data on I/O0 is high, the program lockout feature
has been enabled and the sector cannot be programmed. The software product identification
exit code should be used to return to standard operation.
SECTOR PROGRAMMING LOCKOUT OVERRIDE: The user can override the sector programming lockout by taking the RESET pin to 12V ± 0.5V. By doing this protected data can be
altered through a chip erase, sector erase or byte/word programming. When the RESET pin is
brought back to TTL levels the sector programming lockout feature is again active.
4
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
ERASE SUSPEND/ERASE RESUME: The erase suspend command allows the system to
interrupt a sector erase operation and then program or read data from a different sector within
the same plane. Since this device has a dual plane architecture, there is no need to use the
erase suspend feature while erasing a sector when you want to read data from a sector in the
other plane. After the erase suspend command is given, the device requires a maximum time
of 15 µs to suspend the erase operation. After the erase operation has been suspended, the
plane which contains the suspended sector enters the erase-suspend-read mode. The system
can then read data or program data to any other sector within the device. An address is not
required during the erase suspend command. During a sector erase suspend, another sector
cannot be erased. To resume the sector erase operation, the system must write the erase
resume command. The erase resume command is a one bus cycle command that does
require the plane address which is determined by A18 - A16. The device also supports an
erase suspend during a complete chip erase. While the chip erase is suspended, the user can
read from any sector within the memory that is protected. The command sequence for a chip
erase suspend and a sector erase suspend are the same.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
DATA POLLING: The AT49F8011(T) features DATA polling to indicate the end of a program
cycle. During a program cycle an attempted read of the last byte/word loaded will result in the
complement of the loaded data on I/O7. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has
completed, true data will be read from the device. DATA polling may begin at any time during
the program cycle. Please see “Status Bit Table” for more details.
TOGGLE BIT: In addition to DATA polling the AT49F8011(T) provides another method for
determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2 which can be used in conjunction with the toggle
bit which i s avai lable on I/O6. W hile a s ector i s eras e sus pended, a read or a
program operation from the suspended sector will result in the I/O2 bit toggling. Please see
“Status Bit Table” for more details.
RDY/BUSY: An open drain READY/BUSY output pin provides another method of detecting
the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal
program and erase cycles and is released at the completion of the cycle. The open drain connection allows for OR-tying of several devices to the same RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs
to the AT49F8011(T) in the following ways: (a) VCC sense: if VCC is below 3.8V (typical), the
program function is inhibited. (b) VCC power on delay: once VCC has reached the VCC sense
level, the device will automatically time out 10 ms (typical) before programming. (c) Program
inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 4.5V to 5.5V power supply, the address inputs and
control inputs (OE, CE, and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
5
1264D–FLASH–5/03
Command Definition in Hex(1)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
5555
AA
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
6
5555
AA
2AAA
55
5555
80
5555
AA
Byte/Word Program
4
5555
AA
2AAA
55
5555
A0
Addr
DIN
Bypass Unlock
6
5555
AA
2AAA
55
5555
80
5555
Single Pulse
Byte/Word Program
1
Addr
DIN
Sector Lockout
6
5555
AA
2AAA
55
5555
80
5555
Erase Suspend
1
xxxx
B0
Erase Resume
1
PA(5)
30
Product ID Entry
3
5555
AA
2AAA
55
5555
90
(2)
3
5555
AA
2AAA
55
5555
F0
(2)
1
xxxx
F0
Product ID Exit
Notes:
6th Bus
Cycle
Addr
Sector Erase
Product ID Exit
5th Bus
Cycle
SA
(3)(4)
2AAA
55
AA
2AAA
55
5555
A0
AA
2AAA
55
SA(3)(4)
40
30
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, A14 - A18 (Don’t Care).
2. Either one of the Product ID Exit commands can be used.
3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see next two
pages for details).
4. When the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command).
Once the sector has been protected, data in the protected sectors cannot be changed unless the RESET pin is taken to
12V ± 0.5V.
5. PA is the plane address (A18 - A16).
Absolute Maximum Ratings*
Temperature Under Bias............................... -55° C to +125° C
Storage Temperature .................................... -65° C to +150° C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
6
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
AT49F8011 – Sector Address Table
Plane
Sector
Size (Bytes/Words)
x8
Address Range (A18 - A-1)
x16
Address Range (A18 - A0)
A
SA0
16K/8K
000000 - 003FFF
00000 - 01FFF
A
SA1
32K/16K
004000 - 00BFFF
02000 - 05FFF
A
SA2
8K/4K
00C000 - 00DFFF
06000 - 06FFF
A
SA3
8K/4K
00E000 - 00FFFF
07000 - 07FFF
A
SA4
8K/4K
010000 - 011FFF
08000 - 08FFF
A
SA5
8K/4K
012000 - 013FFF
09000 - 09FFF
A
SA6
32K/16K
014000 - 018FFF
0A000 - 0DFFF
A
SA7
16K/8K
01C000 - 01FFFF
0E000 - 0FFFF
B
SA8
64K/32K
020000 - 02FFFF
10000 - 17FFF
B
SA9
64K/32K
030000 - 03FFFF
18000 - 1FFFF
B
SA10
64K/32K
040000 - 04FFFF
20000 - 27FFF
B
SA11
64K/32K
050000 - 05FFFF
28000 - 2FFFF
B
SA12
64K/32K
060000 - 06FFFF
30000 - 37FFF
B
SA13
64K/32K
070000 - 07FFFF
38000 - 3FFFF
B
SA14
64K/32K
080000 - 08FFFF
40000 - 47FFF
B
SA15
64K/32K
090000 - 09FFFF
48000 - 4FFFF
B
SA16
64K/32K
0A0000 - 0AFFFF
50000 - 57FFF
B
SA17
64K/32K
0B0000 - 0BFFFF
58000 - 5FFFF
B
SA18
64K/32K
0C0000 - 0CFFFF
60000 - 67FFF
B
SA19
64K/32K
0D0000 - 0DFFFF
68000 - 6FFFF
B
SA20
64K/32K
0E0000 - 0EFFFF
70000 - 77FFF
B
SA21
64K/32K
0F0000 - 0FFFFF
78000 - 7FFFF
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1264D–FLASH–5/03
AT49F8011T – Sector Address Table
Plane
8
Sector
Size (Bytes/Words)
x8
Address Range (A18 - A-1)
x16
Address Range (A18 - A0)
B
SA0
64K/32K
000000 - 00FFFF
00000 - 07FFF
B
SA1
64K/32K
010000 - 01FFFF
08000 - 0FFFF
B
SA2
64K/32K
020000 - 02FFFF
10000 - 17FFF
B
SA3
64K/32K
030000 - 03FFFF
18000 - 1FFFF
B
SA4
64K/32K
040000 - 04FFFF
20000 - 27FFF
B
SA5
64K/32K
050000 - 05FFFF
28000 - 2FFFF
B
SA6
64K/32K
060000 - 06FFFF
30000 - 37FFF
B
SA7
64K/32K
070000 - 07FFFF
38000 - 3FFFF
B
SA8
64K/32K
080000 - 08FFFF
40000 - 47FFF
B
SA9
64K/32K
090000 - 09FFFF
48000 - 4FFFF
B
SA10
64K/32K
0A0000 - 0AFFFF
50000 - 57FFF
B
SA11
64K/32K
0B0000 - 0BFFFF
58000 - 5FFFF
B
SA12
64K/32K
0C0000 - 0CFFFF
60000 - 67FFF
B
SA13
64K/32K
0D0000 - 0DFFFF
68000 - 6FFFF
A
SA14
16K/8K
0E0000 - 0E3FFF
70000 - 71FFF
A
SA15
32K/16K
0E4000 - 0EBFFF
72000 - 75FFF
A
SA16
8K/4K
0EC000 - 0EDFFF
76000 - 76FFF
A
SA17
8K/4K
0EE000 - 0EFFFF
77000 - 77FFF
A
SA18
8K/4K
0F0000 - 0F1FFF
78000 - 78FFF
A
SA19
8K/4K
0F2000 - 0F3FFF
79000 - 79FFF
A
SA20
32K/16K
0F4000 - 0FBFFF
7A000 - 7DFFF
A
SA21
16K/8K
0FC000 - 0FFFFF
7E000 - 7FFFF
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
DC and AC Operating Range
AT49F8011(T)-70
AT49F8011(T)-90
0° C - 70° C
0° C - 70° C
-40° C - 85° C
-40° C - 85° C
4.5V to 5.5V
4.5V to 5.5V
Com.
Operating
Temperature (Case)
Ind.
VCC Power Supply
Operating Modes
Mode
Read
Program/Erase
(2)
Standby/Program Inhibit
CE
OE
WE
RESET
Ai
I/O
VIL
VIL
VIH
VIH
Ai
DOUT
VIL
VIH
VIL
VIH
Ai
DIN
X
VIH
X
High Z
VIH
X
(1)
Program Inhibit
X
X
VIH
VIH
Program Inhibit
X
VIL
X
VIH
Output Disable
X
VIH
X
VIH
Reset
X
X
X
VIL
High Z
X
High Z
Product Identification
Hardware
VIL
VIL
VIH
Software(5)
Notes:
1.
2.
3.
4.
5.
VIH
VIH
A1 - A18 = VIL, A9 = VH(3)
A0 = VIL
Manufacturer Code(4)
A1 - A18 = VIL, A9 = VH(3)
A0 = VIH
Device Code(4)
A0 = VIL, A1 - A18 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A18 = VIL
Device Code(4)
X can be VIL or VIH.
Refer to AC Programming Waveforms.
VH = 12.0V ± 0.5V.
Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: 00CB-AT49F8011; 004A-AT49F8011T.
See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
10
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
1
mA
VCC Active Current
f = 5 MHz; IOUT = 0 mA
40
mA
ICCRW
VCC Read While Write Current
f = 5 MHz; IOUT = 0 mA
60
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
Output High Voltage
IOH = -400 µA
ICC
(1)
VOH
Note:
Min
2.0
V
0.45
2.4
V
V
1. In the erase mode, ICC is 50 mA.
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1264D–FLASH–5/03
AC Read Characteristics
AT49F8011(T)-70
Symbol
Parameter
Min
Max
tACC
Address to Output Delay
tCE(1)
CE to Output Delay
tOE(2)
OE to Output Delay
0
35
tDF(3)(4)
CE or OE to Output Float
0
25
tOH
Output Hold from OE, CE or Address, whichever occurred first
0
tRO
RESET to Output Delay
AT49F8011(T)-90
Min
Max
Units
70
90
ns
70
90
ns
0
40
ns
0
25
ns
0
800
ns
800
ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
OUTPUT
Notes:
10
HIGH Z
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
Input Test Waveforms and Measurement Level
3.0
tR, tF < 5 ns
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
11
1264D–FLASH–5/03
AC Byte/Word Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Set-up Time
10
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
100
ns
tDS
Data Set-up Time
50
ns
tDH, tOEH
Data, OE Hold Time
10
ns
tWPH
Write Pulse Width High
50
ns
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
12
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Byte/Word Programming Time
10
50
µs
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tDS
Data Set-up Time
50
ns
tDH
Data Hold Time
10
ns
tWP
Write Pulse Width
100
ns
tWPH
Write Pulse Width High
50
ns
tEC
Chip Erase Cycle Time
tSEC
Sector Erase Cycle Time
10
200
seconds
ms
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP
tBP
tWPH
WE
tAS
A0 -A18
tAH
tDH
5555
5555
2AAA
5555
ADDRESS
tDS
DATA
55
AA
INPUT
DATA
A0
AA
Sector or Chip Erase Cycle Waveforms
OE
(1)
(4)
CE
tWP
tWPH
(4)
WE
tAS
A0-A18
tAH
tDH
5555
5555
5555
2AAA
Note 2
2AAA
tEC
tDS
DATA
Notes:
AA
55
80
AA
55
Note 3
WORD 0
WORD 1
WORD 2
WORD 3
WORD 4
WORD 5
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See
note 3 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
4. The tWPH time between the 5th and 6th bus cycle should be a minimum of 150 ns.
13
1264D–FLASH–5/03
Data Polling Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
Max
(2)
tOE
OE to Output Delay
tWR
Write Recovery Time
Notes:
Typ
Units
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
A0-A18
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
(2)
tOE
OE to Output Delay
tOEHP
OE High Pulse
tWR
Write Recovery Time
Notes:
Typ
Max
Units
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes:
14
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
Software Product Identification Entry(1)
Sector Lockout Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product Identification Exit(1)(6)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
OR
LOAD DATA F0
TO
ANY ADDRESS
LOAD DATA 40
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
PAUSE 200 µs(2)
LOAD DATA F0
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes:
Notes:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0
(Hex) Address Format: A15 - A0 (Hex), A-1, and
A15 - A18 (Don’t Care).
2. Sector lockout feature enabled.
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0
(Hex) Address Format: A15 - A0 (Hex), A-1, and
A15 - A18 (Don’t Care).
2. A1 - A18 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH (x8); 001FH (x16)
6. Device Code:00CBH - AT49BV8011;
004AH - AT49BV8011T.
7. Either one of the Product ID Exit commands can be
used.
15
1264D–FLASH–5/03
Status Bit Table
Status Bit
I/O 7
Read Address In
I/O 6
I/O 2
Plane A
Plane B
Plane A
Plane B
Plane A
Plane B
Programming in Plane A
I/O7
DATA
TOGGLE
DATA
1
DATA
Programming in Plane B
DATA
I/O7
DATA
TOGGLE
DATA
1
Erasing in Plane A
0
DATA
TOGGLE
DATA
TOGGLE
DATA
Erasing in Plane B
DATA
0
DATA
TOGGLE
DATA
TOGGLE
Erase Suspended & Read
Erasing Sector
1
1
1
1
TOGGLE
TOGGLE
Erase Suspended & Read
Non-Erasing Sector
DATA
DATA
DATA
DATA
DATA
DATA
1
1
1
1
TOGGLE
TOGGLE
Erase Suspended &
Program Non-Erasing
Sector in Plane A
I/O7
DATA
TOGGLE
DATA
TOGGLE
DATA
Erase Suspended &
Program Non-Erasing
Sector in Plane B
DATA
I/O7
DATA
TOGGLE
DATA
TOGGLE
While
Erase Suspended &
Program Erasing Sector
16
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
AT49F8011(T) Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
70
40
90
70
90
Ordering Code
Package
Operation Range
0.01
AT49F8011-70CC
AT49F8011-70TC
48C3
48T
Commercial
(0° C to 70° C)
40
0.01
AT49F8011-70CI
AT49F8011-70TI
48C3
48T
Industrial
(-40° C to 85° C)
40
0.01
AT49F8011-90CC
AT49F8011-90TC
48C3
48T
Commercial
(0° C to 70° C)
40
0.01
AT49F8011-90CI
AT49F8011-90TI
48C3
48T
Industrial
(-40° C to 85° C)
40
0.01
AT49F8011T-70CC
AT49F8011T-70TC
48C3
48T
Commercial
(0° C to 70° C)
40
0.01
AT49F8011T-70CI
AT49F8011T-70TI
48C3
48T
Industrial
(-40° C to 85° C)
40
0.01
AT49F8011T-90CC
AT49F8011T-90TC
48C3
48T
Commercial
(0° C to 70° C)
40
0.01
AT49F8011T-90CI
AT49F8011T-90TI
48C3
48T
Industrial
(-40° C to 85° C)
Package Type
48C3
48-ball, Plastic Chip-Size Ball Grid Array Package (CBGA)
48T
48-lead, Thin Small Outline Package (TSOP)
17
1264D–FLASH–5/03
Packaging Information
48C3 – CBGA
48C3, 48-ball (6 x 8 Array), 0.80 mm Pitch, 8 x 8 x 1.2 mm
Chip-scale Ball Grid Array Package (CBGA)
Dimensions in Millimeters and (Inches)*
8.10 (0.319)
7.90 (0.311)
A1 ID
8.10 (0.319)
7.90 (0.311)
0.30 (0.012)MIN
4.00(0.157)
2.00(0.079)REF
6
5
4
3
2
1
1.20 (0.047) MAX
A
B
C
0.80(0.0315) BSC
NON-ACCUMULATIVE
D
5.60(0.220)
E
F
G
H
1.20(0.047) REF
0.80(0.0315) BSC
NON-ACCUMULATIVE
0.45 (0.018) DIA BALL TYP
*Controlling dimension: millimeters
REV. A
18
04/11/2001
AT49F8011(T)
1264D–FLASH–5/03
AT49F8011(T)
48T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
Note 2
E
11.90
12.00
12.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation DD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
48T
B
19
1264D–FLASH–5/03
Atmel Corporation
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Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
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Printed on recycled paper.
1264D–FLASH–5/03
xM
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