ATMEL ATATMEGA325A 8-bit atmel microcontroller with 16/32/64k bytes in-system programmable programmable Datasheet

Features
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High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller
Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz (ATmega165PA/645P)
– Up to 20MIPS Throughput at 20MHz
(ATmega165A/325A/325PA/645A/3250A/3250PA/6450A/6450P)
– On-Chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– In-System Self-programmable Flash Program Memory
• 16KBytes (ATmega165A/ATmega165PA)
• 32KBytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA)
• 64KBytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P)
– EEPROM
• 512Bytes (ATmega165A/ATmega165PA)
• 1Kbytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA)
• 2Kbytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P)
– Internal SRAM
• 1KBytes (ATmega165A/ATmega165PA)
• 2KBytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA)
• 4KBytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P)
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
QTouch® library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix acquisition
– Up to 64 sense channels
JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
I/O and Packages
– 54/69 Programmable I/O Lines
– 64/100-lead TQFP, 64-pad QFN/MLF and 64-pad DRQFN
Speed Grade:
– ATmega 165A/165PA/645A/645P: 0 - 16MHz @ 1.8 - 5.5V
– ATmega325A/325PA/3250A/3250PA/6450A/6450P: 0 - 20MHz @ 1.8 - 5.5V
Temperature range:
– -40°C to 85°C Industrial
Ultra-Low Power Consumption (picoPower devices)
– Active Mode:
• 1MHz, 1.8V: 215µA
• 32kHz, 1.8V: 8µA (including Oscillator)
– Power-down Mode: 0.1µA at 1.8V
– Power-save Mode: 0.6µA at 1.8V (Including 32kHz RTC
Note:
1.
8-bit Atmel
Microcontroller
with 16/32/64K
Bytes In-System
Programmable
Flash
ATmega165A
ATmega165PA
ATmega325A
ATmega325PA
ATmega3250A
ATmega3250PA
ATmega645A
ATmega645P
ATmega6450A
ATmega6450P
Summary
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C or 100 years at 25°C.
Rev 8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
1. Pin Configurations
Pinout - TQFP and QFN/MLF
DNC
1
(RXD/PCINT0) PE0
2
49 PA2
50 PA1
51 PA0
52 VCC
53 GND
54 PF7 (ADC7/TDI)
55 PF6 (ADC6/TDO)
56 PF5 (ADC5/TMS)
57 PF4 (ADC4/TCK)
58 PF3 (ADC3)
59 PF2 (ADC2)
60 PF1 (ADC1)
AREF
62
61 PF0 (ADC0)
GND
63
64A (TQFP)and 64M1 (QFN/MLF) Pinout
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P
AVCC
Figure 1-1.
64
1.1
48 PA3
47 PA4
INDEX CORNER
8
41 PC6
(CLKO/PCINT7) PE7
9
40 PC5
(SS/PCINT8) PB0
10
39 PC4
(SCK/PCINT9) PB1
11
38 PC3
(MOSI/PCINT10) PB2
12
37 PC2
(MISO/PCINT11) PB3
13
36 PC1
(OC0A/PCINT12) PB4
14
35 PC0
(OC1A/PCINT13) PB5
15
34
PG1
(OC1B/PCINT14) PB6
16
33
PG0
Note:
PD7 32
(DO/PCINT6) PE6
PD6 31
42 PC7
PD5 30
7
PD4 29
(DI/SDA/PCINT5) PE5
PD3 28
43 PG2
PD2 27
6
(INT0) PD1 26
(USCK/SCL/PCINT4) PE4
(ICP1) PD0 25
44 PA7
(TOSC1) XTAL1 24
5
(TOSC2) XTAL2 23
(AIN1/PCINT3) PE3
GND 22
45 PA6
VCC 21
4
RESET/PG5 20
(XCK/AIN0/PCINT2) PE2
(T0) PG4 19
46 PA5
(T1) PG3 18
3
(OC2A/PCINT15) PB7 17
(TXD/PCINT1) PE1
The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen
from the board.
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1.2
Pinout - 100A (TQFP)
Figure 1-2.
Pinout ATmega3250A/ATmega3250PA/ATmega6450A/ATmega6450P
AVCC
AGND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
DNC
DNC
PH7 (PCINT23)
PH6 (PCINT22)
PH5 (PCINT21)
PH4 (PCINT20)
DNC
DNC
GND
VCC
DNC
PA0
PA1
PA2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
TQFP
DNC
1
75
PA3
(RXD/PCINT0) PE0
2
74
PA4
(TXD/PCINT1) PE1
3
73
PA5
(XCK/AIN0/PCINT2) PE2
4
72
PA6
(AIN1/PCINT3) PE3
5
71
PA7
(USCK/SCL/PCINT4) PE4
6
70
PG2
(DI/SDA/PCINT5) PE5
7
69
PC7
(DO/PCINT6) PE6
8
68
PC6
(CLKO/PCINT7) PE7
9
67
DNC
VCC
10
66
PH3 (PCINT19)
GND
11
65
PH2 (PCINT18)
DNC
12
64
PH1 (PCINT17)
(PCINT24) PJ0
13
63
PH0 (PCINT16)
(PCINT25) PJ1
14
62
DNC
DNC
15
61
DNC
DNC
16
60
DNC
DNC
17
59
DNC
DNC
18
58
PC5
(SS/PCINT8) PB0
19
57
PC4
(SCK/PCINT9) PB1
20
56
PC3
(MOSI/PCINT10) PB2
21
55
PC2
(MISO/PCINT11) PB3
22
54
PC1
(OC0A/PCINT12) PB4
23
53
PC0
(OC1A/PCINT13) PB5
24
52
PG1
(OC1B/PCINT14) PB6
25
51
PG0
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DNC
(PCINT27) PJ3
(PCINT28) PJ4
(PCINT29) PJ5
(PCINT30) PJ6
DNC
(ICP1) PD0
(INT0) PD1
PD2
PD3
PD4
PD5
PD6
PD7
35
DNC
(PCINT26) PJ2
34
(TOSC1) XTAL1
36
33
(TOSC2) XTAL2
30
RESET/PG5
32
29
(T0) PG4
VCC
28
(T1) PG3
GND
27
DNC
31
26
(OC2A/PCINT15) PB7
INDEX CORNER
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2. Overview
The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, this
microcontroller achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
Block Diagram
Block Diagram
GND
PF0 - PF7
VCC
PORTA DRIVERS
PORTF DRIVERS
DATA DIR.
REG. PORTF
DATA REGISTER
PORTF
PC0 - PC7
PA0 - PA7
PORTC DRIVERS
DATA DIR.
REG. PORTA
DATA REGISTER
PORTA
XTAL2
Figure 2-1.
XTAL1
2.1
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
AGND
CALIB. OSC
ADC
INTERNAL
OSCILLATOR
AREF
STACK
POINTER
WATCHDOG
TIMER
ON-CHIP DEBUG
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
BOUNDARYSCAN
INSTRUCTION
REGISTER
TIMING AND
CONTROL
TIMER/
COUNTERS
GENERAL
PURPOSE
REGISTERS
X
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
CONTROL
LINES
+
-
INTERRUPT
UNIT
ALU
EEPROM
STATUS
REGISTER
AVR CPU
ANALOG
COMPARATOR
Z
Y
RESET
DATA DIR.
REG. PORTH
DATA REGISTER
PORTH
PROGRAM
COUNTER
DATA DIR.
REG. PORTJ
DATA REGISTER
PORTJ
PORTH DRIVERS
PORTJ DRIVERS
PJ0 - PJ6
PH0 - PH7
OSCILLATOR
JTAG TAP
USART
UNIVERSAL
SERIAL INTERFACE
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
PORTE DRIVERS
PE0 - PE7
SPI
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
PORTB DRIVERS
PB0 - PB7
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
PORTD DRIVERS
PD0 - PD7
DATA REG.
PORTG
DATA DIR.
REG. PORTG
PORTG DRIVERS
PG0 - PG4
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
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The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P provides the
following features: 16K/32K/64K bytes of In-System Programmable Flash with Read-While-Write
capabilities, 512/1K/2K bytes EEPROM, 1K/2K/4K byte SRAM, 54/69 general purpose I/O lines,
32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging
support and programming, three flexible Timer/Counters with compare modes, internal and
external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal
Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator,
disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode,
the asynchronous timer continues to run, allowing the user to maintain a timer base while the
rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions.
In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.
Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers
robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key
Suppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel devise is a powerful microcontroller that provides a highly flexible and
cost effective solution to many embedded control applications.
The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro
Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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2.2
Comparison Between
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P
Table 2-1.
2.3
2.3.1
Differences between: ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P
Device
Flash
EEPROM
RAM
MHz
ATmega165A
16Kbyte
512Bytes
1Kbyte
16
ATmega165PA
16Kbyte
512Bytes
1Kbyte
16
ATmega325A
32Kbyte
1Kbyte
2Kbyte
20
ATmega325PA
32Kbyte
1Kbyte
2Kbyte
20
ATmega3250A
32Kbytes
1Kbyte
2Kbyte
20
ATmega3250PA
32Kbyte
1Kbyte
2Kbyte
20
ATmega645A
64Kbyte
2Kbyte
4Kbyte
16
ATmega645P
64Kbyte
2Kbyte
4Kbyte
16
ATmega6450A
64Kbyte
2Kbyte
4Kbyte
20
ATmega6450P
64Kbyte
2Kbyte
4Kbyte
20
Pin Descriptions
VCC
Digital supply voltage.
2.3.2
GND
Ground.
2.3.3
Port A (PA7:PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate Functions of Port B” on page 76.
2.3.4
Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate Functions of Port B” on page 76.
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2.3.5
Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate Functions of Port D” on page 79.
2.3.6
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate Functions of Port D” on page 79.
2.3.7
Port E (PE7:PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate Functions of Port E” on page 80.
2.3.8
Port F (PF7:PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface, see ”Alternate Functions of Port F” on
page 82.
2.3.9
Port G (PG5:PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
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Port G also serves the functions of various special features of the
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on page
84.
2.3.10
Port H (PH7:PH0)
Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port H output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port H pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port H also serves the functions of various
ATmega3250A/3250PA/6450A/6450P as listed on page 85.
2.3.11
special
features
of
the
Port J (PJ6:PJ0)
Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port J pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port J also serves the functions of various
ATmega3250A/3250PA/6450A/6450P as listed on page 87.
2.3.12
special
features
of
the
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 28-13 on page
328. Shorter pulses are not guaranteed to generate a reset.
2.3.13
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.14
XTAL2
Output from the inverting Oscillator amplifier.
2.3.15
AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
2.3.16
AREF
This is the analog reference pin for the A/D Converter.
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3. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
5. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
These code examples assume that the part specific header file is included before compilation.
For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
6. Capacitive touch sensing
The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces
on most Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and
QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library
for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information
and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the
Atmel QTouch Library User Guide - also available for download from the Atmel website.
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7. Register Summary
Note:
Address
Name
(0xFF)
Reserved
(0xFE)
Reserved
(0xFD)
Reserved
(0xFC)
Reserved
(0xFB)
Reserved
(0xFA)
Reserved
(0xF9)
Reserved
(0xF8)
Reserved
(0xF7)
Reserved
(0xF6)
Reserved
(0xF5)
Reserved
(0xF4)
Reserved
(0xF3)
Reserved
(0xF2)
Reserved
(0xF1)
Reserved
(0xF0)
Reserved
(0xEF)
Reserved
(0xEE)
Reserved
(0xED)
Reserved
Registers with bold type only available in ATmega3250A/3250PA/6450A/6450P.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0xEC)
Reserved
(0xEB)
Reserved
-
-
-
-
-
-
-
-
(0xEA)
Reserved
-
-
-
-
-
-
-
-
(0xE9)
Reserved
-
-
-
-
-
-
-
-
(0xE8)
Reserved
-
-
-
-
-
-
-
-
(0xE7)
Reserved
(0xE6)
Reserved
(0xE5)
Reserved
(0xE4)
Reserved
Page
(0xE3)
Reserved
-
-
-
-
-
-
-
-
(0xE2)
Reserved
-
-
-
-
-
-
-
-
(0xE1)
Reserved
-
-
-
-
-
-
-
-
(0xE0)
Reserved
-
-
-
-
-
-
-
-
(0xDF)
Reserved
-
-
-
-
-
-
-
-
(0xDE)
Reserved
-
-
-
-
-
-
-
-
(0xDD)
PORTJ
-
PORTJ6
PORTJ5
PORTJ4
PORTJ3
PORTJ2
PORTJ1
PORTJ0
93
(0xDC)
DDRJ
-
DDJ6
DDJ5
DDJ4
DDJ3
DDJ2
DDJ1
DDJ0
93
(0xDB)
PINJ
-
PINJ6
PINJ5
PINJ4
PINJ3
PINJ2
PINJ1
PINJ0
93
(0xDA)
PORTH
PORTH7
PORTH6
PORTH5
PORTH4
PORTH3
PORTH2
PORTH1
PORTH0
92
(0xD9)
DDRH
DDH7
DDH6
DDH5
DDH4
DDH3
DDH2
DDH1
DDH0
93
(0xD8)
PINH
PINH7
PINH6
PINH5
PINH4
PINH3
PINH2
PINH1
PINH0
93
(0xD7)
Reserved
-
-
-
-
-
-
-
-
(0xD6)
Reserved
-
-
-
-
-
-
-
-
(0xD5)
Reserved
-
-
-
-
-
-
-
-
(0xD4)
Reserved
-
-
-
-
-
-
-
-
(0xD3)
Reserved
-
-
-
-
-
-
-
-
(0xD2)
Reserved
-
-
-
-
-
-
-
-
(0xD1)
Reserved
-
-
-
-
-
-
-
-
(0xD0)
Reserved
-
-
-
-
-
-
-
-
(0xCF)
Reserved
-
-
-
-
-
-
-
-
(0xCE)
Reserved
-
-
-
-
-
-
-
-
(0xCD)
Reserved
-
-
-
-
-
-
-
-
(0xCC)
Reserved
-
-
-
-
-
-
-
-
(0xCB)
Reserved
-
-
-
-
-
-
-
-
(0xCA)
Reserved
-
-
-
-
-
-
-
-
(0xC9)
Reserved
-
-
-
-
-
-
-
-
(0xC8)
Reserved
-
-
-
-
-
-
-
-
(0xC7)
Reserved
-
-
-
-
-
-
-
-
(0xC6)
UDR0
(0xC5)
UBRR0H
USART0 Data Register
193
USART0 Baud Rate Register High
197
10
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
Address
Name
(0xC4)
UBRR0L
(0xC3)
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
USART0 Baud Rate Register Low
-
-
-
-
-
Page
197
(0xC2)
UCSR0C
-
UMSEL0
UPM01
UPM00
USBS0
UCSZ01
UCSZ00
UCPOL0
195
(0xC1)
UCSR0B
RXCIE0
TXCIE0
UDRIE0
RXEN0
TXEN0
UCSZ02
RXB80
TXB80
194
(0xC0)
UCSR0A
RXC0
TXC0
UDRE0
FE0
DOR0
UPE0
U2X0
MPCM0
193
(0xBF)
Reserved
-
-
-
-
-
-
-
-
(0xBE)
Reserved
-
-
-
-
-
-
-
-
(0xBD)
Reserved
-
-
-
-
-
-
-
-
(0xBC)
Reserved
-
-
-
-
-
-
-
-
(0xBB)
Reserved
-
-
-
-
-
-
-
-
(0xBA)
USIDR
(0xB9)
USISR
USISIF
USIOIF
USIPF
USIDC
USICNT3
USICNT2
USICNT1
USICNT0
206
(0xB8)
USICR
USISIE
USIOIE
USIWM1
USIWM0
USICS1
USICS0
USICLK
USITC
207
(0xB7)
Reserved
-
-
-
-
-
-
-
-
(0xB6)
ASSR
-
-
-
EXCLK
AS2
TCN2UB
OCR2UB
TCR2UB
(0xB5)
Reserved
-
-
-
-
-
-
-
-
(0xB4)
Reserved
-
-
-
-
-
-
-
-
(0xB3)
OCR2A
Timer/Counter 2 Output Compare Register A
156
(0xB2)
TCNT2
Timer/Counter2
156
(0xB1)
Reserved
-
-
-
-
-
-
-
-
(0xB0)
TCCR2A
FOC2A
WGM20
COM2A1
COM2A0
WGM21
CS22
CS21
CS20
(0xAF)
Reserved
-
-
-
-
-
-
-
-
USI Data Register
206
157
154
(0xAE)
Reserved
-
-
-
-
-
-
-
-
(0xAD)
Reserved
-
-
-
-
-
-
-
-
(0xAC)
Reserved
-
-
-
-
-
-
-
-
(0xAB)
Reserved
-
-
-
-
-
-
-
-
(0xAA)
Reserved
-
-
-
-
-
-
-
-
(0xA9)
Reserved
-
-
-
-
-
-
-
-
(0xA8)
Reserved
-
-
-
-
-
-
-
-
(0xA7)
Reserved
-
-
-
-
-
-
-
-
(0xA6)
Reserved
-
-
-
-
-
-
-
-
(0xA5)
Reserved
-
-
-
-
-
-
-
-
(0xA4)
Reserved
-
-
-
-
-
-
-
-
(0xA3)
Reserved
-
-
-
-
-
-
-
-
(0xA2)
Reserved
-
-
-
-
-
-
-
-
(0xA1)
Reserved
-
-
-
-
-
-
-
-
(0xA0)
Reserved
-
-
-
-
-
-
-
-
(0x9F)
Reserved
-
-
-
-
-
-
-
-
(0x9E)
Reserved
-
-
-
-
-
-
-
-
(0x9D)
Reserved
-
-
-
-
-
-
-
-
(0x9C)
Reserved
-
-
-
-
-
-
-
-
(0x9B)
Reserved
-
-
-
-
-
-
-
-
(0x9A)
Reserved
-
-
-
-
-
-
-
-
(0x99)
Reserved
-
-
-
-
-
-
-
-
(0x98)
Reserved
-
-
-
-
-
-
-
-
(0x97)
Reserved
-
-
-
-
-
-
-
-
(0x96)
Reserved
-
-
-
-
-
-
-
-
(0x95)
Reserved
-
-
-
-
-
-
-
-
(0x94)
Reserved
-
-
-
-
-
-
-
-
(0x93)
Reserved
-
-
-
-
-
-
-
-
(0x92)
Reserved
-
-
-
-
-
-
-
-
(0x91)
Reserved
-
-
-
-
-
-
-
-
(0x90)
Reserved
-
-
-
-
-
-
-
-
(0x8F)
Reserved
-
-
-
-
-
-
-
-
(0x8E)
Reserved
-
-
-
-
-
-
-
-
(0x8D)
Reserved
-
-
-
-
-
-
-
-
(0x8C)
Reserved
-
-
-
-
-
-
-
-
(0x8B)
OCR1BH
Timer/Counter1 Output Compare Register B High
(0x8A)
OCR1BL
Timer/Counter1 Output Compare Register B Low
134
(0x89)
OCR1AH
Timer/Counter1 Output Compare Register A High
134
(0x88)
OCR1AL
Timer/Counter1 Output Compare Register A Low
134
(0x87)
ICR1H
Timer/Counter1 Input Capture Register High
135
(0x86)
ICR1L
Timer/Counter1 Input Capture Register Low
135
134
11
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x85)
TCNT1H
Timer/Counter1 High
(0x84)
TCNT1L
Timer/Counter1 Low
(0x83)
Reserved
–
–
–
(0x82)
TCCR1C
FOC1A
FOC1B
–
–
–
–
–
–
133
(0x81)
TCCR1B
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
132
–
–
134
134
–
–
–
(0x80)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
–
–
WGM11
WGM10
130
(0x7F)
DIDR1
–
–
–
–
–
–
AIN1D
AIN0D
213
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
231
–
–
–
–
–
–
–
–
(0x7E)
DIDR0
(0x7D)
Reserved
(0x7C)
ADMUX
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
227
(0x7B)
ADCSRB
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
231
(0x7A)
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
(0x79)
ADCH
(0x78)
ADCL
(0x77)
Reserved
–
–
–
–
–
–
–
–
(0x76)
Reserved
–
–
–
–
–
–
–
–
(0x75)
Reserved
–
–
–
–
–
–
–
–
(0x74)
Reserved
–
–
–
–
–
–
–
–
(0x73)
PCMSK3
–
PCINT30
PCINT29
PCINT28
PCINT27
PCINT26
PCINT25
PCINT24
(0x72)
Reserved
–
–
–
–
–
–
–
–
(0x71)
Reserved
–
–
–
–
–
–
–
–
(0x70)
TIMSK2
–
–
–
–
–
–
OCIE2A
TOIE2
(0x6F)
TIMSK1
–
-
ICIE1
–
–
OCIE1B
OCIE1A
TOIE1
135
(0x6E)
TIMSK0
–
–
–
–
–
–
OCIE0A
TOIE0
107
(0x6D)
PCMSK2
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
67
(0x6C)
PCMSK1
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
66
(0x6B)
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
67
(0x6A)
Reserved
–
–
–
–
–
–
–
–
(0x69)
EICRA
–
–
–
–
–
–
ISC01
ISC00
(0x68)
Reserved
–
–
–
–
–
–
–
–
(0x67)
Reserved
–
–
–
–
–
–
–
–
(0x66)
OSCCAL
(0x65)
Reserved
–
–
–
–
–
–
–
–
(0x64)
PRR
–
–
–
–
PRTIM1
PRSPI
PSUSART0
PRADC
(0x63)
Reserved
–
–
–
–
–
–
–
–
(0x62)
Reserved
–
–
–
–
–
–
–
–
(0x61)
CLKPR
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
37
(0x60)
WDTCR
–
–
–
WDCE
WDE
WDP2
WDP1
WDP0
53
I
T
H
S
V
N
Z
C
ADC Data Register High
229
230
ADC Data Register Low
230
Oscillator Calibration Register [CAL7:0]
66
157
64
37
45
0x3F (0x5F)
SREG
0x3E (0x5E)
SPH
0x3D (0x5D)
SPL
0x3C (0x5C)
Reserved
–
–
–
–
–
–
–
–
0x3B (0x5B)
Reserved
–
–
–
–
–
–
–
–
0x3A (0x5A)
Reserved
–
–
–
–
–
–
–
–
0x39 (0x59)
Reserved
–
–
–
–
–
–
–
–
0x38 (0x58)
Reserved
–
–
–
–
–
–
–
–
0x37 (0x57)
SPMCSR
SPMIE
RWWSB
–
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
0x36 (0x56)
Reserved
–
–
–
–
–
–
–
–
0x35 (0x55)
MCUCR
JTD
BODS
BODSE
PUD
–
–
IVSEL
IVCE
0x34 (0x54)
MCUSR
–
–
–
JTRF
WDRF
BORF
EXTRF
PORF
53
0x33 (0x53)
SMCR
–
–
–
–
SM2
SM1
SM0
SE
53
Stack Pointer High
12
15
Stack Pointer Low
15
283
61/90/267
0x32 (0x52)
Reserved
–
–
–
–
–
–
–
–
0x31 (0x51)
OCDR
IDRD/OCDR7
OCDR6
OCDR5
OCDR4
OCDR3
OCDR2
OCDR1
OCDR0
238
0x30 (0x50)
ACSR
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
212
0x2F (0x4F)
Reserved
–
–
–
–
–
–
–
–
–
–
–
–
SPI2X
167
MSTR
CPOL
CPHA
SPR1
SPR0
166
0x2E (0x4E)
SPDR
0x2D (0x4D)
SPSR
SPIF
WCOL
–
SPI Data Register
0x2C (0x4C)
SPCR
SPIE
SPE
DORD
0x2B (0x4B)
GPIOR2
General Purpose I/O Register
0x2A (0x4A)
GPIOR1
General Purpose I/O Register
0x29 (0x49)
Reserved
–
–
–
0x28 (0x48)
Reserved
–
–
–
0x27 (0x47)
OCR0A
168
27
27
–
–
–
–
–
–
–
–
–
–
Timer/Counter0 Output Compare A
107
12
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
–
–
COM0A0
WGM01
CS02
CS01
CS00
105
–
–
–
PSR2
PSR10
139/158
–
–
0x26 (0x46)
TCNT0
Timer/Counter0
0x25 (0x45)
Reserved
–
–
–
–
0x24 (0x44)
TCCR0A
FOC0A
WGM00
COM0A1
0x23 (0x43)
GTCCR
TSM
–
–
0x22 (0x42)
EEARH
–
–
–
0x21 (0x41)
EEARL
EEPROM Address Register Low
0x20 (0x40)
EEDR
EEPROM Data Register
0x1F (0x3F)
EECR
–
–
–
–
Page
107
EERIE
EEPROM Address Register High
26
26
26
EEMWE
EEWE
EERE
General Purpose I/O Register
27
0x1E (0x3E)
GPIOR0
0x1D (0x3D)
EIMSK
PCIE
PCIE2
PCIE1
PCIE0
–
–
–
INT0
28
64
0x1C (0x3C)
EIFR
PCIF3
PCIF2
PCIF1
PCIF0
–
–
–
INTF0
65
0x1B (0x3B)
Reserved
–
–
–
–
–
–
–
–
0x1A (0x3A)
Reserved
–
–
–
–
–
–
–
–
0x19 (0x39)
Reserved
–
–
–
–
–
–
–
–
0x18 (0x38)
Reserved
–
–
–
–
–
–
–
–
0x17 (0x37)
TIFR2
–
–
–
–
–
–
OCF2A
TOV2
157
0x16 (0x36)
TIFR1
–
–
ICF1
–
–
OCF1B
OCF1A
TOV1
136
0x15 (0x35)
TIFR0
–
–
–
–
–
–
OCF0A
TOV0
139
0x14 (0x34)
PORTG
–
–
–
PORTG4
PORTG3
PORTG2
PORTG1
PORTG0
92
0x13 (0x33)
DDRG
–
–
–
DDG4
DDG3
DDG2
DDG1
DDG0
92
0x12 (0x32)
PING
0x11 (0x31)
PORTF
–
–
PING5
PING4
PING3
PING2
PING1
PING0
92
PORTF7
PORTF6
PORTF5
PORTF4
PORTF3
PORTF2
PORTF1
PORTF0
92
0x10 (0x30)
DDRF
DDF7
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0
92
0x0F (0x2F)
PINF
PINF7
PINF6
PINF5
PINF4
PINF3
PINF2
PINF1
PINF0
92
0x0E (0x2E)
PORTE
PORTE7
PORTE6
PORTE5
PORTE4
PORTE3
PORTE2
PORTE1
PORTE0
91
0x0D (0x2D)
DDRE
DDE7
DDE6
DDE5
DDE4
DDE3
DDE2
DDE1
DDE0
91
0x0C (0x2C)
PINE
PINE7
PINE6
PINE5
PINE4
PINE3
PINE2
PINE1
PINE0
92
0x0B (0x2B)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
91
0x0A (0x2A)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
91
0x09 (0x29)
PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
91
0x08 (0x28)
PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
91
0x07 (0x27)
DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
91
0x06 (0x26)
PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
91
0x05 (0x25)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
90
0x04 (0x24)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
90
0x03 (0x23)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
90
0x02 (0x22)
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
90
0x01 (0x21)
DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
90
0x00 (0x20)
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
90
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
13
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
8. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Add with Carry two Registers
Rd ← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd ← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd ← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ← Rd - K - C
Z,C,N,V,H
1
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd ← Rd • Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd ← Rd • K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd ← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd ← Rd ⊕ Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd ← 0xFF − Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd ← 0x00 − Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd ← Rd • (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd ← 0xFF
None
1
2
MUL
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
Z,C
MULS
Rd, Rr
Multiply Signed
R1:R0 ← Rd x Rr
Z,C
2
MULSU
Rd, Rr
Multiply Signed with Unsigned
R1:R0 ← Rd x Rr
Z,C
2
FMUL
Rd, Rr
Fractional Multiply Unsigned
R1:R0 ← (Rd x Rr) << 1
Z,C
2
FMULS
Rd, Rr
Fractional Multiply Signed
R1:R0 ¬ (Rd x Rr) << 1
Z,C
2
FMULSU
Rd, Rr
Fractional Multiply Signed with Unsigned
R1:R0 ¬ (Rd x Rr) << 1
Z,C
2
2
BRANCH INSTRUCTIONS
RJMP
k
IJMP
Relative Jump
PC ← PC + k + 1
None
Indirect Jump to (Z)
PC ← Z
None
2
JMP
k
Direct Jump
PC ← k
None
3
RCALL
k
Relative Subroutine Call
PC ← PC + k + 1
None
3
Indirect Call to (Z)
PC ← Z
None
3
Direct Subroutine Call
PC ← k
None
4
RET
Subroutine Return
PC ← STACK
None
4
RETI
Interrupt Return
PC ← STACK
I
4
ICALL
CALL
k
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC ← PC + 2 or 3
None
CP
Rd,Rr
Compare
Rd − Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd − K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ← PC + 2 or 3
None
1/2/3
1/2/3
1
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC←PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC←PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
14
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
SEC
Set Carry
C←1
C
1
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I←0
I
1
SES
Set Signed Test Flag
S←1
S
1
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Twos Complement Overflow.
V←1
V
1
CLV
Clear Twos Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H←1
H←0
H
H
1
1
Rd ← Rr
Rd+1:Rd ← Rr+1:Rr
None
1
None
1
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
LDI
Rd, K
Load Immediate
Rd ← K
None
LD
Rd, X
Load Indirect
Rd ← (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd ← (X), X ← X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X ← X - 1, Rd ← (X)
None
2
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd ← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y ← Y - 1, Rd ← (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd ← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd ← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z ← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ← (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd ← (k)
None
2
ST
X, Rr
Store Indirect
(X) ← Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) ← Rr, X ← X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X ← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) ← Rr, Y ← Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y ← Y - 1, (Y) ← Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) ← Rr, Z ← Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z ← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
2
Load Program Memory
R0 ← (Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd ← (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd ← (Z), Z ← Z+1
None
3
Store Program Memory
(Z) ← R1:R0
None
-
IN
Rd, P
In Port
Rd ← P
None
1
OUT
P, Rr
Out Port
P ← Rr
None
1
SPM
15
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
Mnemonics
Operands
Description
Operation
Flags
#Clocks
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
None
1
MCU CONTROL INSTRUCTIONS
NOP
No Operation
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
BREAK
Watchdog Reset
Break
(see specific descr. for WDR/timer)
For On-chip Debug Only
None
None
1
N/A
16
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
9. Ordering Information
9.1
ATmega165A
Speed (MHz)(3)
16
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
Operation Range
ATmega165A-AU
ATmega165A-AUR(4)
ATmega165A-MU
ATmega165A-MUR(4)
ATmega165A-MCH
ATmega165A-MCHR(4)
64A
64A
64M1
64M1
64MC
64MC
Industrial
(-40°C to 85°C)
ATmega165A-AN
ATmega165A-ANR(4)
ATmega165A-MN
ATmega165A-MNR(4)
64A
64A
64M1
64M1
Extended
(-40°C to 105°C)(5)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 28-1 on page 326.
4. Tape & Reel
5. See Appendix A - ATmega165A/165PA/325P/3250P specification at 105°C
Package Type
64A
64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M1
64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
64MC
64-lead (2-row Staggered), 7 x 7 x 1.0 mm body, 4.0 x 4.0mm Exposed Pad, Quad Flat No-Lead Package (QFN)
17
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
9.2
ATmega165PA
Speed (MHz)(3)
16
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
Operation Range
ATmega165PA-AU
ATmega165PA-AUR(4)
ATmega165PA-MU
ATmega165PA-MUR(4)
ATmega165PA-MCH
ATmega165PA-MCHR(4)
64A
64A
64M1
64M1
64MC
64MC
Industrial
(-40°C to 85°C)
ATmega165PA-AN
ATmega165PA-ANR(4)
ATmega165PA-MN
ATmega165PA-MNR(4)
64A
64A
64M1
64M1
Extended
(-40°C to 105°C)(5)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 28-1 on page 326.
4. Tape & Reel.
5. See Appendix A - ATmega165A/165PA/325P/3250P specification at 105°C.
Package Type
64A
64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M1
64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
64MC
64-lead (2-row Staggered), 7 x 7 x 1.0mm body, 4.0 x 4.0 mm Exposed Pad, Quad Flat No-Lead Package (QFN)
18
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
9.3
ATmega325A
Speed (MHz)(3)
20
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
Operation Range
ATmega325A-AU
ATmega325A-AUR(4)
ATmega325A-MU
ATmega325A-MUR(4)
64A
64A
64M1
64M1
Industrial
(-40°C to 85°C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 28-1 on page 326.
4. Tape & Reel
Package Type
64A
64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M1
64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
19
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
9.4
ATmega325PA
Speed (MHz)(3)
20
Notes:
Power Supply
1.5 - 5.5V
Ordering Code(2)
Package(1)
Operation Range
ATmega325PA-AU
ATmega325PA-AUR(4)
ATmega325PA-MU
ATmega325PA-MUR(4)
64A
64A
64M1
64M1
Industrial
(-40°C to 85°C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 28-1 on page 326.
4. Tape & Reel
Package Type
64A
64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M1
64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
20
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
9.5
ATmega3250A
Speed (MHz)(3)
Power Supply
20
1.5 - 5.5V
Notes:
Ordering Code(2)
Package(1)
Operation Range
ATmega3250A-AU
ATmega3250A-AUR(4)
100A
100A
Industrial
(-40°C to 85°C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 28-1 on page 326.
4. Tape & Reel
Package Type
100A
100-lead, 14 x 14 x 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
21
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
9.6
ATmega3250PA
Speed (MHz)(3)
Power Supply
20
1.5 - 5.5V
Notes:
Ordering Code(2)
Package(1)
Operation Range
ATmega3250PA-AU
ATmega3250PA-AUR(4)
100A
100A
Industrial
(-40°C to 85°C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 28-1 on page 326.
4. Tape & Reel
Package Type
100A
100-lead, 14 x 14 x 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
22
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
9.7
ATmega645A
Speed (MHz)(3)
20
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
Operation Range
ATmega645A-AU
ATmega645A-AUR(4)
ATmega645A-MU
ATmega645A-MUR(4)
64A
64A
64M1
64M1
Industrial
(-40°C to 85°C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 28-1 on page 326.
4. Tape & Reel
Package Type
64A
64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M1
64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
23
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
9.8
ATmega645P
Speed (MHz)(3)
20
Notes:
Power Supply
1.8 - 5.5V
Ordering Code(2)
Package(1)
Operation Range
ATmega645P-AU
ATmega645P-AUR(4)
ATmega645P-MU
ATmega645P-MUR(4)
64A
64A
64M1
64M1
Industrial
(-40°C to 85°C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 28-1 on page 326.
4. Tape & Reel
Package Type
64A
64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M1
64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
24
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
9.9
ATmega6450A
Speed (MHz)(3)
Power Supply
20
1.8 - 5.5V
Notes:
Ordering Code(2)
ATmega6450A-AU
ATmega6450A-AUR(4)
Package(1)
Operation Range
100A
100A
Industrial
(-40°C to 85°C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 28-1 on page 326.
4. Tape & Reel
Package Type
100A
100-lead, 14 x 14 x 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
25
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
9.10
ATmega6450P
Speed (MHz)(3)
Power Supply
20
1.8 - 5.5V
Notes:
Ordering Code(2)
ATmega6450P-AU
ATmega6450P-AUR(4)
Package(1)
Operation Range
100A
100A
Industrial
(-40°C to 85°C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 28-1 on page 326.
4. Tape & Reel
Package Type
100A
100-lead, 14 x 14 x 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
26
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
10. Packaging Information
10.1
64A
PIN 1
B
PIN 1
e
B
PIN 1 IDENTIFIER
e
PIN 1 IDENTIFIER
E1
E
E1
E
D1
D1
DD
C C 0°~7°
0°~7°
A1
A1
A2
A2
AA
LL
COMMON
DIMENSIONS
COMMON
DIMENSIONS
(Unit
of of
Measure
= mm)
(Unit
Measure
= mm)
SYMBOL
MIN
SYMBOL MIN
–
–
–
A1
0.05
–
A2
0.95
1.00
1.05
D
15.75
16.00
16.25
D1
13.90
14.00
14.10
E
15.75
16.00
16.25
A
A1
A2
D
D1
Notes:
E
Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB.
1.This
package conforms
to do
JEDEC
reference
Variation
AEB.
2. Dimensions
D1 and E1
not include
moldMS-026,
protrusion.
Allowable
2. Dimensions
and E1
include
mold protrusion.
protrusionD1
is 0.25
mmdo
pernot
side.
Dimensions
D1 and E1 Allowable
are maximum
protrusion
is 0.25
mm
per side. including
Dimensions
and E1 are maximum
plastic body
size
dimensions
moldD1
mismatch.
3. Leadbody
coplanarity
is 0.10 mmincluding
maximum.
plastic
size dimensions
mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
NOM
MAX NOTE
NOTE
NOM MAX
A
E1
E1
B
B
0.05
0.95
15.75
13.90
15.75
13.90
0.09
0.45
eL
e
0.15
14.00
16.00
14.00
1.05
16.25
–
Note 2
16.25
14.10
14.00
–
Note 2
14.10
–
0.30
0.09
–
16.00
13.90
C
L
1.20
0.15
1.00
0.30
C
1.20
–
Note 2
14.10
0.45
Note 2
0.45
0.20
–
–
0.45 0.80 TYP
–
0.20
0.75
0.75
0.80 TYP
2010-10-20
TITLE
2325 Orchard Parkway
TITLE
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
San
Jose, CA
95131
2325
Orchard
Parkway
0.8 mm
Lead 14
Pitch,
Thin
Quad
Package
(TQFP)
64A,
64-lead,
x 14
mmProfile
BodyPlastic
Size, 1.0
mmFlat
Body
Thickness,
R
R
San Jose, CA 95131
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.2010-10-20
REV.
DRAWING NO.
64A
64A
REV.
C
C
27
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
10.2
64M1
D
D
Marked Pin# 1 ID
Marked Pin# 1 ID
E
E
SEATING PLANE
CSEATING
PLANE
C
A1
A1
TOP
VIEW
TOP
VIEW
AA
KK
0.08 C C
0.08
L L
Pin
Pin #1
#1 Corner
Corner
D2
D2
11
22
33
Option A
Option
SIDEVIEW
VIEW
SIDE
Pin
Pin#1
#1
Triangle
Triangle
COMMON
DIMENSIONS
COMMON
DIMENSIONS
(Unit
of of
Measure
= mm)
(Unit
Measure
= mm)
SYMBOL
MIN
SYMBOL MIN
E2E2
Option B
Option B
Pin #1
Pin #1
Chamfer
Chamfer
(C
0.30)
(C 0.30)
NOM
NOM
MAX
MAX NOTE
NOTE
A
A
0.80
0.80
0.90
1.00
A1
–
0.02
0.05
A1
K
b
b
e
Option C
e
BOTTOM VIEW
BOTTOM VIEW
Pin #1
Notch
Pin #1
(0.20
NotchR)
(0.20 R)
0.30
D
8.90
9.00
9.10
D2
5.20
5.40
5.60
E
8.90
9.00
9.10
D2
E
E2
0.18
8.90
5.20
8.90
5.20
E2
5.20
e
e
L
K
Notes:
1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
0.05
0.25
L
Notes:
0.02
0.18
D
Option C
1.00
b
b
K
–
0.90
0.35
0.35
1.25
K
1.25
0.25
0.30
9.00
9.10
5.40
5.60
9.00
9.10
5.40
5.60
5.40
0.50 BSC
0.50 BSC
0.40
0.40
5.60
0.45
0.45
1.40
1.55
1.40
1.55
2. Dimension
and MO-220,
tolerance (SAW
conform
to ASMEY14.5M-1994.
1. JEDEC
Standard
Singulation)
Fig. 1, VMMD.
2. Dimension and tolerance conform to ASMEY14.5M-1994.
TITLE
2325 Orchard Parkway
64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,
TITLE
SanOrchard
Jose, CA
95131
2325
Parkway
5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)
R
R
San Jose, CA 95131
64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,
5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)
2010-10-19
2010-10-19
DRAWING NO.
REV.
DRAWING
64M1 NO. HREV.
64M1
H
28
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
10.3
64MC
C
Pin 1 ID
D
SIDE VIEW
y
A1
E
A
TOP VIEW
eT
eT/2
L
eR
A26
A34
B23
B30
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
A25
B1
B22
R0.20
0.40
b
D2
SYMBOL
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.18
0.23
0.28
C
eT
B7
B16
A8
A18
A9
A17
L
(0.18) REF
B8
B15
E2
K
BOTTOM VIEW
Note:
1. The terminal #1 ID is a Laser-marked Feature.
Package Drawing Contact:
[email protected]
(0.1) REF
NOTE
0.20 REF
D
6.90
7.00
7.10
D2
3.95
4.00
4.05
E
6.90
7.00
7.10
E2
3.95
4.00
4.05
eT
–
0.65
–
eR
–
0.65
–
K
0.20
–
–
L
0.35
0.40
0.45
y
0.00
–
0.075
GPC
TITLE
64MC, 64QFN (2-Row Staggered),
ZXC
7 x 7 x 1.00 mm Body, 4.0 x 4.0 mm Exposed Pad,
Quad Flat No Lead Package
(REF)
10/3/07
DRAWING NO. REV.
64MC
A
29
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
10.4
100A
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0°~7°
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.08 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
15.75
16.00
16.25
D1
13.90
14.00
14.10
E
15.75
16.00
16.25
E1
13.90
14.00
14.10
B
0.17
–
0.27
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.50 TYP
2010-10-20
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
100A
REV.
D
30
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
11. Errata
11.1
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P Rev. G
No known errata.
11.2
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P Rev. A to F
Not sampled.
31
8285DS–AVR–06/11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
12. Datasheet Revision History
Please note that the referring page numbers in this section are referring to this document. The
referring revisions in this section are referring to the document revision.
12.1
12.2
12.3
12.4
8285D – 06/11
1.
Removed “Preliminary” from the front page.
1.
Updated ”Signature Bytes” on page 288. A, P and PA devices have different signature (0x002)
bytes.
2.
Updated ”DC Characteristics” on page 319 for all devices.
1.
Updated the datasheet according to the Atmel new Brand Style Guide
2.
Updated “Signature Bytes” , Table 27.3 on page 288.
3.
Updated the power supply voltage (1.5 - 5.5V) for all devices in ”Ordering Information” on page
17.
4.
Added “Ordering Information” for Extended Temperature (-40°C to 105°C)
1.
Initial revision (Based on the ATmega165P/325P/3250P/645/6450/V).
2.
Changes done compared to ATmega165P/325P/3250P/645/6450/V datasheet:
– New EIMSK and EIFR register overview
– New graphics in ”Typical Characteristics” on page 334.
– Ordering Information includes Tape & Reel
– New ”Ordering Information” on page 17.
– QTouch Library Support Features
8285C – 06/11
8285B – 03/11
8285A – 09/10
32
8285DS–AVR–06/11
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: (+1)(408) 441-0311
Fax: (+1)(408) 487-2600
www.atmel.com
Atmel Asia Limited
Unit 1-5 & 16, 19/F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
HONG KONG
Tel: (+852) 2245-6100
Fax: (+852) 2722-1369
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Business Campus
Parkring 4
D-85748 Garching b. Munich
GERMANY
Tel: (+49) 89-31970-0
Fax: (+49) 89-3194621
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1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
JAPAN
Tel: (+81)(3) 3523-3551
Fax: (+81)(3) 3523-7581
© 2011 Atmel Corporation. All rights reserved.
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other countries. Other terms and product names may be trademarks of others.
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8285DS–AVR–06/11
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