Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN74AVC16T245 SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 SN74AVC16T245 16-Bit Dual-Supply Bus Transceiver with Configurable Level-Shifting / Voltage Translation and Tri-State Outputs 1 Features 3 Description • This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC16T245 device is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. The device is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes. 1 • • • • • • • • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage VCC Isolation Feature – If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State Overvoltage-Tolerant Inputs and Outputs Allow Mixed-Voltage-Mode Data Communications Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2 V to 3.6 V Power-Supply Range Ioff Supports Partial-Power-Down Mode Operation I/Os Are 4.6 V Tolerant Maximum Data Rates – 380 Mbps (1.8 V to 3.3 V Level-Shifting) – 200 Mbps (<1.8 V to 3.3 V Level-Shifting) – 200 Mbps (Level-Shifting to 2.5 V or 1.8 V) – 150 Mbps (Level-Shifting to 1.5 V) – 100 Mbps (Level-Shifting to 1.2 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 8000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 2 Applications • • • • The SN74AVC16T245 device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses effectively are isolated. The SN74AVC16T245 control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA. Device Information(1) PART NUMBER SN74AVC16T245 PACKAGE BODY SIZE (NOM) TSSOP (48) 12.50 mm × 6.10 mm TVSOP (48) 9.70 mm × 4.40 mm BGA MICROSTAR 7.00 mm × 4.50 mm JUNIOR (56) (1) For all available packages, see the orderable addendum at the end of the data sheet. Personal Electronics Industrial Enterprise Telecom Logic Diagram (Positive Logic) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 To Seven Other Channels 24 2OE 36 13 1B1 2B1 To Seven Other Channels 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AVC16T245 SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8 1 1 1 2 3 4 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings ............................................................ 5 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Switching Characteristics: VCCA = 1.2 V ................... 8 Switching Characteristics: VCCA = 1.5 V ± 0.1 V....... 8 Switching Characteristics: VCCA = 1.8 V ± 0.15 V .... 8 Switching Characteristics: VCCA = 2.5 V ± 0.2 V....... 9 Switching Characteristics: VCCA = 3.3 V ± 0.3 V..... 9 Operating Characteristics........................................ 9 Typical Characteristics .......................................... 10 Parameter Measurement Information ................ 12 9 Detailed Description ............................................ 13 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 13 13 13 14 10 Application and Implementation........................ 15 10.1 Application Information.......................................... 15 10.2 Typical Application ............................................... 16 11 Power Supply Recommendations ..................... 18 12 Layout................................................................... 18 12.1 Layout Guidelines ................................................. 18 12.2 Layout Example .................................................... 19 13 Device and Documentation Support ................. 20 13.1 13.2 13.3 13.4 13.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 14 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (February 2015) to Revision E • Updated Pin Functions Table. ............................................................................................................................................... 4 Changes from Revision C (August 2005) to Revision D • 2 Page Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 SN74AVC16T245 www.ti.com SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 5 Description (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 3 SN74AVC16T245 SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 www.ti.com 6 Pin Configuration and Functions GQL or ZQL Package 56-Pin BGA MICROSTAR JUNIOR Top View 1 2 3 4 5 DGG or DGV Package 48-Pin TSSOP or TVSOP Top View 6 1DIR 1B1 1B2 GND 1B3 1B4 VCCB 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCCB 2B5 2B6 GND 2B7 2B8 2DIR A B C D E F G H J K 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCCA 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCCA 2A5 2A6 GND 2A7 2A8 2OE Pin Functions PIN NAME TSSOP, TVSOP BGA MICROSTAR I/O DESCRIPTION 1DIR, 2DIR 1, 24 A1, K1 I 1B1 to 1B8 2, 3, 5, 6, 8, 9, 11, 12 B2, B1, C2, C1, D2, D1, E2, E1 I/O Input/Output. Referenced to VCCB 2B1 to 2B8 13, 14, 16, 17, 19, 20, 22, 23 F1, F2, G1, G2, H1, H2, J1, J2 I/O Input/Output. Referenced to VCCB GND 4, 10, 15, 21, 45, 39, 34, 28 B3, D3, G3, J3, J4, G4, D4, B4 — Ground VCCB 7, 18 C3, H3 — B-port supply voltage. 1.2 V ≤ VCCB ≤ 3.6 V 1OE, 2OE 48, 25 A6, K6 — Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State mode. Referenced to VCCA 1A1 to 1A8 47, 46, 44, 43, 41, 40, 38, 37 B5, B6, C5, C6, D5, D6, E5, E6 I/O Input/Output. Referenced to VCCA 2A1 to 2A8 36, 35, 33, 32, 30, 29, 27, 26 F6, F5, G6, G5, H6, H5, J6, J5 I/O Input/Output. Referenced to VCCA 42, 31 C4, H4 — A-port supply voltage. 1.2 V ≤ VCCB ≤ 3.6 V — A2, A3, A4, A5, K2, K3, K4, K5 — No internal connection VCCA N.C. 4 Direction-control signal Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 SN74AVC16T245 www.ti.com SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT –0.5 4.6 V I/O ports (A port) –0.5 4.6 I/O ports (B port) –0.5 4.6 Control inputs –0.5 4.6 A port –0.5 4.6 B port –0.5 4.6 A port –0.5 VCCA + 0.5 B port –0.5 VCCB + 0.5 VCCA VCCB Supply voltage VI Input voltage (2) VO Voltage range applied to any output in the high-impedance or poweroff state (2) VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through each VCCA, VCCB, and GND ±100 mA RθJA Package thermal impedance (4) DGG package 70 DGV package 58 GQL/ZQL package 42 V V V °C/W TJ Junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) (2) (3) (4) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input voltage (VI ) and output negative-voltage ( VO) ratings may be exceeded if the input and output current ratings are observed. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. The package thermal impedance is calculated in accordance with JESD 51-7. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±8000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1000 Machine model (A115-A) ±200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 5 SN74AVC16T245 SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 www.ti.com 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) (2) (3) VCCI VCCO MIN MAX UNIT VCCA Supply voltage 1.2 3.6 V VCCB Supply voltage 1.2 3.6 V High-level input voltage VIH Low-level input voltage VIL Data inputs (4) Data inputs (4) 1.2 V to 1.95 V VCCI × 0.65 1.95 V to 2.7 V 1.6 2.7 V to 3.6 V 2 V 1.2 V to 1.95 V VCCI × 0.35 1.95 V to 2.7 V 0.7 2.7 V to 3.6 V High-level input voltage VIH Low-level input voltage VIL VI DIR (referenced to VCCA) (5) DIR (referenced to VCCA) (5) Output voltage IOH 1.95 V to 2.7 V 1.6 2.7 V to 3.6 V 2 V 1.2 V to 1.95 V VCCA × 0.35 1.95 V to 2.7 V 0.7 2.7 V to 3.6 V 0.8 0 3.6 Active state 0 VCCO Tri-State 0 3.6 Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature (4) (5) VCCA × 0.65 High-level output current IOL (1) (2) (3) 0.8 1.2 V to 1.95 V Input voltage VO V 1.2 V –3 1.4 V to 1.6 V –6 1.65 V to 1.95 V –8 2.3 V to 2.7 V –9 3 V to 3.6 V –12 1.2 V 3 1.4 V to 1.6 V 6 1.65 V to 1.95 V 8 2.3 V to 2.7 V 9 3 V to 3.6 V 12 –40 V V V mA mA 5 ns/V 85 °C VCCI is the VCC associated with the data input port. VCCO is the VCC associated with the output port. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V. For VCCA values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V. 7.4 Thermal Information SN74AVC16T245 DGV (TVSOP) DGG (TSSOP) ZQL (BGA MICROSTAR JUNIOR) 48 PINS 48 PINS 56 PINS 82.5 69.9 64.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 34.2 23.9 16.6 °C/W RθJB Junction-to-board thermal resistance 45.1 36.6 30.8 °C/W ψJT Junction-to-top characterization parameter 2.7 1.7 0.9 °C/W ψJB Junction-to-board characterization parameter 44.6 36.2 64.6 °C/W THERMAL METRIC RθJA (1) 6 (1) Junction-to-ambient thermal resistance UNIT For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 SN74AVC16T245 www.ti.com SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) (1) (2) PARAMETER TEST CONDITIONS IOH = –100 μA VCCA VCCB 1.2 V to 3.6 V 1.2 V to 3.6 V 1.2 V 1.2 V IOH = –3 mA IOH = –6 mA VOH A or B port A or B port IOZ (3) 2.3 V 2.3 V 1.75 IOH = –12 mA 3V 3V 2.3 IOL = 100 μA 1.2 V to 3.6 V 1.2 V to 3.6 V 1.2 V 1.2 V 1.4 V 1.4 V 0.35 1.65 V 1.65 V 0.45 IOL = 9 mA 2.3 V 2.3 V 0.55 IOL = 12 mA 3V 3V 0.7 1.2 V to 3.6 V 1.2 V to 3.6 V VI = VCCA or GND 0.2 0.15 ±0.025 ±0.25 ±1 V μA 0V 0 to 3.6 V ±0.1 ±2.5 ±5 0V ±0.5 ±2.5 ±5 3.6 V 3.6 V ±0.5 ±2.5 ±5 1.2 V to 3.6 V 1.2 V to 3.6 V 25 0V 3.6 V –5 3.6 V 0V 25 1.2 V to 3.6 V 1.2 V to 3.6 V 25 0V 3.6 V 25 3.6 V 0V –5 VI = VCCI or GND, IO = 0 1.2 V to 3.6 V 1.2 V to 3.6 V 45 VI = 3.3 V or GND 3.3 V 3.3 V 3.5 pF 3.3 V 3.3 V 7 pF Ci Control inputs Cio A or B port VO = 3.3 V or GND (1) (2) (3) V 0 to 3.6 V VI or VO = 0 to 3.6 V VI = VCCI or GND, IO = 0 ICCA + ICCB VCCO – 0.2 IOH = –9 mA VI = VIL UNIT 0.95 1.2 VI = VCCI or GND, IO = 0 ICCB MAX 1.05 VO = VCCO or GND, A or B port VI = VCCI or GND, OE =VIH ICCA TYP 1.4 V IOL = 8 mA Ioff MIN 1.65 V IOL = 6 mA II TA = –40°C to 85°C MAX 1.4 V VI = VIH IOL = 3 mA Control inputs TYP 1.65 V IOH = –8 mA VOL TA = 25°C MIN μA μA μA μA μA VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. For I/O ports, the parameter IOZ includes the input leakage current. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 7 SN74AVC16T245 SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 www.ti.com 7.6 Switching Characteristics: VCCA = 1.2 V over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 11) PARAMETER tPLH FROM (INPUT) TO (OUTPUT) A B VCCB = 1.2 V MIN TYP B OE TYP VCCB = 2.5 V MAX MIN TYP VCCB = 3.3 V MAX MIN TYP 3.3 3 2.8 3.2 4.1 3.3 3 2.8 3.2 4.4 4 3.8 3.6 3.5 4.4 4 3.8 3.6 3.5 6.4 6.4 6.4 6.4 6.4 6.4 6.4 6.4 6.4 6.4 6 4.6 4 3.4 3.2 6 4.6 4 3.4 3.2 6.6 6.6 6.6 6.6 6.8 6.6 6.6 6.6 6.6 6.8 6 4.9 4.9 4.2 5.3 6 4.9 4.9 4.2 5.3 UNIT MAX A OE ns B ns OE A ns tPLZ tPHZ MIN 4.1 tPZL tPHZ VCCB = 1.8 V MAX ns tPZL tPZH TYP A tPHL tPZH MIN ns tPHL tPLH VCCB = 1.5 V MAX OE B ns tPLZ 7.7 Switching Characteristics: VCCA = 1.5 V ± 0.1 V over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 11) PARAMETER tPLH FROM (INPUT) TO (OUTPUT) A B VCCB = 1.2 V MIN TYP B OE OE TYP VCCB = 2.5 V ± 0.2 V MAX MIN TYP VCCB = 3.3 V ± 0.3 V MAX MIN TYP 3.6 0.5 6.2 0.5 5.2 0.5 4.1 0.5 3.7 3.6 0.5 6.2 0.5 5.2 0.5 4.1 0.5 3.7 3.3 0.5 6.2 0.5 5.9 0.5 5.6 0.5 5.5 3.3 0.5 6.2 0.5 5.9 0.5 5.6 0.5 5.5 4.3 1 10.1 1 10.1 1 10.1 1 10.1 4.3 1 10.1 1 10.1 1 10.1 1 10.1 5.6 1 10.1 0.5 8.1 0.5 5.9 0.5 5.2 5.6 1 10.1 0.5 8.1 0.5 5.9 0.5 5.2 4.5 1.5 9.1 1.5 9.1 1.5 9.1 1.5 9.1 4.5 1.5 9.1 1.5 9.1 1.5 9.1 1.5 9.1 5.5 1.5 8.7 1.5 7.5 1 6.5 1 6.3 5.5 1.5 8.7 1.5 7.5 1 6.5 1 6.3 B OE ns A OE UNIT MAX ns ns tPLZ tPHZ MIN A tPZL tPHZ VCCB = 1.8 V ± 0.15 V MAX ns tPZL tPZH TYP A tPHL tPZH MIN ns tPHL tPLH VCCB = 1.5 V ± 0.1 V MAX B ns tPLZ 7.8 Switching Characteristics: VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 11) PARAMETER tPLH FROM (INPUT) TO (OUTPUT) A B VCCB = 1.2 V MIN TYP tPHL tPLH B OE OE OE OE TYP VCCB = 2.5 V ± 0.2 V MAX MIN TYP VCCB = 3.3 V ± 0.3 V MAX MIN TYP UNIT MAX 3.4 0.5 5.9 0.5 4.8 0.5 3.7 0.5 3.3 3.4 0.5 5.9 0.5 4.8 0.5 3.7 0.5 3.3 3 0.5 5.2 0.5 4.8 0.5 4.5 0.5 4.4 3 0.5 5.2 0.5 4.8 0.5 4.5 0.5 4.4 3.4 1 7.8 1 7.8 1 7.8 1 7.8 3.4 1 7.8 1 7.8 1 7.8 1 7.8 5.4 1 9.2 0.5 7.4 0.5 5.3 0.5 4.5 5.4 1 9.2 0.5 7.4 0.5 5.3 0.5 4.5 4.2 1.5 7.7 1.5 7.7 1.5 7.7 1.5 7.7 4.2 1.5 7.7 1.5 7.7 1.5 7.7 1.5 7.7 5.2 1.5 8.4 1.5 7.1 1 5.9 1 5.7 5.2 1.5 8.4 1.5 7.1 1 5.9 1 5.7 ns ns ns ns ns B tPLZ 8 MIN A tPLZ tPHZ VCCB = 1.8 V ± 0.15 V MAX B tPZL tPHZ TYP A tPZL tPZH MIN A tPHL tPZH VCCB = 1.5 V ± 0.1 V MAX ns Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 SN74AVC16T245 www.ti.com SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 7.9 Switching Characteristics: VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 11) PARAMETER FROM (INPUT) TO (OUTPUT) A B tPLH VCCB = 1.2 V MIN TYP B OE OE TYP VCCB = 2.5 V ± 0.2 V MAX MIN TYP VCCB = 3.3 V ± 0.3 V MAX MIN TYP 3.2 0.5 5.6 0.5 4.5 0.5 3.3 0.5 2.8 3.2 0.5 5.6 0.5 4.5 0.5 3.3 0.5 2.8 2.6 0.5 4.1 0.5 3.7 0.5 3.3 0.5 3.2 2.6 0.5 4.1 0.5 3.7 0.5 3.3 0.5 3.2 2.5 0.5 5.3 0.5 5.3 0.5 5.3 0.5 5.3 2.5 0.5 5.3 0.5 5.3 0.5 5.3 0.5 5.3 5.2 0.5 9.4 0.5 7.3 0.5 5.1 0.5 4.5 5.2 0.5 9.4 0.5 7.3 0.5 5.1 0.5 4.5 3 1 6.1 1 6.1 1 6.1 1 6.1 3 1 6.1 1 6.1 1 6.1 1 6.1 5 1 7.9 1 6.6 1 6.1 1 5.2 5 1 7.9 1 6.6 1 6.1 1 5.2 B OE ns A OE UNIT MAX ns ns tPLZ tPHZ MIN A tPZL tPHZ VCCB = 1.8 V ± 0.15 V MAX ns tPZL tPZH TYP A tPHL tPZH MIN ns tPHL tPLH VCCB = 1.5 V ± 0.1 V MAX B ns tPLZ 7.10 Switching Characteristics: VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 11) PARAMETER tPLH FROM (INPUT) TO (OUTPUT) A B VCCB = 1.2 V MIN TYP B OE OE TYP VCCB = 2.5 V ± 0.2 V MAX MIN TYP VCCB = 3.3 V ± 0.3 V MAX MIN TYP OE OE UNIT MAX 3.2 0.5 5.5 0.5 4.4 0.5 3.2 0.5 2.7 3.2 0.5 5.5 0.5 4.4 0.5 3.2 0.5 2.7 2.8 0.5 3.7 0.5 3.3 0.5 2.8 0.5 2.7 2.8 0.5 3.7 0.5 3.3 0.5 2.8 0.5 2.7 2.2 0.5 4.3 0.5 4.2 0.5 4.1 0.5 4 2.2 0.5 4.3 0.5 4.2 0.5 4.1 0.5 4 5.1 0.5 9.3 0.5 7.2 0.5 4.9 0.5 4 5.1 0.5 9.3 0.5 7.2 0.5 4.9 0.5 4 3.4 0.5 5 0.5 5 0.5 5 0.5 5 3.4 0.5 5 0.5 5 0.5 5 0.5 5 4.9 1 7.7 1 6.5 1 5.2 0.5 5 4.9 1 7.7 1 6.5 1 5.2 0.5 5 ns B ns A ns tPLZ tPHZ MIN A tPZL tPHZ VCCB = 1.8 V ± 0.15 V MAX ns tPZL tPZH TYP A tPHL tPZH MIN ns tPHL tPLH VCCB = 1.5 V ± 0.1 V MAX B ns tPLZ 7.11 Operating Characteristics TA = 25°C PARAMETER TEST CONDITIONS Outputs enabled VCCA = VCCB = 1.2 V MIN TYP MAX VCCA = VCCB = 1.5 V VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V MIN MIN MIN TYP MAX TYP MAX TYP MAX VCCA = VCCB = 3.3 V MIN TYP 1 1 1 1 2 1 1 1 1 1 13 13 14 15 16 Outputs disabled 1 1 1 1 1 Outputs enabled 13 13 14 15 16 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 UNIT MAX A to B Outputs disabled CpdA (1) Outputs enabled CL = 0, f = 10 MHz, tr = tf = 1 ns pF B to A A to B Outputs disabled CpdB (1) Outputs enabled CL = 0, f = 10 MHz, tr = tf = 1 ns pF B to A Outputs disabled (1) Power dissipation capacitance per transceiver. Refer to the TI application report, CMOS Power Consumption and Cpd Calculation, SCAA035 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 9 SN74AVC16T245 SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 www.ti.com 7.12 Typical Characteristics 6 6 5 5 tPHL − Propagation Delay − ns tPLH − Propagation Delay − ns TA = 25°C 4 3 2 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V 1 4 3 2 0 0 0 10 20 30 40 CL − Load Capacitance − pF 50 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V 1 60 0 10 6 6 5 5 4 3 2 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V 10 20 30 2 40 50 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V 1 60 0 10 40 6 6 5 5 4 3 2 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V 20 30 60 4 3 2 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V 1 0 0 10 50 Figure 4. Typical Propagation Delay tPHL (A to B) vs Load Capacitance tPHL − Propagation Delay − ns tPLH − Propagation Delay − ns 30 VCCA = 1.5 V Figure 3. Typical Propagation Delay tPLH (A to B) vs Load Capacitance 40 50 60 0 CL − Load Capacitance − pF 10 20 30 40 50 60 CL − Load Capacitance − pF VCCA = 1.8 V VCCA = 1.8 V Figure 5. Typical Propagation Delay tPLH (A to B) vs Load Capacitance 10 20 CL − Load Capacitance − pF VCCA = 1.5 V 0 60 3 CL − Load Capacitance − pF 1 50 4 0 0 40 Figure 2. Typical Propagation Delay tPHL (A to B) vs Load Capacitance tPHL − Propagation Delay − ns tPLH − Propagation Delay − ns Figure 1. Typical Propagation Delay tPLH (A to B) vs Load Capacitance 0 30 VCCA = 1.2 V VCCA = 1.2 V 1 20 CL − Load Capacitance − pF Figure 6. Typical Propagation Delay tPHL (A to B) vs Load Capacitance Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 SN74AVC16T245 www.ti.com SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 Typical Characteristics (continued) TA = 25°C 6 6 5 tPHL − Propagation Delay − ns tPLH − Propagation Delay − ns 5 4 3 2 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V 1 0 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V 0 10 20 30 40 50 4 3 2 1 0 60 0 10 30 40 50 60 VCCA = 2.5 V VCCA = 2.5 V Figure 7. Typical Propagation Delay tPLH (A to B) vs Load Capacitance Figure 8. Typical Propagation Delay tPHL (A to B) vs Load Capacitance 6 6 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V 5 tPHL − Propagation Delay − ns 5 tPLH − Propagation Delay − ns 20 CL − Load Capacitance − pF CL − Load Capacitance − pF 4 3 2 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V 1 0 0 10 20 30 40 50 4 3 2 1 0 60 0 CL − Load Capacitance − pF 10 20 30 40 50 60 CL − Load Capacitance − pF VCCA = 3.3 V VCCA = 3.3 V Figure 9. Typical Propagation Delay tPLH (A to B) vs Load Capacitance Figure 10. Typical Propagation Delay tPHL (A to B) vs Load Capacitance Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 11 SN74AVC16T245 SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 www.ti.com 8 Parameter Measurement Information 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.2 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 15 pF 15 pF 15 pF 15 pF 15 pF 2 kW 2 kW 2 kW 2 kW 2 kW 0.1 V 0.1 V 0.15 V 0.15 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V tPLZ tPZL VCCI Input VCCI/2 VCCI/2 0V tPLH Output tPHL VOH VCCO/2 VOL VCCO/2 VCCO Output Waveform 1 S1 at 2 × VCCO (see Note B) VCCO/2 VOL + VTP VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCCO/2 VOH − VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. t PLH and tPHL are the same as tpd. F. VCCI is the VCC associated with the input port. G. VCCO is the VCC associated with the output port. Figure 11. Load Circuit and Voltage Waveforms 12 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 SN74AVC16T245 www.ti.com SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 9 Detailed Description 9.1 Overview The SN74AVC16T245 is a 16-bit, dual-supply noninverting bidirectional voltage level translation. Pins A and control pins (DIR and OE) are supported by VCCA and pins B are supported by VCCB. The A port can accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.2 V to 3.6 V. A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When OE is set to high, both A and B are in the high-impedance state. This device is fully specified for partial-power-down applications using off output current (Ioff). The VCC isolation feature ensures that if either VCC input is at GND, both ports are put in a high-impedance state. 9.2 Functional Block Diagram 1 24 1DIR 2DIR 48 25 1OE 47 2OE 36 1A1 2A1 2 13 1B1 To Seven Other Channels 2B1 To Seven Other Channels 9.3 Feature Description 9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range Both VCCA and VCCB can be supplied at any voltage from 1.2 V to 3.6 V making the device suitable for translating between any of the low voltage nodes (1.2 V, 1.8 V, 2.5 V, and 3.3 V). 9.3.2 Partial-Power-Down Mode Operation This device is fully specified for partial-power-down applications using off output current (Ioff). The Ioff circuitry will prevent backflow current by disabling I/O output circuits when device is in partial power-down mode. 9.3.3 VCC Isolation The VCC isolation feature ensures that if either VCCA or VCCB are at GND, both ports will be in a high-impedance state (IOZ shown in Electrical Characteristics). This prevents false logic levels from being presented to either bus. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 13 SN74AVC16T245 SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 www.ti.com 9.4 Device Functional Modes The SN74AVC16T245 is a voltage level translator that can operate from 1.2 V to 3.6 V (VCCA) and 1.2 V to 3.6 V (VCCB). The signal translation between 1.2 V and 3.6 V requires direction control and output enable control. When OE is low and DIR is high, data transmission is from A to B. When OE is low and DIR is low, data transmission is from B to A. When OE is high, both output ports will be high-impedance. Table 1. Functions Table (1) CONTROL INPUTS OE (1) 14 OUTPUT CIRCUITS B PORT OPERATION DIR A PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B bus H X Hi-Z Hi-Z Isolation Input circuits of the data I/Os always are active. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 SN74AVC16T245 www.ti.com SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The SN74AVC16T245 device can be used in level-shifting applications for interfacing devices and addressing mixed voltage incompatibility. The SN74AVC16T245 device is ideal for data transmission where direction is different for each channel. 10.1.1 Enable Times Calculate the enable times for the SN74AVC16T45 using the following formulas: tPZH (DIR to A) = tPLZ tPZL (DIR to A) = tPHZ tPZH (DIR to B) = tPLZ tPZL (DIR to B) = tPHZ (DIR (DIR (DIR (DIR to to to to B) + B) + A) + A) + tPLH (B to tPHL (B to tPLH (A to tPHL (A to A) A) B) B) (1) (2) (3) (4) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74AVC16T245 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 15 SN74AVC16T245 SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 www.ti.com 10.2 Typical Application 1.8 V 3.3 V 0.1 µF 0.1 µF VCCA 1 µF VCCB 1DIR/2DIR 1OE/2OE 1.8-V Controller 3.3-V System SN74AVC16T245 Data 1A1/2A1 1B1/2B1 1A2/2A2 1B2/2B2 1A3/2A3 1B3/2B3 1A4/2A4 1B4/2B4 1A5/2A5 1B5/2B5 1A6/2A6 1B6/2B6 1A7/2A7 1B7/2B7 1A8/2A8 1B8/2B8 GND Data GND GND Figure 12. Typical Application Schematic 10.2.1 Design Requirements This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the intended flow of data and take care not to violate any of the high or low logic levels. Unused data inputs must not be floating, as this can cause excessive internal leakage on the input CMOS structure. Tie any unused input and output ports directly to ground. For this design example, use the parameters listed in Table 2. Table 2. Design Parameters 16 DESIGN PARAMETER EXAMPLE VALUE Input voltage range 1.2 V to 3.6 V Output voltage range 1.2 V to 3.6 V Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 SN74AVC16T245 www.ti.com SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 10.2.2 Detailed Design Procedure To begin the design process, determine the following: 10.2.2.1 Input Voltage Ranges Use the supply voltage of the device that is driving the SN74AVC16T245 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port. 10.2.2.2 Output Voltage Range Use the supply voltage of the device that the SN74AVC16T245 device is driving to determine the output voltage range. 10.2.3 Application Curve Input (1.2 V) Output (3.3 V) Figure 13. Translation Up (1.2 V to 3.3 V) at 2.5 MHz Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 17 SN74AVC16T245 SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 www.ti.com 11 Power Supply Recommendations The SN74AVC16T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts any supply voltage from 1.2 V to 3.6 V and VCCB accepts any supply voltage from 1.2 V to 3.6 V. The A port and B port are designed to track VCCA and VCCB, respectively, allowing for low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V and 3.3-V voltage nodes. The output-enable OE input circuit is designed so that it is supplied by VCCA and when the OE input is high, all outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to VCCA through a pullup resistor and must not be enabled until VCCAand VCCB are fully ramped and stable. The minimum value of the pullup resistor to VCCA is determined by the current-sinking capability of the driver. 12 Layout 12.1 Layout Guidelines To • • • 18 ensure reliability of the device, following common printed-circuit-board layout guidelines is recommended. Bypass capacitors should be used on power supplies. Short trace lengths should be used to avoid excessive loading. Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depending on the system requirements. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 SN74AVC16T245 www.ti.com SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 12.2 Layout Example LEGEND VIA to Power Plane Polygonal Copper Pour VIA to GND Plane (Inner Layer) Keep OE high until VCCA and VCCB are powered up VCCA 1DIR 1OE 48 To System 2 1B1 1A1 47 From Controller To System 3 1B2 1A2 46 From Controller 4 GND GND 45 To System 5 1B3 1A3 44 From Controller To System 6 1B4 1A4 43 From Controller VCCA 42 7 VCCB 8 1B5 1A5 41 From Controller To System 9 1B6 1A6 40 From Controller 10 GND GND 39 11 1B7 1A7 38 From Controller 12 1B8 1A8 37 From Controller To System 13 2B1 2A1 36 From Controller To System 14 2B2 2A2 35 15 GND GND 34 To System 16 2B3 2A3 33 From Controller To System 17 2B4 2A4 32 From Controller 18 VCCB To System SN74AVCH16T245 VCCA VCCA Bypass Capacitor To System To System VCCB VCCA VCCB 1 From Controller VCCA 31 Bypass Capacitor From Controller From Controller 19 2B5 2A5 To System 20 2B6 2A6 29 21 GND GND 28 To System 22 2B7 2A7 27 From Controller To System 23 2B8 2A8 26 From Controller 24 2DIR 2OE 25 VCCA To System VCCA 31 Keep OE high until VCCA and VCCB are powered up Figure 14. Recommended Layout Example Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 19 SN74AVC16T245 SCES551E – FEBRUARY 2004 – REVISED NOVEMBER 2015 www.ti.com 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation For related documentation see the following: • CMOS Power Consumption and Cpd Calculation, SCAA035 • Implications of Slow or Floating CMOS Inputs, SCBA004 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: SN74AVC16T245 PACKAGE OPTION ADDENDUM www.ti.com 2-Jul-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 74AVC16T245DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AVC16T245 74AVC16T245DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AVC16T245 74AVC16T245DGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 WF245 AVC16T245DGGR-D ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AVC16T245 SN74AVC16T245DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AVC16T245 SN74AVC16T245DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 WF245 SN74AVC16T245GQLR OBSOLETE BGA MICROSTAR JUNIOR GQL 56 TBD Call TI Call TI -40 to 85 WF245 SN74AVC16T245ZQLR ACTIVE BGA MICROSTAR JUNIOR ZQL 56 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 WF245 1000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 2-Jul-2015 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74AVC16T245 : • Automotive: SN74AVC16T245-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74AVC16T245DGGR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74AVC16T245DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74AVC16T245ZQLR BGA MI CROSTA R JUNI OR ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AVC16T245DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74AVC16T245DGVR TVSOP DGV 48 2000 367.0 367.0 38.0 SN74AVC16T245ZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 336.6 336.6 28.6 Pack Materials-Page 2 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. 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