AMD BD160GT54DF 16 megabit (1 m x 16-bit/512 k x 32-bit), cmos 2.5 volt-only burst mode, dual boot, simultaneous read/write flash memory Datasheet

Am29BDD160G
Data Sheet
For new designs, S29CD016G supersedes Am29BDD160G and is the factory-recommended migration
path for this device. Please refer to the S29CD016G datasheet for specifications and ordering information.
The following document contains information on Spansion memory products. Although the doc-ument
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when
appro-priate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 24960 Revision D
Amendment 5 Issue Date June 7, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29BDD160G
16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode,
Dual Boot, Simultaneous Read/Write Flash Memory
NOTE: For new designs, S29CD016G supersedes Am29BDD160G and is the factory-recommended migration path for this device. Please refer to the S29CD016G datasheet for specifications and ordering information.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
„ Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank.
(–40°C to 85°C, 56 MHz and below only)
— Zero latency between read and write operations
— Two bank architecture: 75%/25%
„ User-Defined x16 or x32 Data Bus
„ Dual Boot Block
— Top and bottom boot in the same device
„ Flexible sector architecture
— Eight 8 Kbytes, thirty 64 Kbytes, and eight 8 Kbytes
sectors
„ Manufactured on 0.17 µm process technology
„ SecSi (Secured Silicon) Sector (256 Bytes)
— Current version of device has 64 Kbytes; future
versions will have 256 bytes
— Factory locked and identifiable: 16 bytes for secure,
random factory Electronic Serial Number; remainder
may be customer data programmed by AMD
— Customer lockable: Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed
„ Programmable Burst interface
— Interface to any high performance processor
— Modes of Burst Read Operation:
Linear Burst: 4 double words (x32), 8 words (x16)
and double words (x32), and 32 words (x16) with
wrap around
„ Single power supply operation
— Optimized for 2.5 to 2.75 volt read, erase, and
program operations
„ Compatible with JEDEC standards (JC42.4)
— Pinout and software compatible with
single-power-supply flash standard
PERFORMANCE CHARACTERISTICS
„ High performance read access
— Initial/random access time as fast as 54 ns
— Burst access time as fast as 9 ns for ball grid array
package
„ Ultra low power consumption
— Burst Mode Read: 90 mA @ 66 MHz max
— Program/Erase: 50 mA max
— Standby mode: CMOS: 60 µA max
„ Minimum 1 million write cycles guaranteed per
sector
„ 20 year data retention at 125°C
„ VersatileI/OTM control
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the VIO pin
— 1.65 V to 2.75 V compatible I/O signals
SOFTWARE FEATURES
„ Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector (requires only VCC levels)
„ Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-definable 64-bit password
„ Supports Common Flash Interface (CFI)
„ Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
„ Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
HARDWARE FEATURES
„ Program Suspend/Resume & Erase
Suspend/Resume
— Suspends program or erase operations to allow
reading, programming, or erasing in same bank
„ Hardware Reset (RESET#), Ready/Busy# (RY/BY#),
and Write Protect (WP#) inputs
„ ACC input
— Accelerates programming time for higher throughput
during system production
„ Package options
— 80-pin PQFP
— 80-ball Fortified BGA
Publication# 24960 Rev: D Amendment: 5
Issue Date: June 7, 2006
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29BDD160 is a 16 Megabit, 2.5 Volt-only single power supply burst mode flash memory device.
The device can be configured for either 1,048,576
words in 16-bit mode or 524,288 double words in
32-bit mode. The device can also be programmed in
standard EPROM programmers. The device offers a
configurable burst interface to 16/32-bit microprocessors and microcontrollers.
To eliminate bus contention, each device has separate
chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Additional control inputs are required for synchronous burst operations: Load Burst
Address Valid (ADV#), and Clock (CLK).
Each device requires only a single 2.5 or 2.6 Volt
power supply (2.5 V to 2.75 V) for both read and write
functions. A 12.0-volt VPP is not required for program
or erase operations, although an acceleration pin is
available if faster programming performance is required.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
The software command set is compatible with the
command sets of the 5 V Am29F and 3 V Am29LV
Flash families. Commands are written to the command
register using standard microprocessor write timing.
Register contents serve as inputs to an internal
state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and
erase operations. Reading data out of the device is
similar to reading from other Flash or EPROM devices.
The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory space
into two banks. The device can begin programming or
erasing in one bank, and then simultaneously read
from the other bank, with zero latency. This releases
the system from waiting for the completion of program
or erase operations. See Simultaneous Read/Write
Operations Overview and Restrictions on page 13.
The device provides a 256-byte SecSi™ (Secured
Silicon) Sector with an one-time-programmable
(OTP) mechanism.
In addition, the device features several levels of sector
protection, which can disable both the program and
erase operations in certain sectors or sector groups:
Persistent Sector Protection is a command sector
protection method that replaces the old 12 V controlled protection method; Password Sector Protection is a highly sophisticated protection method that
requires a password before changes to certain sectors
2
or sector groups are permitted; WP# Hardware Protection prevents program or erase in the two outermost 8 Kbytes sectors of the larger bank.
The device defaults to the Persistent Sector Protection
mode. The customer must then choose if the Standard
or Password Protection method is most desirable. The
WP# Hardware Protection feature is always available,
independent of the other protection method chosen.
The VersatileI/O™ (VCCQ ) feature allows the output
voltage generated on the device to be determined
based on the VIO level. This feature allows this device
to operate in the 1.8 V I/O environment, driving and receiving signals to and from other 1.8 V devices on the
same bus. In addition, inputs and I/Os that are driven
externally are capable of handling 3.6 V.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V CC detector that automatically inhibits write operations during power transitions. The password and
software sector protection feature disables both
program and erase operations in any combination of
sectors of memory. This can be achieved in-system at
VCC level.
The Program/Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any
sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
Am29BDD160G
June 7, 2006
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram of
Simultaneous Operation Circuit . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
x16 Mode .................................................................................. 9
x32 Mode .................................................................................. 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11
Table 1. Device Bus Operation .......................................................12
VersatileI/O™ (VIO) Control .................................................... 13
Requirements for Reading Array Data ................................... 13
Simultaneous Read/Write
Operations Overview and Restrictions ................................... 13
Overview ............................................................................. 13
Restrictions .......................................................................... 13
Table 2. Bank Assignment for Boot Bank
Sector Devices ................................................................................13
Simultaneous Read/Write Operations With Zero Latency ...... 13
Table 3. Top Boot Bank Select .......................................................14
Table 4. Bottom Boot Bank Select ..................................................14
Writing Commands/Command Sequences ............................ 14
Accelerated Program and Erase Operations ....................... 14
Autoselect Functions ........................................................... 14
Automatic Sleep Mode (ASM) ................................................ 14
RESET#: Hardware Reset Pin ............................................... 15
Output Disable Mode .............................................................. 15
Autoselect Mode ..................................................................... 15
Table 5. Am29BDD160 Autoselect Codes (High Voltage Method) .16
Asynchronous Read Operation (Non-Burst) ........................... 16
Figure 1. Asynchronous Read Operation........................................ 16
Synchronous (Burst) Read Operation .................................... 17
Linear Burst Read Operations ................................................ 17
Table 6. 16-Bit and 32-Bit Linear and Burst Data Order .................17
CE# Control in Linear Mode ................................................ 18
ADV# Control In Linear Mode .............................................. 18
RESET# Control in Linear Mode ......................................... 18
OE# Control in Linear Mode ................................................ 18
IND/WAIT# Operation in Linear Mode ................................. 18
Table 7. Valid Configuration Register Bit Definition for IND/WAIT# 20
Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word
Burst Operation............................................................................... 20
Burst Access Timing Control ............................................... 21
Initial Burst Access Delay Control ....................................... 21
Table 8. Burst Initial Access Delay ..................................................21
Figure 3. Initial Burst Delay Control ................................................ 21
Configuration Register ............................................................ 22
Table 9. Configuration Register Definitions .....................................22
Table 10. Configuration Register After Device Reset .....................24
Initial Access Delay Configuration .......................................... 24
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . 24
Persistent Sector Protection ................................................... 24
Persistent Protection Bit (PPB) ............................................ 25
Persistent Protection Bit Lock (PPB Lock) .......................... 25
June 7, 2006
Dynamic Protection Bit (DYB) ............................................. 25
Table 11. Sector Protection Schemes ............................................ 26
Persistent Sector Protection Mode Locking Bit ....................... 26
Password Protection Mode ..................................................... 26
Password and Password Mode Locking Bit ............................ 26
64-bit Password ................................................................... 27
Write Protect (WP#) ................................................................ 27
SecSi™ (Secured Silicon) Sector Protection .......................... 27
SecSi Sector Protection Bit ..................................................... 28
Persistent Protection Bit Lock ................................................. 28
Hardware Data Protection ...................................................... 28
Low VCC Write Inhibit ........................................................... 28
Write Pulse “Glitch” Protection ............................................ 28
Logical Inhibit ....................................................................... 28
Power-Up Write Inhibit ......................................................... 28
VCC and VIO Power-up And Power-down Sequencing ......... 28
Table 12. Sector Addresses for Top Boot Sector Devices ............. 29
Table 13. Sector Addresses for Bottom Boot Sector Devices ........ 30
Table 14. CFI Query Identification String ....................................... 31
Table 15. CFI System Interface String ........................................... 31
Table 16. CFI Device Geometry Definition ..................................... 32
Table 17. CFI Primary Vendor-Specific Extended Query ............... 32
Command Definitions . . . . . . . . . . . . . . . . . . . . . 34
Reading Array Data in Non-burst Mode .................................. 34
Reading Array Data in Burst Mode ......................................... 34
Read/Reset Command ........................................................... 34
Autoselect Command ............................................................. 35
Program Command Sequence ............................................... 35
Accelerated Program Command ............................................ 35
Unlock Bypass Command Sequence ..................................... 35
Figure 4. Program Operation ......................................................... 36
Unlock Bypass Entry Command .......................................... 36
Unlock Bypass Program Command .................................... 36
Unlock Bypass Chip Erase Command ................................ 36
Unlock Bypass CFI Command ............................................ 36
Unlock Bypass Reset Command ......................................... 37
Chip Erase Command ............................................................ 37
Sector Erase Command ......................................................... 37
Figure 5. Erase Operation.............................................................. 38
Sector Erase and Program Suspend Command .................... 38
Sector Erase and Program Suspend Operation Mechanics ... 38
Table 18. Allowed Operations During Erase/Program Suspend ... 38
Sector Erase and Program Resume Command ..................... 39
Configuration Register Read Command ................................. 39
Configuration Register Write Command ................................. 39
Common Flash Interface (CFI) Command .............................. 39
SecSi Sector Entry Command ................................................ 41
Password Program Command ................................................ 41
Password Verify Command .................................................... 41
Password Protection Mode Locking Bit Program Command .. 42
Persistent Sector Protection Mode Locking Bit Program Command ....................................................................................... 42
SecSi Sector Protection Bit Program Command .................... 42
PPB Lock Bit Set Command ................................................... 42
DYB Write Command ............................................................. 42
Password Unlock Command .................................................. 42
PPB Program Command ........................................................ 43
Am29BDD160G
3
All PPB Erase Command ....................................................... 43
DYB Write ............................................................................... 43
PPB Lock Bit Set .................................................................... 43
DYB Status ............................................................................. 43
PPB Status ............................................................................. 44
PPB Lock Bit Status ............................................................... 44
Non-volatile Protection Bit Program And Erase Flow ............. 44
Table 19. Memory Array Command Definitions (x32 Mode) ...........45
Table 20. Sector Protection Command Definitions (x32 Mode) ......46
Table 21. Memory Array Command Definitions (x16 Mode) ...........47
Table 22. Sector Protection Command Definitions (x16 Mode) ......48
DQ7: Data# Polling ................................................................. 49
RY/BY#: Ready/Busy# ........................................................... 49
Figure 6. Data# Polling Algorithm ................................................... 50
DQ6: Toggle Bit I .................................................................... 50
DQ2: Toggle Bit II ................................................................... 50
Reading Toggle Bits DQ6/DQ2 .............................................. 51
DQ5: Exceeded Timing Limits ................................................ 51
Figure 7. Toggle Bit Algorithm......................................................... 51
DQ3: Sector Erase Timer ....................................................... 52
Table 23. Write Operation Status ....................................................52
Figure 8. Maximum Negative Overshoot Waveform ....................... 53
Figure 9. Maximum Positive Overshoot Waveform......................... 53
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep
Currents) ......................................................................................... 55
Figure 11. Typical ICC1 vs. Frequency............................................. 55
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 12. Test Setup...................................................................... 56
Table 24. Test Specifications ..........................................................56
4
Key to Switching Waveforms . . . . . . . . . . . . . . . 56
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 56
Figure 13. Input Waveforms and Measurement Levels ................. 56
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 14. VCC and VIO Power-up Diagram ................................. 57
Figure 15. Conventional Read Operations Timings ....................... 60
Figure 16. Burst Mode Read (x32 Mode)....................................... 60
Figure 17. Asynchronous Command Write Timing ........................ 61
Figure 18. Synchronous Command Write/Read Timing................. 61
Figure 19. RESET# Timings .......................................................... 63
Figure 20. WP# Timing .................................................................. 63
Figure 21. Program Operation Timings.......................................... 65
Figure 22. Chip/Sector Erase Operation Timings .......................... 66
Figure 23. Back-to-back Cycle Timings ......................................... 66
Figure 24. Data# Polling Timings (During Embedded Algorithms). 67
Figure 25. Toggle Bit Timings (During Embedded Algorithms)...... 67
Figure 26. DQ2 vs. DQ6 for Erase and Erase Suspend Operations...
68
Figure 27. Synchronous Data Polling Timing/Toggle Bit Timings .. 68
Figure 28. Sector Protect/Unprotect Timing Diagram .................... 69
Figure 29. Alternate CE# Controlled Write Operation Timings ...... 71
Erase and Programming Performance . . . . . . . 72
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 72
PQFP and Fortified BGA Pin Capacitance . . . . . 72
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 73
PQR080–80-Lead Plastic Quad Flat Package ....................... 73
LAA 080–80-ball Fortified Ball Grid Array (13 x 11 mm) ......... 74
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 75
Am29BDD160G
June 7, 2006
PRODUCT SELECTOR GUIDE
Part Number
Am29BDD160G
Standard Voltage Range: VCC = 2.5 – 2.75 V
Synchronous/Burst or Asynchronous
Speed Option (Clock Rate)
54D (66 MHz)
64C (56 MHz)
65A (40 MHz)
54
64
67
9 FBGA/9.5 PQFP
10 FBGA/10 PQFP
17
Max Clock Rate (MHz)
66
56
40
Min Initial Clock Delay (clock cycles)
3
3
2
Max CE# Access, ns (tCE)
58
69
71
Max Initial/Asynchronous Access Time, ns (tACC)
Max Burst Access Delay (ns)
Max OE# Access, ns (tOE)
20
28
Note: The 54D, 64C, and 65A speed options are tested and guaranteed to operate only at the 66 MHz, 56MHz, and 40MHz
frequencies respectively. Operation and other frequencies is not warranted.
BLOCK DIAGRAM
VCC
DQ0–DQ15
A0–A18
VSS
RDY
Buffer
RDY
Erase Voltage
Generator
VIO
Input/Output
Buffers
WE#
ACC
WP#
WORD#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC
Detector
ADV#
CLK
Burst
State
Control
IND/
WAIT#
Timer
Burst
Address
Counter
Address Latch
RESET#
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A20
DQ0–DQ31
A0–A18
June 7, 2006
Am29BDD160G
5
BLOCK DIAGRAM OF
SIMULTANEOUS OPERATION CIRCUIT
16/32#
X-Decoder
A0–A18
RESET#
WE#
CE#
ADV#
Upper Bank
DQ0–DQ31
A0–A18
Y-Decoder
Upper Bank Address
A0–A18
Latches and Control Logic
OE#
VCC
VSS
STATE
CONTROL
&
COMMAND
REGISTER
Status
DQ0–DQ31
Control
6
Lower Bank Address
Lower Bank
Am29BDD160G
Latches and
Control Logic
A0–A18
Y-Decoder
A0–A18
X-Decoder
DQ0–DQ31
DQ0–DQ31
June 7, 2006
June 7, 2006
VCCQ
RESET#
CLK
NC
RY/BY#
VSS
ADV#
VCC
CE#
OE#
WE#
WP#
NC
NC
Am29BDD160G
DQ15
DQ14
DQ13
DQ12
VSS
VCCQ
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
VSS
VCCQ
DQ3
DQ2
DQ1
DQ0
NC
A18
A17
A16
A15
A14
A13
A12
A11
A9
A10
VCC
ACC
VSS
A8
A7
A6
A5
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
63
62
61
60
59
58
57
56
55
54
80-pin PQFP
53
52
51
50
49
48
47
46
45
44
43
42
41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A3
DQ16
DQ17
DQ18
DQ19
VCCQ
VSS
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
VCCQ
VSS
DQ28
DQ29
DQ30
DQ31
A-1
A0
A1
A2
IND/WAIT#
WORD#
CONNECTION DIAGRAM
7
CONNECTION DIAGRAMS
80-Ball Fortified BGA
A8
B8
C8
D8
E8
F8
G8
H8
J8
K8
A2
A1
A0
DQ29
VCCQ
VSS
VCCQ
DQ20
DQ16
WORD#
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
A3
A4
A-1
DQ30
DQ26
DQ24
DQ23
A6
B6
C6
D6
E6
F6
G6
H6
J6
K6
DQ21
DQ19
OE#
WE#
A6
A5
A7
DQ31
DQ28
DQ25
DQ18 IND/WAIT#
NC
A5
B5
C5
D5
E5
F5
G5
H5
J5
K5
VSS
A8
NC
NC
DQ27
RY/BY#
DQ22
DQ17
CE#
VCC
A4
B4
C4
D4
E4
F4
G4
H4
J4
K4
ACC
A9
A10
NC
DQ1
DQ5
DQ9
WP#
NC
VSS
A3
B3
C3
D3
E3
F3
G3
H3
J3
K3
VCC
A12
A11
NC
DQ2
DQ6
DQ10
DQ11
ADV#
CLK
A2
B2
C2
D2
E2
F2
G2
H2
J2
K2
A14
A13
A18
DQ0
DQ4
DQ7
DQ8
DQ12
DQ14
RESET#
A1
B1
C1
D1
E1
F1
G1
H1
J1
K1
A15
A16
A17
DQ3
VCCQ
VSS
VCCQ
DQ13
DQ15
VCCQ
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (BGA). The package and/or
data integrity may be compromised if the package
8
body is exposed to temperatures above 150°C for prolonged periods of time.
Am29BDD160G
June 7, 2006
PIN CONFIGURATION
A–1
= Least significant address bit for the 16-bit
data bus, and selects between the high
and low word. A –1 is not used for the
32-bit mode (WORD# = VIH).
A0–A18
= 19-bit address bus for 16 Mb device. A9
supports 12 V autoselect inputs.
DQ0–DQ31
= 32-bit data inputs/outputs/float
WORD#
= Selects 16-bit or 32-bit mode. When
WORD# = VIH, data is output on
DQ31–DQ0. When WORD# = VIL, data is
output on DQ15–DQ0.
CE#
= Chip Enable Input. This signal is asynchronous relative to CLK for the burst mode.
OE#
= Output Enable Input. This signal is asynchronous relative to CLK for the burst
mode.
WE#
= Write enable. This signal is asynchronous
relative to CLK for the burst mode.
VSS
= Device ground
NC
= Pin not connected internally
RY/BY#
= Ready/Busy output and open drain. When
RY/BY# = VIH, the device is ready to accept read operations and commands.
When RY/BY# = VOL, the device is either
executing an embedded algorithm or the
device is executing a hardware reset operation.
CLK
= Clock Input that can be tied to the system
or microprocessor clock and provides the
fundamental timing and internal operating
frequency.
ADV#
= Load Burst Address input. Indicates that
the valid address is present on the address
inputs.
IND#
= End of burst indicator for finite bursts only.
IND is low when the last word in the burst
sequence is at the data outputs.
WAIT#
= Provides data valid feedback only when
the burst length is set to continuous.
WP#
= Write Protect input. When WP# = VOL, the
two outermost bootblock sector in the 75%
bank are write protected regardless of
other sector protection configurations.
ACC
= Acceleration input. When taken to 12 V,
program and erase operations are accelerated. When not used for acceleration, ACC
= VSS to VCC.
VIO (VCCQ)
= Output Buffer Power Supply (1.65 V to
2.75 V)
VCC
= Chip Power Supply (2.5 V to 2.75 V)
RESET#
= Hardware reset input
LOGIC SYMBOLS
x16 Mode
x32 Mode
20
19
A-1 to A18
CLK
16
A0–A18
DQ0–DQ15
CLK
CE#
CE#
OE#
OE#
WE#
RESET#
RESET#
IND/WAIT#
ADV#
ACC
RY/BY#
WP#
WP#
VIO (VCCQ)
VIO (VCCQ)
WORD#
WORD#
June 7, 2006
DQ0–DQ31
WE#
IND/WAIT#
ADV#
ACC
32
Am29BDD160G
RY/BY#
9
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29BDD160
G
T
54
D
PB
E
TEMPERATURE RANGE
I
= Industrial (–40°C to +85°C)
F
= Industrial (–40°C to +85°C) with Pb-Free Package
E
= Extended (–40°C to +125°C)
K
= Extended (–40°C to +125°C) with Pb-Free Package
PACKAGE TYPE
K
= 80-Pin Plastic Quad Flat Package (PQFP) PQR080
PB
= 80-Ball Fortified Ball Grid Array (Fortified BGA)
1.0 mm pitch, 13 x 11 mm package (LAA080)
CLOCK RATE
A
= 40 MHz
C
= 56 MhZ
D
= 66 MHz
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE
T
= Top sector
B
= Bottom sector
PROCESS TECHNOLOGY
G
= 0.17 µm
DEVICE NUMBER/DESCRIPTION
Am29BDD160G
16 Megabit (1 M x 16-Bit/512 K x 32-Bit)
CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
Valid Combinations for
PFQP Packages
AM29BDD160GT54D,
AM29BDD160GB54D
AM29BDD160GT64C,
AM29BDD160GB64C
AM29BDD160GT65A,
AM29BDD160GB65A
KI, KE,
KF, KK
Valid Combinations for Fortified BGA Packages
Order Number
Package Marking
BD160GT54D,
AM29BDD160GT54D,
BD160GB54D
AM29BDD160GB54D
AM29BDD160GT64C,
I, E,
PBI, BD160GT64C,
AM29BDD160GB64C
F, K
PBE BD160GB64C
AM29BDD160GT65A,
BD160GT65A,
AM29BDD160GB65A
BD160GB65A
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
10
Am29BDD160G
June 7, 2006
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the
June 7, 2006
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Am29BDD160G
11
Table 1.
Operation
Addresses
(Note 1)
Data
(DQ0–DQ31)
X
A9 = VID, A6 = L,
A1 = L, A0 = L
0000001h
X
X
A9 = VID, A6 = L,
A1 = L, A0 = H
000007Eh
(Note 2)
X
X
A9 = VID,
A7–A0 = 0Eh
0000008h
CE#
OE#
WE#
RESET#
CLK
ADV#
L
L
H
H
X
Read Cycle 1
L
L
H
H
Read Cycle 2
L
L
H
H
Autoselect Manufacturer Code
Autoselect Device Code
Device Bus Operation
(Note 2)
Top Boot Block
0000000h
L
L
H
H
X
X
A9 = VID,
A7–A0 = 0Fh
Read
L
L
H
H
X
X
AIN
DOUT
Write
L
H
L
H
X
X
AIN
DIN
Standby (CE#)
H
X
X
H
X
X
X
HIGH Z
Output Disable
L
H
H
H
X
X
HIGH Z
HIGH Z
Reset
X
X
X
L
X
X
X
HIGH Z
Read Cycle 3
PPB Protection Status (Note 4)
L
L
H
H
X
X
Sector Address,
A9 = VID,
A7 – A0 = 02h
Bottom Boot
Block
0000001h
00000001h,
(protected)
A6 = H
00000000h
(unprotect)
A6 = L
Burst Read Operations
Load Starting Burst Address
L
X
H
H
Advance Burst to next address
with appropriate Data presented
on the Data bus
L
L
H
H
Terminate Current Burst Read
Cycle
H
X
H
H
Terminate Current Burst Read
Cycle with RESET#
X
X
H
L
Terminate Current Burst Read
Cycle; Start New Burst Read
Cycle
L
H
H
H
X
AIN
X
H
X
Burst Data Out
X
X
HIGH Z
X
X
HIGH Z
AIN
X
Legend:
L = Logic Low = VIL, H = Logic High = VIH, X = Don’t care.
Notes:
1. DQ31–DQ16 are HIGH Z when WORD# = VIL
2.
3.
4.
5.
12
When WORD# = VIL, DQ31-DQ16 are floating
WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block.
DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB
Addresses are A0:A18 for the x32 mode and A–1:A18 for x16 mode.
Am29BDD160G
June 7, 2006
VersatileI/O™ (VIO) Control
The VersatileI/O (VIO) control allows the host system
to set the voltage levels that the device generates at
its data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on the
VIO pin.
The output voltage generated on the device is determined based on the VIO (VCCQ) level.
A VIO of 1.65–1.95 volts is targeted to provide for I/O
tolerance at the 1.8 volt level.
A VCC and VIO of 2.5–2.75 volts makes the device appear as 2.5 volt-only.
Address/Control signals are 3.6 V tolerant with the exception of CLK.
Word/Double Word Configuration
The WORD# pin controls whether the device data I/O
pins operate in the word or double word configuration.
If the WORD# pin is set at VIH, the device is in double
word configuration, DQ31–DQ0 are active and controlled by CE# and OE#.
If the WORD# pin is set at VIL, the device is in word
configuration, and only data I/O pins DQ15–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ31–DQ16 are tri-stated.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
Address access time (tACC) is the delay from stable addresses to valid output data. The chip enable access
time (tCE) is the delay from stable addresses and stable CE# to valid data at the output pins. The output enable access time (t OE ) is the delay from the falling
edge of OE# to valid data at the output pins (assuming
the addresses have been stable for at least t ACC–tOE
time and CE# has been asserted for at least tCE–tOE
time).
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
June 7, 2006
tions and to Figure 15 for the timing diagram. ICC1 in
the DC Characteristics table represents the active current specification for reading array data.
Simultaneous Read/Write
Operations Overview and Restrictions
Overview
Simultaneous Operation is an advances functionality
providing enhanced speed and flexibility with minimum
overhead. Simultaneous Operation does this by allowing an operation to be executed (embedded operation)
in a bank (busy bank), then going to the other bank
(non-busy bank) and performing desired operations.
The BDD160’s Simultaneous Operation has been optimized for applications that could most benefit from this
capability. These applications store code in the big
bank, while storing data in the small bank. The best
example of this is when a Sector Erase Operation (as
an embedded operation) in the small (busy) bank,
while performing a Burst/synchronous Read Operation
in the big (non-busy) bank.
Restrictions
The BDD160’s Simultaneous Operation is tested by
executing an embedded operation in the small (busy)
bank while performing other operations in the big
(non-busy) bank. However, the opposite case is neither tested nor valid. That is, it is not tested by executing an embedded operation in the big (busy) bank
while performing other operations in the small
(non-busy) bank. See Table 2 Bank assignment for
Boot Bank Sector Devices.
Table 2.
Bank
1
Bank
2
Bank Assignment for Boot Bank
Sector Devices
Top Boot Sector Devices
Bottom Boot Sector
Devices
Small Bank
Big Bank
Big Bank
Small Bank
Also see Table 18, “Allowed Operations During
Erase/Program Suspend,” on page 38. Also see
Table 12, “Sector Addresses for Top Boot Sector Devices,” on page 29 and see Table 13, “Sector Addresses for Bottom Boot Sector Devices,” on page 30.
Simultaneous Read/Write Operations With
Zero Latency
The device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be suspended to read from or program to another location
within the same bank (except the sector being
erased). Refer to the DC Characteristics table for
Am29BDD160G
13
read-while-program and read-while-erase current
specifications.
Simultaneous read/write operations are valid for both
the main Flash memory array and the SecSi OTP sector. Simultaneous operation is disabled during the CFI
and Password Program/Verify operations. PPB Program/Erase operations and the Password Unlock operation permit reading data from the large (75%) bank
while reading the operation status of these commands
from the small (25%) bank.
Table 3. Top Boot Bank Select
Bank
Bank 1
Bank 2
Table 4.
Bank
Bank 1
Bank 2
A18:A17
00
01, 1X
Bottom Boot Bank Select
A18
0X, 10
11
Accelerated Program and Erase Operations
The device offers accelerated program/erase operations through the ACC pin. When the system asserts
VHH (12V) on the ACC pin, the device automatically
enters the Unlock Bypass mode. The system may
then write the two-cycle Unlock Bypass program command sequence to do accelerated programming. The
device uses the higher voltage on the ACC pin to accelerate the operation. A sector that is being protected
with the WP# pin will still be protect during accelerated
program or Erase. Note that the ACC pin must not be
at V HH during any operation other than accelerated
programming, or device damage may result.
Autoselect Functions
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, in the x32-mode the device
accepts program data in 32-bit words and in the x16
mode the device accepts program data in 16-bit
words.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The
Sector Erase and Program Suspend Command section has details on programming data to the device
using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Tables 12 and 13 indicate
the address space that each sector occupies. A “sector address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timing applies in
this mode. Refer to the “Autoselect Mode” section for
more information.
ICC2 in the DC Characteristics table represents the active current specification for erase or program modes.
14
The AC Characteristics section contains timing specification tables and timing diagrams for erase or program operations.
If the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.
Automatic Sleep Mode (ASM)
The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the
device automatically enables this mode when addresses remain stable for tACC + 60 ns. The automatic
sleep mode is independent of the CE#, WE# and OE#
control signals. Standard address access timings provide new data when addresses are changed. While in
sleep mode, output data is latched and always available to the system. While in synchronous mode, the
device automatically enables this mode when either
the first active CLK level is greater than tACC or the
CLK runs slower than 5 MHz. Note that a new burst
operation is required to provide new data.
ICC8 in the “DC Characteristics” section of page 53 represents the automatic sleep mode current specification.
Standby Mode
When the system is not responding or writing to the
device, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# inputs are both held at Vcc ± 0.2 V.
The device requires standard access time (t CE) for
read access, before it is ready to read data.
Am29BDD160G
June 7, 2006
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
ICC5 in the “DC Characteristics” section on page 53
represents the standby current specification.
Caution: entering the standby mode via the RESET#
pin also resets the device to the read mode and floats
the data I/O pins. Furthermore, entering ICC7 during a
program or erase operation will leave erroneous data
in the address locations being operated on at the time
of the RESET# pulse. These locations require updating after the device resumes standard operations.
Refer to the “RESET#: Hardware Reset Pin” section
for further discussion of the RESET# pin and its functions.
RESET#: Hardware Reset Pin
The RESET# pin is an active low signal that is used to
reset the device under any circumstances. A logic “0”
on this pin forces the device out of any mode that is
currently executing back to the reset state. The RESET# pin may be tied to the system reset circuitry. A
system reset would thus also reset the device. To
avoid a potential bus contention during a system reset,
the device is isolated from the DQ data bus by tristating the data output pins for the duration of the RESET
pulse. All pins are “don’t care” during the reset operation.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains low until the reset operation is internally complete. This action requires
between 1 µs and 7µs for either Chip Erase or Sector
Erase. The RY/BY# pin can be used to determine
when the reset operation is complete. Otherwise,
allow for the maximum reset time of 11 µs. If RESET#
is asserted when a program or erase operation is not
executing (RY/BY# = “1”), the reset operation will complete within 500 ns. Since the Am29BDD160 is a Simultaneous Operation device the user may read a
bank after 500 ns if the bank was in the read/reset
mode at the time RESET# was asserted. If one of the
banks was in the middle of either a program or erase
June 7, 2006
operation when RESET# was asserted, the user must
wait 11 µs before accessing that bank.
Asserting RESET# during a program or erase operation leaves erroneous data stored in the address locations being operated on at the time of device reset.
These locations need updating after the reset operation is complete. See Figure 19 for timing specifications.
As s er ti ng RE SE T # ac tiv e du ri ng V C C a nd V I O
power-up is required to guarantee proper device initialization until VCC and VIO have reached their steady
state voltages.
Output Disable Mode
See Table 1 Device Bus Operation for OE# Operation
in Output Disable Mode.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A1, and A0 must be as shown in Table 12 (top
boot devices) or Table 13 (bottom boot devices). In addition, when verifying sector protection, the sector address must appear on the appropriate highest order
address bits (see Tables 11 and 12). See Table 5
shows the remaining address bits that are don’t care.
When all necessary bits have been set as required,
the programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command. This method does not require V ID . See
“Command Definitions” for details on using the autoselect mode.
Am29BDD160G
15
Table 5.
Description
Autoselect Device Code
Manufacturer ID:
AMD
Am29BDD160 Autoselect Codes (High Voltage Method)
A18
to
CE# OE# WE# A11 A10
A9
A8
A7
A6
A5
to
A4
A3
A2
A1
A0
DQ7
to
DQ0
L
L
H
X
X
VID
X
X
L
X
X
X
L
L
0001h
Read Cycle 1
L
L
H
X
X
VID
X
L
L
X
L
L
L
H
007Eh
Read Cycle 2
L
L
H
X
X
VID
X
L
L
L
H
H
H
L
0008h
0000h (top boot
block)
Read Cycle 3
PPB Protection
Status
L
L
H
X
X
VID
X
VID
X
L
L
L
H
H
H
H
0001h (bottom boot
block)
0000h (unprotected)
L
L
H
SA X
L
L
L
L
L
H
L
0001h (protected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Tables 18 and 20.
Asynchronous Read Operation
(Non-Burst)
The device has two control functions which must be
satisfied in order to obtain data at the outputs. CE# is
the power control and should be used for device selection. OE# is the output control and should be used to
gate data to the output pins if the device is selected.
The device is power-up in an asynchronous read
mode. In the asynchronous mode the device has two
control functions which must be satisfied in order to
obtain data at the outputs. CE# is the power control
and should be used for device selection. OE# is the
output control and should be used to gate data to the
output pins if the device is selected.
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t CE ) is the delay from the stable addresses and stable CE# to valid data at the output
pins. The output enable access time is the delay from
the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least
tACC–tOE time).
CE#
CLK
ADV#
A0-A18
Address 0
DQ0-DQ31
Address 1
Address 2
D0
D1
Address 3
D2
D3
D3
OE#
WE#
IND/WAIT#
VIH
Float
Float
VOH
Note: Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
Figure 1.
16
Asynchronous Read Operation
Am29BDD160G
June 7, 2006
Synchronous (Burst) Read Operation
The Am29BDD160 is capable of performing burst read
operations to improve total system data throughput.
The device is available in three burst modes of operation: linear and burst mode. 2, 4 and 8 double word
(x32) and 4 and 8 word (x16) accesses are configurable as either sequential burst accesses. 16 and 32
word (x16) accesses are only configurable as linear
burst accesses. Additional options for all burst modes
include initial access delay configurations (2–16
CLKs) Device configuration for burst mode operation
is accomplished by writing the Configuration Register
with the desired burst configuration information. Once
the Configuration Register is written to enable burst
mode operation, all subsequent reads from the array
are returned using the burst mode protocols. Like the
main memory access, the SecSi Sector memory is accessed with the same burst or asynchronous timing as
defined in the Configuration Register. However, the
user must recognize that continuous burst operations
past the 256 byte SecSi boundary returns invalid data.
Burst read operations occur only to the main flash
memory arrays. The Configuration Register and protection bits are treated as single cycle reads, even
when burst mode is enabled. Read operations to
Table 6.
Data Transfer Sequence
(Independent of the WORD#
pin)
these locations results in the data remaining valid
while OE# is at VIL, regardless of the number of CLK
cycles applied to the device.
Linear Burst Read Operations
Linear burst read mode reads either 4, 8, 16, or 32
words (1 word = 16 bits), depending upon the Configuration Register option. If the device is configured with
a 32 bit interface (WORD# = VIH), the burst access is
comprised of 4 clocked reads for 8 words and 16
clocked reads for 32 words (See Table 6 for all valid
burst output sequences). The number of clocked
reads is doubled when the device is configured in the
16-bit data bus mode (WORD# = VIL). The IND/WAIT#
pin transitions active (VIL ) during the last transfer of
data during a linear burst read before a wrap around,
indicating that the system should initiate another
ADV# to start the next burst access. If the system continues to clock the device, the next access wraps
around to the starting address of the previous burst
access. The IND/WAIT# signal remains inactive (floating) when not active. See Table 6 for a complete 32
and 16 bit data bus interface order. 16 and 32 word
options are restricted to sequential burst accesses,
only.
16-Bit and 32-Bit Linear and Burst Data Order
Output Data Sequence (Initial Access Address)
(x16)
0-1 (A0 = 0)
Two Linear Data Transfers,
(x32 only)
1-0 (A0 = 1)
0-1-2-3 (A0:A-1/A1-A0 = 00)
Four Linear Data Transfers
1-2-3-0 (A0:A-1/A1-A0 = 01)
2-3-0-1 (A:A-1/A1-A0 = 10)
3-0-1-2 (A0:A-1/A1-A0 = 11)
0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000)
1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001)
2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010)
Eight Linear Data Transfers
3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011)
4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100)
5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101)
6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110)
7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111)
June 7, 2006
Am29BDD160G
17
Table 6.
16-Bit and 32-Bit Linear and Burst Data Order (Continued)
Data Transfer Sequence
(Independent of the WORD#
pin)
Output Data Sequence (Initial Access Address)
(x16)
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F (A2:A-1/ A3-A0 = 0000)
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 (A2:A-1/ A3-A0 = 0001)
2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 (A2:A-1/ A3-A0 = 0010)
3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 (A2:A-1/ A3-A0 = 0011)
4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 (A:A-1/ A3-A0 = 0100)
5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 (A2:A-1/ A3-A0 = 0101)
6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 (A2:A-1/ A3-A0 = 0110)
Sixteen Linear Data Transfers
(X16 Only)
7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 (A2:A-1/ A3-A0 = 0111)
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 (A2:A-1/ A3-A0 = 1000)
9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 (A2:A-1/ A3-A0 = 1001)
A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 (A2:A-1/ A3-A0 = 1010)
B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A (A2:A-1/ A3-A0 = 1011)
C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B (A2:A-1/ A3-A0 = 1100)
D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C (A2:A-1/ A3-A0 = 1101)
E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D (A2:A-1/ A3-A0 = 1110)
F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E (A2:A-1/ A3-A0 = 1111)
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V (A3:A-1 = 00000)
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-0 (A3:A-1 = 00001)
Thirty-Two Linear Data Transfers
:
U-V-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T (A3:A-1 = 11110)
V-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U (A3:A-1 = 11111)
CE# Control in Linear Mode
RESET# Control in Linear Mode
The CE# (Chip Enable) pin enables the Am29BDD160
during read mode operations. CE# must meet the required burst read setup times for burst cycle initiation.
If CE# is taken to VIH at any time during the burst linear or burst cycle, the device immediately exits the
burst sequence and floats the DQ bus and IND/WAIT#
signal. Restarting a burst cycle is accomplished by
taking CE# and ADV# to VIL.
The RESET# pin immediately halts the linear burst access when taken to V I L . The DQ data bus and
IND/WAIT# signal float. Additionally, the Configuration
Register contents are reset back to the default condition where the device is placed in asynchronous access mode.
ADV# Control In Linear Mode
The ADV# (Address Valid) pin is used to initiate a linear burst cycle at the clock edge when CE# and ADV#
are at VIL and the device is configured for either linear
burst mode operation. A burst access is initiated and
the address is latched on the first rising CLK edge
when ADV# is active or upon a rising ADV# edge,
whichever occurs first. If the ADV# signal is taken to
VIL prior to the end of a linear burst sequence, the previous address is discarded and subsequent burst
transfers are invalid until ADV# transitions to VIH before a clock edge, which initiates a new burst sequence.
18
OE# Control in Linear Mode
The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus and the IND/WAIT#
pin. De-asserting the OE# pin to VIH during a burst operation floats the data bus and the IND/WAIT# pin.
However, the device will continue to operate internally
as if the burst sequence continues until the linear burst
is complete. The OE# pin does not halt the burst sequence, this is accomplished by either taking CE# to
VIH or re-issuing a new ADV# pulse. The DQ bus and
IND/WAIT# signal remain in the float state until OE# is
taken to VIL.
IND/WAIT# Operation in Linear Mode
The IND/WAIT#, or End of Burst Indicator signal
(when in linear modes), informs the system that the
last address of a burst sequence is on the DQ data
bus. For example, if a 4-word linear burst access is
Am29BDD160G
June 7, 2006
enabled using a 16-bit DQ bus (WORD# = V IL ), the
IND/WAIT# signal transitions active on the fourth access. If the same scenario is used, but instead the
32-bit DQ bus is enabled, the IND/WAIT# signal transitions active on the second access. The IND/WAIT#
signal has the same delay and setup timing as the DQ
pins. Also, the IND/WAIT# signal is controlled by the
OE# signal. If OE# is at V IH, the IND/WAIT# signal
June 7, 2006
floats and is not driven. If OE# is at VIL, the IND/WAIT#
signal is driven at VIH until it transitions to VIL indicating
the end of burst sequence. The IND/WAIT# signal timing and duration is (See “Configuration Register” for
more information). The following table lists the valid
combinations of the Configuration Register bits that
impact the IND/WAIT# timing.
Am29BDD160G
19
Table 7.
Valid Configuration Register Bit Definition for IND/WAIT#
DOC
WC
CC
Definition
0
0
1
IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge
0
1
1
IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge
CE#
CLK
3 Clock Delay
ADV#
A0-A18
Address 1 Latched
Address 1
Address 2
Invalid
D1
D2
D3
D0
OE#
IND/WAIT#
Note: Operation is shown for the 32-bit data bus. For a 16-bit data bus, A-1 is required. Figure shown with 3-CLK initial access
delay configuration, linear address, 4-doubleword burst, output on rising CLK edge, data hold for 1-CLK, IND/WAIT# asserted
on the last transfer before wrap-around.
Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation
20
Am29BDD160G
June 7, 2006
Burst Access Timing Control
In addition to the IND/WAIT# signal control, burst controls exist in the Control Register for initial access delay, delivery of data on the CLK edge, and the length
of time data is held.
with the exception that data is valid after the falling
edge.
Table 8. Burst Initial Access Delay
Initial Burst Access
(CLK cycles)
Initial Burst Access Delay Control
The Am29BDD160 contains options for initial access
delay of a burst access. The initial access delay has
no effect on asynchronous read operations.
Burst Initial Access Delay is defined as the number of
clock cycles that must elapse from the first valid clock
edge after ADV# assertion (or the rising edge of
ADV#) until the first valid CLK edge when the data is
valid.
The burst access is initiated and the address is
latched on the first rising CLK edge when ADV# is active or upon a rising ADV# edge, whichever comes
first. (See Table 8 describes the initial access delay
configurations.) If the Clock Configuration bit in the
Control Register is set to falling edge (CR6 = 0), the
definition remains the same for the initial delay setting
1st CLK
2nd CLK
3rd CLK
CR13
CR12
CR11
CR10
54D,
64C, 65A
0
0
0
0
2
0
0
0
1
3
0
0
1
0
4
0
0
1
1
5
0
1
0
0
6
0
1
0
1
7
0
1
1
0
8
0
1
1
1
9
4th CLK
5th CLK
CLK
ADV#
A18-A0
DQ31-DQ03
DQ31-DQ04
DQ31-DQ05
Address 1 Latched
Valid Address
Three CLK Delay
D0
D1
D2
D3
D4
D0
D1
D2
D3
D0
D1
D2
Four CLK Delay
Five CLK Delay
Figure 3.
Initial Burst Delay Control
Notes:
1. Burst access starts with a rising CLK edge and when ADV# is active.
2.
3.
4.
5.
Configurations register 6 is set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
CR [13-10] = 1 or three clock cycles
CR [13-10] = 2 or four clock cycles
CR [13-10] = 3 or Five clock cycles
June 7, 2006
Am29BDD160G
21
Burst CLK Edge Data Delivery
The Am29BDD160 is capable of delivering data on either the rising or falling edge of CLK. To deliver data
on the rising edge of CLK, bit 6 in the Control Register
(CR6) is set to 1. To deliver data on the falling edge of
CLK, bit 6 in the Control Register is cleared to 0. The
default configuration is set to the rising edge.
Burst Data Hold Control
The device is capable of holding data for one CLKs.
The default configuration is to hold data for one CLK
and is the only valid state.
Asserting RESET# During A Burst Access
If RESET# is asserted low during a burst access, the
burst access is immediately terminated and the device
defaults back to asynchronous read mode. Refer to
RESET#: Hardware Reset Pin for more information on
the RESET# function.
Configuration Register
The Am29BDD160 contains a Configuration Register
for configuring read accesses. The Configuration Register is accessed by the Configuration Register Read
and the Configuration Register Write commands. The
Table 9.
Configuration Register does not occupy any addressable memory location, but rather, is accessed by the
Configuration Register commands. The Configuration
Register is readable any time, however, writing the
Configuration Register is restricted to times when the
Embedded Algorithm™ is not active. If the user attempts to write the Configuration Register while the
Embedded Algorithm™ is active, the write operation is
ignored and the contents of the Configuration Register
remain unchanged.
The Configuration Register is a 16 bit data field which
is accessed by DQ15–DQ0. Data on DQ31–DQ16 is
ignored during a write operation when WORD# = VIL.
During a read operation, DQ31–DQ16 returns all zeroes. Table 9 shows the Configuration Register. Also,
Configuration Register reads operate the same as Autoselect command reads. When the command is issued, the bank address is latched along with the
command. Reads operations to the bank that was
specified during the Configuration Register read command return Configuration Register contents. Read
operations to the other bank return flash memory data.
Either bank address is permitted when writing the
Configuration Register read command.
Configuration Register Definitions
CR15
CR14
CR13
CR12
CR11
CR10
CR9
CR8
RM
Reserved
IAD3
IAD2
IAD1
IAD0
DOC
WC
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
BS
CC
Reserved
Reserved
Reserved
BL2
BL1
BL0
Configuration Register
CR15 = Read Mode (RM)
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
CR14 = Reserved for Future Enhancements
These bits are reserved for future use. Set these bits to “0”.
22
Am29BDD160G
June 7, 2006
Table 9.
Configuration Register Definitions (Continued)
CR13–CR10 = Initial Burst Access Delay Configuration (IAD3-IAD0)
Speed Options 54D, 64C, 65A:
0000 = 2 CLK cycle initial burst access delay
0001 = 3 CLK cycle initial burst access delay
0010 = 4 CLK cycle initial burst access delay
0011 = 5 CLK cycle initial burst access delay
0100 = 6 CLK cycle initial burst access delay
0101 = 7 CLK cycle initial burst access delay
0110 = 8 CLK cycle initial burst access delay
0111 = 9 CLK cycle initial burst access delay—Default
CR9 = Data Output Configuration (DOC)
0 = Hold Data for 1-CLK cycle—Default
1 = Reserved
CR8 = IND/WAIT# Configuration (WC)
0 = IND/WAIT# Asserted During Delay—Default
1 = IND/WAIT# Asserted One Data Cycle Before Delay
CR7 = Burst Sequence (BS)
0 = Reserved
1 = Linear Burst Order—Default
CR6 = Clock Configuration (CC)
0 = Reserved
1 = Burst Starts and Data Output on Rising Clock Edge—Default
CR5–CR3 = Reserved For Future Enhancements (R)
These bits are reserved for future use. Set these bits to “0.”
CR2–CR0 = Burst Length (BL2–BL0)
000 = Reserved, burst accesses disabled (asynchronous reads only)
001 = 64 bit (8-byte) Burst Data Transfer - x16 and x32 Linear
010 = 128 bit (16-byte) Burst Data Transfer - x16 and x32 Linear
011 = 256 bit (32-byte) Burst Data Transfer - x16 Linear Only and x32 Linear
100 = 512 bit (64-byte) Burst Data Transfer - x16 Linear Only - Default
101 = Reserved, burst accesses disabled (asynchronous reads only)
110 = Reserved, burst accesses disabled (asynchronous reads only)
111 = Reserved
June 7, 2006
Am29BDD160G
23
Table 10.
Configuration Register After Device Reset
CR15
CR14
CR13
CR12
CR11
CR10
CR9
CR8
RM
Reserve
IAD3
IAD2
IAD1
IAD0
DOC
WC
1
0
0
1
1
1
0
0
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
BS
CC
Reserve
Reserve
Reserve
BL2
BL1
BL0
1
1
0
0
0
1
0
0
Initial Access Delay Configuration
The frequency configuration informs the device of the
number of clocks that must elapse after ADV# is
driven active before data will be available. This value
is determined by the input clock frequency.
SECTOR PROTECTION
The Am29BDD160 features several levels of sector
protection, which can disable both the program and
erase operations in certain sectors or sector groups
Sector and Sector Groups
The distinction between sectors and sector groups is
fundamental to sector protection. Sector are individual
sectors that can be individually sector protected/unprotected. These are the outermost 4 kword boot sectors, that is, SA0 to SA7 and SA38 to SA45. See
tables 11 and 12.
Sector groups are a collection of three or four adjacent
32 kword sectors. For example, sector group SG8 is
comprised of sector SA8 to SA10. When any sector in
a sector group is protected/unprotected, every sector
in that group is protection/unprotected. See Tables 11
and 12.
Persistent Sector Protection
A command sector protection method that replaces
the old 12 V controlled protection method.
Password Sector Protection
A highly sophisticated protection method that requires
a password before changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase
to the two outermost 8 Kbytes sectors in the 75% bank
All parts default to operate in the Persistent Sector
Protection mode. The customer must then choose if
the Persistent or Password Protection method is most
desirable. There are two one-time programmable
non-volatile bits that define which sector protection
method will be used. If the customer decides to continue using the Persistent Sector Protection method,
24
they must set the Persistent Sector Protection
Mode Locking Bit. This will permanently set the part
to operate only using Persistent Sector Protection. If
the customer decides to use the password method,
they must set the Password Mode Locking Bit. This
will permanently set the part to operate only using
password sector protection.
It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the
Password Mode Locking Bit permanently selects
the protection mode. It is not possible to switch between the two methods once a locking bit has been
set. It is important that one mode is explicitly selected when the device is first programmed, rather
than relying on the default mode alone. This is so
that it is not possible for a system program or virus to
later set the Password Mode Locking Bit, which would
cause an unexpected shift from the default Persistent
Sector Protection Mode into the Password Protection
Mode.
The WP# Hardware Protection feature is always available, independent of the software managed protection
method chosen.
Persistent Sector Protection
The Persistent Sector Protection method replaces the
old 12 V controlled protection method while at the
same time enhancing flexibility by providing three different sector protection states:
■ Persistently Locked—A sector is protected and
cannot be changed.
■ Dynamically Locked—The sector is protected and
can be changed by a simple command
■ Unlocked—The sector is unprotected and can be
changed by a simple command
Am29BDD160G
June 7, 2006
In order to achieve these states, three types of “bits”
are going to be used:
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to a maximum of four sectors (see the sector
address tables for specific sector protection groupings). All 8 Kbyte boot-block sectors have individual
sector Persistent Protection Bits (PPBs) for greater
flexibility. Each PPB is individually modifiable through
the PPB Write Command.
Note: If a PPB requires erasure, all of the sector PPBs
must first be preprogrammed prior to PPB erasing. All
PPBs erase in parallel, unlike programming where individual PPBs are programmable. It is the responsibility of the user to perform the preprogramming
operation. Otherwise, an already erased sector PPBs
has the potential of being over-erased. There is no
har dwar e m ech anis m t o pr ev ent s ec tor PP Bs
over-erasure.
Persistent Protection Bit Lock (PPB Lock)
A global volatile bit. When set to “1”, the PPBs cannot
be changed. When cleared (“0”), the PPBs are
changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock
the PPB Lock.
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector.
After power-up or hardware reset, the contents of all
DYBs is “0”. Each DYB is individually modifiable
through the DYB Write Command.
When the parts are first shipped, the PPBs are
cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state – meaning the
PPBs are changeable.
When the device is first powered on the DYBs power
up cleared (sectors not protected). The Protection
State for each sector is determined by the logical OR
of the PPB and the DYB related to that sector. For the
sectors that have the PPBs cleared, the DYBs control
whether or not the sector is protected or unprotected.
By issuing the DYB Write command sequences, the
DYBs will be set or cleared, thus placing each sector
in the protected or unprotected state. These are the
so-called Dynamic Locked or Unlocked states. They
are called dynamic states because it is very easy to
June 7, 2006
switch back and forth between the protected and unprotected conditions. This allows software to easily
protect sectors against inadvertent changes yet does
not prevent the easy removal of protection when
changes are needed. The DYBs maybe set or cleared
as often as needed.
The PPBs allow for a more static, and difficult to
change, level of protection. The PPBs retain their state
across power cycles because they are Non-Volatile.
Individual PPBs are set with a command but must all
be cleared as a group through a complex sequence of
program and erasing commands. The PPBs are limited to 100 erase cycles.
The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired
settings, the PPB Lock may be set to “1”. Setting the
PPB Lock disables all program and erase commands
to the Non-Volatile PPBs. In effect, the PPB Lock Bit
locks the PPBs into their current state. The only way to
clear the PPB Lock is to go through a power cycle.
System boot code can determine if any changes to the
PPB are needed e.g. to allow new system code to be
downloaded. If no changes are needed then the boot
code can set the PPB Lock to disable any further
changes to the PPBs during system operation.
The WP# write protect pin adds a final level of hardware protection to the two outermost 8 Kbytes sectors
in the 75% bank. When this pin is low it is not possible
to change the contents of these two sectors.
It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic
state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a
simple DYB Write command sequence is all that is
necessary. The DYB write command for the dynamic
sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change
the status of the persistently locked sectors, a few
more steps are required. First, the PPB Lock bit must
be disabled by either putting the device through a
power-cycle, or hardware reset. The PPBs can then
be changed to reflect the desired settings. Setting the
PPB lock bit once again will lock the PPBs, and the
device operates normally again.
Note: to achieve the best protection, it’s recommended
to execute the PPB lock bit set command early in the
boot code, and protect the boot code by holding WP#
= VIL.
Am29BDD160G
25
Table 11.
Sector Protection Schemes
could not place the device in password protection
mode.
DYB
PPB
PPB
Lock
0
0
0
Unprotected—PPB and DYB are
changeable
0
0
1
Unprotected—PPB not
changeable, DYB is changeable
0
1
0
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
Password Protection Mode
Sector State
Protected—PPB and DYB are
changeable
■ When the device is first powered on, or comes out
of a reset cycle, the PPB Lock bit set to the locked
state, rather than cleared to the unlocked state.
■ The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device.
Protected—PPB not
changeable, DYB is changeable
Table 11 contains all possible combinations of the
DYB, PPB, and PPB lock relating to the status of the
sector.
In summary, if the PPB is set, and the PPB lock is set,
the sector is protected and the protection can not be
removed until the next power cycle clears the PPB
lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls
whether or not the sector is protected or unprotected.
If the user attempts to program or erase a protected
sector, the device ignores the command and returns to
read mode. A program command to a protected sector
enables status polling for approximately 1 µs before
the device returns to read mode without having modified the contents of the protected sector. An erase
command to a protected sector enables status polling
for approximately 50 µs after which the device returns
to read mode without having erased the protected sector.
The programming of the DYB, PPB, and PPB lock for
a given sector can be verified by writing a
DYB/PPB/PPB lock verify command to the device.
Persistent Sector Protection Mode
Locking Bit
Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that
the device remain in software sector protection. Once
set, the Persistent Sector Protection locking bit prevents programming of the password protection mode
locking bit. This guarantees that an unauthorized user
26
The Password Sector Protection Mode method allows
an even higher level of security than the Persistent
Sector Protection Mode. There are two main differences between the Persistent Sector Protection and
the Password Sector Protection Mode:
The Password Sector Protection method is otherwise
identical to the Persistent Sector Protection method.
A 64-bit password is the only additional tool utilized in
this method.
The password is stored in a one-time programmable
(OTP) region of the flash memory. Once the Password
Mode Locking Bit is set, the password is permanently
set with no means to read, program, or erase it. The
password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash,
along with a password. The flash device internally
compares the given password with the pre-programmed password. If they match, the PPB Lock bit is
cleared, and the PPBs can be altered. If they do not
match, the flash device does nothing. There is a
built-in 2 µs delay for each “password check.” This
delay is intended to thwart any efforts to run a program
that tries all possible combinations in order to crack
the password.
Password and Password Mode Locking
Bit
In order to select the Password sector protection
scheme, the customer must first program the password. One method of choosing a password would be
to correlate it to the unique Electronic Serial Number
(ESN) of the particular flash device. Another method
could generate a database where all the passwords
are stored, each of which correlates to a serial number
on the device. Each ESN is different for every flash
device; therefore each password should be different
for every flash device. While programming in the password region, the customer may perform Password
Verify operations.
Once the desired password is programmed in, the
customer must then set the Password Mode Locking
Bit. This operation achieves two objectives:
Am29BDD160G
June 7, 2006
1. It permanently sets the device to operate using the
Password Protection Mode. It is not possible to reverse this function.
2. It also disables all further commands to the password region. All program, and read operations are
ignored.
Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors.
The user must be sure that the Password Protection
method is desired when setting the Password Mode
Locking Bit. More importantly, the user must be sure
that the password is correct when the Password Mode
Locking Bit is set. Due to the fact that read operations
are disabled, there is no means to verify what the
password is afterwards. If the password is lost after
setting the Password Mode Locking Bit, there will be
no way to clear the PPB Lock bit.
The Password Mode Locking Bit, once set, prevents
reading the 64-bit password on the DQ bus and further
password programming. The Password Mode Locking
Bit is not erasable. Once Password Mode Locking Bit
is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing
that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory
space and is accessible through the use of the Password Program and Verify commands (see Password
Verify Command). The password function works in
conjunction with the Password Mode Locking Bit,
which when set, prevents the Password Verify command from reading the contents of the password on
the pins of the device.
Write Protect (WP#)
The device features a hardware protection option
using a write protect pin that prevents programming or
erasing, regardless of the state of the sector’s Persistent or Dynamic Protection Bits. The WP# pin is associated with the two outermost 8Kbytes sectors in the
75% bank. The WP# pin has no effect on any other
sector. When WP# is taken to VIL, programming and
erase operations of the two outermost 8 Kbytes sectors in the 75% bank are disabled. By taking WP#
back to VIH, the two outermost 8 Kbytes sectors are
enabled for program and erase operations, depending
upon the status of the individual sector Persistent or
Dynamic Protection Bits. If either of the two outermost
sectors Persistent or Dynamic Protection Bits are programmed, program or erase operations are inhibited.
If the sector Persistent or Dynamic Protection Bits are
both erased, the two sectors are available for programming or erasing as long as WP# remains at VIH.
The user must hold the WP# pin at either V IH or VIL
June 7, 2006
during the entire program or erase operation of the two
outermost sectors in the 75% bank.
SecSi™ (Secured Silicon) Sector
Protection
The SecSi Sector is a 256-byte flash memory area
that is either programmable at the customer or by
AMD at the request of the customer. The SecSi Sector
Entry command enables the host system to address
the SecSi Sector for programming or reading. The
SecSi sector address range is 00000h–0003Fh for the
top bootblock configuration and 7FFC0h–7FFFFh for
the bottom bootblock configuration. Address range
00040h–007FFh for the top bootblock and
7F800h–7FFBFh return invalid data when addressed
with the SecSi sector enabled.
Unlike previous flash memory devices, the
Am29BDD160 allows simultaneous operation while
the SecSi sector is enabled. However, there are a
number of restrictions associated with simultaneous
operation and device operation when the SecSi sector
is enabled:
1. The SecSi sector is not available for reading while
the Password Unlock, any PPB program/erase operation, or Password programming are in progress.
Reading to any location in the small (25%) sector
will return the status of these operations until these
operations have completed execution.
2. Writing the corresponding DYB associated with the
overlaid bootblock sector results in the DYB NOT
being updated. This is only accomplished when the
SecSi sector is not enabled.
3. Reading the corresponding DYB associated with
the overlaid bootblock sector results in reading invalid data when the PPB Lock/DYB Verify command is issued. This function is only accomplished
when the SecSi sector is not enabled.
4. All commands are available for execution when the
SecSi sector is enabled except the following list. Issuing the following commands while the SecSi sector is enabled results in the command being
ignored.
■ All Unlock Bypass commands
■ CFI
■ Accelerated Program
■ Program and Sector Erase Suspend
■ Program and Sector Erase Resume
5. Executing the Sector Erase command is permitted
when the SecSi sector is enabled, however, there is
no provision for erasing the SecSi sector with the
Sector Erase command, regardless of the protection status. The Sector Erase command will erase
all other sectors when the SecSi sector is enabled.
Am29BDD160G
27
6. Executing the Chip Erase command is permitted
when the SecSi sector is enabled. The Chip Erase
command erases all sectors in the memory array
except for sector 0 in top-bootblock configuration
and sector 45 in bottom-bootblock configuration.
The SecSi Sector is a one-time programmable
memory area that cannot be erased.
7. Executing the SecSi Sector Entry command during
program or erase suspend mode is allowed. The
Sector Erase/Program Resume command is disabled while the SecSi sector is enabled, and the
user cannot resume programming of the memory
array until the Exit SecSi Sector command is written.
SecSi Sector Protection Bit
The SecSi Sector Protection Bit prevents programming of the SecSi sector memory area. Once set, the
SecSi sector memory area contents are non-modifiable.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes. In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal erase/program circuits are disabled,
and the device resets. Subsequent writes are ignored
until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent
unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile
bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode
Locking Bit is set, which indicates the device is in
Password Protection Mode, the PPB Lock Bit is also
set after a hardware reset (RESET# asserted) or a
power-up reset. The ONLY means for clearing the
PPB Lock Bit in Password Protection Mode is to issue
the Password Unlock command. Successful execution
of the Password Unlock command clears the PPB
Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on
reset, or issuing the PPB Lock Bit Set command sets
the PPB Lock Bit back to a “1”.
If the Password Mode Locking Bit is not set, indicating
Persistent Sector Protection Mode, the PPB Lock Bit
is cleared after power-up or hardware reset. The PPB
Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB
Lock Bit is by issuing a hardware or power-up reset.
The Password Unlock command is ignored in Persistent Sector Protection Mode.
28
Noise pulses of less than 5 ns (typical) on OE#, CE#,
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero (VIL) while OE#
is a logical one (VIH).
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power-up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
VCC and VIO Power-up And Power-down
Sequencing
The device imposes no restrictions on V CC and V IO
power-up or power-down sequencing. Asserting RESET# to VIL is required during the entire VCC and VIO
power sequence until the respective supplies reach
their operating voltages. Once, VCC and VIO attain their
respective operating voltages, de-assertion of RESET# to VIH is permitted.
Am29BDD160G
June 7, 2006
Table 12. Sector Addresses for Top Boot Sector Devices
Bank 1
(Note 2)
Bank 2
(Note 2)
Sector
SA0 (Note 1)
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44 (Note 3)
SA45 (Note 3)
Sector Group
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
SG14
SG15
SG16
SG17
SG18
SG19
SG20
SG21
SG22
SG23
x16
Address Range
(A18:A-1)
00000h-00FFFh
01000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-04FFFh
05000h-05FFFh
06000h-06FFFh
07000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
40000h-47FFFh
48000h-4FFFFh
50000h-57FFFh
58000h-5FFFFh
60000h-67FFFh
68000h-6FFFFh
70000h-77FFFh
78000h-7FFFFh
80000h-87FFFh
88000h-8FFFFh
90000h-97FFFh
98000h-9FFFFh
A0000h-A7FFFh
A8000h-AFFFFh
B0000h-B7FFFh
B8000h-BFFFFh
C0000h-C7FFFh
C8000h-CFFFFh
D0000h-D7FFFh
D8000h-DFFFFh
E0000h-E7FFFh
E8000h-EFFFFh
F0000h-F7FFFh
F8000h-F8FFFh
F9000h-F9FFFh
FA000h-FAFFFh
FB000h-FBFFFh
FC000h-FCFFFh
FD000h-FDFFFh
FE000h-FEFFFh
FF000h-FFFFFh
x32
Address Range
(A18:A0)
00000h-007FFh
00800h-00FFFh
01000h-017FFh
01800h-01FFFh
02000h-027FFh
02800h-02FFFh
03000h-037FFh
03800h-03FFFh
04000h-07FFFh
08000h-0BFFFh
0C000h-0FFFFh
10000h-13FFFh
14000h-17FFFh
18000h-1BFFFh
1C000h-1FFFFh
20000h-23FFFh
24000h-27FFFh
28000h-2BFFFh
2C000h-2FFFFh
30000h-33FFFh
34000h-37FFFh
38000h-3BFFFh
3C000h-3FFFFh
40000h-43FFFh
44000h-47FFFh
48000h-4BFFFh
4C000h-4FFFFh
50000h-53FFFh
54000h-57FFFh
58000h-5BFFFh
5C000h-5FFFFh
60000h-63FFFh
64000h-67FFFh
68000h-6BFFFh
6C000h-6FFFFh
70000h-73FFFh
74000h-77FFFh
78000h-7BFFFh
7C000h-7C7FFh
7C800h-7CFFFh
7D000h-7D7FFh
7D800h-7DFFFh
7E000h-7E7FFh
7E800h-7EFFFh
7F000h-7F7FFh
7F800h-7FFFFh
Sector Size
(Kwords)
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
Notes:
1. SecSi Sector overlays this sector when enabled.
2. The bank address is determined by A18 and A17. BA = 00 for Bank 1 and BA = 01, 10, or 11 for Bank 2.
3. This sector has the additional WP# pin sector protection feature.
June 7, 2006
Am29BDD160G
29
Table 13.
Bank 1
(Note 2)
Bank 2
(Note 2)
Sector
SA0 (Note 1)
SA1 (Note 1)
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45 (Note 3)
Sector Addresses for Bottom Boot Sector Devices
Sector Group
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
SG14
SG15
SG16
SG17
SG18
SG19
SG20
SG21
SG22
SG23
x16
Address Range
(A18:A-1)
00000h-00FFFh
01000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-04FFFh
05000h-05FFFh
06000h-06FFFh
07000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
40000h-47FFFh
48000h-4FFFFh
50000h-57FFFh
58000h-5FFFFh
60000h-67FFFh
68000h-6FFFFh
70000h-77FFFh
78000h-7FFFFh
80000h-87FFFh
88000h-8FFFFh
90000h-97FFFh
98000h-9FFFFh
A0000h-A7FFFh
A8000h-AFFFFh
B0000h-B7FFFh
B8000h-BFFFFh
C0000h-C7FFFh
C8000h-CFFFFh
D0000h-D7FFFh
D8000h-DFFFFh
E0000h-E7FFFh
E8000h-EFFFFh
F0000h-F7FFFh
F8000h-F8FFFh
F9000h-F9FFFh
FA000h-FAFFFh
FB000h-FBFFFh
FC000h-FCFFFh
FD000h-FDFFFh
FE000h-FEFFFh
FF000h-FFFFFh
x32
Address Range
(A18:A0)
00000h-007FFh
00800h-00FFFh
01000h-017FFh
01800h-01FFFh
02000h-027FFh
02800h-02FFFh
03000h-037FFh
03800h-03FFFh
04000h-07FFFh
08000h-0BFFFh
0C000h-0FFFFh
10000h-13FFFh
14000h-17FFFh
18000h-1BFFFh
1C000h-1FFFFh
20000h-23FFFh
24000h-27FFFh
28000h-2BFFFh
2C000h-2FFFFh
30000h-33FFFh
34000h-37FFFh
38000h-3BFFFh
3C000h-3FFFFh
40000h-43FFFh
44000h-47FFFh
48000h-4BFFFh
4C000h-4FFFFh
50000h-53FFFh
54000h-57FFFh
58000h-5BFFFh
5C000h-5FFFFh
60000h-63FFFh
64000h-67FFFh
68000h-6BFFFh
6C000h-6FFFFh
70000h-73FFFh
74000h-77FFFh
78000h-7BFFFh
7C000h-7C7FFh
7C800h-7CFFFh
7D000h-7D7FFh
7D800h-7DFFFh
7E000h-7E7FFh
7E800h-7EFFFh
7F000h-7F7FFh
7F800h-7FFFFh
Sector Size
(Kwords)
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
Notes:
1. This sector has the additional WP# pin sector protection feature.
2. The bank address is determined by A18 and A17. BA = 00, 01, or 10 for Bank 1 and BA = 11 for Bank 2.
3. SecSi Sector overlays this sector when enabled.
30
Am29BDD160G
June 7, 2006
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The
system can read CFI information at the addresses
given in Tables 13–16. To terminate reading CFI data,
the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 13–16. The
system must write the reset command to return the device to the autoselect mode.
For further information, please refer to the CFI Specification and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/products/nvd/overview/cfi.html. Alternatively, contact an
AMD representative for copies of these documents.
Table 14. CFI Query Identification String
Addresses
(x32 Mode)
Addresses
(x16 Mode)
Data
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Table 15.
Description
CFI System Interface String
Addresses
(x32 Mode)
Addresses
(x16 Mode)
Data
1Bh
36h
0023h
VCC Min. (write/erase)
DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt
1Ch
38h
0027h
VCC Max. (write/erase)
DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt
1Dh
3Ah
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
3Ch
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
3Eh
0004h
Typical timeout per single word/doubleword program 2N µs
20h
40h
0000h
Typical timeout for Min. size buffer program 2N µs (00h = not supported)
21h
42h
0009h
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
46h
0005h
Max. timeout for word/doubleword program 2N times typical
24h
48h
0000h
Max. timeout for buffer write 2N times typical
25h
4Ah
0007h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
June 7, 2006
Description
Am29BDD160G
31
Table 16. CFI Device Geometry Definition
Addresses
(x32 Mode)
27h
Addresses
(x16 Mode)
4Eh
Data
0015h
Description
N
Device Size = 2 byte
Flash Device Interface description (for complete description, please refer
to CFI publication 100)
0000 = x8-only asynchronous interface
28h
29h
50h
52h
0005h
0000h
0001 = x16-only asynchronous interface
0002 = supports x8 and x16 via BYTE# with asynchronous interface
0003 = x 32-only asynchronous interface
0005 = supports x16 and x32 via WORD# with asynchronous interface
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte program = 2N
(00h = not supported)
2Ch
58h
0003h
0004h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
001Dh
0000h
0000h
0001h
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
Table 17.
0003 = Speed options 54D, 65D, 65A
CFI Primary Vendor-Specific Extended Query
Addresses
(x32 Mode)
Addresses
(x16 Mode)
Data
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
86h
0031h
Major version number, ASCII (reflects modifications to the silicon)
44h
88h
0033h
Minor version number, ASCII (reflects modifications to the CFI table)
Description
Address Sensitive Unlock (DQ1, DQ0)
00 = Required, 01 = Not Required
45h
32
8Ah
0004h
Silicon Revision Number (DQ5–DQ2
0000 = CS49
0001 = CS59
0010 = CS99
0011 = CS69
0100 = CS119
Am29BDD160G
June 7, 2006
Table 17. CFI Primary Vendor-Specific Extended Query (Continued)
Addresses
(x32 Mode)
Addresses
(x16 Mode)
Data
Description
46h
8Ch
0002h
Erase Suspend (1 byte)
00 = Not Supported
01 = To Read Only
02 = To Read and Write
47h
8Eh
0001h
Sector Protect (1 byte)
00 = Not Supported, X = Number of sectors in per group
48h
90h
0000h
Temporary Sector Unprotect
00h = Not Supported, 01h = Supported
49h
92h
0006h
Sector Protect/Unprotect scheme (1 byte)
01 =29F040 mode, 02 = 29F016 mode
03 = 29F400 mode, 04 = 29LV800 mode
05 = 29BDS640 mode (Software Command Locking)
06 = BDD160 mode (New Sector Protect)
07 = 29LV800 + PDL128 (New Sector Protect) mode
4Ah
94h
001Fh
Simultaneous Operation (1 byte)
00h = Not Supported, X = Number of sectors in all banks except Bank 1
4Bh
96h
0001h
Burst Mode Type
00h = Not Supported, 01h = Supported
4Ch
98h
0000h
Page Mode Type
00h = Not Supported, 01h = 4 Word Page, 02h = 8 Word Page
4Dh
9Ah
00B5h
ACC (Acceleration) Supply Minimum
00h = Not Supported (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD)
4Eh
9Ch
00C5h
ACC (Acceleration) Supply Maximum
00h = Not Supported, (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD)
4Fh
9Eh
0001h
Top/Bottom Boot Sector Flag (1 byte)
00h = Uniform device, no WP# control,
01h = 8 x 8 Kb sectors at top and bottom with WP# control
02h = Bottom boot device
03h = Top boot device
04h = Uniform, Bottom WP# Protect
05h = Uniform, Top WP# Protect
If the number of erase block regions = 1, then ignore this field
50h
A0h
0001h
Program Suspend
00 = Not Supported
01 = Supported
51h
A2h
0000h
Write Buffer Size
2(N+1) word(s)
57h
AEh
0002h
Bank Organization (1 byte)
00 = If data at 4Ah is zero
XX = Number of banks
58h
B0h
000Fh
Bank 1 Region Information (1 byte)
XX = Number of Sectors in Bank 1
59h
B2h
001Fh
5Ah
B4h
0000h
5Bh
B6h
0000h
June 7, 2006
Bank 2 Region Information (1 byte)
XX = Number of Sectors in Bank 2
Bank 3 Region Information (1 byte)
XX = Number of Sectors in Bank 3
Bank 4 Region Information (1 byte)
XX = Number of Sectors in Bank 4
Am29BDD160G
33
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Tables 18-21 define the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data in Non-burst Mode
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming operation in the Erase Suspend mode, the system may
once again read array data with the same exception.
See Sector Erase and Program Suspend Command
for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify command
to the device. section.
See also Asynchronous Read Operation (Non-Burst) in
the Key to Switching Waveforms section for more
information. See the Sector Erase and Program Resume
Command sections for more information on this mode.
Reading Array Data in Burst Mode
The device is capable of very fast Burst mode read operations. The configuration register sets the read configuration, burst order, frequency configuration, and
burst length.
Upon power on, the device defaults to the asynchronous mode. In this mode, CLK, and ADV# are ignored.
The device operates like a conventional Flash device.
Data is available tACC/tCE nanoseconds after address
becomes stable, CE# become asserted. The device
enters the burst mode by enabling synchronous burst
reads in the configuration register. The device exits
burst mode by disabling synchronous burst reads in
the configuration register. (See Command Definitions).
34
The RESET# command will not terminate the Burst
mode. System reset (power on reset) will terminate
the Burst mode.
The device has the regular control pins, i.e. Chip Enable (CE#), Write Enable (WE#), and Output Enable
(OE#) to control normal read and write operations.
Moreover, three additional control pins have been
added to allow easy interface with minimal glue logic
to a wide range of microprocessors / microcontrollers
for high performance Burst read capability. These additional pins are Address Valid (ADV#) and Clock
(CLK). CE#, OE#, and WE# are asynchronous (relative to CLK). The Burst mode read operation is a synchronous operation tied to the edge of the clock. The
microprocessor / microcontroller supplies only the initial address, all subsequent addresses are automatically generated by the device with a timing defined by
the Configuration Register definition. The Burst read
cycle consists of an address phase and a corresponding data phase.
During the address phase, the Address Valid (ADV#)
pin is asserted (taken Low) for one clock period. Together with the edge of the CLK, the starting burst address is loaded into the internal Burst Address
Counter. The internal Burst Address Counter can be
configured to either the Linear modes (See “Initial Access Delay Configuration”).
During the data phase, the first burst data is available
after the initial access time delay defined in the Configuration Register. For subsequent burst data, every rising (or falling) edge of the CLK will trigger the output
data with the burst output delay and sequence defined
in the Configuration Register.
Tables 17–20 show all the commands executed by the
device. The device automatically powers up in the
read/reset state. It is not necessary to issue a read/reset command after power-up or hardware reset.
Read/Reset Command
After power-up or hardware reset, the Am29BDD160
automatically enter the read state. It is not necessary
to issue the reset command after power-up or hardware reset. Standard microprocessor cycles retrieve
array data, however, after power-up, only asynchronous accesses are permitted since the Configuration
Register is at its reset state with burst accesses disabled.
The Reset command is executed when the user needs
to exit any of the other user command sequences
(such as autoselect, program, chip erase, etc.) to return to reading array data. There is no latency between executing the Reset command and reading
array data.
Am29BDD160G
June 7, 2006
The Reset command does not disable the SecSi sector if it is enabled. This function is only accomplished
by issuing the SecSi Sector Exit command.
Autoselect Command
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. PROM
programmers typically access the signature codes by
raising A9 to VID. However, multiplexing high voltage
onto the address lines is not generally desired system
design practice.
The Am29BDD160 contains an Autoselect Command
operation to supplement traditional PROM programming methodology. The operation is initiated by writing
the Autoselect command sequence into the command
register. The bank address (BA) is latched during the
autoselect command sequence write operation to distinguish which bank the Autoselect command references. Reading the other bank after the Autoselect
command is written results in reading array data from
the other bank and the specified address. Following
the command write, a read cycle from address
(BA)XX00h retrieves the manufacturer code of
(BA)XX01h. Three sequential read cycles at addresses (BA) XX01h, (BA) XX0Eh, and (BA) XX0Fh
read the three-byte device ID (see Tables 19 and 20).
All manufacturer and device codes exhibit odd parity
with the MSB of the lower byte (DQ7) defined as the
parity bit.
(The Autoselect Command requires the user to execute the Read/Reset command to return the device
back to reading the array contents.)
Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically generates the program pulses and verifies the programmed
cell margin. Tables 18 and 20 shows the address and
data requirements for the program command sequence.
During the Embedded Program algorithm, the system
can determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. (See Write Operation
Status for information on these status bits.) When the
Embedded Program algorithm is complete, the device
returns to reading array data and addresses are no
longer latched. Note that an address change is required to begin read valid array data.
June 7, 2006
Except for Program Suspend, any commands written
to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately
terminates the programming operation. The command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may
halt the operation and set DQ5 to “1,” or cause the
Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read will show that
the data is still “0”. Only erase operations can convert
a “0” to a “1”.
Accelerated Program Command
The Accelerated Chip Program mode is designed to
improve the Word or Double Word programming
speed. Improving the programming speed is accomplished by using the ACC pin to supply both the wordline voltage and the bitline current instead of using the
VPP pump and drain pump, which is limited to 2.5 mA.
Because the external ACC pin is capable of supplying
significantly large amounts of current compared to the
drain pump, all 32 bits are available for programming
with a single programming pulse. This is an enormous
improvement over the standard 5-bit programming. If
the user is able to supply an external power supply
and connect it to the ACC pin, significant time savings
are realized.
In order to enter the Accelerated Program mode, the
ACC pin must first be taken to VHH (12 V ± 0.5 V) and
followed by the one-cycle command with the program
address and data to follow. The Accelerated Chip Program command is only executed when the device is in
Unlock Bypass mode and during normal read/reset
operating mode.
In this mode, the write protection function is bypassed
unless the PPB Lock Bit = 1.
The Accelerated Program command is not permitted if
the SecSi sector is enabled.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
Am29BDD160G
35
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. Tables 18 and 20 show the requirements for
the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
Figure 5 illustrates the algorithm for the program operation. See the Erase/Program Operations table in AC
Characteristics for parameters, and to Figure 22 for
timing diagrams.
START
and CFI commands. This feature permits slow PROM
programmers to significantly improve programming/erase throughput since the command sequence
often requires microseconds to execute a single write
operation. Therefore, once the Unlock Bypass command is issued, only the two-cycle program and erase
bypass commands are required. The Unlock Bypass
Command is ignored if the SecSi sector is enabled. To
return back to normal operation, the Unlock Bypass
Reset Command must be issued.
The following four sections describe the commands
that may be executed within the unlock bypass mode.
Unlock Bypass Program Command
The Unlock Bypass Program command is a two-cycle
command that consists of the actual program command (A0h) and the program address/data combination. This command does not require the two-cycle
“unlock” sequence since the Unlock Bypass command
was previously issued. As with the standard program
command, multiple Unlock Bypass Program commands can be issued once the Unlock Bypass command is issued.
To return back to standard read operations, the Unlock
Bypass Reset command must be issued.
Write Program
Command Sequence
The Unlock Bypass Program Command is ignored if
the SecSi sector is enabled.
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Unlock Bypass Chip Erase Command
No
Yes
Increment Address
No
To return back to standard read operations, the Unlock
Bypass Reset command must be issued.
Last Address?
The Unlock Bypass Program Command is ignored if
the SecSi sector is enabled.
Yes
Programming
Completed
Unlock Bypass CFI Command
Note: See Tables 18 and 20 for program command sequence.
Figure 4.
The Unlock Bypass Chip Erase command is a 2-cycle
command that consists of the erase setup command
(80h) and the actual chip erase command (10h). This
command does not require the two-cycle “unlock” sequence since the Unlock Bypass command was previously issued. Unlike the standard erase command,
there is no Unlock Bypass Erase Suspend or Erase
Resume commands.
Program Operation
The Unlock Bypass CFI command is available for
PROM programmers and target systems to read the
CFI codes while in Unlock Bypass mode. See Common Flash Memory Interface (CFI) for specific CFI
codes.
To return back to standard read operations, the Unlock
Bypass Reset command must be issued.
Unlock Bypass Entry Command
The Unlock Bypass command, once issued, is used to
bypass the “unlock” sequence for program, chip erase,
36
The Unlock Bypass Program Command is ignored if
the SecSi sector is enabled.
Am29BDD160G
June 7, 2006
Unlock Bypass Reset Command
The Unlock Bypass Reset command places the device
in standard read/reset operating mode. Once executed, normal read operations and user command sequences are available for execution.
The Unlock Bypass Program Command is ignored if
the SecSi sector is enabled.
Chip Erase Command
The Chip Erase command is used to erase the entire
flash memory contents of the chip by issuing a single
command. Chip erase is a six-bus cycle operation.
There are two “unlock” write cycles, followed by writing
the erase “set up” command. Two more “unlock” write
cycles are followed by the chip erase command. Chip
erase does not erase protected sectors.
The chip erase operation initiates the Embedded
Erase algorithm, which automatically preprograms and
verifies the entire memory to an all zero pattern prior
to electrical erase. The system is not required to provide any controls or timings during these operations.
Note that a hardware reset immediately terminates
the programming operation. The command sequence
should be reinitiated once that bank has returned to
reading array data, to ensure data integrity.
The Embedded Erase algorithm erase begins on the
rising edge of the last WE# or CE# pulse (whichever
occurs first) in the command sequence. The status of
the erase operation is determined three ways:
■ Data# polling of the DQ7 pin (see DQ7: Data# Polling)
■ Checking the status of the toggle bit DQ6 (see DQ6:
Toggle Bit I)
■ Checking the status of the RY/BY# pin (see
RY/BY#: Ready/Busy#)
Once erasure has begun, only the Erase Suspend
command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data, and addresses
are no longer latched. Note that an address change is
required to begin read valid array data.
Figure 5 illustrates the Embedded Erase Algorithm.
See the Erase/Program Operations tables in AC Characteristics for parameters, and to Figure 22 for timing
diagrams.
Sector Erase Command
The Sector Erase command is used to erase individual sectors or the entire flash memory contents. Sector erase is a six-bus cycle operation. There are two
“unlock” write cycles, followed by writing the erase “set
up” command. Two more “unlock” write cycles are
then followed by the erase command (30h). The sec-
June 7, 2006
tor address (any address location within the desired
sector) is latched on the falling edge of WE# or CE#
(whichever occurs last) while the command (30h) is
latched on the rising edge of WE# or CE# (whichever
occurs first).
Specifying multiple sectors for erase is accomplished
by writing the six bus cycle operation, as described
above, and then following it by additional writes of only
the last cycle of the Sector Erase command to addresses or other sectors to be erased. The time between Sector Erase command writes must be less
than 80 µs, otherwise the command is rejected. It is
recommended that processor interrupts be disabled
during this time to guarantee this critical timing condition. The interrupts can be re-enabled after the last
Sector Erase command is written. A time-out of 80 µs
from the rising edge of the last WE# (or CE#) will initiate the execution of the Sector Erase command(s). If
another falling edge of the WE# (or CE#) occurs within
the 80 µs time-out window, the timer is reset. Once the
80 µs window has timed out and erasure has begun,
only the Erase Suspend command is recognized (see
Sector Erase and Program Suspend Command and
Sector Erase and Program Resume Command sections). If that occurs, the sector erase command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Loading the sector erase registers may be done in any
sequence and with any number of sectors.
Sector erase does not require the user to program the
device prior to erase. The device automatically preprograms all memory locations, within sectors to be
erased, prior to electrical erase. When erasing a sector or sectors, the remaining unselected sectors or the
write protected sectors are unaffected. The system is
not required to provide any controls or timings during
sector erase operations. The Erase Suspend and
Erase Resume commands may be written as often as
required during a sector erase operation.
Automatic sector erase operations begin on the rising
edge of the WE# or CE# pulse of the last sector erase
command issued, and once the 80 µs time-out window
has expired. The status of the sector erase operation
is determined three ways:
■ Data# polling of the DQ7 pin
■ Checking the status of the toggle bit DQ6
■ Checking the status of the RY/BY# pin
Further status of device activity during the sector
erase operation is determined using toggle bit DQ2
(refer to DQ2: Toggle Bit II).
When the Embedded Erase algorithm is complete, the
device returns to reading array data, and addresses
are no longer latched. Note that an address change is
required to begin read valid array data.
Am29BDD160G
37
Figure 5 illustrates the Embedded™ Erase Algorithm,
using a typical command sequence and bus operation.
Refer to the Erase/Program Operations tables in the
AC Characteristics section for parameters, and to Figure 22 for timing diagrams.
START
■ Given that 300 successful erase pulses are required, a successful sector erase operation shall
have a maximum of 5680 erase suspends.
The Sector Erase and Program Suspend command is
ignored if written during the execution of the Chip
Erase operation or Embedded Program Algorithm (but
will reset the chip if written improperly during the command sequences). Writing the Sector Erase and Program command during the Sector Erase time-out
results in immediate termination of the time-out period
and suspension of the erase operation. Once in Erase
Suspend, the device is available for reading (note that
in the Erase Suspend mode, the Reset command is
not required for read operations and is ignored) or program operations in sectors not being erased. Any
other command written during the Erase Suspend
mode is ignored, except for the Sector Erase and Program Resume command. Writing the Erase and Program Resume command resumes the sector erase
operation. The bank address of the erase suspended
bank is required when writing this command
Write Erase
Command Sequence
Data Poll
from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Tables 18 and 20 for erase command sequence.
2. See DQ3: Sector Erase Timer for more information.
Figure 5.
The counter is incremented by one every time an
erase pulse is initiated, regardless of whether or not
that erase pulse is successful. An erase pulse is terminated immediately when the suspend command
is executed. A new erase pulse is initiated when the
resume command is executed (and the counter is
incremented).
Erase Operation
Sector Erase and Program Suspend
Command
The Sector Erase and Program Suspend command allows the user to interrupt a Sector Erase or Program
operation and perform data read or programs in a sector that is not being erased or to the sector where a
programming operation was initiated. This command
is applicable only during the Sector Erase and Programming operation, which includes the time-out period for Sector Erase.
If the Sector Erase and Program Suspend command
is written during a programming operation, the device
suspends programming operations and allows only
read operations in sectors not selected for programming. Further nesting of either erase or programming
operations is not permitted. Table 18 summarizes permissible operations during Erase and Program Suspend. (A busy sector is one that is selected for
programming or erasure.):
Table 18. Allowed Operations During
Erase/Program Suspend
Sector
Busy Sector
Non-busy
sectors
Program Suspend
Program Resume
Erase Suspend
Erase Resume
Read Only
Read or Program
■ A successful sector erase operation requires 300
successful erase pulses.
When the Sector Erase and Program Suspend command is written during a Sector Erase operation, the
chip will take between 0.1 µs and 20 µs to actually
suspend the operation and go into the erase suspended read mode (pseudo-read mode), at which time
the user can read or program from a sector that is not
erase suspended. Reading data in this mode is the
same as reading from the standard read mode, except
that the data must be read from sectors that have not
been erase suspended.
■ An internal counter monitors the number of erase
pulses initiated and has a maximum value of 5980.
Polling DQ6 on two immediately consecutive reads
from a given address provides the system with the
Sector Erase and Program Suspend
Operation Mechanics
■ A successful erase pulse has a duration or 1.2 ms
± 20%, depending on the number of previous erase
cycles (among other factors).
38
Am29BDD160G
June 7, 2006
ability to determine if the device is in Erase or Program
Suspend. Before the device enters Erase or Program
Suspend, the DQ6 pin toggles between two immediately consecutive reads from the same address. After
the device has entered Erase suspend, DQ6 stops
toggling between two immediately consecutive reads
to the same address. During the Sector Erase operation and also in Erase suspend mode, two immediately
consecutive readings from the erase-suspended sector causes DQ2 to toggle. DQ2 does not toggle if reading from a non-busy (non-erasing) sector (stored data
is read). No bits are toggled during program suspend
mode. Software must keep track of the fact that the
device is in a suspended mode.
After entering the erase-suspend-read mode, the system may read or program within any non-suspended
sector:
■ A read operation from the erase-suspended bank
returns polling data during the first 8 µs after the
erase suspend command is issued; read operations
thereafter return array data. Read operations from
the other bank return array data with no latency.
■ A program operation while in the erase suspend
mode is the same as programming in the regular
program mode, except that the data must be programmed to a sector that is not erase suspended.
Write operation status is obtained in the same manner as a normal program operation.
Sector Erase and Program Resume
Command
tents. The contents of the Configuration Register are
place on DQ15–DQ0. If WORD# is at VIH (32-bit DQ
Bus), the contents of DQ31–DQ16 are XXXXh and
should be ignored. The user should execute the
Read/Reset command to place the device back in
standard user operation after executing the Configuration Register Read command.
The Configuration Register Read Command is fully
operational if the SecSi sector is enabled.
Configuration Register Write Command
The Configuration Register Write command is used to
modify the contents of the Configuration Register. Execution of this command is only allowed while in user
mode and is not available during Unlock Bypass mode
or during Security mode. The Configuration Register
Write command is preceded by the standard two-cycle
“unlock” sequence, followed by the Configuration Register Write command (D0h), and finally followed by
writing the contents of the Configuration Register to
any address. The contents of the Configuration Register are place on DQ15–DQ0. If WORD# is at V IH
(32-bit DQ Bus), the contents of DQ31–DQ16 are
XXXXh and are ignored. Writing the Configuration
Register while an Embedded Algorithm™ or Erase
Suspend modes are executing results in the contents
of the Configuration Register not being updated.
The Configuration Register Read Command is fully
operational if the SecSi sector is enabled.
Common Flash Interface (CFI) Command
The Sector Erase and Program Resume command
(30h) resumes a Sector Erase or Program operation
that has been suspended. Any further writes of the
Sector Erase and Program Resume command ignored. However, another Sector Erase and Program
Suspend command can be written after the device has
resumed sector erase operations. Note that until a
suspended program or erase operation has resumed,
the contents of that sector are unknown.
The Common Flash Interface (CFI) command provides device size, geometry, and capability information
directly to the users system. Flash devices that support CFI, have a “Query Command” that returns information about the device to the system. The Query
structure contents are read at the specific address locations following a single system write cycle where:
The Sector Erase and Program Resume Command is
ignored if the SecSi sector is enabled.
■ The device is initially in any valid read state, such as
“Read Array” or “Read ID Data”
Configuration Register Read Command
Other device statistics may exist within a long sequence of commands or data input; such sequences
must first be completed or terminated before writing of
the 98H Query command, otherwise invalid Query
data structure output may result.
The Configuration Register Read command is used to
verify the contents of the Configuration Register. Execution of this command is only allowed while in user
mode and is not available during Unlock Bypass mode
or during Security mode. The Configuration Register
Read command is preceded by the standard two-cycle
“unlock” sequence, followed by the Configuration Register Read command (C6h), and finally followed by
performing a read operation to the bank address specified when the C6h command was written. Reading the
other bank results in reading the flash memory con-
June 7, 2006
■ A 98h query command code is written to 55h address location within the device’s address space
No t e t ha t f or d a ta bu s bi t s gr e a te r th a n DQ 7
(DQ31–DQ8), the valid Query access code has all zeroes (“0”s) in the upper DQ bus locations. Thus, the
16-bit Query command code is 0098h and the 32-bit
Query command code is 00000098h.
To terminate the CFI operation, it is necessary to execute the Read/Reset command.
Am29BDD160G
39
The CFI command is not permitted if the SecSi sector
is enabled and Simultaneous Operation is disabled
once the command is entered.
40
See Common Flash Memory Interface (CFI) for the
specific CFI command codes.
Am29BDD160G
June 7, 2006
SecSi Sector Entry Command
The SecSi Sector Entry command enables the SecSi
(OTP) sector to overlay the 8 KB outermost sector in
the small (25%) bank. The SecSi sector overlays
00000h–0003Fh for the top bootblock configuration
and 7FFC0h–7FFFFh for the bottom bootblock confiuration. Address range 00040h–007FFh for the top
bootblock and 7F800h–7FFBFh return invalid data
when addressed with the SecSi sector enabled. The
following commands are permitted after issuing the
SecSi Sector Entry command:
1. Autoselect
2. Password Program (x16 and x32)
3. Password Verify
4. Password Unlock (x16 and x32)
5. Read/Reset
6. Program
7. Chip and Sector Erase
8. SecSi Sector Protection Bit Program
9. PPB Program
10.All PPB Erase
11. PPB Lock Bit Set
12.DYB Write
13.DYB/PPB/PPB Lock Bit Verify
14.Security Reset
15.Configuration Register Write
16.Configuration Register Read
The following commands are unavailable when the
SecSi sector is enabled. Issuing the following commands while the SecSi sector is enabled results in the
command being ignored.
1. Unlock Bypass
2. CFI
Password Program Command
The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is
64-bits long. Depending upon the state of the WORD#
pin, multiple Password Program Commands are required. For a x16 bit data bus, 4 Password Program
commands are required to program the password. For
a x32 bit data bus, 2 Password Program commands
are required. The user must enter the unlock cycle,
password program command (38h) and the program
address/data for each portion of the password when
programming. There are no provisions for entering the
2-cycle unlock cycle, the password program command, and all the password data. There is no special
addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read
operations to any memory location will return the programming status. Once programming is complete, the
user must issue a Read/Reset command to return the
device to normal operation. Once the Password is
written and verified, the Password Mode Locking Bit
must be set in order to prevent verification. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is
programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell remaining
as a “0”. The password is all F’s when shipped from
the factory. All 64-bit password combinations are valid
as a password.
Password Programming is permitted if the SecSi sector is enabled.
3. Accelerated Program
4. Program and Sector Erase Suspend
Password Verify Command
5. Program and Sector Erase Resume
The SecSi Sector Entry command is allowed when the
device is in either program or erase suspend modes. If
the SecSi sector is enabled, the program or erase suspend command is ignored. This prevents resuming either programming or erasure on the SecSi sector if the
overlayed sector was undergoing programming or erasure. The host system must ensure that the device
resume any suspended program or erase operation after exiting the SecSi sector.
Executing any of the PPB program/erase commands,
or Password Unlock command results in the small
bank (25% bank) returning the status of these opera-
June 7, 2006
tions while they are in progress, thus making the
SecSi sector unavailable for reading. If the SecSi sector is enabled while the DYB command is issued, the
DYB for the overlayed sector is NOT updated. Reading the DYB status using the PPB Lock Bit/DYBDYB
verify command when the SecSi sector is enabled returns invalid data.
The Password Verify Command is used to verify the
Password. The Password is verifiable only when the
Password Mode Locking Bit is not programmed. If the
Password Mode Locking Bit is programmed and the
user attempts to verify the Password, the device will
always drive all F’s onto the DQ data bus.
The Password Verify command is permitted if the
SecSi sector is enabled. Also, the device will not operate in Simultaneous Operation when the Password
Verify command is executed. Only the password is returned regardless of the bank address. The lower two
address bits (A0:A-1) are valid during the Password
Am29BDD160G
41
Verify. Writing the Read/Reset command returns the
device back to normal operation.
The SecSi Sector Protection Bit Program command is
permitted if the SecSi sector is enabled.
Password Protection Mode Locking Bit
Program Command
PPB Lock Bit Set Command
The Password Protection Mode Locking Bit Program
Command programs the Password Protection Mode
Locking Bit, which prevents further verifies or updates
to the Password. Once programmed, the Password
Protection Mode Locking Bit cannot be erased! If the
Password Protection Mode Locking Bit is verified as
program without margin, the Password Protection
Mode Locking Bit Program command can be executed
to improve the program margin. Once the Password
Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry
is disabled, thereby forcing the device to remain in the
Password Protection mode. Exiting the Mode Locking
Bit Program command is accomplished by writing the
Read/Reset command.
The Password Protection Mode Locking Bit Program
command is permitted if the SecSi sector is enabled.
Persistent Sector Protection Mode
Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit
Program Command programs the Persistent Sector
Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed.
If the Persistent Sector Protection Mode Locking Bit is
verified as programmed without margin, the Persistent
Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin.
By disabling the program circuitry of the Password
Mode Locking Bit, the device is forced to remain in the
Persistent Sector Protection mode of operation, once
this bit is set. Exiting the Persistent Protection Mode
Locking Bit Program command is accomplished by
writing the Read/Reset command.
The Persistent Sector Protection Mode Locking Bit
Program command is permitted if the SecSi sector is
enabled.
SecSi Sector Protection Bit Program
Command
The SecSi Sector Protection Bit Program Command
programs the SecSi Sector Protection Bit, which prevents the SecSi sector memory from being cleared. If
the SecSi Sector Protection Bit is verified as programmed without margin, the SecSi Sector Protection
Bit Program Command should be reissued to improve
program margin. Exiting the V CC-level SecSi Sector
Protection Bit Program Command is accomplished by
writing the Read/Reset command.
42
The PPB Lock Bit Set command is used to set the
PPB Lock bit if it is cleared either at reset or if the
Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command.
Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or
the Password Unlock command is executed. Upon
setting the PPB Lock Bit, the PPBs are latched into the
DYBs. If the Password Mode Locking Bit is set, the
PPB Lock Bit status is reflected as set, even after a
power-on reset cycle. Exiting the PPB Lock Bit Set
command is accomplished by writing the Read/Reset
command.
The PPB Lock Bit Set command is permitted if the
SecSi sector is enabled.
DYB Write Command
The DYB Write command is used to set or clear a DYB
for a given sector. The high order address bits
(A18–A11) are issued at the same time as the code
01h or 00h on DQ7-DQ0. All other DQ data bus pins
are ignored during the data write cycle. The DYBs are
modifiable at any time, regardless of the state of the
PPB or PPB Lock Bit. The DYBs are cleared at
power-up or hardware reset.Exiting the DYB Write
command is accomplished by writing the Read/Reset
command.
The DYB Write command is permitted if the SecSi
sector is enabled.
Password Unlock Command
The Password Unlock command is used to clear the
PPB Lock Bit so that the PPBs can be unlocked for
modification, thereby allowing the PPBs to become accessible for modification. The exact password must be
entered in order for the unlocking function to occur.
This command cannot be issued any faster than 2 µs
at a time to prevent a hacker from running through the
all 64-bit combinations in an attempt to correctly match
a password. If the command is issued before the 2 µs
execution window for each portion of the unlock, the
command will be ignored.
The Password Unlock function is accomplished by
writing Password Unlock command and data to the
device to perform the clearing of the PPB Lock Bit.
The password is 64 bits long, so the user must write
the Password Unlock command 2 times for a x32 bit
data bus and 4 times for a x16 data bus. A0 is used to
determine whether the 32 bit data quantity is used to
match the upper 32 bits or lower 32 bits. A0 and A-1 is
used for matching when the x16 bit data bus is se-
Am29BDD160G
June 7, 2006
lected (WORD# = 0). Writing the Password Unlock
command is address order specific. In other words, for
the x32 data bus configuration, the lower 32 bits of the
password are written first and then the upper 32 bits of
the password are written. For the x16 data bus configuration, the lower address A0:A-1= 00, the next Password Unlock command is to A0:A -1 = 01, then to
A0:A-1= 10, and finally to A0:A-1= 11. Writing out of sequence results in the Password Unlock not returning a
match with the password and the PPB Lock Bit remains set.
Once the Password Unlock command is entered, the
RDY/BSY# pin goes LOW indicating that the device is
busy. Also, reading the small bank (25% bank) results
in the DQ6 pin toggling, indicating that the Password
Unlock function is in progress. Reading the large bank
(75% bank) returns actual array data. Approximately
1uSec is required for each portion of the unlock. Once
the first portion of the password unlock completes
(RDY/BSY# is not driven and DQ6 does not toggle
when read), the Password Unlock command is issued
again, only this time with the next part of the password. If WORD# = 1, the second Password Unlock
command is the final command before the PPB Lock
Bit is cleared (assuming a valid password). If WORD#
= 0, this is the fourth Password Unlock command. In
x16 mode, four Password Unlock commands are required to successfully clear the PPB Lock Bit. As with
the first Password Unlock command, the RY/BY# signal goes LOW and reading the device results in the
DQ6 pin toggling on successive read operations until
complete. It is the responsibility of the microprocessor
to keep track of the number of Password Unlock commands (2 for x32 bus and 4 for x16 bus), the order,
and when to read the PPB Lock bit to confirm successful password unlock
The Password Unlock command is permitted if the
SecSi sector is enabled.
The All PPB Erase command is used to erase all
PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the
PPB erase command is written (60h) and A6 = 1, all
Sector PPBs are erased in parallel. If the PPB Lock Bit
is set the ALL PPB Erase command will not execute
and the command will time-out without erasing the
PPBs. The host system must determine whether all
PPB has been fully erased by noting the status of DQ0
in the sixth cycle of the All PPB Erase command. If
DQ0 = 1, the entire six-cycle All PPB Erase command
sequence must be reissued until DQ0 = 1.
It is the responsibility of the user to preprogram all
PPBs prior to issuing the All PPB Erase command. If
the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB
at a later time. Also note that the total number of PPB
program/erase cycles is limited to 100 cycles. Cycling
the PPBs beyond 100 cycles is not guaranteed.
The All PPB Erase command is permitted if the SecSi
sector is enabled.
DYB Write
The DYB Write command is used for setting the DYB,
which is a volatile bit that is cleared at reset. There is
one DYB per sector. If the PPB is set, the sector is
protected regardless of the value of the DYB. If the
PPB is cleared, setting the DYB to a 1 protects the
sector from programs or erases. Since this is a volatile
bit, removing power or resetting the device will clear
the DYBs. The bank address is latched when the command is written.
The DYB Write command is permitted if the SecSi
sector is enabled.
PPB Lock Bit Set
PPB Program Command
The PPB Program command is used to program, or
set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs).
The specific sector address (A18–A11) are written at
the same time as the program command 60h with A6
= 0. If the PPB Lock Bit is set and the corresponding
PPB is set for the sector, the PPB Program command
will not execute and the command will time-out without
programming the PPB.
The host system must determine whether a PPB has
been fully programmed by noting the status of DQ0 in
the sixth cycle of the PPB Program command. If DQ0
= 0, the entire six-cycle PPB Program command sequence must be reissued until DQ0 = 1.
June 7, 2006
All PPB Erase Command
The PPB Lock Bit set command is used for setting the
DYB, which is a volatile bit that is cleared at reset.
There is one DYB per sector. If the PPB is set, the
sector is protected regardless of the value of the DYB.
If the PPB is cleared, setting the DYB to a 1 protects
the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will
clear the DYBs. The bank address is latched when the
command is written.
The PPB Lock command is permitted if the SecSi sector is enabled.
DYB Status
The programming of the DYB for a given sector can be
verified by writing a DYB status verify command to the
device.
Am29BDD160G
43
PPB Status
The programming of the PPB for a given sector can be
verified by writing a PPB status verify command to the
device.
PPB Lock Bit Status
The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status
verify command to the device.
Non-volatile Protection Bit Program And
Erase Flow
The device uses a standard command sequence for
programming or erasing the SecSi Sector Protection,
Password Locking, Persistent Sector Protection Mode
Locking, or Persistent Protection Bits. Unlike devices
that have the Single High Voltage Sector Unprotect/Protect feature, the Am29BDD160 has the standard two-cycle unlock followed by 60h, which places
the device into non-volatile bit program or erase mode.
Once the mode is entered, the specific non-volatile bit
44
status is read on DQ0. Figure 4 shows a typical flow
for programming the non-volatile bit and Figure 5
shows a typical flow for erasing the non-volatile bits.
The SecSi Sector Protection, Password Locking, Persistent Sector Protection Mode Locking bits are not
erasable after they are programmed. However, the
PPBs are both erasable and programmable (depending upon device security).
Unlike Single High Voltage Sector Protect/Unprotect,
the A6 pin no longer functions as the program/erase
selector nor the program/erase margin enable. Instead, this function is accomplished by issuing the
specific command for either program (68h) or erase
(60h).
In asynchronous mode, the DQ6 toggle bit indicates
whether the program or erase sequence is active. (In
synchronous mode, ADV# indicates the status.) If the
DQ6 toggle bit toggles with either OE# or CE#, the
non-volatile bit program or erase operation is in
progress. When DQ6 stops toggling, the value of the
non-volatile bit is available on DQ0.
Am29BDD160G
June 7, 2006
Command (Notes)
Read (5)
Reset (6)
Memory Array Command Definitions (x32 Mode)
Cycles
Table 19.
Bus Cycles (Notes 1–4)
First
Second
Addr Data Addr Data
1
RA
Third
Fourth
Addr
Data
Addr
Fifth
Data
Sixth
Addr
Data
(BA)X0E
08
Addr
Data
RD
1
XXX
F0
Manufacturer ID
4
555
AA
2AA
55
555
90
(BA)X00
01
Device ID (11)
6
555
AA
2AA
55
555
90
(BA)X01
7E
Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Program/Erase Suspend (12)
1
BA
B0
30
Autoselect
(7)
Program/Erase Resume (13)
1
BA
CFI Query (14, 15)
1
55
98
Accelerated Program (16)
2
XX
A0
PA
PD
Configuration Register Verify (15)
3
555
AA
2AA
55
(BA)555
C6
(BA)XX
RD
Configuration Register Write (17)
4
555
AA
2AA
55
555
D0
XX
WD
Unlock Bypass Entry (18)
3
555
AA
2AA
55
555
20
Unlock Bypass Program (18)
2
XX
A0
PA
PD
XX
10
XX
00
Unlock Bypass Erase (18)
2
XX
80
Unlock Bypass CFI (14, 18)
1
XX
98
Unlock Bypass Reset (18)
2
XX
90
Legend:
BA = Address of the bank that is being switched to autoselect mode,
is in bypass mode, or is being erased. Determined by A18 and A17,
see Tables 11 and 12 for more detail.
PA = Program Address (A18:A0). Addresses latch on the falling edge
of the WE# or CE# pulse, whichever happens later.
PD = Program Data (DQ31:DQ0) written to location PA. Data latches
on the rising edge of WE# or CE# pulse, whichever happens first.
(BA)X0F 00/01
RA = Read Address (A18:A0).
RD = Read Data (DQ31:DQ0) from location RA.
SA = Sector Address (A18:A11) for verifying (in autoselect mode),
erasing, or applying security commands.
WD = Write Data. See “Configuration Register” definition for specific
write data. Data latched on rising edge of WE#.
X = Don’t care
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
9.
3.
Shaded cells in table denote read cycles. All other cycles are
write operations.
10. Valid read operations include asynchronous and burst read mode
operations.
4.
During unlock cycles, (lower address bits are 555 or 2AAh as
shown in table) address bits higher than A11 (except where BA is
required) and data bits higher than DQ7 are don’t cares.
11. The device ID must be read across the fourth, fifth, and sixth
cycles. 00h in the sixth cycle indicates top boot block, 01h
indicates bottom boot block.
5.
No unlock or command cycles required when bank is reading
array data.
6.
The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high (while
the bank is providing status information).
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Program/Erase Suspend
mode. The Program/Erase Suspend command is valid only
during a sector erase operation, and requires the bank address.
7.
8.
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID or device ID information. See the Autoselect
Command section for more information.
This command cannot be executed until The Unlock Bypass
command must be executed before writing this command
sequence. The Unlock Bypass Reset command must be
executed to return to normal operation.
June 7, 2006
This command is ignored during any embedded program, erase
or suspended operation.
13. The Program/Erase Resume command is valid only during the
Erase Suspend mode, and requires the bank address.
14. Command is valid when device is ready to read array data or
when device is in autoselect mode.
15. Asynchronous read operations.
16. ACC must be at VID during the entire operation of this command.
17. Command is ignored during any Embedded Program, Embedded
Erase, or Suspend operation.
18. The Unlock Bypass Entry command is required prior to any
Unlock Bypass operation. The Unlock Bypass Reset command is
required to return to the read mode.
Am29BDD160G
45
Command (Notes)
Reset
Sector Protection Command Definitions (x32 Mode)
Bus Cycles (Notes 1-4)
Cycles
Table 20.
Addr Data Addr Data
1
XXX
First
Second
Third
Addr
Fourth
Data
Addr
Fifth
Data
Sixth
Addr
Data
Addr
Data
OW
48
OW
RD(0)
F0
SecSi Sector Entry
3
555
AA
2AA
55
555
88
SecSi Sector Exit
4
555
AA
2AA
55
555
90
XX
00
SecSi Protection Bit Program (5, 6)
6
555
AA
2AA
55
555
60
OW
68
SecSi Protection Bit Status
6
555
AA
2AA
55
555
60
OW
RD(0)
Password Program (5, 7, 8)
4
555
AA
2AA
55
555
38
PWA[0-1] PWD[0-1]
Password Verify
4
555
AA
2AA
55
555
C8
PWA[0-1] PWD[0-1]
Password Unlock (7, 8)
5
555
AA
2AA
55
555
28
PWA[0-1] PWD[0-1]
PPB Program (5, 6)
6
555
AA
2AA
55
555
60
(SA)WP
68
(SA)WP
48
(SA)WP RD(0)
All PPB Erase (5, 9, 10)
6
555
AA
2AA
55
555
60
WP
60
(SA)WP
40
(SA)WP RD(0)
PPB Status (11, 12)
4
555
AA
2AA
55
555
90
(SA)X02
00/01
78
RD(1)
PL
48
PL
RD(0)
SL
48
SL
RD(0)
PPB Lock Bit Set
3
555
AA
2AA
55
555
PPB Lock Bit Status
4
555
AA
2AA
55
(BA) 555
58
SA
DYB Write (7)
4
555
AA
2AA
55
555
48
SA
X1
DYB Erase (7)
4
555
AA
2AA
55
555
48
SA
X0
RD(0)
DYB Status (12)
4
555
AA
2AA
55
(BA) 555
58
SA
PPMLB Program (5,6)
6
555
AA
2AA
55
555
60
PL
68
PPMLB Status (5)
6
555
AA
2AA
55
555
60
PL
RD(0)
SPMLB Program (5, 6)
6
555
AA
2AA
55
555
60
SL
68
SPMLB Status (5)
6
555
AA
2AA
55
555
60
SL
RD(0)
DYB = Dynamic Protection Bit
OW = Address (A5–A0) is (011X10).
PPB = Persistent Protection Bit
PWA = Password Address. A0 selects between the low and high
32-bit portions of the 64-bit Password
PWD = Password Data. Must be written over two cycles.
PL = Password Protection Mode Lock Address (A5–A0) is (001X10)
RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0= 1,
if unprotected, DQ0 = 0.
RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 =
1, if unprotected, DQ1 = 0.
SA = Sector Address where security command applies. Address bits
A18:A11 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10)
WP = PPB Address (A5–A0) is (111X10)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
1.
7.
Data is latched on the rising edge of WE#.
8.
The entire four bus-cycle sequence must be entered for each
portion of the password.
9.
The fourth cycle erases all PPBs. The fifth and sixth cycles are
used to validate whether the bits have been fully erased. If DQ0
(in the sixth cycle) reads 1, the erase command must be issued
and verified again.
2.
See Table 1 for description of bus operations.
All values are in hexadecimal.
3.
Shaded cells in table denote read cycles. All other cycles are
write operations.
4.
During unlock cycles, (lower address bits are 555 or 2AAh as
shown in table) address bits higher than A11 (except where BA is
required) and data bits higher than DQ7 are don’t cares.
5.
The reset command returns the device to reading the array.
6.
The fourth cycle programs the addressed locking bit. The fifth and
sixth cycles are used to validate whether the bit has been fully
programmed. If DQ0 (in the sixth cycle) reads 0, the program
command must be issued and verified again.
46
10. Before issuing the erase command, all PPBs should be
programmed in order to prevent over-erasure of PPBs.
11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not
set.
12. The status of additional PPBs and DYBs may be read (following
the fourth cycle) without reissuing the entire command sequence.
Am29BDD160G
June 7, 2006
Command (Notes)
Read (5)
Cycles
Table 21.
1
Reset (6)
Memory Array Command Definitions (x16 Mode)
Bus Cycles (Notes 1–4)
First
Second
Addr Data Addr Data
RA
Third
Fourth
Addr
Data
Addr
Fifth
Data
Sixth
Addr
Data
(BA)X1C
08
Addr
Data
RD
1
XXX
F0
Manufacturer ID
4
AAA
AA
555
55
AAA
90
(BA)X00
01
Device ID (11)
6
AAA
AA
555
55
AAA
90
(BA)X02
7E
Program
4
AAA
AA
555
55
AAA
A0
PA
PD
Chip Erase
6
AAA
AA
555
55
AAA
80
AAA
AA
555
55
555
10
Sector Erase
6
AAA
AA
555
55
AAA
80
AAA
AA
555
55
SA
30
Program/Erase Suspend (12)
1
BA
B0
Program/Erase Resume (13)
1
BA
30
CFI Query (14, 15)
1
AA
98
Accelerated Program (16)
2
XX
A0
PA
PD
Configuration Register Verify (15)
3
AAA
AA
555
55
(BA)555
C6
(BA)XX
RD
Configuration Register Write (17)
4
AAA
AA
555
55
AAA
D0
XX
WD
Unlock Bypass Entry (18)
3
AAA
AA
555
55
AAA
20
Unlock Bypass Program (18)
2
XX
A0
PA
PD
XX
10
XX
00
Autoselect
(7)
Unlock Bypass Erase (18)
2
XX
80
Unlock Bypass CFI (14, 18)
1
XX
98
Unlock Bypass Reset (18)
2
XX
90
(BA)X1E 00/01
Legend:
BA = Address of the bank that is being switched to autoselect mode,
is in bypass mode, or is being erased. Determined by A18 and A17,
see Tables 11 and 12 for more detail.
PA = Program Address (A18:A-1). Addresses latch on the falling edge
of the WE# or CE# pulse, whichever happens later.
PD = Program Data (DQ15:DQ0) written to location PA. Data latches
on the rising edge of WE# or CE# pulse, whichever happens first.
RA = Read Address (A18:A-1).
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (A18:A11) for verifying (in autoselect mode),
erasing, or applying security commands.
WD = Write Data. See “Configuration Register” definition for specific
write data. Data latched on rising edge of WE#.
X = Don’t care
Notes:
1. See Table 1 for description of bus operations.
9.
This command is ignored during any embedded program, erase
or suspended operation.
2.
All values are in hexadecimal.
3.
Shaded cells in table denote read cycles. All other cycles are
write operations.
10. Valid read operations include asynchronous and burst read mode
operations.
4.
During unlock cycles, (lower address bits are AAA or 555h as
shown in table) address bits higher than A11 (except where BA is
required) and data bits higher than DQ7 are don’t cares.
11. The device ID must be read across the fourth, fifth, and sixth
cycles. 00h in the sixth cycle indicates top boot block, 01h
indicates bottom boot block.
5.
No unlock or command cycles required when bank is reading
array data.
6.
The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high (while
the bank is providing status information).
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Program/Erase Suspend
mode. The Program/Erase Suspend command is valid only
during a sector erase operation, and requires the bank address.
7.
8.
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID or device ID information. See the Autoselect
Command section for more information.
This command cannot be executed until The Unlock Bypass
command must be executed before writing this command
sequence. The Unlock Bypass Reset command must be
executed to return to normal operation.
June 7, 2006
13. The Program/Erase Resume command is valid only during the
Erase Suspend mode, and requires the bank address.
14. Command is valid when device is ready to read array data or
when device is in autoselect mode.
15. Asynchronous read operations.
16. ACC must be at VID during the entire operation of this command.
17. Command is ignored during any Embedded Program, Embedded
Erase, or Suspend operation.
18. The Unlock Bypass Entry command is required prior to any
Unlock Bypass operation. The Unlock Bypass Reset command is
required to return to the read mode.
Am29BDD160G
47
Table 22.
Sector Protection Command Definitions (x16 Mode)
Cycles
Bus Cycles (Notes 1-4)
Addr Data Addr Data
Reset
1
XXX
F0
SecSi Sector Entry
3
AAA
AA
555
55
AAA
88
SecSi Sector Exit
4
AAA
AA
555
55
AAA
90
XX
00
SecSi Protection Bit Program
(5, 6)
6
AAA
AA
555
55
AAA
60
OW
68
SecSi Protection Bit Status
6
AAA
AA
555
55
AAA
60
OW
RD(0)
Password Program (5, 7, 8)
5
AAA
AA
555
55
AAA
38
PWA[0–3] PWD[0–3]
Command (Notes)
First
Second
Third
Fourth
Addr
Data
Fifth
Addr
Data
Sixth
Addr
Data
Addr
Data
OW
48
OW
RD(0)
Password Verify
4
AAA
AA
555
55
AAA
C8
PWA[0–3] PWD[0–3]
Password Unlock (7, 8)
5
AAA
AA
555
55
AAA
28
PWA[0–3] PWD[0–3]
PPB Program (5, 6)
6
AAA
AA
555
55
AAA
60
(SA)WP
68
(SA)WP
48
(SA)WP RD(0)
All PPB Erase (5, 9, 10)
6
AAA
AA
555
55
AAA
60
WP
60
(SA)WP
40
(SA)WP RD(0)
PPB Status (11, 12)
4
AAA
AA
555
55
AAA
90
(SA)X04
00/01
PL
48
PL
RD(0)
SL
48
SL
RD(0)
PPB Lock Bit Set
3
AAA
AA
555
55
AAA
78
PPB Lock Bit Status
4
AAA
AA
555
55
(BA) AAA
58
SA
RD(1)
DYB Write (7)
4
AAA
AA
555
55
AAA
48
SA
X1
DYB Erase (7)
4
AAA
AA
555
55
AAA
48
SA
X0
DYB Status (12)
4
AAA
AA
555
55
(BA) AAA
58
SA
RD(0)
PPMLB Program (5, 6)
6
AAA
AA
555
55
AAA
60
PL
68
PPMLB Status (5)
6
AAA
AA
555
55
AAA
60
PL
RD(0)
SPMLB Program (5, 6)
6
AAA
AA
555
55
AAA
60
SL
68
SPMLB Status (5)
6
AAA
AA
555
55
AAA
60
SL
RD(0)
Legend:
DYB = Dynamic Protection Bit
OW = Address (A5–A0) is (011X10).
PD3:0 = Four 32-bit quantities representing the password.
PPB = Persistent Protection Bit
PWA = Password Address. A0:A-1 selects between the low and high
16-bit portions of the 64-bit Password
PWD = Password Data.Must be written over four cycles.
PL = Password Protection Mode Lock Address (A5-A0) is (001X10)
RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0 =
1, if unprotected, DQ0 = 0.
RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 =
1, if unprotected, DQ1 = 0.
SA = Sector Address where security command applies. Address bits
A18:A11 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10)
WP = PPB Address (A5–A0) is (111X10)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
1.
See Table 1 for description of bus operations.
8.
2.
All values are in hexadecimal.
3.
Shaded cells in table denote read cycles. All other cycles are
write operations.
The entire four bus-cycle sequence must be entered for each
portion of the password. PWA[0–3] represent the four addresses
over which the password is stored. PWD[0–3] represent the four
word data that comprise the password.
4.
During unlock cycles, (lower address bits are AAA or 555h as
shown in table) address bits higher than A11 (except where BA is
required) and data bits higher than DQ7 are don’t cares.
9.
The fourth cycle erases all PPBs. The fifth and sixth cycles are
used to validate whether the bits have been fully erased. If DQ0
(in the sixth cycle) reads 1, the erase command must be issued
and verified again.
5.
The reset command returns the device to reading the array.
6.
The fourth cycle programs the addressed locking bit. The fifth and
sixth cycles are used to validate whether the bit has been fully
programmed. If DQ0 (in the sixth cycle) reads 0, the program
command must be issued and verified again.
7.
48
Data is latched on the rising edge of WE#.
10. Before issuing the erase command, all PPBs should be
programmed in order to prevent over-erasure of PPBs.
11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not
set.
12. The status of additional PPBs and DYBs may be read (following
the fourth cycle) without reissuing the entire command sequence.
Am29BDD160G
June 7, 2006
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 23 and the following subsections
describe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Am29BDD160 features a Data# polling flag as a
method to indicate to the host system whether the embedded algorithms are in progress or are complete.
During the Embedded Program Algorithm an attempt
to read the bank in which programming was initiated
will produce the complement of the data last written to
DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the
true last data written to DQ7. Note that DATA# polling
returns invalid data for the address being programmed
or erased.
For example, the data read for an address programmed as 0000 0000 1000 0000b will return XXXX
XXXX 0XXX XXXXb during an Embedded Program
operation. Once the Embedded Program Algorithm is
complete, the true data is read back on DQ7. Note that
at the instant when DQ7 switches to true data, the
other bits may not yet be true. However, they will all be
true data on the next read from the device. Please
note that Data# polling may give misleading status
when an attempt is made to write to a protected sector.
For chip erase, the Data# polling flag is valid after the
rising edge of the sixth WE# pulse in the six write
pulse sequence. For sector erase, the Data# polling is
valid after the last rising edge of the sector erase WE#
pulse. Data# polling must be performed at sector addresses within any of the sectors being erased and not
a sector that is a protected sector. Otherwise, the status may not be valid. DQ7 = 0 during an Embedded
Erase Algorithm (chip erase or sector erase operation)
but will return a “1” after the operation completes because it will have dropped back into read mode.
In asynchronous mode, just prior to the completion of
the Embedded Algorithm operations, DQ7 may
change asynchronously while OE# is asserted low. (In
synchronous mode, ADV# exhibits this behavior.) The
status information may be invalid during the instance
of transition from status information to array (memory)
data. An extra validity check is therefore specified in
the data polling algorithm. The valid array data on
DQ31–DQ0 (DQ15–DQ0 when WORD# = 0) is available for reading on the next successive read attempt.
gorithm, Erase Suspend, Erase Suspend-Program
mode, or sector erase time-out.
If the user attempts to write to a protected sector,
Data# polling will be activated for about 1 µs: the device will then return to read mode, with the data from
the protected sector unchanged. If the user attempts
to erase a protected sector, Toggle Bit (DQ6) will be
activated for about 150 µs; the device will then return
to read mode, without having erased the protected
sector.
Table 23 shows the outputs for Data# Polling on DQ7.
Figure 6 shows the Data# Polling algorithm. Figure 27
shows the timing diagram for synchronous status DQ7
data polling.
RY/BY#: Ready/Busy#
The device provides a RY/BY# open drain output pin as
a way to indicate to the host system that the Embedded
Algorithms are either in progress or have been completed. If the output is low, the device is busy with either
a program, erase, or reset operation. If the output is
floating, the device is ready to accept any read/write or
erase operation. When the RY/BY# pin is low, the device will not accept any additional program or erase
commands with the exception of the Erase suspend
command. If the device has entered Erase Suspend
mode, the RY/BY# output will be floating. For programming, the RY/BY# is valid (RY/BY# = 0) after the rising
edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the RY/BY# is valid after the
rising edge of the sixth WE# pulse in the six write pulse
sequence. For sector erase, the RY/BY# is also valid
after the rising edge of the sixth WE# pulse.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the
reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “floating”), the reset operation is completed in a time of tREADY (not during Embedded Algorithms). The system can read data t RH after the
RESET# pin returns to VIH.
Since the RY/BY# pin is an open-drain output, several
RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC. An external pull-up resistor is required to take RY/BY# to a VIH level since the output is
an open drain.
Table 23 shows the outputs for RY/BY#. Figures 15, 19,
21 and 22 shows RY/BY# for read, reset, program, and
erase operations, respectively.
The Data# polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Al-
June 7, 2006
Am29BDD160G
49
During an Embedded Program or Erase algorithm operation, two immediately consecutive read cycles to
any address cause DQ6 to toggle. When the operation
is complete, DQ6 stops toggling. For asynchronous
mode, either OE# or CE# can be used to control the
read cycles. For synchronous mode, the rising edge of
ADV# is used or the rising edge of clock while ADV# is
Low.
START
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
Yes
No
No
Read DQ7–DQ0
Addr = VA
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Polling).
DQ7 = Data?
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ5 = 1?
Yes
Yes
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program algorithm is complete.
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Table 23 shows the outputs for Toggle Bit I on DQ6.
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section Reading Toggle Bits DQ6/DQ2
explains the algorithm. Figure 25 in the AC Characteristics section shows the toggle bit timing diagrams. Figure 25 shows the differences between DQ2 and DQ6 in
graphical form. See also the subsection on DQ2: Toggle Bit II. Figure 27 shows the timing diagram for synchronous toggle bit status.
DQ2: Toggle Bit II
Figure 6. Data# Polling Algorithm
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase operation), and during the sector erase time-out.
50
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system performs two immediately consecutive reads at addresses within those sectors that have been selected for erasure. (For
asynchronous mode, either OE# or CE# can be used
to control the read cycles. For synchronous mode,
ADV# is used.) But DQ2 cannot distinguish whether
Am29BDD160G
June 7, 2006
the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and mode
information. Refer to Table 23 to compare outputs for
DQ2 and DQ6.
START
Read Byte
(DQ0-DQ7)
Address = VA
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section Reading Toggle Bits DQ6/DQ2
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 25 shows the toggle bit timing diagram. Figure 25 shows the differences between DQ2
and DQ6 in graphical form. Figure 27 shows the timing
diagram for synchronous DQ2 toggle bit status.
Read Byte
(DQ0-DQ7)
Address = VA
DQ6 = Toggle?
(Note 1)
No
Reading Toggle Bits DQ6/DQ2
Refer to Figure 25 for the following discussion. Whenever the system initially begins reading toggle bit status, it must perform two immediately consecutive
reads of DQ7–DQ0 to determine whether a toggle bit
is toggling. Typically, the system would note and store
the value of the toggle bit after the first read. After the
second read, the system would compare the new
value of the toggle bit with the first. If the toggle bit is
not toggling, the device has completed the program or
erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
However, if after the initial two immediately consecutive
read cycles, the system determines that the toggle bit
is still toggling, the system also should note whether
the value of DQ5 is high (see the section on DQ5). If it
is, the system should then determine again whether the
toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle bit
is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation
successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 7).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
June 7, 2006
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ 0-DQ7)
Adrdess = VA
DQ6 = Toggle?
(Notes
1, 2)
No
Yes
FAIL
PASS
Notes:
1. Read toggle bit with two immediately consecutive reads
to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 7. Toggle Bit Algorithm
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
Am29BDD160G
51
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from “0”
to “1.” The system may ignore DQ3 if the system can
guarantee that the time between additional sector
erase commands will always be less than 50 µs. See
also the Sector Erase Command section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been accepted. Table 23 shows the outputs for DQ3.
Table 23. Write Operation Status
Operation
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See DQ5: Exceeded Timing Limits for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
52
Am29BDD160G
June 7, 2006
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
20 ns
VCC , VIO (Note 1) . . . . . . . . . . . . . . . . –0.5 V to +3.0 V
ACC, A9, OE#,
and RESET# (Note 2) . . . . . . . . . . . –0.5 V to +13.0 V
Address, Data, Control Signals
(with the exception of CLK (Note 1) . . –0.5 V to +3.6 V
20 ns
+0.8 V
–0.5 V
–0.7 V
All other pins (Note 1) . . . . . . . . . . . . –0.5 V to +5.5 V
20 ns
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Figure 8. Maximum Negative
Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may overshoot VSS to
–0.7 V for periods of up to 20 ns. See Figure 8. Maximum
DC voltage on input or I/O pins is VCC +0.5 V. During
voltage transitions, input or I/O pins may overshoot to VCC
+0.7 V for periods up to 20 ns. See Figure 9.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot VSS to –0.7 V for periods of up to
20 ns. See Figure 8. Maximum DC input voltage on pin A9
is +13.0 V which may overshoot to 14.0 V for periods up
to 20 ns. See Figure 9.
20 ns
VCC+0.7 V
VCC+0.5 V
–0.7 V
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
4. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
20 ns
20 ns
Figure 9. Maximum Positive
Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –40°C to +125°C
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . . 2.5 V to 2.75 V
VIO Supply Voltages
VIO for all devices . . . . . . . . . . . . . . . . 1.65 V to 2.75 V
Note: Operating ranges define those limits between which
the functionality of the device is guaranteed.
June 7, 2006
Am29BDD160G
53
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
Input Load Current
VIN = VSS to VIO, VIO = VIO max
±1.0
µA
ILIWP
Input Load Current, WP#
VIN = VSS to VIO, VIO = VIO max
–25
µA
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC max
±1.0
µA
ICCB
VCC Active Burst Read Current
(Note 1)
CE# = VIL,
OE# = VIL
90
mA
ICC1
VCC Active Asynchronous Read Current
(Note 1)
CE# = VIL, OE# = VIL
4
mA
ICC3
VCC Active Program Current (Notes 2, 4) CE# = VIL, OE# = VIH, ACC = VIH
40
50
mA
ICC4
VCC Active Erase Current (Notes 2, 4)
CE# = VIL, OE# = VIH, ACC = VIH
20
50
mA
VCC Standby Current (CMOS)
VCC= VCC max, CE# = VCC ± 0.3 V
60
µA
VCC Active Current (Read While Write)
CE# = VIL, OE# = VIL
90
mA
ICC7 (Note 5)
VCC Reset Current
RESET# = VIL
60
µA
ICC8 (Note 5)
Automatic Sleep Mode Current
VIH = VCC ± 0.3 V, VIL = VSS ± 0.3 V
60
µA
IACC
VACC Acceleration Current
ACC = VHH
20
mA
VIL
Input Low Voltage
–0.5
0.3 x VIO
V
VIH
Input High Voltage
0.7 x VIO
3.6
V
–0.2
0.3 x VIO
V
ILI
ICC5 (Note 5)
ICC6
VILCLK
CLK Input Low Voltage
VIHCLK
CLK Input High Voltage
56 MHz
8 Double-Word
70
66 MHz
VID
Voltage for Autoselect
VCC = 2.5 V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
IOLRB
RY/BY#, Output Low Current
VOL = 0.4 V
VHH
Accelerated (ACC pin) High Voltage
VOH
Output High Voltage
VLKO
Low VCC Lock-Out Voltage (Note 3)
1 MHz
30
0.7 x VCC
2.75
V
11.5
12.5
V
0.45
V
8
mA
IOH = –2.0 mA, VCC = VCC min
0.85 x VCC
V
IOH = –100 µA, VCC = VCC min
VIO –0.1
V
1.6
2.0
V
Notes:
1. The ICC current listed includes both the DC operating current and the frequency dependent component.
2.
ICC active while Embedded Erase or Embedded Program is in progress.
3.
Not 100% tested.
4.
Maximum ICC specifications are tested with VCC = VCCmax.
5.
Current maximum has been increased significantly from datasheet Revision B+4, Dated April 8, 2003.
54
Am29BDD160G
June 7, 2006
DC CHARACTERISTICS (Continued)
Zero Power Flash
Supply Current in mA
5
4
3
2
1
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 10.
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
20
2.7 V
Supply Current in mA
16
12
8
4
0
1
2
3
4
5
Frequency in MHz
Note: T = -40 °C
Figure 11.
June 7, 2006
Typical ICC1 vs. Frequency
Am29BDD160G
55
TEST CONDITIONS
Table 24. Test Specifications
54D,
64C
Test Condition
Device
Under
Test
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
CL
65A
30
Input Rise and Fall Times
100
pF
5
ns
0.0 V – VIO
V
Input timing measurement
reference levels
VIO/2
V
Output timing measurement
reference levels
VIO/2
V
Input Pulse Levels
Note: Diodes are IN3064 or equivalent
Figure 12.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
KS000010-PAL
SWITCHING WAVEFORMS
VIO
Input
VIO/2 V
Measurement Level
VIO/2 V
Output
VSS
Figure 13. Input Waveforms and Measurement Levels
56
Am29BDD160G
June 7, 2006
AC CHARACTERISTICS
VCC and VIO Power-up
Parameter
Description
Test Setup
Speed
Unit
tVCS
VCC Setup Time
Min
50
µs
tVIOS
VIO Setup Time
Min
50
µs
tRSTH
RESET# Low Hold Time
Min
50
µs
Figure 14.
VCC and VIO Power-up Diagram
tVCS
VCC
tVIOS
VIOP
tRSTH
RESET#
June 7, 2006
Am29BDD160G
57
AC CHARACTERISTICS
Asynchronous Read Operations
Parameter
Speed Options
JEDEC
Std.
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
Output Enable to Output Delay
Max
tEHQZ
tDF
Chip Enable to Output High Z
(Note 1)
Max
10
ns
Min
2
ns
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
10
ns
Read
Min
0
ns
tOEH
Output Enable
Hold Time (Note 1)
Toggle and
Data# Polling
Min
10
ns
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
Min
2
ns
tAXQX
Description
Test Setup
54D
64C
65A
Unit
Max
54
64
67
ns
CE# = VIL
OE# = VIL
Max
54
64
67
ns
OE# = VIL
Max
58
69
71
ns
28
ns
20
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 24 for test specifications
58
Am29BDD160G
June 7, 2006
AC CHARACTERISTICS
Burst Mode Read
Parameter
JEDEC
Speed Options
Std.
Description
54D
64C
65A
Unit
tIACC
Asynchronous Access Time ADV# Valid Clock
to Output Delay (See Note)
Max
54
64
67
ns
tBACC
Burst Access Time Valid Clock to Output Delay
Max
9 FBGA 9.5
PQFP
10 FBGA 10
PQFP
17
ns
tADVCS
ADV# Setup Time to Rising (Falling) Edge of
CLK
Min
4
5
7
ns
tADVCH
ADV# Hold Time
Min
tADVP
ADV# Pulse Width
Min
tBDH
Data Hold Time from Next Clock Cycle
Max
tDVCH
Valid Data Hold from CLK
Min
2
3
3
ns
tDIND
CLK to Valid IND/WAIT#
Max
9 FBGA 9.5
PQFP
10 FBGA 10
PQFP
17
ns
tINDH
IND/WAIT# Hold from CLK
Min
2
3
3
ns
tIACC
CLK to Valid Data Out, Initial Burst Access
Max
54
60
68
ns
Min
15
18
25
tCLK
CLK Period
tCR
2
15
ns
15
18
4
ns
ns
ns
Max
60
CLK Rise Time
Max
3
ns
tCF
CLK Fall Time
Max
3
ns
tCH
CLK High Time
Min
2.5
2.5
3
ns
tCL
CLK Low Time
Min
2.5
2.5
3
ns
tCH
CE# Hold Time
Min
3
tACS
Address Setup Time to CLK (See Note)
Min
5
6
7
ns
tACH
Address Hold Time from ADV# Rising Edge
(See Note)
Min
1
2
2
ns
tOE
Output Enable to Output Valid
Max
tDF
tOEZ
Output Enable to Output High Z
tEHQZ
tCEZ
tCES
ns
20
ns
Min
2
3
3
Max
10
15
17
Chip Enable to Output High Z
Max
10
15
17
ns
CE# Setup Time to Clock
Min
4
5
6
ns
ns
Note: See Product Selector Guide for minimum initial clock delay prior to initial valid data. tIACC may also be calculated using the
following formula: tIACC = (clock delays) x (clock period) + tBACC.
June 7, 2006
Am29BDD160G
59
AC CHARACTERISTICS
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 15. Conventional Read Operations Timings
tCEZ
tCES
CE#
CLK
tADVCS
ADV#
tADVCH
tACS
A0: A18
Aa
tBDH
tACH
tBACC
DQ0: DQ31
tIACC
Da
Da + 1
Da + 2
Da + 3
tOE
Da + 31
tOEZ
OE#*
IND#
Figure 16.
60
Burst Mode Read (x32 Mode)
Am29BDD160G
June 7, 2006
AC CHARACTERISTICS
CLK
ADV#
CE#
tCS
tCH
Stable Address
A18-A0
tWC
DQ31-DQ0
Valid Data
tAH
tAS
tDH
tDS
WE#
tOEH
OE#
tWPH
IND/WAIT#
Figure 17. Asynchronous Command Write Timing
Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the
READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are
burst mode when the burst mode option is enabled in the Configuration Register.
CE#
tCES
CLK
tADVCS
tADVP
ADV#
tACS
tACH
ttACS
AS
A18-A0,
WORD#
Valid Address
tADVCH
DQ31-DQ0
WE#
tWC
tEHQZ
Data In
tWADVH
OE#
tACH
Valid Address
tDS
Data Out
tDF
tWCKS
tOE
tDH
tWP
10 ns
IND/WAIT#
Figure 18. Synchronous Command Write/Read Timing
Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the
READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are
burst mode when the burst mode option is enabled in the Configuration Register.
June 7, 2006
Am29BDD160G
61
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
Test Setup
All Speed Options
Unit
tREADY
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
Max
11
µs
tREADY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
RESET# High Time Before Read (See
Note)
Min
50
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
RESET# Active for Bank NOT Executing
Embedded Algorithm
Max
500
ns
RESET# High Time before Read
Max
50
ns
tREADY
RESET# Active for Bank Executing
Embedded Algorithm
Max
11
µs
tDRNE
RESET# Delay to Read Mode During
Normal Erase
Max
7
µs
tRMX
RESET# Delay to Read Mode if RESET# is
held active for maximum delay (see
previous two parameters)
Max
50
ns
tREADY
tRH
Note: Not 100% tested.
62
Am29BDD160G
June 7, 2006
AC CHARACTERISTICS
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timing to Bank NOT Executing Embedded Algorithm
Reset Timing to Bank Executing Embedded Algorithm
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 19. RESET# Timings
Program/Erase Command
DQ31-DQ0
tDS
tDH
tWP
WE#
tWPWS
Valid WP#
WP#
tCH
tWPRH
RY/BY#
Figure 20.
June 7, 2006
WP# Timing
Am29BDD160G
63
AC CHARACTERISTICS
Erase/Program Operations
Parameter
JEDEC
Std.
Description
All Speed Options
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
60
ns
tAVWL
tAS
Address Setup Time
Min
0
ns
tWLAX
tAH
Address Hold Time
Min
25
ns
tDVWH
tDS
Data Setup to WE# Rising Edge
Min
15
ns
tWHDX
tDH
Data Hold from WE# Rising Edge
Min
2
ns
tOES
Output Enable Setup Time
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tGHWL
tGHWL
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
CE# Setup to CLK
Min
7
tWLWH
tWP
WE# Width
Min
25
ns
tWHWL
tWPH
Write Pulse Width High
Min
30
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
9
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec.
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Recovery Time from RY/BY#
Min
0
ns
tBUSY
RY/BY# Delay After WE# Rising Edge
Max
90
ns
tWPWS
WP# Setup to WE# Rising Edge with
Command
Min
20
ns
tWPRH
WP# Hold after RY/BY# Rising Edge
Max
2
ns
Notes:
1. Not 100% tested.
2. See the section for more information.
64
Am29BDD160G
June 7, 2006
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
A0h
Data
PD
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 21. Program Operation Timings
June 7, 2006
Am29BDD160G
65
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status).
Figure 22.
Addresses
Chip/Sector Erase Operation Timings
tWC
tWC
tRC
Valid PA
Valid RA
tWC
Valid PA
Valid PA
tAH
tCPH
tACC
tCE
CE#
tCP
tOE
OE#
tOEH
tWP
tGHWL
tWPH
WE#
tWPH
tDF
tDS
tOH
tDH
Data
Valid
Out
Valid
In
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Read Cycle
Figure 23.
66
CE# Controlled Write Cycles
Back-to-back Cycle Timings
Am29BDD160G
June 7, 2006
AC CHARACTERISTICS
tWC
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
Valid Data
True
High Z
Valid Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 24.
Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUSY
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 25.
June 7, 2006
Toggle Bit Timings (During Embedded Algorithms)
Am29BDD160G
67
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase
Complete
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 26. DQ2 vs. DQ6 for Erase and Erase Suspend Operations
CE#
CLK
AVD#
Addresses
VA
VA
OE#
tOE
tOE
Data
Status Data
Status Data
RDY
1.
The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,
the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one
clock cycle before data.
4. Data polling requires burst access time delay.
Figure 27. Synchronous Data Polling Timing/Toggle Bit Timings
68
Am29BDD160G
June 7, 2006
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Protect/Unprotect
Data
60h
Valid*
Verify
60h/68h**
40h/48h***
Status
Sector Protect: 150 μs
Sector Unprotect: 15 ms
1 μs
CE#
WE#
OE#
* Valid address for sector protect: A6 = 0, A1 = 1, A0 = 0. Valid address for sector unprotect:A6 = 1, A1 = 1, A0 = 0.
** Command for sector protect is 68h. Command for sector unprotect is 60h.
*** Command for sector protect verify is 48h. Command for sector unprotect verify is 40h.
Figure 28.
June 7, 2006
Sector Protect/Unprotect Timing Diagram
Am29BDD160G
69
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
JEDEC
Std.
Description
All Speed Options
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
65
ns
tAVEL
tAS
Address Setup Time
Min
0
ns
tELAX
tAH
Address Hold Time
Min
45
ns
tDVEH
tDS
Data Setup Time
Min
35
ns
tEHDX
tDH
Data Hold Time
Min
2
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
WE# Rising Edge Setup to ADV# Falling Edge
Min
5
ns
WE# Width
Min
15
ns
tWADVH
WE# Falling Edge After ADV# Falling Edge
Min
0
ns
tWCKS
WE# Rising Edge Setup to CLK Rising Edge
Min
5
ns
tWADVS
tWP
tELEH
tCP
CE# Pulse Width
Min
35
ns
tEHEL
tCPH
CE# Pulse Width High
Min
30
ns
tWHWsH1
tWHWH1
Programming Operation (Note 2)
Typ
9
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec.
Notes:
1. Not 100% tested.
2. See the section for more information.
70
Am29BDD160G
June 7, 2006
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tWH
tWPH
tAH
tWP
WE#
tGHEL
OE#
tCP
CE#
tWS
tWHWH1 or 2
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the
device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 29.
June 7, 2006
Alternate CE# Controlled Write Operation Timings
Am29BDD160G
71
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
1.0
5
s
Chip Erase Time
23
230
s
Excludes 00h programming
prior to erasure (Note 4)
Double Word Program Time
18
250
µs
Word (x16) Program Time
15
210
µs
Accelerated Double Word Program Time
8
130
µs
Accelerated Chip Program Time
5
50
s
x16
10
100
x32
12
120
Chip Program Time
(Note 3)
Excludes system level
overhead (Note 5)
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 2.5 V VCC, 1M cycles. Additionally, programming
typicals assume checkerboard pattern.
2. Under worst case conditions of 145°C, VCC = 2.5 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Tables 19 and 20 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1M cycles.
7. PPBs have a minimum program/erase cycle endurance of 100 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, ACC, and WP#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PQFP AND FORTIFIED BGA PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
72
Am29BDD160G
June 7, 2006
PHYSICAL DIMENSIONS
PQR080–80-Lead Plastic Quad Flat Package
June 7, 2006
Am29BDD160G
73
PHYSICAL DIMENSIONS
LAA 080–80-ball Fortified Ball Grid Array (13 x 11 mm)
74
Am29BDD160G
June 7, 2006
REVISION SUMMARY
Revision B (September 30, 2002)
number of delay cycles callouts. Moved start of Valid
Address cycle.
Initial public release.
Falling CLK Edge Output and Two-CLK Data Hold
Revision B+1 (October 7, 2002)
Deleted figure.
Distinctive Characteristics
Changed maximum power consumption on burst
mode read, program/erase operations, and standby
mode.
Burst Mode Read table
Changed tCES specification from 7, 8, and 9 ns to 4, 5,
and 6 ns, respectively.
DC Characteristics table
See Table 9 , Configuration Register Definitions
Modified descriptions for CR3–CR10.
See Table 16 , CFI Device Geometry Definition
Modified description of data at address 2Ch (x32
mode); added data 0003h.
DC Characteristics
Added maximum ICC6 specification.
Deleted I CC2 specification. Changed I CCB OE# test
condition from VIH to VIL. Added 1 MHz test condition
to ICC1 ; changed OE# test condition from VIH to V IL .
Changed ICC3 and I CC4 maximum values and added
typical values. Changed maximum values for I CC5 ,
ICC7, and ICC8. Added Note 4 to table.
Asynchronous Read Operations: Changed tCE specifications for 54D, 65D, 64C, and 65A speed options.
Changed tDF specifications for 65A and 90A speed options.
AC Characteristics
Revision B+4 (April 8, 2003)
Erase and Program Operations table: Replaced TBDs
for tAH and tWP with values.
Distinctive Characteristics
Erase and Programming Performance table
Replaced TBDs and existing typical and maximum values with new values.
AC Characteristics
Corrected typo in Single power supply operation.
Corrected typo in Performance characteristics.
Product Selector Guide
Updated Max Burst Access Delay for the 54D, 65D,
64C, and 80C speed options.
Revision B+2 (October 14, 2002)
Distinctive Characteristics, DC Characteristics
Changed VCC CMOS standby current to 30 mA max.
Absolute Maximum Ratings
Changed maximum rating for VCC to 3.0 V.
Global
Removed references to interleaving operations
throughout datasheet.
Table 6. 16-Bit and 32-Bit Linear and Interleaved
Burst Data Order
Revision B+3 (November 22, 2002)
Removed 2nd row for “Four Interleaved Data Transfers” and “Eight Interleaved Data Transfers”.
Product Selector Guide
Added availability note. Changed minimum initial clock
delay and maximum CE# access time on 54D, 65D,
64C, and 65A speeds. Changed maximum OE# access time on 65A and 90A speeds.
Ordering Information
Continuous Burst Read Operations, Figure 3. and
Figure 4. Wait Function During Continuous Burst
Reads at Wordline Boundary, Figure 5. and Figure
6. Odd/Even Starting address Continuous Burst
Mode Alignment
Added availability note.
Removed from datasheet.
See Table 8 , Burst Initial Access Delay
Table 9. Configuration Register Definitions
Deleted definitions and settings columns and added
initial burst access columns.
Added “Reserved” references to table.
Figure 3, Initial Burst Delay Control
Added Sector and Sector Group section.
Sector Protection
Modified drawing: Deleted arrows connecting address/data cycles. Deleted setting callouts. Changed
June 7, 2006
Am29BDD160G
75
Sector Erase and Program Suspend Operation
Mechanics
DQ7: Data# Polling, DQ6: Toggle Bit I and DQ2:
Toggle Bit II
Added bulleted section.
Added reference to Figure 27.
Absolute Maximum Ratings and Operating Ranges
Absolute Maximum Ratings
Added VIO
Added ACC reference.
Changed 1.65 V to –0.5 V
CMOS Compatible
Changed 2.3 V to 2.5 V
Corrected Max values for the ICC5, 7, and 8
CMOS Compatible
Added Note #5.
Removed “VIO” from Max column of output high voltage row.
Figure 27. Synchronous Data Polling
Timings/Toggle Bit Timing
Figure 16. Burst Mode Read (x32 mode)
Added Figure.
Corrected typos to subscripts.
Simultaneous Read/Write Operations Overview
and Restrictions
Corrected values for the tBACC and tDIND for the 54D,
65D, 64C, and 80C speed options.
Figure 17. Asynchronous Command Write Timing
Added tWC and tWPH.
Figure 18. Synchronous Command Write/ Read
Timing
Added Sections and table.
Table 7. Burst Initial Access Delay, Table 8.
Configuration Register Definitions, Table 23. Test
Specifications, Asynchronous Read Operations,
and Burst Mode Read
Added tWC and tWPH.
Removed the 65D, 80C, and 90A speed options from
tables.
Hardware Reset (RESET#)
Revision C (May 19, 2003)
Corrected tREADY max.
No revisions made, repost on web.
Figure 20. WP# Write Timing
Revision C+1 (May 29, 2003)
Added tWP.
Distinctive Characteristics
Figure 23. Back-to-back Cycle Timings
Changed the standby mode to 60 μA.
Added tWPH.
Product Selector Guide
Figure 24. Data# Polling Timings (During
Embedded Algorithms)
Changed the standard voltage range to 2.5-2.75 V
Added tWC.
Output Disable Mode
Figure 29. Alternate CE# Controlled Write
Operation Timings
Replace paragraph.
Added tWP and tWPH
Erase and Programming Performance
Removed reference to “continuous sequential” from
section.
Changed the sector erase time typical to 1.0.
Figure 3. Initial Burst Delay Control
Synchronous (Burst) Read Operation
Renumbered waveform to read two, three, four.
Revision B+5 (May 6, 2003)
Toggle Bit I
Global
Converted data sheet from Advanced Information to
Preliminary.
Added sentence to second paragraph of section.
CMOS Compatible
Ordering Information
Removed reference to continuous burst from table.
Removed some OPNs and markings.
Burst Mode Read
Automatic Sleep Mode (ASM) and Standby Mode
Changed the tIACC Max for the 65A speed option to 67
ns.
Reworded first paragraph.
76
Am29BDD160G
June 7, 2006
Figure 15. Typical ICC1 vs. Frequency
Revision D (June 30, 2003)
Renumbered Supply Current axis, removed 2.3 V
graph, and changed other graph to 2.5 V.
Global
Converted to a Preliminary Datasheet.
Figure 27. Synchronous Data Polling
Timing/Toggle Bit Timings
Revision D+1 (June 30, 2003)
Deleted line under the pulse in OE#.
Global
Revision C+2 (June 26, 2003)
Removed “Preliminary” status from data sheet.
Product Selector Guide
Distinctive Characteristics
Added Note.
Added temperature range to simultaneous read/write
operations section.
Synchronous (Burst) Read Operation,
ADV#Control In Linear Mode, and IND/WAIT#
Operation in Linear Mode
DC Characteristics
Inserted IACC field to table.
Removed feature.
Revision D2 (January 7, 2005)
Table. 7 Valid Configuration Register Bit Definition
for IND/WAIT#
Removed features.
Added note on cover page and first page of data sheet
that the Am29BDD160G has been superceded by the
Spansion S29CD016G.
Table 20. Sector Protection Command Definitions
(x32 mode)
Revision D3 (February 2, 2005)
Changed the address for OW A5-A0 to 011X10.
Ordering Information
Table 22. Sector Protection Command Definitions
(x16 mode)
Added lead free to package. Added new package
types to valid combinations.
Changed the PWA sector to A0:A-1
Revision D4 (November 4, 2005)
Figure 11. Typical ICC1 vs. Frequency
Block Diagram: Changed “DQ0-DQ15 to DQ0-DQ31”
in the block diagram.
Changed 2.5 to 2.7 and made T= 40°C
Connection Diagram: Restored labels to figure.
Burst Mode Read
Changed tBACC for 54D to 9 FBGA and 9.5 PQFP.
Absolute Maximum Ratings: Changed voltages in
vvershoot diagrams.
Changed tDIND for 54D to 9 FBGA and 9.5 PQFP and
for the 64C to 10 FBGA and 10 PQFP.
AC Characteristics, Burst Mode Read table: Deleted
parameters tDS, tDH, tAS, tAH, tCS
Figure 27. Synchronous Data Polling
Timing/Toggle Bit Timing
Revision D5 (June 7, 2006)
Global: Restored previous formatting to document.
Added note 4.
Trademarks
Copyright © 2003–2006 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
June 7, 2006
Am29BDD160G
77
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