Rohm BD4223FVM Silicon monolithic integrated circuit Datasheet

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STRUCTURE
Silicon Monolithic Integrated Circuit
PRODUCT SERIES
Strobe Charge Control IC
BD4223FVM
TYPE
Functions
1.
Built-in Low Vth DMOS 45V
2.
Adjustable transformer primary-side peak current by RADJ pin
3.
Standby mode switching with the START pin.
4.
Includes charge complete signal output (FULL) pin.
Includes charge voltage detection (VC) pin (can be set externally).
5.
Built-in thermal shutdown circuit (TSD).
6.
Built-in transformer secondary-side OPEN, SHORT protection.
7.
SOP 10pin package MSOP10 (2.9mm×4.0mm×0.9mm)
Built-in under voltage looked out (UVLO).
○ Absolute maximum ratings(Ta=25℃)
Parameter
VCC pin
SW pin
VC pin
START pin
FULL pin
IGBT_IN pin
Symbol
VCC
VSW
VC
START
FULL
IGBT_IN
Limit
-0.3 to 7
45
-0.3 to 7
-0.3 to 7
-0.3 to 7
-0.3 to 7
Unit
V
V
V
V
V
V
Operating temperature
Topr
−35 to 85
℃
Storage temperature range
Tstg
−55 to 150
℃
Tjmax
150
℃
Pd
712
mW
Junction temperature
Power dissipation
Reduced by
5.70 mW/℃ over Ta = 25℃. (When mounted on 74.2 mm  74.2 mm  1.6 mm, glass epoxy)
○ Recommended operating ranges
Parameter
VCC power supply input voltage range
VC pin input voltage range
START pin input voltage range
IGBT_IN pin input voltage range
FULL pin input voltage range
SW pin current
Symbol
VCC
VC
VSTART
VIGBT_IN
VFULL
ISW
REV. A
Limit
2.5 to 5.5
-0.3 to VCC
0 to VCC
0 to VCC
0 to 5.5
0 to 2
Unit
V
V
V
V
V
A
2/4
○ Electrical characteristics (Ta=25℃,VCC=V(START)=3.4 V, V(IGBT_IN)=0V)
Parameter
Symbol
Limit
Min.
Typ.
Max.
Unit
Conditions
[Overall device]
VCC circuit current
ICC
-
1.6
3.2
mA
Circuit current standby operation
ISTB
-
-
1
μA
VSTH
2.0
-
-
V
START=0V
[Standby control START pin]
START pin high voltage
START pin low voltage
VSTL
-
-
0.6
V
ISTART
12
24
36
μA
START=3.4V
SW pin leak current
ISWL
―
―
1
μA
SW=45V
SW pin peak current
IPEAK
0.4
0.5
0.6
A
RADJ=100kΩ
SW saturation voltage
VSAT
-
0.175
0.35
V
ISW=0.5A
RADJ adjustable range
RADJ
33
―
100
kΩ
Max on time
TONMAX
25
50
100
μsec
Max off time
TOFFMAX
12
25
50
μsec
Input bias current
[Transformer primary-side driver block]
[Charging control block]
[Transformer secondary-side detection block]
IVC
―
―
1
μA
VFULLTH
0.9875
1
1.0125
V
FULL pin ON resistor
RFULLL
0.5
1
2
kΩ
VC=VCC,FULL=0.5V
FULL pin leak current
IFULLH
-
-
1
μA
FULL=3.4V
UVLO detect voltage
VUVLOTH
1.95
2.1
2.25
V
UVLO hysteresis
VUVLOHYS
120
200
280
mV
Output short high current
Ioso
90
140
200
mA
Output short low current
Iosi
30
60
90
mA
IGBT_IN response time Rise
Trise1
-
15
80
nsec
IGBT_IN response time Fall
Tfall1
-
120
200
nsec
IGBT_IN input high voltage range1
VIGBTH1
2.0
-
―
V
IGBT_IN input high voltage range2
VIGBTH2
1.4
-
―
V
IGBT_IN input high voltage range
VIGBTL
―
-
0.6
V
START=0V
IGBT_IN sink current
IIGBT_IN
12
24
36
μA
START=0V
VC pin input current
Full charge detection voltage
VC=VCC
[Protection circuit block]
VCC detection
[IGBT driver block]
IGBT_IN=3.4V,START=0V,
IGBT_OUT =0V
IGBT_IN=0V,START=0V,
IGBT_OUT=3.4V
START=0V
START=0V,VCC=3.0Vto3.6V,
Ta=-25℃ to 85℃
◎This product is not designed for normal operation within a radioactive environment.
REV. A
3/4
○ Block Diagram
VCC
SW
5
STB
VREF
UVLO
UVLO
OS
START 6
START
STB
TSD
TSD
ENABLE
S Q
VCC
R
FULL
10
VCC
SDP
STB
UVLO
TSD
MAX_ON
MAX OFF TIME
LOGIC
PGND
SQ
MAX ON MAX_ON
TIME
R
OFF
SDP
RADJ 8
SDP
DRIVER
+
-
1 PGND
I/V
FULL
Q
S
R
FULL 9
OS
+
-
4
OFF
+
-
VC
3
GND
VCC
STB
2 IGBT_OUT
IGBT_IN 7
Fig.1
○ Package (UNIT:mm)
Block Diagram
○ Pin No.
Pin No.
Fig. 2 Marking specification
REV. A
Pin Name
Function
1
PGND
Power GND
2
IGBT_OUT
IGBT driver output
3
GND
Ground pin
4
VC
5
VCC
VCC supply pin
6
START
Standby pin
7
IGBT_IN
8
RADJ
primary-side current control pin
9
FULL
FULL charge detection flag pin
10
SW
Switching pin
Secondary–side voltage detection
pin
nput terminal of trigger signal for
starting output of IGBT driver
4/4
○ Cautions on use
1.
Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the
devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect
to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses.
2.
GND and PGND potential
Ensure a minimum GND and PGND(Except for SW pin and VC pin) pin potential in all operating conditions. In addition, ensure that
no pins other than the GND and PGND pin carry a voltage less than or equal to the GND and PGND pin, including during actual
transient phenomena.
Don’t use VC pin under Absolute Maximum Rating.
3.
Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4.
Protect circuit
The IC does not incorporate built-in malfunction protection such as overcurrent protection, short detection, or thermal shutdown
circuitry. For this reason, the IC may be damaged if it is shorted or subjected to a load that exceeds the package power. The
design of peripheral application circuits should reflect these potential risks.
5.
Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection
error or if positive and ground power supply terminals are reversed. The IC may also be damaged if pins are shorted together or
are shorted to other circuit’s power lines.
6.
Common impedance
The power supply and ground lines must be as short and thick as possible to reduce line impedance. Fluctuating voltage on the
power ground line may damage the device.
7.
IC Pin Input
This is the monolithic IC and has P+ isolation and P substrate for element isolation between each element. By the P layer and N
layer of each element, a P-N junction is formed and various parasitic elements are configured.
For example, in the case of a resistor and transistor being connected to a pin as shown in Fig.-3;
P-N junction operates as a parasitic diode when GND > (Pin A) in the case of the resistor, and when GND > (Pin B) in the case of
the transistor (NPN)
Also, a parasitic NPN transistor operates by the N layer of another element adjacent to the previous diode in the case of a
transistor (NPN) when GND > (Pin B).
The parasitic element consequently emerges through the potential relationship because of IC’s structure. The parasitic element
pulls interference out of the circuit which may be the cause of malfunction or destruction. Therefore, excessive caution is
required to avoid operation of the parasitic element which is caused by applying voltage to an input pin lower than GND (P board),
etc
(Pin A)
B
(Pin B)
C
~
~
Transistor (NPN)
E
GND
N
N
P substrate
P+
P+
N
N
P
N
(PinA)
P+
~
~
P
P+
N
N
Parasitic element
P substrate
Parasitic element
Parasitic Element
Fig.3
GND
Other adjacent elements
REV. A
GND
Notice
Notes
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R1120A
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