Rohm BD9351MWV Silicon monolithic integrated circuit Datasheet

1/4
STRUCTURE
PRODUCT SERIES
Silicon Monolithic Integrated Circuit
7-Channel Switching Regulator Controller for Digital Camera
TYPE
PIN ASSIGNMENT
BLOCK DIAGRAM
PACKAGE
Functions
BD9351MWV
Fig.1
Fig.1
Fig.2
●1.5V minimum input operating
●Supplies power for the internal circuit by using charge-pump circuit which outputs a voltage twice bigger than VBATvoltage.
or a equal voltage as VBAT + VIN.
●Contains step-up converter(1ch), step-down converter(2ch), cross converter(1ch), configurable for step-up/step-down converter(1ch),
with 59 step brightness controller for step-up converter(1ch).
●Contains 4FETs for the cross converter channel.
●3channels contain transistor for synchronous rectifying action mode.
●2channels contain FETs for the step-up converter.
●All channels contain internal compensation between inputs outputs of error amps.
●Contains sequence control circuit for ch1,2 and 4.
●Operating frequency 1.2MHz(CH1,3,4), 600kHz(CH2,5,6,7).
●Contains output interception circuit when over load.
●2 channels have high side switches with soft start function, one channel has PMOS back gate control circuit.
●Thermally enhanced UQFN044V6060 package.(6mm x 6mm, 0.4mm pitch)
○Absolute maximum ratings (Ta=25℃)
Parameter
P o w e r
S u p p l y
V o l t a g e
P o w e r
I n p u t
V o l t a g e
O
P
O
S
J
u
t
o w
p e r
t o r
u n c
p
e
a
a
t
u
t
C
u
r
r
e
n
t
r
D i s s i p a t i o
t i n g
T e m p e r a t u r
g e
T e m p e r a t u r
i o n
T e m p a r e t u r
n
e
e
e
Symbol
Limit
Unit
VBAT
VHx1~4
HS67H
VLx6~7
VIN
IomaxLx1
IomaxHx2
IomaxHx3
IomaxHx4, Lx4
IomaxHS6~7
IomaxLx6~7
Pd
Topr
Tstg
Tjmax
-0.3~7
-0.3~7
-0.3~7
-0.3~20
-0.3~7
±0.4
±1.5
±1.2
±2.2
±1.2
±0.8
0.54 (*1)
-25~+85
-55~+150
+150
V
V
V
V
V
A
A
A
A
A
A
W
℃
℃
℃
(*1) Without external heat sink, the power dissipation reduces by 4.32mW/℃ over 25℃。
○Recommended operating conditions
Parameter
Power Supply Voltage
VREF Pin Connecting Capacitor
VREGA Pin Connecting Capacitor
SCP Pin Connecting Capacitor
C+H to C+L connecting Capacitor
【Oscillator】
Oscillator Frequency (CH1,3,4)
OSC Timing Resistor
Symbol
VBAT
CVREF
CVREGA
CSCP
CF
fosc
RT
○CH7 recommended operating conditions
MIN
Limit
TYP
MAX
1.5
0.47
0.47
-
1.0
1.0
1.0
-
5.5
4.7
4.7
0.47
-
0.6
47
1.2
62
1.5
120
MIN
Limits
TYP
MAX
T(ON)
T(OFF)
T(H)
T(L)
65X1/fosc
65X1/fosc
420
420
-
10000
10000
[S]
[S]
[nS]
[nS]
Fixed H when EN start-up
T(EN)
5X1/fosc
-
-
[S]
Fixed L before setting brightness
Brightness setting time When start-up
T(CLR)
T(SET)
5X1/fosc
-
-
63X1/fosc
2048X1/fosc
[S]
[S]
Unit
Parameter
Symbol
V
μF
μF
μF
μF
Fixed H when determine brightness
Fixed L when OFF
Fixed H when setting brightness
Fixed L when setting brightness
MHz
kΩ
Status of this document
The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version.
If these are any uncertainty in translation version of this document, official version takes priority.
REV. A
Unit
2/4
○Electrical characteristics (Ta=25℃, VBAT=3V, RT=62k, STB1~6=3V,UPIC7=2.5V)
Parameter
Symbol
【Charge Pump Circuit】
Output Voltage
Vcpout1
(Regulated)
Output Voltage
( X2 Step up)
Vcpout2
MIN
Standard value
TYP
MAX
Units
Io=1mA,, INV1~7=1.2V
NON5= -0.2V
Only for internal Current
VBAT=2.5V, INV1~7=1.2V
NON5= -0.2V
5.2
5.4
-
V
4.5
4.8
-
V
50
Ω
CF=1μF, VBAT=2.5V
90
kHz
RT=62kΩ
-
V
2.6
V
2.30
200
V
mA
Output
Vcpro
-
35
Resistance
Operating
fcp
60
75
Frequency
Minimum VBAT
Vst1
1.5
-
Voltage
【Internal Regulator VREGA】
Output Voltage
VREGA
2.4
2.5
【Prevention Circuit of Miss Operation by Low voltage Input】
Threshold Voltage
Vstd1
-
2.15
Hysteresis Width
⊿Vstd1
50
100
【Short Circuit Protection】
Timer start
Vtcinv
0.42
0.48
threshold voltage
SCP Stand by
Vssc
-
22
Voltage
SCP Out Source
Iscp
2
4
Current
SCP Threshold
Vscp
0.9
1.0
Voltage
【Oscillator】
Frequency
fosc1
1.0
1.2
CH1,3,4
Frequency
fosc2
0.5
0.6
CH2,5,6,7
Max Duty
Dmax1d
-
-
1,3,4(Step Down)
Max Duty
Dmax1u
86
92
1,4(Step Up)
Max Duty 5,6,7
Dmax2
86
92
Max Duty
Dmax3
-
-
CH2 LX21
Max Duty
Dmax4
86
92
CH2 LX22
【Error AMP】
Input Biias Current
IINV
-
0
INV Threshold
VINV1
0.79
0.80
Voltage1
INV Threshold
VINV2
0.99
1.00
Voltage2
INV Threshold
VINV3
855
900
Voltage3
INV Threshold
VINV4
570
Voltage4
INV Threshold
VINV5
285
Voltage5
INV Threshold
VINV6
135
Voltage6
INV Threshold
VINV7
60
Voltage7
INV Threshold
VINV8
15
Voltage8
【Base Bias Voltage Vref for inverted Channel】
CH5
VOUT5
-6.09
OutputVoltage
Line Regulation
DVLi
-
Output Current
Ios
0.2
When shorted
0.54
V
170
mV
6
μA
1.1
V
1.4
MHz
Parameter
Conditions
Io=5mA
VREGA Monitor
INV monitor CH4
Vscp=0.1V
RT=62kΩ
0.7
MHz
RT=62kΩ
100
%
96
%
96
%
100
%
96
%
50
nA
INV1~7, NON5=3.0V
0.81
V
CH1~4
1.01
V
CH6, 7V
945
mv
Vscp=0V (※1)
UDSEL4
Control
Voltage
630
mv
CH7I
300
315
mv
CH7I
Conditions
1.5
2.5
3.5
msec
RT=62kΩ
Tss3
0.5
1.5
2.5
msec
RT=62kΩ
Tss5
1.5
2.5
3.5
msec
RT=62kΩ
Tss6
2.0
3.0
4.0
msec
RT=62kΩ
Tss7
4.7
5.7
6.7
msec
RT=62kΩ
RON1P
-
480
720
mΩ
HX1=3V,
CPOUT=5.4V
RON1N
-
260
390
mΩ
CPOUT=5.4V
RON21P
-
160
240
mΩ
HX2=3.0V,
CPOUT=5.4V
RON21N
-
130
200
mΩ
CPOUT=5.4V
RON22P
-
180
280
mΩ
VOUT2=5.0V
RON22N
-
130
200
mΩ
CPOUT=5.4V
RON3P
-
160
260
mΩ
HX3=3.0V,
CPOUT=5.4V
RON3N
-
130
200
mΩ
CPOUT=5.4V
RON4P
-
190
290
mΩ
HX4=5.0V
RON4N
-
110
170
mΩ
CPOUT=5.4V
RON6N
-
500
800
mΩ
CPOUT=5.4V
RON67P
-
200
300
mΩ
Vout5H
PVCC5
-1.5
PVCC5
-1.0
-
V
-
0.5
1.0
V
HS67H=3.0V
CPOUT=5.4V
IOUT5=50mA,
NON5=0.2V,
PVCC5=3V
IOUT5=50mA,
NON5=0.2V
CPOUT
×0.7
-
CPOUT
V
Step up
VUDUP
0
-
CPOUT
×0.3
V
Active
VSTBH1
1.5
-
5.5
V
Non Active
VSTBL1
RSTB1
-0.3
250
-
400
0.3
700
V
kΩ
Active
VUPIH
2.05
-
4.0
V
Non Active
VUPIL
0
-
0.4
V
ISTB1
-
-
5
μA
ISTB2
-
-
5
μA
ISTB3
-
-
5
μA
Step –down
UDSEL4=CPOUT
ISTB4
-
-
5
μA
Step-up UDSEL4=0V
Icc1
-
7.0
11.0
mA
INV1~7=1.2V,
NON5=-0.2V, VBAT=3.0V
Icc2
-
3.0
5.0
mA
【STB1~6】
STB
control
Voltage
mv
CH7I
Pull down Resistance
【UPIC7】
75
90
mv
CH7I
30
45
mv
CH7I
UPIC7
control
Voltage
-6.00
-5.91
V
4.0
12.5
mV
mA
Units
VUDDO
165
-
Standard value
TYP
MAX
Step down
150
1.0
Min
Tss1,2,4
CH5 Driver
Vout5L
Output Voltage L
【Switch to configure step up/down】
CH7I
600
【Soft Start】
CH1,2,4
Soft Start Time
CH3
Soft Start Time
CH5
Soft Start Time
CH6
Soft Start Time
CH7
Soft Start Time
【Output Driver】
CH1 Highside SW
ON Resistance
CH1 Lowside SW
ON Resistance
CH2 LX21Pin
Highside SW
ON Resistance
CH2 LX21Pin
Lowside SW
ON Resistance
CH2 LX22Pin
Highside SW
ON Resistance
CH2 LX22Pin
Lowside SW
ON Resistance
CH3 Highside SW
ON Resistance
CH3 Lowside SW
ON Resistance
CH4 Highside SW
ON Resistance
CH4 Lowside SW
ON Resistance
CH6 NMOS SW
ON Resistance
CH6,7 Load SW
ON Resistance
CH5 Driver
Output Voltage H
Symbol
【Circuit Current】
NON5 resistor12kΩ, 72kΩ
(※2)
CPOUT=1.5~5.5V
Stand-by
Current
Vref=0V
VBAT
terminal
HS67H
terminal
HX terminal
LX terminal
Circuit Current1
(VBAT current
when voltage supplied
for the terminal)
Circuit Current2
(CPOUT current
when voltage supplied
for the terminal)
(※1)The protective circuit start working when circuit is operated by 100% duty.
So it is possible to use only for transition time shorter than charge time for SCP.
(※2)Recommend resistor value over 20kΩ between VREF to NON5, because VREF current is under 100uA.
(※3)UPIC7 is not connected pull-down resistor. UPIC7 must input H or L level voltage when CH1~6 is active.
◎This product is not designed for normal operation with in a radioactive environment
REV. A
INV1~7=1.2V,
NON5=-0.2V, CPOUT=5.4V
C+H, C+L=OPEN
3/4
NON5
34
INV6
35
INV7
36
INV7I
37
UPIC7
38
HS6L
39
HS67H
40
HS7L
41
VREGA
CPOUT
C+H
VBAT
VIN
C+L
GND
RT
SCP
INV1
33
32
31
30
29
28
27
26
25
24
23
1.0V
VREF
CHARGE PUMP
OSC
+
UVLO
REF
+
1.0V
REF
+
1.0V
+
TSD
PWM &
LOGIC BLOCK
OCP
PRE D RIVER
HI-SIDE SW
42
PGND567
43
Lx6
44
REF
0.8V
+
DAC
PRE
DRIVER
PRE
DRIVER
PRE DRIVER
REF
0.8V
22
INV3
21
INV2
20
INV4
19
Hx4
18
Lx4
17
PGND4
16
Hx2
15
Lx21
14
PGND2
13
Lx22
12
VOUT2
B.G.CTL
OCP
PRE DRIVER
400k
2
3
4
5
6
7
8
9
10
11
STB56
OUT5
Hx1
Lx1
PGND13
Lx3
Hx3
STB3
STB124
UDSEL4
400k
1
PVCC5
400k
PRE
DRIVER
○Package
REF
0.8V
REF
0.8V
+
OCP
Lx7
+
SCP
2.5V
REG
+
PRE DRIVER
REF
0V
VREF
○Pin Assignment ・Block Diagram
Fig. 1
○Pin Description
B D 9 3 5 1 M W
Pin Name
Description
VBAT
VIN
CPOUT
GND
Input for battery voltage
Returning voltage from output terminal
Output terminal for Charge Pump
Ground terminal
Terminal for connecting flying capacitor for Charge
Pump(H side)
Terminal for connecting flying capacitor for Charge
Pump(L side)
Ground terminal for internal FET
VREGA output
CH5 base bias voltage
CH5 PMOS VCC input for driver
Terminal for connecting gate of CH5 PMOS
Input terminal for synchronous
High side switch, Power supply for Pch Driver
Terminal for connecting inductors
Power supply for channel 2
Terminal for connecting inductor for CH2 input
Terminal for connecting inductor for CH2 output
CH2 output voltage
Power supply for internal load switch
Output terminal for internal load switch
Error AMP inverted input
Error AMP non-inverted input
Error AMP inverted input
For connecting a resistor
to set the OSC frequency
For connecting a capacitor
to set up the delay time of the SCP
Step-up/down switching mode
selection(H: step-down, L:step-up)
ON/OFF switch H: operating over 1.5V
ON/OFF switch for CH7 brightness control
C+H
C+L
PGND13,2,4,567
VREGA
VREF
PVCC5
OUT5
Hx1,3,4
LOT No.
Lx1,3,4,6,7
Hx2
Lx21
Lx22
VOUT2
HS67H
HS6L,HS7L
INV1,2,3,4,6,7
NON5
INV7I
RT
SCP
UDSEL4
STB124,3,56
UPIC7
Fig. 2
REV. A
4/4
○Operation Notes
1.) Absolute maximum ratings
This product is produced with strict quality control. However, the IC may be destroyed if operated beyond its absolute
maximum ratings. If the device is destroyed by exceeding the recommended maximum ratings, the failure mode will be difficult
to determine. (E.g. short mode, open mode) Therefore, physical protection counter-measures (like fuse) should be implemented
when operating conditions beyond the absolute maximum ratings anticipated.
2.) GND potential
Make sure GND is connected at lowest potential. All pins except NON5, must not have voltage below GND. Also, NON5 pin must
not have voltage below - 0.3V on start up.
3.) Setting of heat
Make sure that power dissipation does not exceed maximum ratings.
4.) Pin short and mistake fitting
Avoid placing the IC near hot part of the PCB. This may cause damage to IC. Also make sure that the output-to-output and output
to GND condition will not happen because this may damage the IC.
5.) Actions in strong magnetic field
Exposing the IC within a strong magnetic field area may cause malfunction.
6.) Mutual impedance
Use short and wide wiring tracks for the main supply and ground to keep the mutual impedance as small as possible. Use inductor
and capacitor network to keep the ripple voltage minimum.
7.) Voltage of STB pin
The threshold voltages of STB pin are 0.3V and 1.5V. STB state is set below 0.3V while action state is set beyond 1.5V.
The region between 0.3V and 1.5V is not recommended and may cause improper operation.
The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01μF.
8.) Thermal shutdown circuit (TSD circuit)
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only
to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not
continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed.
9.)Rush current at the time of power supply injection.
An IC which has plural power supplies, or CMOS IC could have momentary rush current at the time of power supply injection.
Please take care about power supply coupling capacity and width of power Supply and GND pattern wiring.
10.)IC Terminal Input
This IC is a monolithic IC that has a P- board and P+ isolation for the purpose of keeping distance between elements. A P-N junction
is formed between the P-layer and the N-layer of each element, and various types of parasitic elements are then formed.
For example, an application where a resistor and a transistor are connected to a terminal (shown in Fig.15):
○When GND > (terminal A) at the resistor and GND > (terminal B) at the transistor (NPN), the P-N junction operates as
a parasitic diode.
○When GND > (terminal B) at the transistor (NPN), a parasitic NPN transistor operates as a result of the NHayers of other
elements in the proximity of the aforementioned parasitic diode.
Parasitic elements are structurally inevitable in the IC due to electric potential relationships. The operation of parasitic elements
Induces the interference of circuit operations, causing malfunctions and possibly the destruction of the IC. Please be careful not to
use the IC in a way that would cause parasitic elements to operate. For example, by applying a voltage that is lower than the
GND (P-board) to the input terminal.
Transistor (NPN)
B
(Terminal B)C
Resistor
(Terminal A)
E
GND
(TerminalA)
P
P+
N
N
P-board
P
P+
P+
N
N
N
Parasitic element
~
~
N
P+
Parasitic element
N
P-board
Parasitic element
GND
Fig - 3 Simplified structure of a Bipolar IC
REV. A
GND
Notice
Notes
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which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
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The technical information specified herein is intended only to show the typical functions of and
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