PHILIPS BH16501ADGG 18-bit universal bus transceiver 3-state Datasheet

INTEGRATED CIRCUITS
74ABT16501A
74ABTH16501A
18-bit universal bus transceiver (3-State)
Product specification
Supersedes data of 1997 Jun 12
IC23 Data Handbook
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16501A
74ABTH16501A
18-bit universal bus transceiver (3-State)
FEATURES
DESCRIPTION
• 18-bit bidirectional bus interface
• 3-State buffers
• Output capability: +64mA/-32mA
• TTL input and output switching levels
• 74ABTH16501A incorporates bus-hold data inputs which
The 74ABT16501A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is High, the outputs
are active. When OEAB is Low, the outputs are in the
high-impedance state.
eliminate the need for external pull-up resistors to hold unused
inputs
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-State
• Positive edge-triggered clock inputs
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA. The output enables are complimentary (OEAB is
active High, and OEBA is active Low).
and 200V per Machine Model
• Flexible operation permits 18 embedded D-type latches or
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
flip-flops to operate in clocked, transparent, and latched modes.
Two options are available, 74ABT16501A which does not have the
bus-hold feature and 74ABTH16501A which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
SYMBOL
CONDITIONS
Tamb = 25°C; GND = 0V
PARAMETER
TYPICAL
UNIT
2.2
1.8
ns
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50pF;
VCC = 5V
CIN
Input capacitance (Control pins)
VI = 0V or VCC
3
pF
CI/O
I/O pin capacitance
Outputs disabled; VI/O = 0V or VCC
7
pF
500
µA
9
mA
ICCZ
ICCL
Quiescent supply current
Outputs disabled; VCC = 5.5V
Outputs low; VCC = 5.5V
ORDERING INFORMATION
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
PACKAGES
–40°C to +85°C
74ABT16501A DL
BT16501A DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40°C to +85°C
74ABT16501A DGG
BT16501A DGG
SOT364-1
56-Pin Plastic SSOP Type III
–40°C to +85°C
74ABTH16501A DL
BH16501A DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40°C to +85°C
74ABTH16501A DGG
BH16501A DGG
SOT364-1
1998 Feb 27
2
853-1788 19027
Philips Semiconductors
Product specification
74ABT16501A
74ABTH16501A
18-bit universal bus transceiver (3-State)
LOGIC SYMBOL
PIN CONFIGURATION
30 28 27 55 2
OEAB
CPAB
LEAB
B1
LEBA
B0
OEBA
52
CPBA
54
1
A0
A1
3
5
OEAB
1
56
GND
LEAB
2
55
CPAB
A0
3
54
B0
4
53
GND
B1
51
B2
A2
6
GND
49
B3
A3
8
A1
5
52
48
B4
A4
9
A2
6
51
B2
47
B5
A5
10
VCC
7
50
VCC
45
B6
A6
12
A3
8
49
B3
44
B7
A7
13
43
9
48
B4
B8
A8
14
A4
A5
10
47
B5
11
46
GND
42
B9
A9
15
41
B10
A10
16
GND
40
B11
A11
17
A6
12
45
B6
38
B12
A12
19
A7
13
44
B7
37
B13
A13
20
A8
14
43
B8
36
B14
A14
21
A9
15
42
B9
34
B15
A15
23
33
B16
A10
16
41
B10
A11
17
40
B11
GND
18
39
GND
A12
19
38
B12
A13
20
37
B13
A14
21
36
B14
VCC
22
35
VCC
B15
31
A16
B17
A17
24
26
SA00127
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
OEAB
A-to-B Output enable input
A15
23
34
27
OEBA
B-to-A Output enable input
(active low)
A16
24
33
B16
GND
25
32
GND
A-to-B/B-to-A Latch
enable input
A17
26
31
B17
OEBA
27
30
CPBA
LEBA
28
29
GND
2, 28
55,30
LEAB/LEBA
CPAB/
CPBA
A-to-B/B-to-A Clock input
(active rising edge)
3, 5, 6, 8, 9, 10, 12,
13, 14, 15, 16, 17,
19, 20, 21, 23, 24, 26
A0-A17
Data inputs/outputs
(A side)
54, 52, 51, 49, 48,
47, 45, 44, 43, 42,
41, 40, 38, 37, 36,
34, 33, 31
B0-B17
Data inputs/outputs
(B side)
4, 11, 18, 25, 32, 39,
46, 53
GND
Ground (0V)
7, 22, 35, 50
VCC
Positive supply voltage
1998 Feb 27
SA00128
3
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
LOGIC SYMBOL (IEEE/IEC)
OEAB
1
CPAB
55
LEAB
2
OEBA
27
CPBA
30
LEBA
28
EN1
2C3
C3
G2
EN4
5C6
C6
G5
A0
3
3D
1
1
4
1
6D
54
B0
A1
5
52
B1
A2
6
51
B2
A3
8
49
B3
9
48
B4
A5
10
47
B5
A6
12
45
B6
A7
13
44
B7
A8
14
43
B8
A9
15
42
B9
A10
16
41
B10
A11
17
40
B11
A12
19
38
B12
A13
20
37
B13
A14
21
36
B14
A15
23
34
B15
A16
24
33
B16
A17
26
31
B17
A4
SA00129
1998 Feb 27
4
74ABT16501A
74ABTH16501A
Philips Semiconductors
Product specification
74ABT16501A
74ABTH16501A
18-bit universal bus transceiver (3-State)
FUNCTION TABLE
INPUTS
Internal
Registers
OUTPUTS
OPERATING MODE
OEAB
LEAB
CPAB
An
Bn
L
H
X
X
X
Z
L
↓
X
h
H
Z
L
↓
X
I
L
Z
L
L
H or L
X
NC
Z
L
L
↑
h
H
Z
L
L
↑
I
L
Z
H
H
X
H
H
H
H
H
X
L
L
L
H
↓
X
h
H
H
H
↓
X
I
L
L
H
L
↑
h
H
H
H
L
↑
I
L
L
H
L
H or L
X
H
H
H
L
H or L
X
L
L
Disabled
Disabled Latch data
Disabled,
Disabled, Hold data
Disabled Clock data
Disabled,
Transparent
Trans
arent
Latch data & dis
display
lay
Clock data & display
dis lay
Hold data & display
dis lay
NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
H = High voltage level
h = High voltage level one set-up time prior to the Enable or Clock transition
L = Low voltage level
I = Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change
X = Don’t care
Z = High Impedance ”off” state
↓ = High-to-Low Enable or Clock transition
↑ = Low-to-High Clock transition
1998 Feb 27
5
Philips Semiconductors
Product specification
74ABT16501A
74ABTH16501A
18-bit universal bus transceiver (3-State)
LOGIC DIAGRAM
OEAB
1
CLKAB 55
LEAB 2
LEBA
28
CLKBA 30
OEBA 27
A1
3
ID
54 B1
C1
CLK
ID
C1
CLK
To 17 other channels
SW00235
1998 Feb 27
6
Philips Semiconductors
Product specification
74ABT16501A
74ABTH16501A
18-bit universal bus transceiver (3-State)
ABSOLUTE MAXIMUM RATINGS1, 2
PARAMETER
SYMBOL
VCC
IIK
RATING
UNIT
–0.5 to +7.0
V
–18
mA
–1.2 to +7.0
V
VO < 0
–50
mA
Output in Off or High state
–0.5 to +5.5
V
Output in Low state
128
Output in High state
–64
DC supply voltage
DC input diode current
VI < 0
voltage3
VI
DC input
IOK
DC output diode current
VOUT
CONDITIONS
DC output
voltage3
IOUT
O
DC output current
Tstg
Storage temperature range
mA
–65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
VCC
PARAMETER
UNIT
DC supply voltage
MIN
MAX
4.5
5.5
V
0
VCC
V
VI
Input voltage
VIH
High-level input voltage
VIL
Input voltage
0.8
V
IOH
High-level output current
–32
mA
IOL
Low-level output current
64
mA
∆t/∆v
Input transition rise or fall rate; Outputs enabled
10
ns/V
Tamb
Operating free-air temperature range
+85
°C
1998 Feb 27
2.0
–40
7
V
Philips Semiconductors
Product specification
74ABT16501A
74ABTH16501A
18-bit universal bus transceiver (3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
VIK
VOH
Input clamp voltage
High-level output voltage
Tamb = –40°C
to +85°C
Tamb = +25°C
VCC = 4.5V; IIK = –18mA
TYP
MAX
–0.8
–1.2
MIN
UNIT
MAX
–1.2
V
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
2.5
2.9
2.5
V
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
3.0
4.0
3.0
V
VCC = 4.5V; IOH = –32mA; VI = VIL or VIH
2.0
2.4
2.0
V
VOL
Low-level output voltage
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
0.35
0.55
0.55
V
VRST
Power-up output voltage3
VCC = 5.5V; IO = 1mA; VI = GND or VCC
0.13
0.55
0.55
V
Input leakage
current
VCC = 5.5V; VI = GND or
5.5V
0.01
±1.0
±1.0
µA
II
Control pins
VCC = 4.5V; VI = 0.8V
35
35
VCC = 4.5V; VI = 2.0V
–75
–75
VCC = 5.5V; VI = 0 to 5.5V
±800
IHOLD
Bus Hold
B
H ld currentt A and
dB
ports5 74ABTH16501A
IOFF
Power-off leakage current
VCC = 0.0V; VO or VI ≤ 4.5V
2
±100
±100
µA
Power-up/down 3-State
output current4
VCC = 2.1V; VO = 0.0V or VCC;
VI = GND or VCC; VOE = Don’t care
2
±50
±50
µA
IIH + IOZH
3-State output High current
VCC = 5.5V; VO = 5.5V; VI = VIL or VIH
1.0
10
10
µA
IIL + IOZL
3-State output Low current
VCC = 5.5V; VO = 0.0V; VI = VIL or VIH
–1.0
–10
–10
µA
Output High leakage
current
VCC = 5.5V; VO = 5.5V; VI = GND or VCC
2.0
50
50
µA
Output current1
VCC = 5.5V; VO = 2.5V
–80
–180
–180
mA
0.5
2
2
mA
9
19
19
mA
VCC = 5.5V; Outputs 3–State;
VI = GND or VCC
0.5
2
2
mA
IPU/PD
ICEX
IO
VCC = 5.5V; Outputs High, VI = GND or
VCC
ICCH
ICCL
–50
Quiescent supply current
ICCZ
VCC = 5.5V; Outputs Low, VI = GND or VCC
–50
µA
∆ICC
Additional supply current
per input pin2
74ABT16501A
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND
5.0
50
50
µA
∆ICC
Additional supply current
per input pin2
74ABTH16501A
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND
200
500
500
µA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a
transition time of up to 100µsec is permitted.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 27
8
Philips Semiconductors
Product specification
74ABT16501A
74ABTH16501A
18-bit universal bus transceiver (3-State)
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
Tamb = +25oC
VCC = +5.0V
WAVEFORM
Tamb = –40 to +85oC
VCC = +5.0V ±0.5V
MAX
MIN
UNIT
MIN
TYP
fmax
Maximum clock frequency
1
150
225
MAX
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
2
1.0
1.0
2.2
1.8
3.0
2.5
1.0
1.0
3.5
3.0
ns
tPLH
tPHL
Propagation delay
LEAB to Bn or LEBA to An
3
1.5
1.4
3.2
2.9
4.3
3.8
1.5
1.4
5.0
4.2
ns
tPLH
tPHL
Propagation delay
CPAB to Bn or CPBA to An
1
1.6
1.4
3.5
2.9
4.5
3.8
1.6
1.4
5.0
4.2
ns
tPZH
tPZL
Output enable time
to HIGH and LOW level
5
6
1.1
1.0
3.0
2.4
4.0
3.4
1.1
1.0
4.7
3.9
ns
tPHZ
tPLZ
Output disable time
from HIGH and LOW level
5
6
1.3
1.0
3.3
2.4
4.3
3.4
1.3
1.0
5.3
3.9
ns
150
MHz
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Tamb = +25oC
VCC = +5.0V
Tamb = –40 to +85oC
VCC = +5.0V ±0.5V
UNIT
MIN
TYP
MIN
4
2.0
2.0
0.5
0.5
2.0
2.0
ns
Hold time, HIGH or LOW
An to CPAB or Bn to CPBA
4
0.7
0.7
–0.5
–0.5
0.7
0.7
ns
ts(H)
ts(L)
Setup time, HIGH or LOW
An to LEAB or Bn to LEBA
4
2.0
2.0
0.5
0.4
2.0
2.0
ns
th(H)
th(L)
Hold time HIGH or LOW
An to LEAB or Bn to LEBA
4
0.7
0.7
–0.4
–0.5
0.7
0.7
ns
tw
Pulse width, HIGH or LOW
CPAB or CPBA
1
3
1.9
3
ns
tw(H)
Pulse width, HIGH
LEAB or LEBA
3
3
1.2
3
ns
ts(H)
ts(L)
Setup time, HIGH or LOW
An to CPAB or Bn to CPBA
th(H)
th(L)
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
1/fMAX
An or Bn
CPBA or
CPAB
VM
VM
VM
VM
tPLH
tW(L)
tW(H)
tPHL
VOH
tPLH
An or Bn
An or Bn
VM
tPHL
VM
VM
VM
VOL
SA00132
SA00131
Waveform 2. Propagation Delay, Transparent Mode
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
1998 Feb 27
9
Philips Semiconductors
Product specification
74ABT16501A
74ABTH16501A
18-bit universal bus transceiver (3-State)
AC WAVEFORMS (Continued)
VM = 1.5V, VIN = GND to 3.0V
OEBA
VM
LEAB or
LEBA
VM
VM
VM
VM
OEAB
tW(H)
tPLH
tPZH
tPHL
tPHZ
VOH
VOH
An or Bn
VM
VOH –0.3V
VM
VM
An or Bn
VOL
SA00133
SA00135
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 3. Propagation Delay, Enable to Output, and Enable
Pulse Width
An
or
Bn
ÉÉÉ ÉÉÉÉÉ ÉÉÉ
ÉÉÉ ÉÉÉÉÉ ÉÉÉ
ÉÉÉ ÉÉÉÉÉ ÉÉÉ
VM
VM
VM
tS(H)
th(H)
OEBA
VM
VM
VM
OEAB
th(L)
tS(L)
tPZL
tPLZ
An or Bn
CPAB or CPBA,
LEAB or LEBA
VM
VM
Note: The shaded areas indicate when the input is permitted
to change for predictable output performance.
VM
VOL +0.3V
VOL
SA00136
SA00134
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
Waveform 4. Data Setup and Hold Times
TEST CIRCUIT AND WAVEFORMS
VCC
7.0V
PULSE
GENERATOR
VIN
tW
90%
VOUT
VM
NEGATIVE
PULSE
RL
10%
0V
tTHL (tF)
CL
tTLH (tR)
tTLH (tR)
RL
tTHL (tF)
90%
POSITIVE
PULSE
Test Circuit for 3-State Outputs
AMP (V)
90%
VM
VM
10%
10%
tW
SWITCH POSITION
TEST
SWITCH
tPLZ
closed
tPZL
closed
All other
open
0V
VM = 1.5V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
AMP (V)
VM
10%
D.U.T.
RT
90%
FAMILY
74ABT/H16
Amplitude
Rep. Rate
tW
tR
tF
3.0V
1MHz
500ns
2.5ns
2.5ns
SA00018
1998 Feb 27
10
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
1998 Feb 27
11
74ABT16501A
74ABTH16501A
SOT371-1
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
1998 Feb 27
12
74ABT16501A
74ABTH16501A
SOT364-1
Philips Semiconductors
Product specification
74ABT16501A
74ABTH16501A
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
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Date of release: 05-96
9397-750-03494
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