PHILIPS BH16841ADGG 20-bit bus interface latch 3-state Datasheet

INTEGRATED CIRCUITS
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
FEATURES
DESCRIPTION
• High speed parallel latches
• Live insertion/extraction permitted
• Extra data width for wide address/data paths or buses carrying
The 74ABT16841A Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT16841A consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is High. This allows asynchronous operation, as
the output transition follows the data in transition. On the nLE
High-to-Low transition, the data that meets the setup and hold time
is latched.
parity
• Power-up 3-State
• 74ABTH16841A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Data appears on the bus when the Output Enable (nOE) is Low.
When nOE is High the output is in the High-impedance state.
• Power-up reset
• Ideal where high speed, light loading, or increased fan-in are
Two options are available, 74ABT16841A which does not have the
bus-hold feature and 74ABTH16841A which incorporates the
bus-hold feature.
required with MOS microprocessors
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C; GND = 0V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
nDx to nQx
CL = 50pF; VCC = 5V
3.1
2.2
ns
CIN
Input capacitance
VI = 0V or VCC
4
pF
VO = 0V or VCC; 3-State
7
pF
Outputs disabled; VCC = 5.5V
500
µA
Outputs LOW; VCC = 5.5V
10
mA
COUT
Output capacitance
ICCZ
Quiescent supply current
ICCL
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40°C to +85°C
74ABT16841A DL
BT16841A DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40°C to +85°C
74ABT16841A DGG
BT16841A DGG
SOT364-1
56-Pin Plastic SSOP Type III
–40°C to +85°C
74ABTH16841A DL
BH16841A DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40°C to +85°C
74ABTH16841A DGG
BH16841A DGG
SOT364-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
1D0 – 1D9
2D0 – 2D9
Data inputs
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1Q0 – 1Q9
2Q0 – 2Q9
Data outputs
1, 28
1OE, 2OE
Output enable inputs (active-Low)
56, 29
1LE, 2LE
Latch enable inputs (active rising edge)
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
VCC
Positive supply voltage
1998 Feb 27
FUNCTION
2
853-1797 19025
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
1OE
1
56
1LE
1Q0
2
55
1D0
1Q1
3
54
GND
4
53
1Q2
5
52
1D2
1Q3
6
51
1D3
VCC
7
1Q4
8
GND
1D1
2OE
28
EN4
GND
2LE
29
C3
1D0
55
2
1Q0
1D1
54
3
1Q1
1D2
52
5
1Q2
1D3
51
6
1Q3
1D4
49
8
1Q4
1D5
48
9
1Q5
1D6
47
10
1Q6
1D7
45
12
1Q7
1D8
44
13
1Q8
1D9
43
14
1Q9
2D0
42
15
2Q0
2D1
41
16
2Q1
2D2
40
17
2Q2
2D3
38
19
2Q3
1D5
1D6
47
11
1LE
1D4
48
10
1
56
VCC
49
9
1Q5
1Q6
50
1OE
EN2
C1
2∇
1D
46
GND
45
1D7
13
44
1D8
1Q9
14
43
1D9
2Q0
15
42
2D0
2Q1
16
41
2D1
2Q2
17
40
2D2
GND
18
39
GND
2Q3
19
38
2D3
2D4
37
20
2Q4
2Q4
20
37
2D4
2D5
36
21
2Q5
2Q5
21
36
2D5
2D6
34
23
2Q6
VCC
22
35
VCC
2D7
33
24
2Q7
2Q6
23
34
2D6
2D8
31
26
2Q8
2Q7
24
33
2D7
2D9
30
27
2Q9
GND
25
32
GND
2Q8
26
31
2D8
2Q9
27
30
2D9
2OE
28
29
2LE
1Q7
1Q8
12
4∇
3D
SH00081
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
nOE
nLE
nDx
nQ0 – nQ9
L
L
H
H
L
H
L
H
Transparent
L
L
↓
↓
l
h
L
H
Latched
H
X
X
Z
High impedance
SA00076
LOGIC SYMBOL
55
54
52
51
49
48
47
1D0 1D1 1D2 1D3 1D4 1D5 1D6
56
1LE
1
1OE
45
44
43
1D7 1D8
1D9
L
L
X
NC
Hold
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low LE
transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low LE
transition
↓ = High-to-Low LE transition
NC= No change
X = Don’t care
Z = High impedance “off” state
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
2
3
5
6
8
9
10
12
13
14
42
41
40
38
37
36
34
33
31
30
2D0 2D1 2D2 2D3 2D4 2D5 2D6
29
2LE
28
2OE
2D7 2D8
2D9
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15
16
17
19
20
21
23
24
26
27
SH00023
1998 Feb 27
3
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
LOGIC DIAGRAM
nD0
nD1
D
L
nD2
D
Q
L
nD3
D
Q
nD4
D
D
L
Q
L
Q
nD6
nD5
D
L
Q
L
nD7
D
Q
L
nD8
nD9
D
Q
L
D
D
Q
L
Q
L
Q
nLE
nOE
nQ0
nQ1
nQ2
nQ4
nQ3
nQ5
nQ6
nQ7
nQ8
nQ9
SH00024
ABSOLUTE MAXIMUM RATINGS1, 2
PARAMETER
SYMBOL
VCC
IIK
CONDITIONS
RATING
UNIT
–0.5 to +7.0
V
–18
mA
–1.2 to +7.0
V
VO < 0
–50
mA
Output in Off or High state
–0.5 to +5.5
V
Output in Low state
128
Output in High state
–64
DC supply voltage
DC input diode current
VI < 0
voltage3
VI
DC input
IOK
DC output diode current
VOUT
DC output voltage3
IOUT
O
DC output current
Tstg
Storage temperature range
mA
–65 to 150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
VCC
PARAMETER
UNIT
DC supply voltage
Min
Max
4.5
5.5
V
0
VCC
V
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level Input voltage
0.8
V
IOH
High-level output current
–32
mA
IOL
Low-level output current
64
mA
0
5
ns/V
–40
+85
°C
∆t/∆v
Input transition rise or fall rate
Tamb
Operating free-air temperature range
1998 Feb 27
2.0
4
V
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
VIK
VOH
Input clamp voltage
High-level output voltage
Tamb = -40°C
to +85°C
Tamb = +25°C
VCC = 4.5V; IIK = -18mA
Typ
Max
–0.9
–1.2
Min
UNIT
Max
–1.2
V
VCC = 4.5V; IOH = -3mA; VI = VIL or VIH
2.5
2.9
2.5
V
VCC = 5.0V; IOH = -3mA; VI = VIL or VIH
3.0
3.4
3.0
V
VCC = 4.5V; IOH = -32mA; VI = VIL or VIH
2.0
2.4
2.0
V
VOL
Low-level output voltage
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
0.42
0.55
0.55
V
VRST
Power-up output voltage3
VCC = 5.5V; IO = 1mA; VI = GND or VCC
0.13
0.55
0.55
V
II
Input
In
ut leakage current
74ABT16841A
VCC = 5.5V; VI = VCC or GND
±0.01
±1
±1.0
µ
µA
Input leakage current
74ABTH16841A
±0.01
±1
±1
µA
II
0.01
1
1
µA
–2
–3
–5
µA
VCC = 5.5V; VI = VCC or GND
VCC = 5.5V; VI = VCC
Data pins
ins5
VCC = 5.5V; VI = 0
IHOLD
Bus Hold current inputs6
74ABTH16841A
Control pins
VCC = 4.5V; VI = 0.8V
35
35
VCC = 4.5V; VI = 2.0V
–75
–75
VCC = 5.5V; VI = 0 to 5.5V
±800
µA
Power-off leakage current
VCC = 0.0V; VO or VI ≤ 4.5V
±5.0
±100
±100
µA
Power-up/down 3-State
output current4
VCC = 2.1V; VO = 0.5V; VI = GND or VCC;
VOE = Don’t care
±5.0
±50
±50
µA
IOZH
3-State output High current
VCC = 5.5V; VO = 2.7V; VI = VIL or VIH
5.0
10
10
µA
IOZL
3-State output Low current
VCC = 5.5V; VO = 0.5V; VI = VIL or VIH
–5.0
–10
–10
µA
ICEX
Output High leakage current
VCC = 5.5V; VO = 5.5V; VI = GND or VCC
5.0
50
50
µA
Output current1
VCC = 5.5V; VO = 2.5V
–70
–180
–180
mA
0.5
1
1
mA
VCC = 5.5V; Outputs Low, VI = GND or VCC
10
19
19
mA
VCC = 5.5V; Outputs 3-State; VI = GND or VCC
0.5
1
1
mA
VCC = 5.5V; one input at 3.4V, other inputs at
VCC or GND
0.2
1
1
mA
IOFF
IPU/PD
IO
ICCH
ICCL
VCC = 5.5V; Outputs High, VI = GND or VCC
Quiescent supply current
ICCZ
∆ICC
–50
Additional supply current per
input pin2
–50
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a
transition time of up to 100µsec is permitted.
5. Unused pins at VCC or GND.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
+25oC
Tamb = -40 to +85oC
VCC = +5.0V ±0.5V
Tamb =
VCC = +5.0V
WAVEFORM
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation delay
nDx to nQx
2
1.1
1.5
3.1
2.2
4.1
3.1
1.1
1.5
4.9
3.6
ns
tPLH
tPHL
Propagation delay
nLE to nQx
1
1.5
1.0
2.5
2.1
3.3
2.8
1.5
1.0
3.7
3.1
ns
tPZH
tPZL
Output enable time
to High and Low level
4
5
1.2
1.2
2.4
2.2
3.2
2.9
1.2
1.2
4.0
3.6
ns
tPHZ
tPLZ
Output disable time
from High and Low level
4
5
1.8
1.5
3.0
2.5
4.0
3.2
1.8
1.5
4.9
3.7
ns
1998 Feb 27
5
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
Tamb = +25oC
VCC = +5.0V
WAVEFORM
Tamb = -40 to +85oC
VCC = +5.0V ±0.5V
UNIT
Min
Typ
Min
3
2.0
1.0
1.0
0.4
2.0
1.0
ns
Hold time, High or Low
nDx to nLE
3
2.0
2.0
–0.3
–0.7
2.0
2.0
ns
nLE pulse width High
1
2.9
1.9
2.9
ns
ts(H)
ts(L)
Setup time, High or Low
nDx to nLE
th(H)
th(L)
tw(H)
Max
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
VM
nLE
VM
3.0V or VCC
whichever
is less
VM
3.0V or VCC
whichever
is less
nOE
VM
VM
0V
0V
tPZH
tw(H)
tPHZ
tPLH
tPHL
VOH
VOH
VM
nQx
VY
VM
VM
nQx
0V
VOL
SH00007
SA00078
Waveform 4. 3–State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 1. Propagation Delay, Latch Enable Input to
Output, and Enable Pulse Width
3.0V or VCC
whichever
is less
nOE
VM
nDx INPUT
3.0V or VCC
whichever
is less
VM
VM
0V
tPZL
0V
tPLH
VM
Waveform 5. 3–State Output Enable Time to Low Level and
Output Disable Time from Low Level
Waveform 2. Propagation Delay for Data to Outputs
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉ
VM
VM
3.0V or VCC
whichever
is less
VM
0V
ts(H)
nLE
th(H)
VM
ts(L)
th(L)
VM
3.0V or VCC
whichever
is less
0V
NOTE: The shaded areas indicate when the input is
permitted to change for predictable output performance.
SA00080
Waveform 3. Data Setup and Hold Times
1998 Feb 27
0V
SH00008
SA00079
VM
VX
VOL
0V
nDx
3.0V or VCC
VM
3.0V or VCC
whichever
is less
VM
tPLZ
nQx
tPHL
nQx OUTPUT
VM
6
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
TEST CIRCUIT AND WAVEFORM
VCC
7.0V
PULSE
GENERATOR
VIN
tW
90%
VOUT
VM
NEGATIVE
PULSE
10%
0V
tTHL (tF)
CL
tTLH (tR)
tTLH (tR)
RL
tTHL (tF)
90%
POSITIVE
PULSE
Test Circuit for 3-State Outputs
AMP (V)
90%
VM
VM
10%
10%
tW
SWITCH POSITION
TEST
SWITCH
tPLZ
closed
tPZL
closed
All other
open
0V
VM = 1.5V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
AMP (V)
VM
10%
RL
D.U.T.
RT
90%
FAMILY
74ABT/H16
Amplitude
Rep. Rate
tW
tR
tF
3.0V
1MHz
500ns
2.5ns
2.5ns
SA00018
1998 Feb 27
7
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
1998 Feb 27
8
SOT371-1
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
1998 Feb 27
9
SOT364-1
Philips Semiconductors
Product specification
74ABT16841A
74ABTH16841A
20-bit bus interface latch (3-State)
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
yyyy mmm dd
10
Date of release: 05-96
9397-750-03506
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