BSI BH62UV1600AIG70 Ultra low power/high speed cmos sram 2m x 8 bit Datasheet

Ultra Low Power/High Speed CMOS SRAM
2M X 8 bit
BSI
BH62UV1600
n FEATURES
n DESCRIPTION
Ÿ Wide VCC low operation voltage : 1.65V ~ 3.6V
Ÿ Ultra low power consumption :
VCC = 3.0V
Operation current : 5.0mA at 70ns at 25OC
1.5mA at 1MHz at 25OC
Standby current : 3uA at 25OC
VCC = 2.0V
Data retention current : 3uA at 25OC
Ÿ High speed access time :
-70
70ns at 1.8V at 85OC
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation, no clock, no refreash
Ÿ Data retention supply voltage as low as 1.0V
The BH62UV1600 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 2,048K by 8 bits and operates in
a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical operating current of 1.5mA at
1MHz at 3.6V/25OC and maximum access time of 70ns at 1.8V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH62UV1600 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BH62UV1600 is made with two chips of 8Mbit SRAM by stacked
multi-chip-package.
The BH62UV1600 is available 48-ball BGA package.
n PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
VCC
RANGE
VCC=1.8~3.6V
+0OC to +70OC
BH62UV1600AI
2
3
4
5
6
NC
OE
A0
A1
A2
CE2
NC
A3
A4
CE1
DQ0
NC
A5
A6
NC
D04
D
VSS
DQ1
A17
A7
DQ5
VCC
F
G
H
VCC
D3
NC
A18
DQ2
NC
A20
A8
VSS
A14
A12
A9
PKG TYPE
VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V
70
20uA
15uA
10mA
7mA
70
25uA
20uA
10mA
7mA
A16
A15
A13
A10
DQ6
NC
WE
A11
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
NC
C
E
(ICC, Max)
n BLOCK DIAGRAM
1
NC
Operating
(ICCSB1, Max)
BGA-48-0608
n PIN CONFIGURATIONS
B
STANDBY
1.65V ~ 3.6V
-25OC to +85OC
A
POWER CONSUMPTION
SPEED
(ns)
Address
1024
10
Input
Row
Buffer
Decoder
Memory Array
1024 x 16384
16384
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSS
DQ7
NC
CE1
CE2
WE
OE
VCC
GND
A19
8
8
Data
Input
Buffer
Data
Output
Buffer
8
Column I/O
Write Driver
Sense Amp
8
2048
Column Decoder
11
Control
Address Input Buffer
A20 A19 A18 A17 A15 A14 A13 A16 A2 A1 A0
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH62UV1600
1
Revision 1.0
Jul.
2005
BSI
BH62UV1600
n PIN DESCRIPTIONS
Name
Function
A0-A20 Address Input
These 21 address inputs select one of the 2,048K x 8 bit in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
VCC
8 bi-directional ports are used to read data from or write data into the RAM.
VSS
Ground
Power Supply
n TRUTH TABLE
MODE
CE1
CE2
WE
OE
I/O OPERATION
VCC CURRENT
Chip De-selected
(Power Down)
H
X
X
X
X
L
X
X
High Z
ICCSB, ICCSB1
Output Disabled
L
H
H
H
High Z
ICC
Read
L
H
H
L
DOUT
ICC
Write
L
H
L
X
DIN
ICC
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
n ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
TBIAS
TSTG
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
(1)
RATING
(2)
-0.5
to 4.6V
n OPERATING RANGE
UNITS
RANG
AMBIENT
TEMPERATURE
VCC
V
Commercial
0OC to + 70OC
1.65V ~ 3.6V
-40 to +125
O
C
-60 to +150
O
C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
Industrial
n CAPACITANCE
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
2. –2.0V in case of AC pulse width less than 30 ns
R0201-BH62UV1600
O
O
-25 C to + 85 C
(1)
1.65V ~ 3.6V
O
(TA = 25 C, f = 1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
Input
VIN = 0V
10
Capacitance
Input/Output
CIO
VI/O = 0V
15
Capacitance
1. This parameter is guaranteed and not 100% tested.
CIN
2
pF
pF
Revision 1.0
Jul.
2005
BSI
BH62UV1600
O
O
n DC ELECTRICAL CHARACTERISTICS (TA = -25 C to +85 C)
PARAMETER
NAME
PARAMETER
VCC
Power Supply
VIL
Input Low Voltage
TEST CONDITIONS
VCC=1.8V
MIN.
TYP.(1)
MAX.
UNITS
1.65
--
3.6
V
-0.3(2)
--
VCC=3.6V
VIH
Input High Voltage
Input Leakage Current
ILO
Output Leakage Current
VOL
Output Low Voltage
Operating
Current
ICCSB
1.
2.
3.
4.
5.
CE1 = VIH or CE2 = VIL or OE = VIH
Supply
Operating Power Supply
Current
ICC1
ICCSB1
Power
(5)
2.0
VI/O = 0V to V CC,
Output High Voltage
ICC
1.4
VCC=3.6V
VIN = 0V to VCC,
CE1 = VIH or CE2 = VIL
IIL
VOH
VCC=1.8V
Standby Current – CMOS
VCC+0.3(3)
V
--
--
1
uA
--
--
1
uA
--
--
VCC=1.8V
V CC = Max, IOL = 2.0mA
VCC=3.6V
V CC = Min, IOH = -0.1mA
VCC=1.8V
VCC-0.2
V CC = Min, IOH = -1.0mA
VCC=3.6V
2.4
CE1 = VIL, CE2 = VIH,
IDQ = 0mA, f = FMAX(4)
VCC=1.8V
CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = 1MHz
VCC=1.8V
--
VCC=3.6V
--
VCC=3.6V
VCC=1.8V
--
--
0.2
0.4
--
4.5
7
5.0
10
1.0
1.5
1.5
2.0
--
VCC=3.6V
VCC=1.8V
V
0.8
--
V CC = Max, IOL = 0.1mA
CE1 = VIH, or CE2 = VIL,
IDQ = 0mA
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧V CC-0.2V or VIN≦0.2V
Standby Current – TTL
0.4
0.5
1.0
V
V
mA
mA
mA
3.0
20
3.0
25
MIN.
TYP. (1)
MAX.
UNITS
1.0
--
--
V
1.0
7.0
3.0
20
0
--
--
ns
tRC (2)
--
--
ns
--
VCC=3.6V
uA
Typical characteristics are at TA=25OC.
Undershoot: -1.0V in case of pulse width less than 20 ns.
Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
FMAX=1/tRC.
ICCSB1(MAX.) is 15uA/20uA at VCC=1.8V/3.6V and TA=0OC ~ 70OC.
O
O
n DATA RETENTION CHARACTERISTICS (TA = -25 C to +85 C)
SYMBOL
VDR
(3)
ICCDR
tCDR
tR
PARAMETER
TEST CONDITIONS
VCC for Data Retention
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
Data Retention Current
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
Chip Deselect to Data
Retention Time
VCC=1.0V
--
VCC=2.0V
uA
See Retention Waveform
Operation Recovery Time
O
1. TA=25 C.
2. tRC = Read Cycle Time.
3. ICCDR(MAX.) is 6.0uA/15uA at VCC=1.0V/2.0V and TA=0OC ~ 70OC.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
VCC
VCC
VDR≧1.0V
tCDR
CE1
R0201-BH62UV1600
VIH
VCC
tR
CE1≧VCC - 0.2V
3
VIH
Revision 1.0
Jul.
2005
BSI
BH62UV1600
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
VDR≧1.0V
VCC
VCC
VCC
tCDR
tR
CE2≦0.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
VCC / 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
tCLZ1, tCLZ2, tOLZ, tCHZ1,
tCHZ2, tOHZ, tWHZ, tOW
Output Load
WAVEFORM
0.5Vcc
CL = 5pF+1TTL
Others
Output
CL(1)
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
WILL BE CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
CL = 30pF+1TTL
ALL INPUT PULSES
1 TTL
INPUTS
VCC
GND
90%
90%
10%
→ ←
Rise Time:
1V/ns
10%
→ ←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
O
O
n AC ELECTRICAL CHARACTERISTICS (TA = -25 C to +85 C)
READ CYCLE
JEDEC
PARAMETER
NAME
PARANETER
NAME
tAVAX
tRC
tAVQX
tAA
CYCLE TIME : 70ns
DESCRIPTION
Read Cycle Time
Address Access Time
tE1LQV
tACS1
Chip Select Access Time
tE2LQV
tACS2
Chip Select Access Time
tGLQV
tOE
UNITS
MIN.
TYP.
MAX.
70
--
--
ns
--
--
70
ns
(CE1)
--
--
70
ns
(CE2)
--
--
70
ns
Output Enable to Output Valid
--
--
30
ns
(CE1)
10
--
--
ns
(CE2)
10
--
--
ns
5
--
--
ns
tE1LQX
tCLZ1
Chip Select to Output Low Z
tE2LQX
tCLZ2
Chip Select to Output Low Z
tGLQX
tOLZ
Output Enable to Output Low Z
tE1HQZ
tCHZ1
Chip Select to Output High Z
(CE1)
--
--
25
ns
tE2HQZ
tCHZ2
Chip Select to Output High Z
(CE2)
--
--
25
ns
tGHQZ
tOHZ
Output Enable to Output High Z
--
--
25
ns
tAVQX
tOH
Data Hold from Address Change
10
--
--
ns
R0201-BH62UV1600
4
Revision 1.0
Jul.
2005
BSI
BH62UV1600
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
READ CYCLE 2
(1,3,4)
CE1
tACS1
CE2
tACS2
tCLZ
tCHZ1, tCHZ2
(5)
(5)
DOUT
READ CYCLE 3
(1, 4)
tRC
ADDRESS
tAA
OE
tOH
tOE
tOLZ
CE1
(5)
tACS1
tCLZ1
CE2
tOHZ
(5)
tCHZ1
(1,5)
tCHZ2
(2,5)
tACS2
(5)
tCLZ2
DOUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BH62UV1600
5
Revision 1.0
Jul.
2005
BSI
BH62UV1600
O
O
n AC ELECTRICAL CHARACTERISTICS (TA = -25 C to +85 C)
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARANETER
NAME
tAVAX
tWC
tAVWL
CYCLE TIME : 70ns
DESCRIPTION
UNITS
MIN.
TYP.
MAX.
Write Cycle Time
70
--
--
ns
tAS
Address Set up Time
0
--
--
ns
tAVWH
tAW
Address Valid to End of Write
50
--
--
ns
tELWH
tCW
Chip Select to End of Write
50
--
--
ns
tWLWH
tWP
Write Pulse Width
35
--
--
ns
tWHAX
tWR1
Write Recovery Time
(CE1, WE)
0
--
--
ns
tE2LAX
tWR2
Write Recovery Time
(CE2)
0
--
--
ns
tWLQZ
tWHZ
Write to Output High Z
--
--
20
ns
tDVWH
tDW
Data to Write Time Overlap
30
--
--
ns
tWHDX
tDH
Data Hold from Write Time
0
--
--
ns
tGHQZ
tOHZ
Output Disable to Output in High Z
--
--
25
ns
tWHQX
tOW
End of Write to Output Active
5
--
--
ns
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1
(1)
tWC
ADDRESS
tWR1
(3)
tWR2
(3)
OE
tCW
CE1
(5)
CE2
(5)
tAW
WE
(11)
tWP
tAS
tOHZ
tCW
(11)
(2)
(4,10)
DOUT
tDH
tDW
DIN
R0201-BH62UV1600
6
Revision 1.0
Jul.
2005
BSI
WRITE CYCLE 2
BH62UV1600
(1,6)
tWC
ADDRESS
(5)
CE1
CE2
tCW
(11)
tCW
(11)
(5)
tAW
tWP
WE
tAS
tWHZ
tWR2
(2)
(3)
(4,10)
tOW
(7)
(8)
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of the signal
that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11. tCW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BH62UV1600
7
Revision 1.0
Jul.
2005
BSI
BH62UV1600
n ORDERING INFORMATION
BH62UV1600
X
X
Z
YY
SPEED
70: 70ns
PKG MATERIAL
-: Normal
G: Green
GRADE
I: -25oC ~ +85oC
PACKAGE
A: BGA-48-0608
Note:
Brilliance Semiconductor Inc. (BSI) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not
authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in
significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
1.4 Max.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
E1
e
D1
VIEW A
48 mini-BGA (6 x 8)
R0201-BH62UV1600
8
Revision 1.0
Jul.
2005
BSI
BH62UV1600
n Revision History
Revision No.
History
Draft Date
Remark
1.0
Initial Production Version
July 15,2005
Initial
R0201-BH62UV1600
9
Revision 1.0
Jul.
2005
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