High Performance Narrow-Band Transceiver IC ADF7021 Data Sheet FEATURES On-chip VCO and fractional-N PLL On-chip, 7-bit ADC and temperature sensor Fully automatic frequency control loop (AFC) Digital received signal strength indication (RSSI) Integrated Tx/Rx switch 0.1 µA leakage current in power-down mode Low power, narrow-band transceiver Frequency bands using dual VCO 80 MHz to 650 MHz 862 MHz to 950 MHz Modulation schemes 2FSK, 3FSK, 4FSK, MSK Spectral shaping Gaussian and raised cosine filtering Data rates supported 0.05 kbps to 32.8 kbps 2.3 V to 3.6 V power supply Programmable output power −16 dBm to +13 dBm in 63 steps Automatic PA ramp control Receiver sensitivity −130 dBm at 100 bps, 2FSK −122 dBm at 1 kbps, 2FSK −113 dBm at 25 kbps, raised cosine 2FSK Patent pending, on-chip image rejection calibration APPLICATIONS Narrow-band standards ETSI EN 300 220, FCC Part 15, FCC Part 90, FCC Part 95, ARIB STD-T67 Low cost, wireless data transfer Remote control/security systems Wireless metering Private mobile radio Wireless medical telemetry service (WMTS) Keyless entry Home automation Process and building control Pagers FUNCTIONAL BLOCK DIAGRAM CE RSET TEMP SENSOR RLNA MUX 2FSK 3FSK 4FSK RSSI/ LOG AMP IF FILTER RFINB MUXOUT LDO(1:4) TEST MUX 7-BIT ADC LNA RFIN CREG(1:4) CLOCK AND DATA RECOVERY DEMODULATOR TxRxCLK Tx/Rx CONTROL TxRxDATA SWD GAIN AGC CONTROL SLE SERIAL PORT AFC CONTROL PA RAMP DIV P VCO1 VCO2 VCOIN SCLK GAUSSIAN/ RAISED COSINE FILTER 3FSK ENCODING CP PFD DIV R L2 2FSK 3FSK 4FSK MOD CONTROL Σ-Δ MODULATOR ÷2 MUX L1 N/N + 1 SREAD CPOUT CLK DIV OSC OSC1 OSC2 CLKOUT 05876-001 ÷1/÷2 RFOUT SDATA Figure 1. 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Technical Support www.analog.com ADF7021 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Receiver Setup............................................................................. 34 Applications ....................................................................................... 1 Demodulator Considerations ................................................... 36 Functional Block Diagram .............................................................. 1 AFC Operation ........................................................................... 36 Revision History ............................................................................... 3 Automatic Sync Word Detection (SWD) ................................ 37 General Description ......................................................................... 4 Applications Information .............................................................. 38 Specifications..................................................................................... 5 IF Filter Bandwidth Calibration ............................................... 38 RF and PLL Specifications........................................................... 5 LNA/PA Matching ...................................................................... 38 Transmission Specifications ........................................................ 6 Image Rejection Calibration ..................................................... 39 Receiver Specifications ................................................................ 8 Packet Structure and Coding .................................................... 41 Digital Specifications ................................................................. 10 Programming After Initial Power-Up ..................................... 41 General Specifications ............................................................... 11 Applications Circuit ................................................................... 44 Timing Characteristics .............................................................. 11 Serial Interface ................................................................................ 45 Absolute Maximum Ratings.......................................................... 15 Readback Format........................................................................ 45 ESD Caution ................................................................................ 15 Interfacing to Microcontroller/DSP ........................................ 46 Pin Configuration and Function Descriptions ........................... 16 Register 0—N Register............................................................... 47 Typical Performance Characteristics ........................................... 18 Register 1—VCO/Oscillator Register ...................................... 48 Frequency Synthesizer ................................................................... 22 Register 2—Transmit Modulation Register ............................ 49 Reference Input ........................................................................... 22 Register 3—Transmit/Receive Clock Register ........................ 50 MUXOUT.................................................................................... 23 Register 4—Demodulator Setup Register ............................... 51 Voltage Controlled Oscillator (VCO) ...................................... 24 Register 5—IF Filter Setup Register ......................................... 52 Choosing Channels for Best System Performance ................. 25 Register 6—IF Fine Cal Setup Register ................................... 53 Transmitter ...................................................................................... 26 Register 7—Readback Setup Register ...................................... 54 RF Output Stage .......................................................................... 26 Register 8—Power-Down Test Register .................................. 55 Modulation Schemes .................................................................. 26 Register 9—AGC Register ......................................................... 56 Spectral Shaping ......................................................................... 28 Register 10—AFC Register ....................................................... 57 Modulation and Filtering Options ........................................... 29 Register 11—Sync Word Detect Register ................................ 58 Transmit Latency ........................................................................ 29 Register 12—SWD/Threshold Setup Register ........................ 58 Test Pattern Generator ............................................................... 29 Register 13—3FSK/4FSK Demod Register ............................. 59 Receiver Section .............................................................................. 30 Register 14—Test DAC Register ............................................... 60 RF Front End ............................................................................... 30 Register 15—Test Mode Register ............................................. 61 IF Filter......................................................................................... 30 Outline Dimensions ....................................................................... 62 RSSI/AGC .................................................................................... 31 Ordering Guide .......................................................................... 62 Demodulation, Detection, and CDR ....................................... 32 Rev. B | Page 2 of 64 Data Sheet ADF7021 REVISION HISTORY 4/13—Rev. A to Rev. B Changes to Figure 10 ......................................................................16 Updated Outline Dimensions ........................................................62 Changes to Ordering Guide ...........................................................62 9/07—Rev. 0 to Rev. A Change to UART/SPI Mode Section.............................................14 Changes to Figure 10 ......................................................................16 Change to Table 8 ............................................................................16 Changes to Figure 12 ......................................................................18 Change to Internal Inductor VCO Section ..................................24 Changes to Figure 40 ......................................................................26 Changes to Figure 47 ......................................................................32 Change to Table 19 ..........................................................................34 Changes to Figure 56 ......................................................................44 Change to SPI Mode Section .........................................................46 Changes to Figure 59 ......................................................................46 Changes to Figure 60 ......................................................................46 Change to Register 3—Transmit/Receive Clock Register Section ............................................................................... 50 Change to Register 4—Demodulator Setup Register Section ............................................................................... 51 Change to Register 7—Readback Setup Register ........................ 54 Change to Register 13—3FSK/4FSK Demod Register Heading ............................................................................. 59 3/07—Revision 0: Initial Version Rev. B | Page 3 of 64 ADF7021 Data Sheet GENERAL DESCRIPTION The ADF7021 is a high performance, low power, highly integrated 2FSK/3FSK/4FSK transceiver. It is designed to operate in the narrow-band, license-free ISM bands, and in the licensed bands with frequency ranges of 80 MHz to 650 MHz and 862 MHz to 950 MHz. The part has both Gaussian and raised cosine transmit data filtering options to improve spectral efficiency for narrowband applications. It is suitable for circuit applications targeted at European ETSI EN 300 220, the Japanese ARIB STD-T67, the Chinese short range device regulations, and the North American FCC Part 15, Part 90, and Part 95 regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7021 very suitable for price sensitive and area sensitive applications. The range of on-chip FSK modulation and data filtering options allows users greater flexibility in their choice of modulation schemes while meeting tight spectral efficiency requirements. The ADF7021 also supports protocols that dynamically switch between 2FSK/3FSK/4FSK to maximize communication range and data throughput. The transmit section contains dual voltage controlled oscillators (VCOs) and a low noise fractional-N PLL with an output resolution of <1 ppm. The ADF7021 has a VCO using an internal LC tank (431 MHz to 475 MHz, 862 MHz to 950 MHz) and a VCO using an external inductor as part of its tank circuit (80 MHz to 650 MHz). The dual VCO design allows dual-band operation where the user can transmit and/or receive at any frequency supported by the internal inductor VCO and can also transmit and/or receive at a particular frequency band supported by the external inductor VCO. The frequency agile PLL allows the ADF7021 to be used in frequency hopping spread spectrum (FHSS) systems. Both VCOs operate at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 63 steps from −16 dBm to +13 dBm, and has an automatic power ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use. A low IF architecture is used in the receiver (100 kHz), which minimizes power consumption and the external component count, yet avoids dc offset and flicker noise at low frequencies. The IF filter has programmable bandwidths of 12.5 kHz, 18.75 kHz, and 25 kHz. The ADF7021 supports a wide variety of programmable features including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop with programmable pull-in range that allows the PLL to track out the frequency error in the incoming signal. The receiver achieves an image rejection performance of 56 dB using a patent-pending IR calibration scheme that does not require the use of an external RF source. An on-chip ADC provides readback of the integrated temperature sensor, external analog input, battery voltage, and RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ±10°C over the full operating temperature range of −40°C to +85°C. This accuracy can be improved by performing a 1-point calibration at room temperature and storing the result in memory. Rev. B | Page 4 of 64 Data Sheet ADF7021 SPECIFICATIONS VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C. All measurements are performed with the EVAL-ADF7021DBx using the PN9 data sequence, unless otherwise noted. RF AND PLL SPECIFICATIONS Table 1. Parameter RF CHARACTERISTICS Max Unit 650 950 325 475 26/30 MHz MHz MHz MHz MHz Test Conditions/Comments See Table 9 for required VCO_BIAS and VCO_ADJUST settings External inductor VCO Internal inductor VCO External inductor VCO, RF divide-by-2 enabled Internal inductor VCO, RF divide-by-2 enabled Crystal reference/external reference 58 29 27 6 MHz/V MHz/V MHz/V MHz/V VCO_ADJUST = 0, VCO_BIAS = 8 VCO_ADJUST = 0, VCO_BIAS = 8 VCO_ADJUST = 0, VCO_BIAS = 3 VCO_ADJUST = 0, VCO_BIAS = 2 −97 dBc/Hz 433 MHz, Internal Inductor VCO −103 dBc/Hz 426 MHz, External Inductor VCO −95 dBc/Hz Phase Noise (Out-of-Band) −124 dBc/Hz 10 kHz offset, PA = 10 dBm, VDD = 3.0 V, PFD = 19.68 MHz, VCO_BIAS = 8 10 kHz offset, PA = 10 dBm, VDD = 3.0 V, PFD = 19.68 MHz, VCO_BIAS = 8 10 kHz offset, PA = 10 dBm, VDD = 3.0 V, PFD = 9.84 MHz, VCO_BIAS = 3 1 MHz offset, fRF = 433 MHz, PA = 10 dBm, VDD = 3.0 V, PFD = 19.68 MHz, VCO_BIAS = 8 Normalized In-Band Phase Noise Floor 3 PLL Settling −203 40 dBc/Hz µs Frequency Ranges (Direct Output) Frequency Ranges (RF Divide-by-2 Mode) Phase Frequency Detector (PFD) Frequency 1 PHASE-LOCKED LOOP (PLL) VCO Gain 2 868 MHz, Internal Inductor VCO 434 MHz, Internal Inductor VCO 426 MHz, External Inductor VCO 160 MHz, External Inductor VCO Phase Noise (In-Band) 868 MHz, Internal Inductor VCO REFERENCE INPUT Crystal Reference 4 External Oscillator4, 5 Crystal Start-Up Time 6 XTAL Bias = 20 µA XTAL Bias = 35 µA Input Level for External Oscillator 7 OSC1 OSC2 ADC PARAMETERS INL DNL Min Typ 160 862 80 431 RF/256 3.625 3.625 26 30 Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 19.68 MHz, loop bandwidth (LBW) = 100 kHz MHz MHz 0.930 0.438 ms ms 10 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V 10 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V 0.8 CMOS levels V p-p V Clipped sine wave ±0.4 ±0.4 LSB LSB VDD = 2.3 V to 3.6 V, TA = 25°C VDD = 2.3 V to 3.6 V, TA = 25°C The maximum usable PFD at a particular RF frequency is limited by the minimum N divide value. VCO gain measured at a VCO tuning voltage of 1 V. The VCO gain varies across the tuning range of the VCO. The software package ADIsimPLL™ can be used to model this variation. 3 This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance as seen at the PA output: −203 + 10 log(fPFD) + 20 logN. 4 Guaranteed by design. Sample tested to ensure compliance. 5 A TCXO, VCXO, or OCXO can be used as an external oscillator. 6 Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin. 7 Refer to the Reference Input section for details on using an external oscillator. 1 2 Rev. B | Page 5 of 64 ADF7021 Data Sheet TRANSMISSION SPECIFICATIONS Table 2. Parameter DATA RATE 2FSK, 3FSK 4FSK MODULATION Frequency Deviation (fDEV) 3 Deviation Frequency Resolution Gaussian Filter BT Raised Cosine Filter Alpha TRANSMIT POWER Maximum Transmit Power 4 Transmit Power Variation vs. Temperature Transmit Power Variation vs. VDD Transmit Power Flatness Programmable Step Size ADJACENT CHANNEL POWER (ACP) 426 MHz, External Inductor VCO 12.5 kHz Channel Spacing 25 kHz Channel Spacing 868 MHz, Internal Inductor VCO 12.5 kHz Channel Spacing 25 kHz Channel Spacing 433 MHz, Internal Inductor VCO 12.5 kHz Channel Spacing 25 kHz Channel Spacing Min Typ Max Unit Test Conditions/Comments 0.05 0.05 25 1 32.8 2 kbps kbps IF_BW = 25 kHz IF_BW = 25 kHz 0.056 0.306 56 28.26 156 kHz kHz Hz PFD = 3.625 MHz PFD = 20 MHz PFD = 3.625 MHz 0.5 0.5/0.7 Programmable +13 ±1 dBm dB VDD = 3.0 V, TA = 25°C −40°C to +85°C ±1 ±1 0.3125 dB dB dB 2.3 V to 3.6 V at 915 MHz, TA = 25°C 902 MHz to 928 MHz, 3 V, TA = 25°C −20 dBm to +13 dBm −50 dBc −50 dBc −46 dBm −43 dBm −50 dBm −47 dBm 3.9 9.9 kHz kHz 4.4 10.2 kHz kHz 3.9 9.5 kHz kHz 13.2 kHz OCCUPIED BANDWIDTH 2FSK Gaussian Data Filtering 12.5 kHz Channel Spacing 25 kHz Channel Spacing 2FSK Raised Cosine Data Filtering 12.5 kHz Channel Spacing 25 kHz Channel Spacing 3FSK Raised Cosine Filtering 12.5 kHz Channel Spacing 25 kHz Channel Spacing 4FSK Raised Cosine Filtering 25 kHz Channel Spacing PFD = 9.84 MHz Gaussian 2FSK modulation, measured in a ±4.25 kHz bandwidth at ±12.5 kHz offset, 2.4 kbps PN9 data, 1.2 kHz frequency deviation, compliant with ARIB STD-T67 Gaussian 2FSK modulation, measured in a ±8 kHz bandwidth at ±25 kHz offset, 9.6 kbps PN9 data, 2.4 kHz frequency deviation, compliant with ARIB STD-T67 PFD = 19.68 MHz Gaussian 2FSK modulation, 10 dBm output power, measured in a ±6.25 kHz bandwidth at ±12.5 kHz offset, 2.4 kbps PN9 data, 1.2 kHz frequency deviation, compliant with ETSI EN 300-220 Gaussian 2FSK modulation, 10 dBm output power, measured in a ±12.5 kHz bandwidth at ±25 kHz offset, 9.6 kbps PN9 data, 2.4 kHz frequency deviation, compliant with ETSI EN 300-220 PFD = 19.68 MHz Gaussian 2FSK modulation, 10 dBm output power, measured in a ±6.25 kHz bandwidth at ±12.5 kHz offset, 2.4 kbps PN9 data, 1.2 kHz frequency deviation, compliant with ETSI EN 300-220 Gaussian 2FSK modulation, 10 dBm output power, measured in a ±12.5 kHz bandwidth at ±25 kHz offset, 9.6 kbps PN9 data, 2.4 kHz frequency deviation, compliant with ETSI EN 300-220 99.0% of total mean power; 12.5 kHz channel spacing (2.4 kbps PN9 data, 1.2 kHz frequency deviation); 25 kHz channel spacing (9.6 kbps PN9 data, 2.4 kHz frequency deviation) 19.2 kbps PN9 data, 1.2 kHz frequency deviation Rev. B | Page 6 of 64 Data Sheet Parameter SPURIOUS EMISSIONS Reference Spurs HARMONICS 5 Second Harmonic Third Harmonic All Other Harmonics OPTIMUM PA LOAD IMPEDANCE 6 fRF = 915 MHz fRF = 868 MHz fRF = 450 MHz fRF = 426 MHz fRF = 315 MHz fRF = 175 MHz ADF7021 Min Typ Max Unit Test Conditions/Comments −65 dBc 100 kHz loop bandwidth 13 dBm output power, unfiltered conductive/filtered conductive −35/−52 −43/−60 −36/−65 dBc dBc dBc 39 + j61 48 + j54 98 + j65 100 + j65 129 + j63 173 + j49 Ω Ω Ω Ω Ω Ω Using Gaussian or raised cosine filtering. The frequency deviation should be chosen to ensure that the transmit occupied signal bandwidth is within the receiver IF filter bandwidth. 2 Using raised cosine filtering with an alpha = 0.7. The inner frequency deviation = 1.78 kHz, and the POST_DEMOD_BW = 24.6 kHz. 3 For the definition of frequency deviation, refer to the Register 2—Transmit Modulation Register section. 4 Measured as maximum unmodulated power. 5 Conductive filtered harmonic emissions measured on the EVAL-ADF7021DBx, which includes a T-stage harmonic filter (two inductors and one capacitor). 6 For matching details, refer to the LNA/PA Matching section. 1 Rev. B | Page 7 of 64 ADF7021 Data Sheet RECEIVER SPECIFICATIONS Table 3. Parameter SENSITIVITY Unit Test Conditions/Comments Bit error rate (BER) = 10−3, low noise amplifier (LNA) and power amplifier (PA) matched separately −130 −127 −122 −115 −110 dBm dBm dBm dBm dBm fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz fDEV = 4 kHz, high sensitivity mode, IF_BW = 18.75 kHz fDEV = 10 kHz, high sensitivity mode, IF_BW = 25 kHz −129 −127 −121 −114 −111 dBm dBm dBm dBm dBm fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz fDEV = 4 kHz, high sensitivity mode, IF_BW = 18.75 kHz fDEV = 10 kHz, high sensitivity mode, IF_BW = 25 kHz −113 dBm fDEV = 2.4 kHz, high sensitivity mode, IF_BW = 18.75 kHz −127 −121 −114 −113 dBm dBm dBm dBm fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz fDEV = 4 kHz, high sensitivity mode, IF_BW = 18.75 kHz fDEV = 10 kHz, high sensitivity mode, IF_BW = 25 kHz −110 dBm fDEV = 2.4 kHz, high sensitivity mode, IF_BW = 18.75 kHz, Viterbi detection on −110 dBm −106 dBm fDEV = 2.4 kHz, high sensitivity mode, IF_BW = 12.5 kHz, alpha = 0.5, Viterbi detection on fDEV = 4.8 kHz, high sensitivity mode, IF_BW = 18.75 kHz, alpha = 0.5, Viterbi detection on −112 dBm Sensitivity at 19.6 kbps −107 dBm Raised Cosine 4FSK Sensitivity at 9.6 kbps −109 dBm Sensitivity at 19.2 kbps −103 dBm Sensitivity at 32.8 kbps −100 dBm −3 dBm fDEV (inner) = 1.2 kHz, high sensitivity mode, IF_BW = 12.5 kHz, alpha = 0.5 fDEV (inner) = 1.2 kHz, high sensitivity mode, IF_BW = 18.75 kHz, alpha = 0.5 fDEV (inner) = 1.8 kHz, high sensitivity mode, IF_BW = 25 kHz, alpha = 0.7 Two-tone test, fLO = 860 MHz, F1 = fLO + 100 kHz, F2 = fLO − 800 kHz LNA_GAIN = 3, MIXER_LINEARITY = 1 −13.5 −24 dBm dBm LNA_GAIN = 10, MIXER_LINEARITY = 0 LNA_GAIN = 30, MIXER_LINEARITY = 0 2FSK Sensitivity at 0.1 kbps Sensitivity at 0.25 kbps Sensitivity at 1 kbps Sensitivity at 9.6 kbps Sensitivity at 25 kbps Gaussian 2FSK Sensitivity at 0.1 kbps Sensitivity at 0.25 kbps Sensitivity at 1 kbps Sensitivity at 9.6 kbps Sensitivity at 25 kbps GMSK Sensitivity at 9.6 kbps Raised Cosine 2FSK Sensitivity at 0.25 kbps Sensitivity at 1 kbps Sensitivity at 9.6 kbps Sensitivity at 25 kbps 3FSK Sensitivity at 9.6 kbps Raised Cosine 3FSK Sensitivity at 9.6 kbps Sensitivity at 19.6 kbps 4FSK Sensitivity at 9.6 kbps Min Typ Max INPUT IP3 Low Gain Enhanced Linearity Mode Medium Gain Mode High Sensitivity Mode fDEV (inner) = 1.2 kHz, high sensitivity mode, IF_BW = 12.5 kHz fDEV (inner) = 2.4 kHz, high sensitivity mode, IF_BW = 25 kHz Rev. B | Page 8 of 64 Data Sheet Parameter ADJACENT CHANNEL REJECTION 868 MHz ADF7021 Min 12.5 kHz Channel Spacing 25 kHz Channel Spacing 25 kHz Channel Spacing 426 MHz, External Inductor VCO Typ Max Unit 25 27 39 dB dB dB 12.5 kHz Channel Spacing 25 kHz Channel Spacing 25 kHz Channel Spacing CO-CHANNEL REJECTION 25 30 41 dB dB dB 868 MHz IMAGE CHANNEL REJECTION −3 dB 900 MHz 450 MHz 450 MHz, External Inductor VCO BLOCKING 23/39 29/50 38/53 dB dB dB ±1 MHz ±2 MHz ±5 MHz ±10 MHz SATURATION (MAXIMUM INPUT LEVEL) RSSI Range at Input 2 69 75 78 78.5 12 dB dB dB dB dBm −120 to −47 ±2 ±3 300 dBm Linearity Absolute Accuracy Response Time AFC Pull-In Range Response Time Accuracy Rx SPURIOUS EMISSIONS 3 Internal Inductor VCO External Inductor VCO Test Conditions/Comments Wanted signal is 3 dB above the sensitivity point (BER = 10−3); unmodulated interferer is at the center of the adjacent channel; rejection measured as the difference between interferer level and wanted signal level in dB 12.5 kHz IF_BW 25 kHz IF_BW 18 kHz IF_BW Wanted signal 3 dB above reference sensitivity point (BER = 10−2); modulated interferer (1 kHz sine, ±2 kHz deviation) at the center of the adjacent channel; rejection measured as the difference between interferer level and reference sensitivity level in dB 12.5 kHz IF_BW 25 kHz IF_BW 18 kHz IF_BW, compliant with ARIB STD-T67 Wanted signal (2FSK, 9.6 kbps, ±4 kHz deviation) is 10 dB above the sensitivity point (BER = 10−3), modulated interferer Wanted signal (2FSK, 9.6 kbps, ±4 kHz deviation) is 10 dB above the sensitivity point (BER = 10−3); modulated interferer (2FSK, 9.6 kbps, ±4 kHz deviation) is placed at the image frequency of fRF − 200 kHz; interferer level is increased until BER = 10−3 Uncalibrated/calibrated 1, VDD = 3.0 V, TA = 25°C Uncalibrated/calibrated1,VDD = 3.0 V, TA = 25°C Uncalibrated/calibrated1, VDD = 3.0 V, TA = 25°C Wanted signal is 10 dB above the input sensitivity level; CW interferer level is increased until BER = 10−3 2FSK mode, BER = 10−3 dB dB µs Input power range = −100 dBm to −47 dBm Input power range = −100 dBm to −47 dBm See the RSSI/AGC section kHz Bits kHz The range is programmable, R10_DB[24:31] 48 0.5 −91/−91 dBm −52/−70 dBm −62/−72 dBm −64/−85 dBm <1 GHz at antenna input, unfiltered conductive/filtered conductive >1 GHz at antenna input, unfiltered conductive/filtered conductive <1 GHz at antenna input, unfiltered conductive/filtered conductive >1 GHz at antenna input, unfiltered conductive/filtered conductive 0.5 1.5 × IF_BW Input power range = −100 dBm to +12 dBm Rev. B | Page 9 of 64 ADF7021 Parameter LNA INPUT IMPEDANCE fRF = 915 MHz fRF = 868 MHz fRF = 450 MHz fRF = 426 MHz fRF = 315 MHz fRF = 175 MHz 1 2 3 Data Sheet Min Typ Max Unit 24 − j60 26 − j63 63 − j129 68 − j134 96 − j160 178 − j190 Test Conditions/Comments RFIN to RFGND Ω Ω Ω Ω Ω Ω Calibration of the image rejection used an external RF source. For received signal levels < −100 dBm, it is recommended to average the RSSI readback value over a number of samples to improve the RSSI accuracy at low input powers. Filtered conductive receive spurious emissions measured on the EVAL-ADF7021DBx, which includes a T-stage harmonic filter (two inductors and one capacitor). DIGITAL SPECIFICATIONS Table 4. Parameter TIMING INFORMATION Chip Enabled to Regulator Ready Chip Enabled to Tx Mode TCXO Reference XTAL Chip Enabled to Rx Mode Min Max Unit Test Conditions/Comments 10 µs CREG = 100 nF 32-bit register write time = 50 µs 1 2 ms ms 32-bit register write time = 50 µs, IF filter coarse calibration only TCXO Reference XTAL Tx to Rx Turnaround Time LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN Control Clock Input LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL CLKOUT Rise/Fall CLKOUT Load Typ 1.2 2.2 300 µs + (5 × tBIT) ms ms Time to synchronized data out, includes AGC settling and CDR synchronization; see AGC Information and Timing section for more details; tBIT = data bit period 0.7 × VDD 0.2 × VDD ±1 10 50 V V µA pF MHz 0.4 5 10 V V ns pF DVDD − 0.4 Rev. B | Page 10 of 64 IOH = 500 µA IOL = 500 µA Data Sheet ADF7021 GENERAL SPECIFICATIONS Table 5. Parameter TEMPERATURE RANGE (TA) POWER SUPPLIES Voltage Supply, VDD TRANSMIT CURRENT CONSUMPTION 1 868 MHz 0 dBm 5 dBm 10 dBm 450 MHz, Internal Inductor VCO 0 dBm 5 dBm 10 dBm 426 MHz, External Inductor VCO 0 dBm 5 dBm 10 dBm RECEIVE CURRENT CONSUMPTION 868 MHz Low Current Mode High Sensitivity Mode 433MHz, Internal Inductor VCO Low Current Mode High Sensitivity Mode 426 MHz, External Inductor VCO Low Current Mode High Sensitivity Mode POWER-DOWN CURRENT CONSUMPTION Low Power Sleep Mode 1 Min −40 Typ 2.3 Max +85 Unit °C Test Conditions/Comments 3.6 V All VDD pins must be tied together VDD = 3.0 V, PA is matched into 50 Ω VCO_BIAS = 8 20.2 24.7 32.3 mA mA mA 19.9 23.2 29.2 mA mA mA 13.5 17 23.3 mA mA mA VCO_BIAS = 8 VCO_BIAS = 2 VDD = 3.0 V VCO_BIAS = 8 22.7 24.6 mA mA 24.5 26.4 mA mA 17.5 19.5 mA mA VCO_BIAS = 8 VCO_BIAS = 2 0.1 1 µA CE low The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021DBx evaluation boards. Improved PA efficiency is achieved by using a separate PA matching network. TIMING CHARACTERISTICS VDD = 3 V ± 10%, DGND = AGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design but not production tested. Table 6. Parameter t1 t2 t3 t4 t5 t6 t8 t9 t10 t11 t12 t13 t14 t15 Limit at TMIN to TMAX >10 >10 >25 >25 >10 >20 <25 <25 >10 5 < t11 < (¼ × tBIT) >5 >5 >¼ × tBIT >¼ × tBIT Unit ns ns ns ns ns ns ns ns ns ns ns ns µs µs Test Conditions/Comments SDATA to SCLK setup time SDATA to SCLK hold time SCLK high duration SCLK low duration SCLK to SLE setup time SLE pulse width SCLK to SREAD data valid, readback SREAD hold time after SCLK, readback SCLK to SLE disable time, readback TxRxCLK negative edge to SLE TxRxDATA to TxRxCLK setup time (Tx mode) TxRxCLK to TxRxDATA hold time (Tx mode) TxRxCLK negative edge to SLE SLE positive edge to positive edge of TxRxCLK Rev. B | Page 11 of 64 ADF7021 Data Sheet Timing Diagrams Serial Interface t3 t4 SCLK t1 SDATA DB31 (MSB) t2 DB30 DB1 (CONTROL BIT C2) DB2 DB0 (LSB) (CONTROL BIT C1) t6 05876-002 SLE t5 Figure 2. Serial Interface Timing Diagram t1 t2 SCLK SDATA REG7 DB0 (CONTROL BIT C1) SLE t3 t10 RV16 RV2 RV15 RV1 X 05876-003 X SREAD t9 t8 Figure 3. Serial Interface Readback Timing Diagram 2FSK/3FSK Timing ±1 × DATA RATE/32 1/DATA RATE TxRxCLK TxRxDATA 05876-004 DATA Figure 4. TxRxDATA/TxRxCLK Timing Diagram in Receive Mode 1/DATA RATE TxRxCLK TxRxDATA FETCH 05876-005 DATA SAMPLE Figure 5. TxRxDATA/TxRxCLK Timing Diagram in Transmit Mode Rev. B | Page 12 of 64 Data Sheet ADF7021 4FSK Timing In 4FSK receive mode, MSB/LSB synchronization should be guaranteed by SWD in the receive bit stream. REGISTER 0 WRITE SWITCH FROM Rx TO Tx tSYMBOL t13 t12 t11 tBIT SLE TxRxCLK Rx SYMBOL MSB Rx SYMBOL LSB Rx SYMBOL MSB Rx SYMBOL LSB Tx SYMBOL MSB Tx SYMBOL LSB Rx MODE Tx/Rx MODE Tx SYMBOL MSB Tx MODE 05876-074 TxRxDATA Figure 6. Receive-to-Transmit Timing Diagram in 4FSK Mode REGISTER 0 WRITE SWITCH FROM Tx TO Rx t15 tSYMBOL t14 tBIT SLE TxRxCLK Tx/Rx MODE Tx SYMBOL MSB Tx SYMBOL LSB Tx SYMBOL MSB Tx SYMBOL LSB Tx MODE Figure 7. Transmit-to-Receive Timing Diagram in 4FSK Mode Rev. B | Page 13 of 64 Rx SYMBOL MSB Rx SYMBOL LSB Rx MODE 05876-075 TxRxDATA ADF7021 Data Sheet UART/SPI Mode UART mode is enabled by setting R0_DB28 to 1. SPI mode is enabled by setting R0_DB28 to 1 and setting R15_DB[17:19] to 0x7. The transmit/receive data clock is available on the CLKOUT pin. tBIT CLKOUT (TRANSMIT/RECEIVE DATA CLOCK IN SPI MODE. NOT USED IN UART MODE.) Tx BIT SAMPLE Tx BIT TxRxDATA (RECEIVE DATA OUTPUT IN UART/SPI MODE.) Tx BIT Tx BIT Tx BIT HIGH-Z Tx/Rx MODE 05876-082 TxRxCLK (TRANSMIT DATA INPUT IN UART/SPI MODE.) FETCH Tx MODE Figure 8. Transmit Timing Diagram in UART/SPI Mode tBIT CLKOUT (TRANSMIT/RECEIVE DATA CLOCK IN SPI MODE. NOT USED IN UART MODE.) FETCH SAMPLE TxRxCLK (TRANSMIT DATA INPUT IN UART/SPI MODE.) Tx/Rx MODE Rx BIT Rx BIT Rx BIT Rx BIT Rx MODE Figure 9. Receive Timing Diagram in UART/SPI Mode Rev. B | Page 14 of 64 Rx BIT 05876-078 TxRxDATA (RECEIVE DATA OUTPUT IN UART/SPI MODE.) HIGH-Z Data Sheet ADF7021 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to GND1 Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature MLF θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature 1 Rating −0.3 V to +5 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 26°C/W 260°C 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION GND = CPGND = RFGND = DGND = AGND = 0. Rev. B | Page 15 of 64 ADF7021 Data Sheet 48 47 46 45 44 43 42 41 40 39 38 37 CVCO GND1 L1 GND L2 VDD CPOUT CREG3 VDD3 OSC1 OSC2 MUXOUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADF7021 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 CLKOUT TxRxCLK TxRxDATA SWD VDD2 CREG2 ADCIN GND2 SCLK SREAD SDATA SLE NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GND. 05876-006 MIX_I MIX_I MIX_Q MIX_Q FILT_I FILT_I GND4 FILT_Q FILT_Q GND4 TEST_A CE 13 14 15 16 17 18 19 20 21 22 23 24 VCOIN 1 CREG1 2 VDD1 3 RFOUT 4 RFGND 5 RFIN 6 RFINB 7 RLNA 8 VDD4 9 RSET 10 CREG4 11 GND4 12 Figure 10. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 Mnemonic VCOIN 2 CREG1 3 VDD1 4 RFOUT 5 6 RFGND RFIN 7 8 9 10 11 RFINB RLNA VDD4 RSET CREG4 12, 19, 22 13 to 18 24 GND4 MIX_I, MIX_I, MIX_Q, MIX_Q, FILT_I, FILT_I FILT_Q, FILT_Q, TEST_A CE 25 SLE 26 SDATA 27 SREAD 28 SCLK 20, 21, 23 Description The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and ground for regulator stability and noise rejection. Voltage Supply for PA Block. Place decoupling capacitors of 0.1 μF and 100 pF as close as possible to this pin. Tie all VDD pins together. The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The output should be impedance matched to the desired load using suitable components (see the Transmitter section). Ground for Output Stage of Transmitter. All GND pins should be tied together. LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer (see the LNA/PA Matching section). Complementary LNA Input (see the LNA/PA Matching section). External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance. Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor. External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with 5% tolerance. Regulator Voltage for LNA/MIXER Block. Place a 100 nF capacitor between this pin and GND for regulator stability and noise rejection. Ground for LNA/MIXER Block. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Chip Enable. Bringing CE low puts the ADF7021 into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed once CE is brought high. Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of the four latches. A latch is selected using the control bits. Serial Data Input. The serial data is loaded MSB first with the 4 LSBs as the control bits. This pin is a high impedance CMOS input. Serial Data Output. This pin is used to feed readback data from the ADF7021 to the microcontroller. The SCLK input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 32-bit shift register on the CLK rising edge. This pin is a digital CMOS input. Rev. B | Page 16 of 64 Data Sheet Pin No. 29 30 Mnemonic GND2 ADCIN 31 CREG2 32 33 VDD2 SWD 34 TxRxDATA 35 TxRxCLK 36 CLKOUT 37 MUXOUT 38 OSC2 39 OSC1 40 41 VDD3 CREG3 42 CPOUT 43 44, 46 VDD L2, L1 45, 47 48 49 GND, GND1 CVCO EPAD ADF7021 Description Ground for Digital Section. Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to 1.9 V. Readback is made using the SREAD pin. Regulator Voltage for Digital Block. Place a 100 nF capacitor between this pin and ground for regulator stability and noise rejection. Voltage Supply for Digital Block. Place a decoupling capacitor of 10 nF as close as possible to this pin. Sync Word Detect. The ADF7021 asserts this pin when it has found a match for the sync word sequence (see the Register 11—Sync Word Detect Register section). This provides an interrupt for an external microcontroller indicating valid data is being received. Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply. In UART/SPI mode, this pin provides an output for the received data in receive mode. In transmit UART/SPI mode, this pin is high impedance (see the Interfacing to Microcontroller/DSP section). Outputs the data clock in both receive and transmit modes. This is a digital pin and normal CMOS levels apply. The positive clock edge is matched to the center of the received data. In transmit mode, this pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. In UART/SPI mode, this pin is used to input the transmit data in transmit mode. In receive UART/SPI mode, this pin is high impedance (see the Interfacing to Microcontroller/DSP section). A divided-down version of the crystal reference with output driver. The digital clock output can be used to drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio and is inverted with respect to the reference. Place a series 1 kΩ resistor as close as possible to the pin in applications where the CLKOUT feature is being used. Provides the DIGITAL_LOCK_DETECT Signal. This signal is used to determine if the PLL is locked to the correct frequency. It also provides other signals such as REGULATOR_READY, which is an indicator of the status of the serial interface regulator (see the MUXOUT section for more information). Connect the reference crystal between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the internal crystal oscillator. Connect the reference crystal between this pin and OSC2. A TCXO reference can be used by driving this pin with ac-coupled 0.8 V p-p levels and by enabling the internal crystal oscillator. Voltage Supply for the Charge Pump and PLL Dividers. Decouple this pin to ground with a 10 nF capacitor. Regulator Voltage for Charge Pump and PLL Dividers. Place a 100 nF capacitor between this pin and ground for regulator stability and noise rejection. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Voltage Supply for VCO Tank Circuit. Decouple this pin to ground with a 10 nF capacitor. External VCO Inductor Pins. If using an external VCO inductor, connect a chip inductor across these pins to set the VCO operating frequency. If using the internal VCO inductor, these pins can be left floating. See the Voltage Controlled Oscillator (VCO) section for more information. Grounds for VCO Block. Place a 22 nF capacitor between this pin and CREG1 to reduce VCO noise. Exposed Pad. The exposed pad must be connected to GND. Rev. B | Page 17 of 64 ADF7021 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS –70 PHASE NOISE (dBc/Hz) ICP = 0.8mA –90 DR = 9.6kbps DATA = PRBS9 RF FREQ = 900MHz VDD = 2.3V TEMPERATURE = 25°C VCO BIAS = 8 VCO ADJUST = 3 –80 fDEV = 2.4kHz RF FREQ = 869.5MHz ICP = 1.4mA FSK –100 GFSK –110 ICP = 2.2mA –120 –130 1 10 100 1000 10000 FREQUENCY OFFSET (MHz) CENTER 869.5 25MHz RES BW 300Hz VBW 300Hz Figure 14. Output Spectrum in 2FSK and GFSK Modes Figure 11. Phase Noise Response at 900 MHz, VDD = 2.3 V 16 8 PA BIAS = 9µA 4 0 PA BIAS = 5µA –4 2FSK PA BIAS = 7µA –8 –12 –16 –20 –24 RC2FSK –28 –32 0 4 8 05876-051 –40 12 16 20 24 28 32 36 40 44 48 52 56 60 PA SETTING Figure 12. RF Output Power vs. PA Setting 1R CENTER 869.5 25MHz RES BW 300Hz VBW 300Hz SPAN 50kHz SWEEP 2.118s (601pts) 05876-048 –36 Figure 15. Output Spectrum in 2FSK and Raised Cosine 2FSK Modes RF FREQ = 440MHz OUTPUT POWER = 10dBm FILTER = T-STAGE LC FILTER MARKER Δ = 52.2dB SR = 4.8ksym/s DATA = PRBS9 fDEV = 2.4kHz RF FREQ = 869.5MHz 4FSK 1 START 300MHz RES BW 100Hz STOP 3.5GHz VBW 100Hz SWEEP 385.8ms (601pts) CENTER 869.493 8MHz RES BW 300Hz Figure 13. PA Output Harmonic Response with T-Stage LC Filter VBW 300Hz SPAN 100kHz SWEEP 4.237s (601pts) 05876-049 RC4FSK 05876-050 RF OUTPUT POWER (dBm) DR = 9.6kbps DATA = PRBS9 fDEV = 2.4kHz RF FREQ = 869.5MHz PA BIAS = 11µA 12 SPAN 50kHz SWEEP 2.118s (601pts) 05876-047 –150 05876-060 –140 Figure 16. Output Spectrum in 4FSK and Raised Cosine 4FSK Modes Rev. B | Page 18 of 64 Data Sheet ADF7021 REF 15dBm SAMP LOG 10dB/ 0 ATTEN 25dB DR = 9.6kbps DATA = PRS9 fDEV = 2.4kHz RF FREQ = 869.5MHz DATA RATE = 1kbps fDEV = 1kHz RF FREQ = 135MHz IF BW = 12.5kHz –1 –2 VAVG 100 V1 V2 S3 FC LOG BER –3 3FSK 3.0V, +25°C 2.3V, +85°C –4 –5 3.6V, –40°C RC3FSK –6 VBW 300Hz SPAN 50Hz SWEEP2.226s (401pts) 05876-070 CENTER 869.5MHz RES BW 300Hz –8 –130 –128 –126 –124 –122 –120 –118 –116 –114 –112 –110 –108 RF INPUT POWER (dBm) Figure 20. 2FSK Sensitivity vs. VDD and Temperature, fRF = 135 MHz Figure 17. Output Spectrum in 3FSK and Raised Cosine 3FSK Modes 10 0 TRACE = MAX HOLD PA ON/OFF RATE = 3Hz PA ON/OFF CYCLES = 10000 VDD = 3.0V 3FSK MODULATION DATA RATE = 9.6kbps MOD INDEX = 0.5 RF FREQ = 440 MHz –2 –10 –30 –4 –5 –40 –6 –50 –7 –50 0 50 100 FREQUENCY OFFSET (kHz) –8 –120 0 –2 3.0V, +25°C 3.6V, –40°C fDEV (inner) = 2.4kHz –2 MOD INDEX = 0.5 RF FREQ = 420MHz IF BW = 12.5kHz –4 –6 –6 –7 –7 –118 –116 –114 –112 –110 –108 –106 –104 RF INPUT POWER (dBm) 05876-052 –5 –120 –95 DATA RATE = 19.6kbps SYMBOL RATE = 9.8ksym/s –1 –5 –8 –122 –100 –8 –120 2.3V +25°C 3.0V +25°C 3.6V +25°C 2.3V –40°C 3.0V –40°C 3.6V –40°C 2.3V +85°C 3.0V +85°C 3.6V +85°C –115 –110 –105 –100 –95 RF INPUT POWER (dBm) Figure 22. 4FSK Sensitivity vs. VDD and Temperature, fRF = 420 MHz Figure 19. 2FSK Sensitivity vs. VDD and Temperature, fRF = 868 MHz Rev. B | Page 19 of 64 05876-066 2.3V, +85°C –4 –105 –3 LOG BER –3 –110 Figure 21. 3FSK Sensitivity vs. VDD and Temperature, fRF = 440 MHz DATA RATE = 9.6kbps fDEV = 4kHz RF FREQ = 868MHz IF BW = 25kHz –1 –115 RF INPUT POWER (dBm) Figure 18. Output Spectrum in Maximum Hold for Various PA Ramp Rate Options 0 2.3V +25°C 3.0V +25°C 3.6V +25°C 2.3V –40°C 3.0V –40°C 3.6V –40°C 2.3V +85°C 3.0V +85°C 3.6V +85°C 05876-065 LOG BER –3 –20 –60 –100 LOG BER fDEV = 2.4kHz –1 05876-068 OUTPUT POWER (dBm) 0 RAMP RATE: CW ONLY 256 CODES/BIT 128 CODES/BIT 64 CODES/BIT 32 CODES/BIT 05876-053 –7 ADF7021 Data Sheet 90 –100 80 –102 50 RF FREQ = 868MHz WANTED SIGNAL (10dB ABOVE SENSITIVITY POINT) = 2FSK, fDEV = 4kHz, DATA RATE = 9.8kbps BLOCKER = 2FSK, fDEV = 4kHz, DATA RATE = 9.8kbps VDD = 3.0V TEMPERATURE = 25°C 40 30 20 10 0 –10 –22 –18 –14 –6 –10 –2 0 2 10 6 14 18 22 FREQUENCY OFFSET (MHz) –104 –106 –108 DISCRIMINATOR BANDWIDTH = 2× FSK FREQUENCY DEVIATION –110 –112 –114 –116 DISCRIMINATOR BANDWIDTH = 1× FSK FREQUENCY DEVIATION –118 05876-059 BLOCKING (dB) 60 0 0.2 0.4 0.6 0.8 1.0 1.2 MODULATION INDEX Figure 23. Wideband Interference Rejection 05876-058 SENSITIVITY POINT (dBm) 70 RF FREQ = 860MHz 2FSK MODULATION DATA RATE = 9.6kbps IF BW = 25kHz VDD = 3.0V TEMPERATURE = 25°C Figure 26. 2FSK Sensitivity vs. Modulation Index vs. Correlator Discriminator Bandwidth –20 0 RSSI READBACK LEVEL –40 –1 THRESHOLD DETECTION –60 VITERBI DETECTION LOG BER –100 –4 ACTUAL RF INPUT LEVEL –5 –120 –6 –62.5 –52.5 –42.5 INPUT POWER (dBm) Figure 27. 3FSK Receiver Sensitivity Using Viterbi Detection and Threshold Detection Figure 24. Digital RSSI Readback Linearity CALIBRATED 60 RF FREQ = 430MHz EXTERNAL VCO INDUCTOR DATA RATE = 9.6kbps TEMPERATURE = 25°C, VDD = 3.0V +3 RECEIVER SYMBOL LEVEL 70 40 30 UNCALIBRATED 20 10 +1 0 –1 –3 RF I/P LEVEL = –70dBm DATA RATE = 9.7kbps 0 fDEV (inner) = 1.2kHz RF FREQUENCY (MHz) Figure 25. Image Rejection, Uncalibrated vs. Calibrated 22452 ACQS 05876-054 BLOCKING (dB) 50 –10 429.80 429.85 429.90 429.95 430.00 430.05 430.10 430.15 430.20 TYPICALLY 3dB –7 –120 –118 –116 –114 –112 –110 –108 –106 –104 –102 –100 05876-055 –140 –122.5 –112.5 –102.5 –92.5 –82.5 –72.5 RF INPUT (dBm) 3FSK MODULATION VDD = 3.0V, TEMP = 25°C DATA RATE = 9.6kbps fDEV = 2.4kHz RF FREQ = 868MHz IF BW = 18.75kHz 05876-062 –80 –3 IF BW = 25kHz POST DEMOD BW = 12.4kHz 05876-064 RSSI LEVEL (dBm) –2 M 50µs Figure 28. 4FSK Receiver Eye Diagram Measure Using the Test DAC Output Rev. B | Page 20 of 64 Data Sheet ADF7021 SENSITIVITY (dBm) 0 –90 20834 ACQS IF BW = 12.5kHz POST DEMOD BW = 12.4kHz M 20µs C13 MODULATION = 2FSK DATA RATE = 9.6kbps fDEV = 4kHz IF BW = 12.5kHz DEMOD = CORRELATOR SENSITIVITY @ 1E-3 BER IP3 = –9dBm IP3 = –3dBm IP3 = –20dBm –110 –120 DEFAULT MIXER LINEARITY IP3 = –13.5dBm IP3 = –24dBm –130 1.7V 3, 72 10, 72 30, 72 (LOW GAIN MODE) (MEDIUM GAIN MODE) (HIGH GAIN MODE) LNA GAIN, FILTER GAIN Figure 29. 3FSK Receiver Eye Diagram Measured Using the Test DAC Output 05876-069 RF I/P LEVEL = –70dBm DATA RATE = 10kbps fDEV = 2.5kHz IP3= –5dBm –100 –1 4 HIGH MIXER LINEARITY –80 +1 05876-063 RECEIVER SYMBOL LEVEL –70 Figure 30. Receive Sensitivity vs. LNA/IF Filter Gain and Mixer Linearity Settings (The Input IP3 at Each Setting is Also Shown) Rev. B | Page 21 of 64 ADF7021 Data Sheet FREQUENCY SYNTHESIZER CLKOUT Divider and Buffer The on-board crystal oscillator circuitry (see Figure 31) can use a quartz crystal as the PLL reference. Using a quartz crystal with a frequency tolerance of ≤10 ppm for narrow-band applications is recommended. It is possible to use a quartz crystal with >10 ppm tolerance, but to comply with the absolute frequency error specifications of narrow-band regulations (for example, ARIB STD-T67 and ETSI EN 300-220), compensation for the frequency error of the crystal is necessary. The CLKOUT circuit takes the reference clock signal from the oscillator section, shown in Figure 31, and supplies a divideddown, 50:50 mark-space signal to the CLKOUT pin. The CLKOUT signal is inverted with respect to the reference clock. An even divide from 2 to 30 is available. This divide number is set in R1_DB[7:10]. On power-up, the CLKOUT defaults to divide-by-8. DVDD CLKOUT ENABLE BIT The oscillator circuit is enabled by setting R1_DB12 high. It is enabled by default on power-up and is disabled by bringing CE low. Errors in the crystal can be corrected by using the automatic frequency control feature or by adjusting the fractional-N value (see the N Counter section). 05876-083 CP1 Two parallel resonant capacitors are required for oscillation at the correct frequency. Their values are dependent upon the crystal specification. They should be chosen to make sure that the series value of capacitance added to the PCB track capacitance adds up to the specified load capacitance of the crystal, usually 12 pF to 20 pF. Track capacitance values vary from 2 pF to 5 pF, depending on board layout. When possible, choose capacitors that have a very low temperature coefficient to ensure stable frequency operation over all conditions. Using a TCXO Reference A single-ended reference (TCXO, VCXO, or OCXO) can also be used with the ADF7021. This is recommended for applications having absolute frequency accuracy requirements of <10 ppm, such as ARIB STD-T67 or ETSI EN 300-220. There are two options for interfacing the ADF7021 to an external reference oscillator. • CLKOUT Figure 32. CLKOUT Stage R Counter Figure 31. Oscillator Circuit on the ADF7021 • ÷2 To disable CLKOUT, set the divide number to 0. The output buffer can drive up to a 20 pF load with a 10% rise time at 4.8 MHz. Faster edges can result in some spurious feedthrough to the output. A series resistor (1 kΩ) can be used to slow the clock edges to reduce these spurs at the CLKOUT frequency. OSC2 CP2 DIVIDER 1 TO 15 An oscillator with CMOS output levels can be applied to OSC2. The internal oscillator circuit should be disabled by setting R1_DB12 low. An oscillator with 0.8 V p-p levels can be ac-coupled through a 22 pF capacitor into OSC1. The internal oscillator circuit should be enabled by setting R1_DB12 high. Programmable Crystal Bias Current Bias current in the oscillator circuit can be configured between 20 µA and 35 µA by writing to the XTAL_BIAS bits (R1_DB[13:14]). Increasing the bias current allows the crystal oscillator to power up faster. The 3-bit R counter divides the reference input frequency by an integer of 1 to 7. The divided-down signal is presented as the reference clock to the phase frequency detector (PFD). The divide ratio is set in R1_DB[4:6]. Maximizing the PFD frequency reduces the N value. This reduces the noise multiplied at a rate of 20 log(N) to the output and reduces occurrences of spurious components. Register 1 defaults to R = 1 on power-up. PFD [Hz] = XTAL/R Loop Filter The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by the PLL. A typical loop filter design is shown in Figure 33. CHARGE PUMP OUT VCO 05876-010 OSC1 OSC1 05876-008 REFERENCE INPUT Figure 33. Typical Loop Filter Configuration The loop should be designed so that the loop bandwidth (LBW) is approximately 100 kHz. This provides a good compromise between in-band phase noise and out-of-band spurious rejection. Widening the LBW excessively reduces the time spent jumping between frequencies, but it can cause insufficient spurious attenuation. Narrow-loop bandwidths can result in the loop taking long periods to attain lock and can also result in a higher level of power falling into the adjacent channel. The loop filter design on the EVAL-ADF7021DBX should be used for optimum performance. Rev. B | Page 22 of 64 Data Sheet ADF7021 The free design tool ADIsimPLL can also be used to design loop filters for the ADF7021 (go to www.analog.com/ADIsimPLL for details). must be stabilized. Regulator status (CREG4) can be monitored using the REGULATOR_READY signal from MUXOUT. N Counter The MUXOUT pin allows access to various digital points in the ADF7021. The state of MUXOUT is controlled by R0_DB[29:31]. The feedback divider in the ADF7021 PLL consists of an 8-bit integer counter (R0_DB[19:26]) and a 15-bit Σ-Δ fractional_N divider (R0_DB[4:18]). The integer counter is the standard pulse-swallow type that is common in PLLs. This sets the minimum integer divide value to 23. The fractional divide value provides very fine resolution at the output, where the output frequency of the PLL is calculated as Fractional _ N XTAL Integer _ N R 215 When RF_DIVIDE_BY_2 (see the Voltage Controlled Oscillator (VCO) section) is selected, this formula becomes f OUT REGULATOR_READY REGULATOR_READY is the default setting on MUXOUT after the transceiver is powered up. The power-up time of the regulator is typically 50 μs. Because the serial interface is powered from the regulator, the regulator must be at its nominal voltage before the ADF7021 can be programmed. The status of the regulator can be monitored at MUXOUT. When the regulator ready signal on MUXOUT is high, programming of the ADF7021 can begin. DVDD Fractional _ N XTAL 0.5 Integer_N R 2 15 REGULATOR_READY (DEFAULT) FILTER_CAL_COMPLETE DIGITAL_LOCK_DETECT The combination of the integer_N (maximum = 255) and the fractional_N (maximum = 32,768/32,768) give a maximum N divider of 255 + 1. Therefore, the minimum usable PFD is PFD MIN Hz RSSI_READY Tx_Rx MUX LOGIC_ZERO Maximum Required Output Frequency TRISTATE 255 1 LOGIC_ONE For example, when operating in the European 868 MHz to 870 MHz band, PFDMIN equals 3.4 MHz. DGND Figure 35. MUXOUT Circuit REFERENCE IN 4\R MUXOUT CONTROL 05876-009 f OUT MUXOUT PFD/ CHARGE PUMP FILTER_CAL_COMPLETE VCO MUXOUT can be set to FILTER_CAL_COMPLETE. This signal goes low for the duration of both a coarse IF filter calibration and a fine IF filter calibration. It can be used as an interrupt to a microcontroller to signal the end of the IF filter calibration. 4\N THIRD-ORDER Σ-∆ MODULATOR INTEGER-N 05876-011 FRACTIONAL-N DIGITAL_LOCK_DETECT Figure 34. Fractional-N PLL Voltage Regulators The ADF7021 contains four regulators to supply stable voltages to the part. The nominal regulator voltage is 2.3 V. Regulator 1 requires a 3.9 Ω resistor and a 100 nF capacitor in series between CREG1 and GND, whereas the other regulators require a 100 nF capacitor connected between CREGx and GND. When CE is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 mA. Bringing the CE pin low disables the regulators, reduces the supply current to less than 1 μA, and erases all values held in the registers. The serial interface operates from a regulator supply. Therefore, to write to the part, the user must have CE high and the regulator voltage DIGITAL_LOCK_DETECT indicates when the PLL has locked. The lock detect circuit is located at the PFD. When the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. Lock detect remains high until a 25 ns phase error is detected at the PFD. RSSI_READY MUXOUT can be set to RSSI_READY. This indicates that the internal analog RSSI has settled and a digital RSSI readback can be performed. Tx_Rx Tx_Rx signifies whether the ADF7021 is in transmit or receive mode. When in transmit mode, this signal is low. When in receive mode, this signal is high. It can be used to control an external Tx/Rx switch. Rev. B | Page 23 of 64 ADF7021 Data Sheet To minimize spurious emissions, both VCOs operate at twice the RF frequency. The VCO signal is then divided by 2 inside the synthesizer loop, giving the required frequency for the transmitter and the required local oscillator (LO) frequency for the receiver. A further divide-by-2 (RF_DIVIDE_BY_2) is performed outside the synthesizer loop to allow operation in the 431 MHz to 475 MHz band (internal inductor VCO) and 80 MHz to 325 MHz band (external inductor VCO). The VCO needs an external 22 nF capacitor between the CVCO pin and the regulator (CREG1) to reduce internal noise. VCO BIAS R1_DB(19:22) LOOP FILTER VCO MUX ÷2 TO PA ÷2 CVCO PIN TO N DIVIDER DIVIDE-BY-2 R1_DB18 05876-012 220µF Figure 36. Voltage Controlled Oscillator (VCO) Internal Inductor VCO To select the internal inductor VCO, set R1_DB25 to Logic 0, which is the default setting. VCO bias current can be adjusted using R1_DB[19:22]. To ensure VCO oscillation, the minimum bias current setting under all conditions when using the internal inductor VCO is 0x8. The VCO should be re-centered, depending on the required frequency of operation, by programming the VCO_ADJUST bits (R1_DB[23:24]). This is detailed in Table 9. External Inductor VCO When using the external inductor VCO, the center frequency of the VCO is set by the internal varactor capacitance and the combined inductance of the external chip inductor, bond wire, and PCB track. The external inductor is connected between the L2 and L1 pins. 750 700 650 fMAX (MHz) 600 550 500 450 400 350 fMIN (MHz) 300 05876-061 The ADF7021 contains two VCO cores. The first VCO, the internal inductor VCO, uses an internal LC tank and supports 862 MHz to 950 MHz and 431 MHz to 475 MHz operating bands. The second VCO, the external inductor VCO, uses an external inductor as part of its LC tank and supports the RF operating band of 80 MHz to 650 MHz. A plot of the VCO operating frequency vs. total external inductance (chip inductor + PCB track) is shown in Figure 37. FREQUENCY (MHz) VOLTAGE CONTROLLED OSCILLATOR (VCO) 250 200 0 5 10 15 20 25 30 TOTAL EXTERNAL INDUCTANCE (nH) Figure 37. Direct RF Output vs. Total External Inductance The inductance for a PCB track using FR4 material is approximately 0.57 nH/mm. This should be subtracted from the total value to determine the correct chip inductor value. Typically, a particular inductor value allows the ADF7021 to function over a range of ±6% of the RF operating frequency. When the RF_DIVIDE_BY_2 bit (R1_DB18) is selected, this range becomes ±3%. At 400 MHz, for example, an operating range of ±24 MHz (that is, 376 MHz to 424 MHz) with a single inductor (VCO range centered at 400 MHz) can be expected. The VCO tuning voltage can be checked for a particular RF output frequency by measuring the voltage on the VCOIN pin when the part is fully powered up in transmit or receive mode. The VCO tuning range is 0.2 V to 2 V. The external inductor value should be chosen to ensure that the VCO is operating as close as possible to the center of this tuning range. This is particularly important for RF frequencies <200 MHz, where the VCO gain is reduced and a tuning range of <±6 MHz exists. The VCO operating frequency range can be adjusted by programming the VCO_ADJUST bits (R1_DB[23:24]). This typically allows the VCO operating range to be shifted up or down by a maximum of 1% of the RF frequency. To select the external inductor VCO, set R1_DB25 to Logic 1. The VCO_BIAS_CURRENT should be set depending on the frequency of operation (as indicated in Table 9). Table 9. RF Output Frequency Ranges for Internal and External Inductor VCOs and Required Register Settings RF Frequency Output (MHz) 900 to 950 862 to 900 450 to 470 431 to 450 450 to 650 200 to 450 80 to 200 VCO to Be Used Internal L Internal L Internal L Internal L External L External L External L RF Divide by 2 No No Yes Yes No No Yes (VCO_INDUCTOR) R1_DB25 0 0 0 0 1 1 1 Register Settings (RF_DIVIDE_BY_2) (VCO_ADJUST) R1_DB18 R1_DB[23:24] 0 11 0 00 1 11 1 00 0 XX 0 XX 1 XX Rev. B | Page 24 of 64 (VCO_BIAS) R1_DB[19:22] 8 8 8 8 4 3 2 Data Sheet ADF7021 CHOOSING CHANNELS FOR BEST SYSTEM PERFORMANCE An interaction between the RF VCO frequency and the reference frequency can lead to fractional spur creation. When the synthesizer is in fractional mode (that is, the RF VCO and reference frequencies are not integer related), spurs can appear on the VCO output spectrum at an offset frequency that corresponds to the difference frequency between an integer multiple of the reference and the VCO frequency. These spurs are attenuated by the loop filter. They are more noticeable on channels close to integer multiples of the reference where the difference frequency may be inside the loop bandwidth; thus, the name integer boundary spurs. The occurrence of these spurs is rare because the integer frequencies are around multiples of the reference, which is typically >10 MHz. To avoid having very small or very large values in the fractional register, choose a suitable reference frequency. Rev. B | Page 25 of 64 ADF7021 Data Sheet TRANSMITTER 1 RF OUTPUT STAGE 2 3 4 ... 8 ... 16 DATA BITS The power amplifier (PA) of the ADF7021 is based on a singleended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dBm into a 50 Ω load at a maximum frequency of 950 MHz. The PA output current and consequently, the output power, are programmable over a wide range. The PA configuration is shown in Figure 38. The output power is set using R2_DB[13:18]. PA RAMP 0 (NO RAMP) PA RAMP 1 (256 CODES PER BIT) PA RAMP 2 (128 CODES PER BIT) PA RAMP 3 (64 CODES PER BIT) PA RAMP 4 (32 CODES PER BIT) R2_DB(11:12) PA RAMP 5 (16 CODES PER BIT) 2 05876-014 PA RAMP 6 (8 CODES PER BIT) R2_DB(13:18) PA RAMP 7 (4 CODES PER BIT) Figure 39. PA Ramping Settings RFOUT R2_DB7 + PA Bias Currents R0_DB27 05876-013 RFGND FROM VCO Figure 38. PA Configuration The PA is equipped with overvoltage protection, which makes it robust in severe mismatch conditions. Depending on the application, users can design a matching network for the PA to exhibit optimum efficiency at the desired radiated output power level for a wide range of antennas, such as loop or monopole antennas. See the LNA/PA Matching section for more information. PA Ramping The PA_BIAS bits (R2_DB[11:12]) facilitate an adjustment of the PA bias current to further extend the output power control range, if necessary. If this feature is not required, the default value of 9 µA is recommended. If output power of greater than 10 dBm is required, a PA bias setting of 11 µA is recommended. The output stage is powered down by resetting R2_DB7. MODULATION SCHEMES The ADF7021 supports 2FSK, 3FSK, and 4FSK modulation. The implementation of these modulation schemes is shown in Figure 40. When the PA is switched on or off quickly, its changing input impedance momentarily disturbs the VCO output frequency. This process is called VCO pulling, and it manifests as spectral splatter or spurs in the output spectrum around the desired carrier frequency. Some radio emissions regulations place limits on these PA transient-induced spurs (for example, ETSI EN 300 220). By gradually ramping the PA on and off, PA transient spurs are minimized. The ADF7021 has built-in PA ramping configurability. As Figure 39 illustrates, there are eight ramp rate settings, defined as a certain number of PA setting codes per one data bit period. The PA steps through each of its 64 code levels but at different speeds for each setting. The ramp rate is set by configuring R2_DB[8:10]. PFD/ CHARGE PUMP REF TO PA STAGE LOOP FILTER ÷2 VCO ÷N FRAC_N THIRD-ORDER Σ-Δ MODULATOR F_DEVIATION INTEGER-N 2FSK GAUSSIAN OR RAISED COSINE FILTERING If the PA is enabled/disabled by PA_ENABLE (R2_DB7), it ramps up at the programmed rate but turns off hard. If the PA is enabled/disabled by Tx/Rx (R0_DB27), it ramps up and down at the programmed rate. Rev. B | Page 26 of 64 TxDATA MUX 3FSK 4FSK 1 – D2 PR SHAPING PRECODER 4FSK BIT SYMBOL MAPPER Figure 40. Transmit Modulation Implementation 05876-015 6 IDAC Data Sheet ADF7021 Setting the Transmit Data Rate 3-Level Frequency Shift Keying (3FSK) In all modulation modes except oversampled 2FSK mode, an accurate clock is provided on the TxRxCLK pin to latch the data from the microcontroller into the transmit section at the required data rate. The exact frequency of this clock is defined by In 3-level FSK modulation (also known as modified Duobinary FSK), the binary data (Logic 0 and Logic 1) is mapped onto three distinct frequencies, the carrier frequency (fC), the carrier frequency minus a deviation frequency (fC − fDEV), and the carrier frequency plus the deviation frequency (fC + fDEV). DATA CLK = A Logic 0 is mapped to the carrier frequency while a Logic 1 is either mapped onto frequency fC − fDEV or fC + fDEV. 0 where: XTAL is the crystal or TCXO frequency. DEMOD_CLK_DIVIDE is the divider that sets the demodulator clock rate (R3_DB[6:9]). CDR_CLK_DIVIDE is the divider that sets the CDR clock rate (R3_DB[10:17]). Setting the FSK Transmit Deviation Frequency In all modulation modes, the deviation from the center frequency is set using the Tx_FREQUENCY_DEVIATION bits (R2_DB[19:27]). The deviation from the center frequency in Hz is as follows: For direct RF output, fDEV [Hz] = PFD × Tx _ FREQUENCY _ DEVIATION 2 16 For RF_DIVIDE_BY_2 enabled, PFD × Tx _ FREQUENCY _ DEVIATION fDEV [Hz] = 0.5 × 216 where Tx_FREQUENCY_DEVIATION is a number from 1 to 511 (R2_DB[19:27]). In 4FSK modulation, the four symbols (00, 01, 11, 10) are transmitted as ±3 × fDEV and ±1 × fDEV. Binary Frequency Shift Keying (2FSK) Two-level frequency shift keying is implemented by setting the N value for the center frequency and then toggling it with the TxDATA line. The deviation from the center frequency is set using the Tx_FREQUENCY_DEVIATION bits, R2_DB[19:27]. fC – fDEV fC + fDEV Figure 41. 3FSK Symbol-to-Frequency Mapping Compared to 2FSK, this bits-to-frequency mapping results in a reduced transmission bandwidth because some energy is removed from the RF sidebands and transferred to the carrier frequency. At low modulation index, 3FSK improves the transmit spectral efficiency by up to 25% when compared to 2FSK. Bit-to-symbol mapping for 3FSK is implemented using a linear convolutional encoder that also permits Viterbi detection to be used in the receiver. A block diagram of the transmit hardware used to realize this system is shown in Figure 42. The convolutional encoder polynomial used to implement the transmit spectral shaping is P(D) = 1 − D2 where: P is the convolutional encoder polynomial. D is the unit delay operator. A digital precoder with transfer function 1/P(D) implements an inverse modulo-2 operation of the 1 − D2 shaping filter in the transmitter. Tx DATA 0, 1 PRECODER 1/P(D) 0, 1 CONVOLUTIONAL ENCODER P(D) 0, +1, –1 fC 2FSK is selected by setting the MODULATION_SCHEME bits (R2_DB[4:6]) to 000. Minimum shift keying (MSK) or Gaussian minimum shift keying (GMSK) is supported by selecting 2FSK modulation and using a modulation index of 0.5. A modulation index of 0.5 is set up by configuring R2_DB[19:27] for a FREQDEVIATION = 0.25 × transmit data rate. fC RF FREQUENCY fC + fDEV FSK MOD fC – fDEV CONTROL AND DATA FILTERING TO N DIVIDER 05876-046 Refer to the Register 3—Transmit/Receive Clock Register section for more programming information. +1 –1 05876-057 XTAL DEMOD _ CLK _ DIVIDE × CDR _ CLK _ DIVIDE × 32 Figure 42. 3FSK Encoding The signal mapping of the input binary transmit data to the 3-level convolutional output is shown in Table 10. The convolutional encoder restricts the maximum number of sequential +1s or −1s to two and delivers an equal number of +1s and −1s to the FSK modulator, thus ensuring equal spectral energy in both RF sidebands. Rev. B | Page 27 of 64 ADF7021 Data Sheet Table 10. 3-Level Signal Mapping of the Convolutional Encoder TxDATA Precoder Output Encoder Output 1 0 1 0 +1 0 1 0 −1 1 1 +1 0 0 0 0 1 0 1 1 +1 0 1 0 0 1 0 1 0 −1 Another property of this encoding scheme is that the transmitted symbol sequence is dc-free, which facilitates symbol detection and frequency measurement in the receiver. In addition, there is no code rate loss associated with this 3-level convolutional encoder; that is, the transmitted symbol rate is equal to the data rate presented at the transmit data input. 3FSK is selected by setting the MODULATION_SCHEME bits (R2_DB[4:6]) to 010. It can also be used with raised cosine filtering to further increase the spectral efficiency of the transmit signal. By minimizing the separation between symbol frequencies, 4FSK can have high spectral efficiency. The bit-to-symbol mapping for 4FSK is gray coded and is shown in Figure 43. 0 0 1 1 0 1 This is the only modulation mode that can be used with the UART mode interface for data transmission (refer to the Interfacing to Microcontroller/DSPsection for more information). Gaussian Frequency Shift Keying (GFSK) 1 Gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the transmit data. The BT product of the Gaussian filter used is 0.5. f +3fDEV +fDEV Gaussian filtering can only be used with 2FSK modulation. This is selected by setting R2_DB[4:6] to 001. –fDEV Raised Cosine Filtering –3fDEV t 05876-016 SYMBOL FREQUENCIES In oversampled 2FSK, there is no data clock from the TxRxCLK pin. Instead, the transmit data at the TxRxDATA pin is sampled at 32 times the programmed rate. Gaussian or raised cosine filtering can be used to improve transmit spectral efficiency. The ADF7021 supports Gaussian filtering (bandwidth time [BT] = 0.5) on 2FSK modulation. Raised cosine filtering can be used with 2FSK, 3FSK, or 4FSK modulation. The roll off factor (alpha) of the raised cosine filter has programmable options of 0.5 and 0.7. Both the Gaussian and raised cosine filters are implemented using linear phase digital filter architectures that deliver precise control over the BT and alpha filter parameters, and guarantee a transmit spectrum that is very stable over temperature and supply variation. In 4FSK modulation, two bits per symbol spectral efficiency is realized by mapping consecutive input bit-pairs in the Tx data bit stream to one of four possible symbols (−3, −1, +1, +3). Thus, the transmitted symbol rate is half of the input bit rate. 0 Oversampled 2FSK SPECTRAL SHAPING 4-Level Frequency Shift Keying (4FSK) Tx DATA The transmit clock from Pin TxRxCLK is available after writing to Register 3 in the power-up sequence for receive mode. The MSB of the first symbol should be clocked into the ADF7021 on the first transmit clock pulse from the ADF7021 after writing to Register 3. Refer to Figure 6 for more timing information. Figure 43. 4FSK Bit-to-Symbol Mapping The inner deviation frequencies (+fDEV and − fDEV) are set using the Tx_FREQUENCY_DEVIATION bits, R2_DB[19:27]. The outer deviation frequencies are automatically set to three times the inner deviation frequency. Raised cosine filtering provides digital prefiltering of the transmit data by using a raised cosine filter with a roll-off factor (alpha) of either 0.5 or 0.7. The alpha is set to 0.5 by default, but the raised cosine filter bandwidth can be increased to provide less aggressive data filtering by using an alpha of 0.7 (set R2_DB30 to Logic 1). Raised cosine filtering can be used with 2FSK, 3FSK, and 4FSK. Raised cosine filtering is enabled by setting R2_DB[4:6] as outlined in Table 11. Rev. B | Page 28 of 64 Data Sheet ADF7021 MODULATION AND FILTERING OPTIONS The various modulation and data filtering options are described in Table 11. Table 11. Modulation and Filtering Options Modulation BINARY FSK 2FSK MSK1 OQPSK with half sine baseband shaping2 GFSK GMSK3 RC2FSK Oversampled 2FSK 3-LEVEL FSK 3FSK RC3FSK 4-LEVEL FSK 4FSK RC4FSK Data Filtering R2_DB[4:6] None None None 000 000 000 Gaussian Gaussian Raised cosine None 001 001 101 100 None Raised cosine 010 110 None Raised cosine 011 111 is inverted by setting R2_DB[28:29], an additional 0.5 bit latency can be added to all values in Table 12. Table 12. Bit/Symbol Latency in Transmit Mode for Various Modulation Schemes Modulation 2FSK GFSK RC2FSK, Alpha = 0.5 RC2FSK, Alpha = 0.7 3FSK RC3FSK, Alpha = 0.5 RC3FSK, Alpha = 0.7 4FSK RC4FSK, Alpha = 0.5 RC4FSK, Alpha = 0.7 Latency 1 bit 4 bits 5 bits 4 bits 1 bit 5 bits 4 bits 1 symbol 5 symbols 4 symbols TEST PATTERN GENERATOR The ADF7021 has a number of built-in test pattern generators that can be used to facilitate radio link setup or RF measurement. A full list of the supported patterns is shown in Table 13. The data rate for these test patterns is the programmed data rate set in Register 3. MSK is 2FSK modulation with a modulation index = 0.5. 2 Offset quadrature phase shift keying (OQPSK) with half sine baseband shaping is spectrally equivalent to MSK. 3 GMSK is GFSK with a modulation index = 0.5. 1 TRANSMIT LATENCY Transmit latency is the delay time from the sampling of a bit/symbol by the TxRxCLK signal to when that bit/symbol appears at the RF output. The latency without any data filtering is 1 bit. The addition of data filtering adds a further latency as outlined in Table 12. It is important that the ADF7021 be left in transmit mode after the last data bit is sampled by the data clock to account for this latency. The ADF7021 should stay in transmit mode for a time equal to the number of latency bit periods for the applied modulation scheme. This ensures that all of the data sampled by the TxRxCLK signal appears at RF. The PN9 sequence is suitable for test modulation when carrying out adjacent channel power (ACP) or occupied bandwidth measurements. Table 13. Transmit Test Pattern Generator Options Test Pattern Normal Transmit Carrier Transmit + fDEV tone Transmit − fDEV tone Transmit 1010 pattern Transmit PN9 sequence Transmit SWD pattern repeatedly The figures for latency in Table 12 assume that the positive TxRxCLK edge is used to sample data (default). If the TxRxCLK Rev. B | Page 29 of 64 R15_DB[8:10] 000 001 010 011 100 101 110 ADF7021 Data Sheet RECEIVER SECTION RF FRONT END The ADF7021 is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from powerlineinduced interference problems. Figure 44 shows the structure of the receiver front end. The many programming options allow users to trade off sensitivity, linearity, and current consumption to best suit their application. To achieve a high level of resilience against spurious reception, the low noise amplifier (LNA) features a differential input. Switch SW2 shorts the LNA input when transmit mode is selected (R0_DB27 = 0). This feature facilitates the design of a combined LNA/PA matching network, avoiding the need for an external Rx/Tx switch. See the LNA/PA Matching section for details on the design of the matching network. I (TO FILTER) RFIN Tx/Rx SELECT (R0_DB27) RFINB SW2 LNA LO Q (TO FILTER) LNA MODE (R9_DB25) MIXER LINEARITY (R9_DB28) LNA CURRENT (R9_DB[26:27]) 05876-017 LNA GAIN (R9_DB[20:21]) LNA/MIXER ENABLE (R8_DB6) If the AGC loop is disabled, the gain of the IF filter can be set to one of three levels by using the FILTER_GAIN bits (R9_DB[22:23]). The filter gain is adjusted automatically if the AGC loop is enabled. IF Filter Bandwidth and Center Frequency Calibration To compensate for manufacturing tolerances, the IF filter should be calibrated after power-up to ensure that the bandwidth and center frequency are correct. Coarse and fine calibration schemes are provided to offer a choice between fast calibration (coarse calibration) and high filter centering accuracy (fine calibration). Coarse calibration is enabled by setting R5_DB4 high. Fine calibration is enabled by setting R6_DB4 high. For details on when it is necessary to perform a filter calibration, and in what applications to use either a coarse calibration or fine calibration, refer to the IF Filter Bandwidth Calibration section. It is necessary to do a coarse calibration before doing a fine calibration. If the IF_FINE_CAL bit (R6_DB4) has already been configured high, it is possible to do a fine calibration by writing only to Register 5. Once initiated by writing to the part, the calibration is performed automatically without any user intervention. Calibration time is 200 μs for coarse calibration and a few milliseconds for fine calibration, during which time the ADF7021 should not be accessed. The IF filter calibration logic requires that the IF_FILTER_DIVIDER bits (R5_DB[5:13]) be set such that Figure 44. RF Front End XTAL [Hz] The LNA is followed by a quadrature downconversion mixer, which converts the RF signal to the IF frequency of 100 kHz. An important consideration is that the output frequency of the synthesizer must be programmed to a value 100 kHz below the center frequency of the received channel. The LNA has two basic operating modes: high gain/low noise mode and low gain/low power mode. To switch between these two modes, use the LNA_MODE bit (R9_DB25). The mixer is also configurable between a low current and an enhanced linearity mode using the MIXER_LINEARITY bit (R9_DB28). IF _ FILTER _ DIVIDER Based on the specific sensitivity and linearity requirements of the application, it is recommended to adjust the LNA_MODE bit and MIXER_LINEARITY bit as outlined in Table 14. The gain of the LNA is configured by the LNA_GAIN bits (R9_DB[20:21]) and can be set by either the user or the automatic gain control (AGC) logic. 50 kHz IF Filter Fine Calibration Overview The fine calibration uses two internally generated tones at certain offsets around the IF filter. The two tones are attenuated by the IF filter, and the level of this attenuation is measured using the RSSI. The filter center frequency is adjusted to allow equal attenuation of both tones. The attenuation of the two test tones is then remeasured. This continues for a maximum of 10 RSSI measurements, at which stage the calibration algorithm sets the IF filter center frequency to within 0.5 kHz of 100 kHz. The frequency of these tones is set by the following bits: IF_CAL_LOWER_TONE_DIVIDER (R6_DB[5:12]) IF_CAL_UPPER_TONE_DIVIDER (R6_DB[13:20]) It is recommended to place the lower and upper tones as close as possible to 65.8 kHz and 131.5 kHz, respectively, as outlined in the following equations: IF FILTER IF Filter Settings Out-of-band interference is rejected by means of a fifth-order Butterworth polyphase IF filter centered on a frequency of 100 kHz. The bandwidth of the IF filter can be programmed to 12.5 kHz, 18.75 kHz, or 25 kHz by R4_DB[30:31] and should be chosen as a compromise between interference rejection and attenuation of the desired signal. Rev. B | Page 30 of 64 XTAL 65.8 kHz IF _ CAL _ LOWER _ TONE _ DIVIDE 2 XTAL 131.5 kHz IF _ CAL _ UPPER _ TONE _ DIVIDE 2 Data Sheet ADF7021 The user has the option of changing the two threshold values from the defaults of 30 and 70 (Register 9). The default AGC setup values should be adequate for most applications. The threshold values must be chosen to be more than 30 apart for the AGC to operate correctly. The calibration algorithm adjusts the filter center frequency and measures the RSSI 10 times during the calibration. The time for an adjustment plus RSSI measurement is given by IF Tone Calibration Time = IF_CAL_DWELL_TIME SEQ CLK It is recommended that the IF tone calibration time be at least 500 µs. The total time for the IF filter fine calibration is given by IF Filter Fine Calibration Time = IF Tone Calibration Time × 10 RSSI/AGC The RSSI is implemented as a successive compression log amp following the baseband (BB) channel filtering. The log amp achieves ±3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. The offset correction circuit uses the BBOS_CLK_DIVIDE bits (R3_DB[4:5]), which should be set between 1 MHz and 2 MHz. The RSSI level is converted for user readback and for digitally controlled AGC by an 80-level (7-bit) flash ADC. This level can be converted to input power in dBm. By default, the AGC is on when powered up in receive mode. OFFSET CORRECTION A 1 IFWR A A IFWR IFWR LATCH In Register 3, the user should set the BBOS_CLK_DIVIDE bits (R3_DB[4:5]) to give a baseband offset clock (BBOS CLK) frequency between 1 MHz and 2 MHz. BBOS CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE) where BBOS_CLK_DIVIDE can be set to 4, 8, 16, or 32. AGC Information and Timing AGC is selected by default and operates by setting the appropriate LNA and filter gain settings for the measured RSSI level. It is possible to disable AGC by writing to Register 9 if the user wants to enter one of the modes listed in Table 14. The time for the AGC circuit to settle and, therefore, the time it takes to measure the RSSI accurately, is typically 300 µs. However, this depends on how many gain settings the AGC circuit has to cycle through. After each gain change, the AGC loop waits for a programmed time to allow transients to settle. This AGC update rate is set according to FSK DEMOD SEQ _ CLK _ DIVIDE [Hz] AGC Update Rate [Hz] = CLK IFWR Offset Correction Clock RSSI 05876-018 ADC R Figure 45. RSSI Block Diagram AGC _ CLK _ DIVIDE where: AGC_CLK_DIVIDE is set by R3_DB[26:31]. A value of 10 is recommended. SEQ_CLK_DIVIDE = 100 kHz (R3_DB[18:25]). By using the recommended setting for AGC_CLK_DIVIDE, the total AGC settling time is RSSI Thresholds When the RSSI is above AGC_HIGH_THRESHOLD (R9_DB[11:17]), the gain is reduced. When the RSSI is below AGC_LOW_THRESHOLD (R9_DB[4:10]), the gain is increased. The thresholds default to 30 and 70 on power-up in receive mode. A delay (set by AGC_CLOCK_DIVIDE, R3_DB[26:31]) is programmed to allow for settling of the loop. A value of 10 is recommended. AGC Settling Time [sec] = Number of AGC Gain Changes AGC Update Rate [Hz] The worst case for AGC settling is when the AGC control loop has to cycle through all five gain settings, which gives a maximum AGC settling time of 500 µs. Table 14. LNA/Mixer Modes Receiver Mode High Sensitivity Mode (Default) Enhanced Linearity High Gain Medium Gain Enhanced Linearity Medium Gain Low Gain Enhanced Linearity Low Gain LNA_MODE (R9_DB25) 0 LNA_GAIN (R9_DB[20:21]) 30 MIXER_LINEARITY (R9_DB28) 0 Sensitivity (2FSK, DR = 4.8 kbps, fDEV = 4 kHz) −118 Rx Current Consumption (mA) 24.6 Input IP3 (dBm) −24 0 30 1 −114.5 24.6 −20 1 1 10 10 0 1 −112 −105.5 22.1 22.1 −13.5 −9 1 1 3 3 0 1 −100 −92.3 22.1 22.1 −5 −3 Rev. B | Page 31 of 64 ADF7021 Data Sheet FREQUENCY CORRELATOR Q Input Power [dBm] = −130 dBm + (Readback Code + Gain Mode Correction) × 0.5 MUX LINEAR DEMODULATOR where: Readback Code is given by Bit RV7 to Bit RV1 in the readback register (see the Readback Format section). Gain Mode Correction is given by the values in Table 15. The LNA gain (LG2, LG1) and filter gain (FG2, FG1) values are also obtained from the readback register, as part of an RSSI readback. THRESHOLD DETECTION 2/3/4FSK TxRxDATA TxRx CLK CLOCK AND DATA RECOVERY MUX VITERBI DETECTION 3FSK Table 15. Gain Mode Correction Filter Gain (FG2, FG1) H (1, 0) H (1, 0) M (0, 1) L (0, 0) L (0, 0) Gain Mode Correction 0 24 38 58 86 Figure 46. Overview of Demodulation, Detection, and CDR Process Correlator Demodulator The correlator demodulator can be used for 2FSK, 3FSK, and 4FSK demodulation. Figure 47 shows the operation of the correlator demodulator for 2FSK. FREQUENCY CORRELATOR DISCRIM BW An additional factor should be introduced to account for losses in the front-end-matching network/antenna. I OUTPUT LEVELS: 2FSK = +1, –1 3FSK = +1, 0, –1 4FSK = +3, +1, –1, –3 LIMITERS DEMODULATION, DETECTION, AND CDR Q System Overview IF – fDEV An overview of the demodulation, detection, and clock and data recovery (CDR) of the received signal on the ADF7021 is shown in Figure 46. The quadrature outputs of the IF filter are first limited and then fed to either the correlator FSK demodulator or the linear FSK demodulator. The correlator demodulator is used to demodulate 2FSK, 3FSK, and 4FSK. The linear demodulator is used for frequency measurement and is enabled when the AFC loop is active. The linear demodulator can also be used to demodulate 2FSK. Following the demodulator, a digital post demodulator filter removes excess noise from the demodulator signal output. Threshold/slicer detection is used for data recovery of 2FSK and 4FSK. Data recovery of 3FSK can be implemented using either threshold detection or Viterbi detection. R4_DB(10:19) DISCRIMINATOR BW IF IF + fDEV R4_DB9 Rx DATA INVERT R4_DB7 DOT/CROSS PRODUCT 05876-079 LNA Gain (LG2, LG1) H (1, 0) M (0, 1) M (0, 1) M (0, 1) L (0, 0) 05876-080 The RSSI formula is POST DEMOD FILTER LIMITERS I RSSI Formula (Converting to dBm) Figure 47. 2FSK Correlator Demodulator Operation The quadrature outputs of the IF filter are first limited and then fed to a digital frequency correlator that performs filtering and frequency discrimination of the 2FSK/3FSK/4FSK spectrum. For 2FSK modulation, data is recovered by comparing the output levels from two correlators. The performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of additive white Gaussian noise (AWGN). This method of FSK demodulation provides approximately 3 dB to 4 dB better sensitivity than a linear demodulator. An on-chip CDR PLL is used to resynchronize the received bit stream to a local clock. It outputs the retimed data and clock on the TxRxDATA and TxRxCLK pins, respectively. Rev. B | Page 32 of 64 Data Sheet ADF7021 Figure 48 shows a block diagram of the linear demodulator. 4FSK demodulation is implemented using the correlator demodulator followed by the post demodulator filter and threshold detection. The output of the post demodulation filter is a 4-level signal that represents the transmitted symbols (−3, −1, +1, +3). Threshold detection of 4FSK requires three threshold settings, one that is always fixed at 0 and two that are programmable and are symmetrically placed above and below 0 using the 3FSK/4FSK_SLICER_THRESHOLD bits (R13_DB[4:10]). I LEVEL IF LIMITER Q FREQUENCY LINEAR DISCRIMINATOR ENVELOPE DETECTOR 3FSK and 4FSK Threshold Detection POST DEMOD FILTER Linear Demodulator + SLICER 2FSK 2FSK Rx DATA RxCLK R4_DB(20:29) 05876-073 FREQUENCY READBACK AND AFC LOOP Figure 48. Block Diagram of Linear FSK Demodulator A digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. The discriminator output is filtered and averaged using a combined averaging filter and envelope detector. The demodulated 2FSK data from the post demodulator filter is recovered by threshold detecting the envelope detector output, as shown in Figure 48. This method of demodulation corrects for frequency errors between transmitter and receiver when the received spectrum is close to or within the IF bandwidth. This envelope detector output is also used for AFC readback and provides the frequency estimate for the AFC control loop. Post Demodulator Filter A second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. The bandwidth of this post demodulator filter is programmable and must be optimized for the user’s data rate and received modulation type. If the bandwidth is set too narrow, performance degrades due to intersymbol interference (ISI). If the bandwidth is set too wide, excess noise degrades the performance of the receiver. The POST_DEMODULATOR_BW bits (R4_DB[20:29]) set the bandwidth of this filter. 2FSK Bit Slicer/Threshold Detection 2FSK demodulation can be implemented using the correlator FSK demodulator or the linear FSK demodulator. In both cases, threshold detection is used for data recovery at the output of the post demodulation filter. The output signal levels of the correlator demodulator are always centered about zero. Therefore, the slicer threshold level can be fixed at zero, and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. This results in robust data recovery that does not suffer from the classic baseline wander problems that exist in the more traditional FSK demodulators. When the linear demodulator is used for 2FSK demodulation, the output of the envelope detector is used as the slicer threshold, and this output tracks frequency errors that are within the IF filter bandwidth. 3FSK demodulation is implemented using the correlator demodulator, followed by a post demodulator filter. The output of the post demodulator filter is a 3-level signal that represents the transmitted symbols (−1, 0, +1). Data recovery of 3FSK can be implemented using threshold detection or Viterbi detection. Threshold detection is implemented using two thresholds that are programmable and are symmetrically placed above and below zero using the 3FSK/4FSK_SLICER_THRESHOLD bits (R13_DB[4:10]). 3FSK Viterbi Detection Viterbi detection of 3FSK operates on a four-state trellis and is implemented using two interleaved Viterbi detectors operating at half the symbol rate. The Viterbi detector is enabled by R13_DB11. To facilitate different run length constraints in the transmitted bit stream, the Viterbi path memory length is programmable in steps of 4 bits, 6 bits, 8 bits, or 32 bits by setting the VITERBI_PATH_MEMORY bits (R13_DB[13:14]). This should be set equal to or longer than the maximum number of consecutive 0s in the interleaved transmit bit stream. When used with Viterbi detection, the receiver sensitivity for 3FSK is typically +3 dB better than that obtained using threshold detection. When the Viterbi detector is enabled, however, the receiver bit latency is increased by twice the Viterbi path memory length. Clock Recovery An oversampled digital clock and data recovery (CDR) PLL is used to resynchronize the received bit stream to a local clock in all modulation modes. The oversampled clock rate of the PLL (CDR CLK) must be set at 32 times the symbol rate (see the Register 3—Transmit/Receive Clock Register section). The maximum data/symbol rate tolerance of the CDR PLL is determined by the number of zero-crossing symbol transitions in the transmitted packet. For example, if using 2FSK with a 101010 preamble, a maximum tolerance of ±3.0% of the data rate is achieved. However, this tolerance is reduced during recovery of the remainder of the packet where symbol transitions may not be guaranteed to occur at regular intervals. To maximize the data rate tolerance of the CDR, some form of encoding and/or data scrambling is recommended that guarantees a number of transitions at regular intervals. For Rev. B | Page 33 of 64 ADF7021 Data Sheet example, using 2FSK with Manchester-encoded data achieves a data rate tolerance of ±2.0%. The CDR PLL is designed for fast acquisition of the recovered symbols during preamble and typically achieves bit synchronization within 5-symbol transitions of preamble. In 4FSK modulation, the tolerance using the +3, −3, +3, −3 preamble is ±3% of the symbol rate (or ±1.5% of the data rate). However, this tolerance is reduced during recovery of the remainder of the packet where symbol transitions may not be guaranteed to occur at regular intervals. To maximize the symbol/data rate tolerance, the remainder of the 4FSK packet should be constructed so that the transmitted symbols retain close to dc-free properties by using data scrambling and/or by inserting specific dc balancing symbols that are inserted in the transmitted bit stream at regular intervals such as after every 8 or 16 symbols. In 3FSK modulation, the linear convolutional encoder scheme guarantees that the transmitted symbol sequence is dc-free, facilitating symbol detection. However, Tx data scrambling is recommended to limit the run length of zero symbols in the transmit bit stream. Using 3FSK, the CDR data rate tolerance is typically ±0.5%. RECEIVER SETUP Correlator Demodulator Setup To enable the correlator for various modulation modes, refer to Table 16. (DEMOD CLK × K ) 400 × 10 3 where: DEMOD CLK is as defined in the Register 3—Transmit/Receive Clock Register section. K is set for each modulation mode according to the following: 100 × 10 3 K = Round f DEV 100 × 10 3 K = Round4 FSK 4 × f DEV where: Round is rounded to the nearest integer. Round4FSK is rounded to the nearest of the following integers: 32, 31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3. fDEV is the transmit frequency deviation in Hz. For 4FSK, fDEV is the frequency deviation used for the ±1 symbols (that is, the inner frequency deviations). To optimize the coefficients of the correlator, R4_DB7 and R4_DB[8:9] must also be assigned. The value of these bits depends on whether K is odd or even. These bits are assigned according to Table 17 and Table 18. Table 17. Assignment of Correlator K Value for 2FSK and 3FSK K Even Even Odd Odd K/2 Even Odd N/A N/A (K + 1)/2 N/A N/A Even Odd R4_DB7 0 0 1 1 R4_DB[8:9] 00 10 00 10 R4_DB7 0 1 R4_DB[8:9] 00 00 Linear Demodulator Setup To optimize receiver sensitivity, the correlator bandwidth must be optimized for the specific deviation frequency and modulation used by the transmitter. The discriminator bandwidth is controlled by R4_DB[10:19] and is defined as For 2FSK, For 4FSK, K Even Odd DEMOD_SCHEME (R4_DB[4:6]) 001 010 011 DISCRIMINATOR _ BW = 100 × 10 3 K = Round 2 × f DEV Table 18. Assignment of Correlator K Value for 4FSK Table 16. Enabling the Correlator Demodulator Received Modulation 2FSK 3FSK 4FSK For 3FSK, The linear demodulator can be used for 2FSK demodulation. To enable the linear demodulator, set the DEMOD_SCHEME bits (R4_DB[4:6]) to 000. Post Demodulator Filter Setup The 3 dB bandwidth of the post demodulator filter should be set according to the received modulation type and data rate. The bandwidth is controlled by R4_DB[20:29] and is given by POST _ DEMOD _ BW = 2 11 × π × f CUTOFF DEMOD CLK where fCUTOFF is the target 3 dB bandwidth in Hz of the post demodulator filter. Table 19. Post Demodulator Filter Bandwidth Settings for 2FSK/3FSK/4FSK Modulation Schemes Received Modulation 2FSK 3FSK 4FSK Rev. B | Page 34 of 64 Post Demodulator Filter Bandwidth, fCUTOFF (Hz) 0.75 × data rate 1 × data rate 1.6 × symbol rate (= 0.8 × data rate) Data Sheet ADF7021 3FSK Viterbi Detector Setup 3FSK Threshold Detector Setup The Viterbi detector can be used for 3FSK data detection. This is activated by setting R13_DB11 to Logic 1. To activate threshold detection of 3FSK, R13_DB11 should be set to Logic 0. The 3FSK/4FSK_SLICER_THRESHOLD bits (R13_DB[4:10]) should be set as outlined in the 3FSK Viterbi Detector Setup section. The Viterbi path memory length is programmable in steps of 4, 6, 8, or 32 bits (VITERBI_PATH_MEMORY, R13_DB[13:14]). The path memory length should be set equal to or greater than the maximum number of consecutive 0s in the interleaved transmit bit stream. The Viterbi detector also uses threshold levels to implement the maximum likelihood detection algorithm. These thresholds are programmable via the 3FSK/4FSK_SLICER_THRESHOLD bits (R13_DB[4:10]). These bits are assigned as follows: 3FSK CDR Setup In 3FSK, a transmit preamble of at least 40 bits of continuous 1s is recommended to ensure a maximum number of symbol transitions for the CDR to acquire lock. The clock and data recovery for 3FSK requires a number of parameters in Register 13 to be set (see Table 20). 4FSK Threshold Detector Setup The threshold for the 4FSK detector is set using the 3FSK/4FSK_SLICER_THRESHOLD bits (R13_DB[4:10]). The threshold should be set according to 3FSK/4FSK_SLICER_THRESHOLD = Transmit Frequency Deviation × K 57 × 100 × 10 3 3FSK/4FSK_SLICER_THRESHOLD = 4FSK Outer Tx Deviation × K 78 × 100 × 10 3 where K is the value calculated for correlator discriminator bandwidth. where K is the value calculated for correlator discriminator bandwidth. Table 20. 3FSK CDR Settings Parameter PHASE_CORRECTION (R13_DB12) 3FSK_CDR_THRESHOLD (R13_DB[15:21]) 3FSK_PREAMBLE_TIME_VALIDATE (R13_DB [22:25]) Recommended Setting 1 Transmit Frequency Deviation × K 62 × 100 × 10 3 where K is the value calculated for correlator discriminator bandwidth. 1111 Rev. B | Page 35 of 64 Purpose Phase correction on Sets CDR decision threshold levels Preamble detector time qualifier ADF7021 Data Sheet DEMODULATOR CONSIDERATIONS 2FSK Preamble The recommended preamble bit pattern for 2FSK is a dc-free pattern (such as a 10101010… pattern). Preamble patterns with longer run-length constraints (such as 11001100…) can also be used but result in a longer synchronization time of the received bit stream in the receiver. The preamble needs to allow enough bits for AGC settling of the receiver and CDR acquisition. A minimum of 16 preamble bits is recommended. When the receiver is using the internal AFC, the minimum recommended number of preamble bits is 48. The remaining fields that follow the preamble header do not have to use dc-free coding. For these fields, the ADF7021 can accommodate coding schemes with a run length of up to eight bits without any performance degradation. If longer run lengths are required, an encoding scheme such as 8B/10B or Manchester encoding is recommended. 4FSK Preamble and Data Coding The recommended preamble bit pattern for 4FSK is a repeating 00100010… bit sequence. This 2-level sequence of repeating −3, +3, −3, +3 symbols is dc-free and maximizes the symbol timing performance and data recovery of the 4FSK preamble in the receiver. The minimum recommended length of the preamble is 32 bits (16 symbols). The remainder of the 4FSK packet should be constructed so that the transmitted symbols retain close to dc-free property by using data scrambling and/or by inserting specific dc balancing symbols in the transmitted bit stream at regular intervals, such as after every 8 or 16 symbols. 2FSK Correlator Demodulator and Frequency Errors The ADF7021 has a number of options to combat frequency errors that exist due to mismatches between the transmit and receive crystals/TCXOs. With AFC disabled, the correlator demodulator is tolerant to frequency errors over the ±0.4 × fDEV range, where fDEV is the FSK frequency deviation. For larger frequency errors, the frequency tolerance can be widened to ±0.8 × fDEV by adjusting the value of K and thus doubling the correlator bandwidth. K should then be calculated as 100 × 10 K = Round 2 × f DEV 3 The DISCRIMINATOR_BW setting should also be recalculated using the new K value. Doubling the correlator bandwidth to improve frequency error tolerance in this manner typically results in a 1 dB to 2 dB loss in receiver sensitivity. Correlator Demodulator and Low Modulation Indices The modulation index in 2FSK is defined as Modulation Index = The receiver sensitivity performance can be maximized at low modulation index by increasing the discriminator bandwidth of the correlator demodulator. For modulation indices of less than 0.4, it is recommended to double the correlator bandwidth by calculating K as follows: 100 e 3 K = Round 2 × f DEV The DISCRIMINATOR_BW should be recalculated using the new K value. Figure 26 highlights the improved sensitivity that can be achieved for 2FSK modulation, at low modulation indices, by doubling the correlator bandwidth. AFC OPERATION The ADF7021 also supports a real-time AFC loop that is used to remove frequency errors due to mismatches between the transmit and receive crystals/TCXOs. The AFC loop uses the linear frequency discriminator block to estimate frequency errors. The linear FSK discriminator output is filtered and averaged to remove the FSK frequency modulation using a combined averaging filter and envelope detector. In receive mode, the output of the envelope detector provides an estimate of the average IF frequency. Two methods of AFC supported on the ADF7021 are external and internal. External AFC Here, the user reads back the frequency information through the ADF7021 serial port and applies a frequency correction value to the fractional-N synthesizer-N divider. The frequency information is obtained by reading the 16-bit signed AFC readback, as described in the Readback Format section, and by applying the following formula: Frequency Readback [Hz] = (AFC_READBACK × DEMOD CLK)/218 Although the AFC_READBACK value is a signed number, under normal operating conditions, it is positive. In the absence of frequency errors, the frequency readback value is equal to the IF frequency of 100 kHz. Internal AFC The ADF7021 supports a real-time, internal, automatic frequency control loop. In this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer-N divider using an internal proportional integral (PI) control loop. The internal AFC control loop parameters are controlled in Register 10. The internal AFC loop is activated by setting R10_DB4 to 1. A scaling coefficient must also be entered, based on the crystal frequency in use. This is set up in R10_DB[5:16] and should be calculated using 2 × f DEV Data Rate 2 24 × 500 AFC _ SCALING _ FACTOR = Round XTAL Rev. B | Page 36 of 64 Data Sheet ADF7021 Maximum AFC Range AUTOMATIC SYNC WORD DETECTION (SWD) The maximum frequency correction range of the AFC loop is programmable on the ADF7021. This is set by R10_DB[24:31]. The maximum AFC correction range is the difference in frequency between the upper and lower limits of the AFC tuning range. For example, if the maximum AFC correction range is set to 10 kHz, the AFC can adjust the receiver LO within the fLO ± 5 kHz range. The ADF7021 also supports automatic detection of the sync or ID fields. To activate this mode, the sync (or ID) word must be preprogrammed into the ADF7021. In receive mode, this preprogrammed word is compared to the received bit stream. When a valid match is identified, the external SWD pin is asserted by the ADF7021 on the next Rx clock pulse. However, when RF_DIVIDE_BY_2 (R1_DB18) is enabled, the programmed range is halved. The user should account for this halving by doubling the programmed maximum AFC range. The recommended maximum AFC correction range should be ≤ 1.5 × IF filter bandwidth. If the maximum frequency correction range is set to be > 1.5 × IF bandwidth, the attenuation of the IF filter can degrade the AFC loop sensitivity. The adjacent channel rejection (ACR) performance of the receivers can be degraded when AFC is enabled and the AFC correction range is close to the IF filter bandwidth. However, because the AFC correction range is programmable, the user can trade off correction range and ACR performance. When AFC errors are removed using either the internal or external AFC, further improvement in receiver sensitivity can be obtained by reducing the IF filter bandwidth using the IF_BW bits (R4_DB[30:31]). This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational requirements of the microprocessor and reduces the overall power consumption. The SWD signal can also be used to frame the received packet by staying high for a preprogrammed number of bytes. The data packet length can be set in R12_DB[8:15]. The SWD pin status can be configured by setting R12_DB[6:7]. R11_DB[4:5] are used to set the length of the sync/ID word, which can be 12, 16, 20, or 24 bits long. A value of 24 bits is recommended to minimize false sync word detection in the receiver that can occur during recovery of the remainder of the packet or when noise/no signal is present at the receiver input. The transmitter must transmit the sync byte MSB first and the LSB last to ensure proper alignment in the receiver sync-byte-detection hardware. An error tolerance parameter can also be programmed that accepts a valid match when up to 3 bits of the word are incorrect. The error tolerance value is assigned in R11_DB[6:7]. Rev. B | Page 37 of 64 ADF7021 Data Sheet APPLICATIONS INFORMATION IF FILTER BANDWIDTH CALIBRATION The IF filter should be calibrated on every power-up in receive mode to correct for errors in the bandwidth and filter center frequency due to process variations. The automatic calibration requires no external intervention once it is initiated by a write to Register 5. Depending on numerous factors, such as IF filter bandwidth, received signal bandwidth, and temperature variation, the user must determine whether to carry out a coarse calibration or a fine calibration. For information on calibration setup, refer to the IF Filter section. This method should only be used if the successive power-ups in receive mode are over a short duration, during which time there is little variation in temperature (>15°C). IF Filter Variation with Temperature The performance of both calibration methods is outlined in Table 21. Table 21. IF Filter Calibration Specifications Filter Calibration Method Coarse Cal Center Frequency Accuracy1 100 kHz ± 2.5 kHz Calibration Time (Typ) 200 µs Fine Cal 100 kHz ± 0.5 kHz 5.2 ms 1 After the initial coarse calibration and fine calibration, the result of the fine calibration can be read back through the serial interface using the FILTER_CAL_READBACK result (refer to the Filter Bandwidth Calibration Readback section). On subsequent power-ups in receive mode, the filter is manually adjusted using the previous fine filter calibration result. This manual adjust is performed using the IF_FILTER_ADJUST bits (R5_DB[14:19]). After calibration. When to Use Coarse Calibration It is recommended to perform a coarse calibration on every receive mode power-up. This calibration typically takes 200 µs. The FILTER_CAL_COMPLETE signal from MUXOUT can be used to monitor the filter calibration duration or to signal the end of calibration. The ADF7021 should not be accessed during calibration. When to Use a Fine Calibration In cases where the receive signal bandwidth is very close to the bandwidth of the IF filter, it is recommended to perform a fine filter calibration every time the unit powers up in receive mode. A fine calibration should be performed if OBW + Coarse Calibration Variation > IF_FILTER_BW where: OBW is the 99% occupied bandwidth of the transmit signal. Coarse Calibration Variation is 2.5 kHz. IF_FILTER_BW is set by R4_DB[30:31]. The FILTER_CAL_COMPLETE signal from MUXOUT (set by R0_DB[29:31]) can be used to monitor the filter calibration duration or to signal the end of calibration. A coarse filter calibration is automatically performed prior to a fine filter calibration. When to Use Single Fine Calibration In applications where the receiver powers up numerous times in a short period, it is only necessary to perform a one-time fine calibration on the initial receiver power-up. When calibrated, the filter center frequency can vary with changes in temperature. If the ADF7021 is used in an application where it remains in receive mode for a considerable length of time, the user must consider this variation of filter center frequency with temperature. This variation is typically 0.7 kHz per 10°C, which means that if a coarse filter calibration and fine filter calibration are performed at 25°C, the initial maximum error is ±0.5 kHz, and the maximum possible change in the filter center frequency over temperature (−40°C and +85°C) is ±4.5 kHz. This gives a total error of ±5 kHz. If the receive signal occupied bandwidth is considerably less than the IF filter bandwidth, the variation of filter center frequency over the operating temperature range may not be an issue. Alternatively, if the IF filter bandwidth is not wide enough to tolerate the variation with temperature, a periodic filter calibration can be performed, or alternatively, the on-chip temperature sensor can be used to determine when a filter calibration is necessary by monitoring for changes in temperature. LNA/PA MATCHING The ADF7021 exhibits optimum performance in terms of sensitivity, transmit power, and current consumption, only if its RF input and output ports are properly matched to the antenna impedance. For cost sensitive applications, the ADF7021 is equipped with an internal Rx/Tx switch that facilitates the use of a simple, combined passive PA/LNA matching network. Alternatively, an external Rx/Tx switch such as the ADG919 can be used, which yields a slightly improved receiver sensitivity and lower transmitter power consumption. Internal Rx/Tx Switch Figure 49 shows the ADF7021 in a configuration where the internal Rx/Tx switch is used with a combined LNA/PA matching network. This is the configuration used on the EVALADF7021DBX evaluation board. For most applications, the slight performance degradation of 1 dB to 2 dB caused by the internal Rx/Tx switch is acceptable, allowing the user to take advantage of the cost saving potential of this solution. The design of the combined matching network must compensate for the reactance presented by the networks in the Tx and the Rx paths, taking the state of the Rx/Tx switch into consideration. Rev. B | Page 38 of 64 Data Sheet ADF7021 VBAT C1 L1 PA_OUT PA ANTENNA ZOPT_PA OPTIONAL BPF OR LPF ZIN_RFIN CA RFIN LA LNA RFINB 05876-022 ZIN_RFIN CB ADF7021 Figure 49. ADF7021 with Internal Rx/Tx Switch The procedure typically requires several iterations until an acceptable compromise has been reached. The successful implementation of a combined LNA/PA matching network for the ADF7021 is critically dependent on the availability of an accurate electrical model for the PCB. In this context, the use of a suitable CAD package is strongly recommended. To avoid this effort, a small form-factor reference design for the ADF7021 is provided, including matching and harmonic filter components. The design is on a 2-layer PCB to minimize cost. Gerber files are available at www.analog.com. External Rx/Tx Switch Figure 50 shows a configuration using an external Rx/Tx switch. This configuration allows an independent optimization of the matching and filter network in the transmit and receive path. Therefore, it is more flexible and less difficult to design than the configuration using the internal Rx/Tx switch. The PA is biased through Inductor L1, while C1 blocks dc current. Together, L1 and C1 form the matching network that transforms the source impedance into the optimum PA load impedance, ZOPT_PA. VBAT OPTIONAL LPF C1 L1 PA_OUT PA ANTENNA ZOPT_PA ZIN_RFIN OPTIONAL CA BPF (SAW) RFIN LA Depending on the antenna configuration, the user may need a harmonic filter at the PA output to satisfy the spurious emission requirement of the applicable government regulations. The harmonic filter can be implemented in various ways, such as a discrete LC pi or T-stage filter. Dielectric low-pass filter components, such as the LFL18924MTC1A052 (for operation in the 915 MHz and 868 MHz band) by Murata Manufacturing Co. Ltd., represent an attractive alternative to discrete designs. The immunity of the ADF7021 to strong out-of-band interference can be improved by adding a band-pass filter in the Rx path. Apart from discrete designs, SAW or dielectric filter components such as the SAFCH869MAM0T00, SAFCH915MAL0N00, DCFB2869MLEJAA-TT1, or DCFB3915MLDJAA-TT1, all by Murata Manufacturing Co. Ltd., are well-suited for this purpose. Alternatively, the ADF7021 blocking performance can be improved by selecting one of the enhanced linearity modes, as described in Table 14. IMAGE REJECTION CALIBRATION The image channel in the ADF7021 is 200 kHz below the desired signal. The polyphase filter rejects this image with an asymmetric frequency response. The image rejection performance of the receiver is dependent on how well matched the I and Q signals are in amplitude, and how well matched the quadrature is between them (that is, how close to 90° apart they are). The uncalibrated image rejection performance is approximately 29 dB (at 450 MHz). However, it is possible to improve on this performance by as much as 20 dB by finding the optimum I/Q gain and phase adjust settings. ZIN_RFIN CB ADF7021 05876-021 Calibration Using Internal RF Source ADG919 Rx/Tx – SELECT LNA RFINB Due to the differential LNA input, the LNA matching network must be designed to provide both a single-ended-to-differential conversion and a complex, conjugate impedance match. The network with the lowest component count that can satisfy these requirements is the configuration shown in Figure 50, consisting of two capacitors and one inductor. A first-order implementation of the matching network can be obtained by understanding the arrangement as two L-type matching networks in a back-toback configuration. Due to the asymmetry of the network with respect to ground, a compromise between the input reflection coefficient and the maximum differential signal swing at the LNA input must be established. The use of appropriate CAD software is strongly recommended for this optimization. Figure 50. ADF7021 with External Rx/Tx Switch ZOPT_PA depends on various factors, such as the required output power, the frequency range, the supply voltage range, and the temperature range. Selecting an appropriate ZOPT_PA helps to minimize the Tx current consumption in the application. Application Note AN-764 contains a number of ZOPT_PA values for representative conditions. Under certain conditions, however, it is recommended to obtain a suitable ZOPT_PA value by means of a load-pull measurement. With the LNA powered off, an on-chip generated, low level RF tone is applied to the mixer inputs. The LO is adjusted to make the tone fall at the image frequency where it is attenuated by the image rejection of the IF filter. The power level of this tone is then measured using the RSSI readback. The I/Q gain and phase adjust DACs (R5_DB[20:31]) are adjusted and the RSSI is remeasured. This process is repeated until the optimum values for the gain and phase adjust are found that provide the lowest RSSI readback level, thereby maximizing the image rejection performance of the receiver. Rev. B | Page 39 of 64 ADF7021 Data Sheet ADF7021 RFIN LNA RFINB GAIN ADJUST MUX INTERNAL SIGNAL SOURCE POLYPHASE IF FILTER RSSI/ LOG AMP 7-BIT ADC PHASE ADJUST Q I FROM LO SERIAL INTERFACE 4 PHASE ADJUST REGISTER 5 RSSI READBACK 4 GAIN ADJUST REGISTER 5 MICROCONTROLLER 05876-072 I/Q GAIN/PHASE ADJUST AND RSSI MEASUREMENT ALGORITHM Figure 51. Image Rejection Calibration Using the Internal Calibration Source and a Microcontroller Calibration Using External RF Source IR calibration can also be implemented using an external RF source. The IR calibration procedure is the same as that used for the internal RF source, except that an RF tone is applied to the LNA input. Calibration Procedure and Setup applied to either the I or Q channel, depending on the value of IR_GAIN_ADJUST_I/Q bit (R5_DB30), whereas the IR_GAIN_ADJUST_UP/DN bit (R5_DB31) sets whether the gain adjustment defines a gain or an attenuation adjust. The calibration results are valid over changes in the ADF7021 supply voltage. However, there is some variation with temperature. A typical plot of variation in image rejection over temperature after initial calibrations at −40°C, +25°C, and +85°C is shown in Figure 52. The internal temperature sensor on the ADF7021 can be used to determine if a new IR calibration is required. The IR calibration algorithm available from Analog Devices, Inc. is based on a low complexity, 2D optimization algorithm that can be implemented in an external microprocessor or microcontroller. The magnitude of the phase adjust is set by using the IR_PHASE_ ADJUST_MAG bits (R5_DB[20:23]). This correction can be applied to either the I channel or Q channel, depending on the value of the IR_PHASE_ADJUST_DIRECTION bit (R5_DB24). CAL AT +25°C 50 IMAGE REJECTION (dB) To enable the internal RF source, the IR_CAL_SOURCE_ DRIVE_LEVEL bits (R6_DB[28:29]) should be set to the maximum level. The LNA should be set to its minimum gain setting, and the AGC should be disabled if the internal source is being used. Alternatively, an external RF source can be used. 60 The magnitude of the I/Q gain is adjusted by the IR_GAIN_ ADJUST_MAG bits (R5_DB[25:29]). This correction can be 40 CAL AT +85°C CAL AT –40°C 30 VDD = 3.0V IF BW = 25kHz 20 10 WANTED SIGNAL: RF FREQ = 430MHz MODULATION = 2FSK DATA RATE = 9.6kbps, PRBS9 fDEV = 4kHz LEVEL= –100dBm 0 –60 –40 –20 0 INTERFERER SIGNAL: RF FREQ = 429.8MHz MODULATION = 2FSK DATA RATE = 9.6kbps, PRBS11 fDEV = 4kHz 20 40 TEMPERATURE (°C) 60 80 100 05876-067 Using the internal RF source, the RF frequencies that can be utilized for image calibration are programmable and are odd multiples of the reference frequency. Figure 52. Image Rejection Variation with Temperature after Initial Calibrations at −40°C, +25°C, and +85°C Rev. B | Page 40 of 64 Data Sheet ADF7021 PACKET STRUCTURE AND CODING particular application, such as setting up sync byte detection or enabling AFC. When going from Tx to Rx or vice versa, the user needs to toggle the Tx/Rx bit and write only to Register 0 to alter the LO by 100 kHz. PREAMBLE SYNC WORD ID FIELD DATA FIELD CRC 05876-023 The suggested packet structure to use with the ADF7021 is shown in Figure 53. Figure 53. Typical Format of a Transmit Protocol Refer to the Receiver Setup section for information on the required preamble structure and length for the various modulation schemes. PROGRAMMING AFTER INITIAL POWER-UP Table 22 lists the minimum number of writes needed to set up the ADF7021 in either Tx or Rx mode after CE is brought high. Additional registers can also be written to tailor the part to a Table 22. Minimum Register Writes Required for Tx/Rx Setup Mode Tx Rx Tx to Rx and Rx to Tx Reg 1 Reg 1 Reg 0 Reg 3 Reg 3 Registers Reg 0 Reg 2 Reg 0 Reg 5 Reg 4 The recommended programming sequences for transmit and receive are shown in Figure 54 and Figure 55, respectively. The difference in the power-up routine for a TCXO and XTAL reference is shown in these figures. Rev. B | Page 41 of 64 ADF7021 Data Sheet TCXO REFERENCE XTAL REFERENCE POWER-DOWN CE LOW CE HIGH WAIT 10µs + 1ms (REGULATOR POWER-UP + TYPICAL XTAL SETTLING) CE HIGH WAIT 10µs (REGULATOR POWER-UP) WRITE TO REGISTER 1 (TURNS ON VCO) WAIT 0.7ms (TYPICAL VCO SETTLING) WRITE TO REGISTER 3 (TURNS ON Tx/Rx CLOCKS) WRITE TO REGISTER 0 (TURNS ON PLL) WAIT 40µs (TYPICAL PLL SETTLING) WRITE TO REGISTER 2 (TURNS ON PA) WAIT FOR PA TO RAMP UP (ONLY IF PA RAMP ENABLED) Tx MODE WAIT FOR Tx LATENCY NUMBER OF BITS (REFER TO TABLE 12) WRITE TO REGISTER 2 (TURNS OFF PA) WAIT FOR PA TO RAMP DOWN 05876-086 CE LOW POWER-DOWN OPTIONAL. ONLY NECESSARY IF PA RAMP DOWN IS REQUIRED. Figure 54. Power-Up Sequence for Transmit Mode Rev. B | Page 42 of 64 Data Sheet ADF7021 TCXO REFERENCE XTAL REFERENCE POWER-DOWN CE LOW CE HIGH WAIT 10µs + 1ms (REGULATOR POWER-UP + TYPICAL XTAL SETTLING) CE HIGH WAIT 10µs (REGULATOR POWER-UP) WRITE TO REGISTER 1 (TURNS ON VCO) WAIT 0.7ms (TYPICAL VCO SETTLING) WRITE TO REGISTER 3 (TURNS ON Tx/Rx CLOCKS) WRITE TO REGISTER 6 (SETS UP IF FILTER CALIBRATION) OPTIONAL: ONLY NECESSARY IF IF FILTER FINE CAL IS REQUIRED. WRITE TO REGISTER 5 (STARTS IF FILTER CALIBRATION) WAIT 0.2ms (COARSE CAL) OR WAIT 5.2ms (COARSE CALIBRATION + FINE CALIBRATION) WRITE TO REGISTER 11 (SET UP SWD) WRITE TO REGISTER 12 (ENABLE SWD) OPTIONAL: ONLY NECESSARY IF SWD IS REQUIRED. WRITE TO REGISTER 0 (TURNS ON PLL) WAIT 40µs (TYPICAL PLL SETTLING) WRITE TO REGISTER 4 (TURNS ON DEMOD) WRITE TO REGISTER 10 (TURNS ON AFC) OPTIONAL: ONLY NECESSARY IF AFC IS REQUIRED. Rx MODE 05876-087 CE LOW POWER-DOWN OPTIONAL. Figure 55. Power-Up Sequence for Receive Mode Rev. B | Page 43 of 64 ADF7021 Data Sheet APPLICATIONS CIRCUIT For recommended component values, refer to the ADF7021 evaluation board data sheet and AN-915 application note accessible from the ADF7021 product page. Follow the reference design schematic closely to ensure optimum performance in narrow-band applications. The ADF7021 requires very few external components for operation. Figure 56 shows the recommended application circuit. Note that the power supply decoupling and regulator capacitors are omitted for clarity. LOOP FILTER VDD TCXO EXT VCO L* CVCO CAP REFERENCE 4 RFOUT 5 RFGND 6 RFIN 38 OSC2 39 OSC1 41 40 VDD3 CREG3 42 CPOUT 44 45 L2 43 VDD GND 46 47 37 CLKOUT 36 TxRxCLK 35 SWD 33 VDD2 32 ADF7021 ADCIN 30 RFINB 8 RLNA GND2 29 9 VDD4 SCLK 28 10 RSET SREAD SDATA CREG4 SLE 25 CE TEST_A TO MICROCONTROLLER CONFIGURATION INTERFACE 27 26 24 23 FILT_Q GND4 FILT_Q 22 GND4 21 20 FILT_I RSET RESISTOR 19 MIX_Q FILT_I 18 17 13 RLNA RESISTOR MIX_Q GND4 MIX_I 12 VDD CREG2 31 7 11 TO MICROCONTROLLER Tx/Rx SIGNAL INTERFACE TxRxDATA 34 16 VDD VDD1 MIX_I T-STAGE LC FILTER 3 15 VDD VCOIN CREG1 14 ANTENNA CONNECTION 2 MUXOUT 1 MATCHING L1 VDD GND1 CVCO 48 VDD CHIP ENABLE TO MICROCONTROLLER NOTES 1. PINS [13:18], PINS [20:21], AND PIN 23 ARE TEST PINS AND ARE NOT USED IN NORMAL OPERATION. Figure 56. Typical Application Circuit (Regulator Capacitors and Power Supply Decoupling Not Shown) Rev. B | Page 44 of 64 05876-084 *PIN 44 AND PIN 46 CAN BE LEFT FLOATING IF EXTERNAL INDUCTOR VCO IS NOT USED. Data Sheet ADF7021 SERIAL INTERFACE RSSI Readback The serial interface allows the user to program the 16-/32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). It consists of a level shifter, 32-bit shift register, and 16 latches. Signals should be CMOS compatible. The serial interface is powered by the regulator, and, therefore, is inactive when CE is low. The format of the readback word is shown in Figure 57. It comprises the RSSI-level information (Bit RV1 to Bit RV7), the current filter gain (FG1, FG2), and the current LNA gain (LG1, LG2) setting. The filter and LNA gain are coded in accordance with the definitions in the Register 9—AGC Register section. For signal levels below −100 dBm, averaging the measured RSSI values improves accuracy. The input power can be calculated from the RSSI readback value as outlined in the RSSI/AGC section. Data is clocked into the register, MSB first, on the rising edge of each clock (SCLK). Data is transferred to one of 16 latches on the rising edge of SLE. The destination latch is determined by the value of the four control bits (C4 to C1); these are the bottom 4 LSBs, DB3 to DB0, as shown in Figure 2. Data can also be read back on the SREAD pin. Battery Voltage/ADCIN/Temperature Sensor Readback The battery voltage is measured at Pin VDD4. The readback information is contained in Bit RV1 to Bit RV7. This also applies for the readback of the voltage at the ADCIN pin and the temperature sensor. From the readback information, the battery or ADCIN voltage can be determined using READBACK FORMAT The readback operation is initiated by writing a valid control word to the readback register and enabling the READBACK bit (R7_DB8 = 1). The readback can begin after the control word has been latched with the SLE signal. SLE must be kept high while the data is being read out. Each active edge at the SCLK pin successively clocks the readback word out at the SREAD pin, as shown in Figure 57, starting with the MSB first. The data appearing at the first clock cycle following the latch operation must be ignored. An extra clock cycle is needed after the 16th readback bit to return the SREAD pin to tristate. Therefore, 18 total clock cycles are needed for each read back. After the 18th clock cycle, SLE should be brought low. VBATTERY = (BATTERY_VOLTAGE_READBACK)/21.1 VADCIN = (ADCIN_VOLTAGE_READBACK)/42.1 The temperature can be calculated using Temp [°C] = −40 + (68.4 − TEMP_READBACK) × 9.32 Silicon Revision Readback The silicon revision readback word is valid without setting any other registers. The silicon revision word is coded with four quartets in BCD format. The product code (PC) is coded with three quartets extending from Bit RV5 to Bit RV16. The revision code (RC) is coded with one quartet extending from Bit RV1 to Bit RV4. The product code for the ADF7021 should read back as PC = 0x210. The current revision code should read as RC = 0x4. AFC Readback The AFC readback is valid only during the reception of FSK signals with either the linear or correlator demodulator active. The AFC readback value is formatted as a signed 16-bit integer comprising Bit RV1 to Bit RV16 and is scaled according to the following formula: Filter Bandwidth Calibration Readback The filter calibration readback word is contained in Bit RV1 to Bit RV8. This readback can be used for manual filter adjust, thereby avoiding the need to do an IF filter calibration in some instances. The manual adjust value is programmed by R5_DB[14:19]. To calculate the manual adjust based on a filter calibration readback, use the following formula: FREQ RB [Hz] = (AFC_READBACK × DEMOD CLK)/218 In the absence of frequency errors, FREQ RB is equal to the IF frequency of 100 kHz. Note that, for the AFC readback to yield a valid result, the down converted input signal must not fall outside the bandwidth of the analog IF filter. At low input signal levels, the variation in the readback value can be improved by averaging. IF_FILTER_ADJUST = FILTER_CAL_READBACK − 128 The result should be programmed into R5_DB[14:19] as outlined in the Register 5—IF Filter Setup Register section. DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AFC READBACK RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1 RSSI READBACK X X X X X LG2 LG1 FG2 FG1 RV7 RV6 RV5 RV4 RV3 RV2 RV1 BATTERY VOLTAGE/ADCIN/ TEMP. SENSOR READBACK X X X X X X X X X RV7 RV6 RV5 RV4 RV3 RV2 RV1 SILICON REVISION RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1 FILTER CAL READBACK 0 0 0 0 0 0 0 0 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1 Figure 57. Readback Value Table Rev. B | Page 45 of 64 05876-029 READBACK VALUE READBACK MODE ADF7021 Data Sheet INTERFACING TO MICROCONTROLLER/DSP SPI Mode Standard Transmit/Receive Data Interface In SPI mode, the TxRxCLK pin is configured to input transmit data in transmit mode. In receive mode, the receive data is available on the TxRxDATA pin. The data clock in both transmit and receive modes is available on the CLKOUT pin. In transmit mode, data is clocked into the ADF7021 on the positive edge of CLKOUT. In receive mode, the TxRxDATA data pin should be sampled by the microcontroller on the positive edge of the CLKOUT. The standard transmit/receive signal and configuration interface to a microcontroller is shown in Figure 58. In transmit mode, the ADF7021 provides the data clock on the TxRxCLK pin, and the TxRxDATA pin is used as the data input. The transmit data is clocked into the ADF7021 on the rising edge of TxRxCLK. ADF7021 To enable SPI interface mode, set R0_DB28 high and set R15_DB[17:19] to 0x7. Figure 8 and Figure 9 show the relevant timing diagrams for SPI mode, while Figure 60 shows the recommended interface to a microcontroller using the SPI mode of the ADF7021. MOSI TxRxCLK SCLOCK SS CE P3.7 SWD GPIO P2.4 SREAD P2.5 SLE P2.6 SDATA P2.7 SCLK MICROCONTROLLER 05876-026 P3.2/INT0 SPI Figure 58. ADuC84x to ADF7021 Connection Diagram TxDATA TxRxDATA SCLK Figure 60. ADF7021 (SPI Mode) to Microcontroller Interface ADSP-BF533 interface The suggested method of interfacing to the Blackfin® ADSPBF533 is given in Figure 61. CE SWD SREAD SLE SDATA SCLK 05876-085 GPIO SLE SDATA ADF7021 RxDATA CLKOUT SREAD In UART mode, the TxRxCLK pin is configured to input transmit data in transmit mode. In receive mode, the receive data is available on the TxRxDATA pin, thus providing an asynchronous data interface. The UART mode can only be used with oversampled 2FSK. Figure 59 shows a possible interface to a microcontroller using the UART mode of the ADF7021. To enable this UART interface mode, set R0_DB28 high. Figure 8 and Figure 9 show the relevant timing diagrams for UART mode. UART TxRxDATA GPIO Figure 59. ADF7021(UART Mode) to Asynchronous Microcontroller Interface Rev. B | Page 46 of 64 ADF7021 ADSP-BF533 SCK SCLK MOSI SDATA MISO SREAD PF5 TxRxCLK MOSI SCLK SWD UART Mode MICROCONTROLLER TxRxCLK CE In receive mode, the ADF7021 provides the synchronized data clock on the TxRxCLK pin. The receive data is available on the TxRxDATA pin. The rising edge of TxRxCLK should be used to clock the receive data into the microcontroller. Refer to Figure 4 and Figure 5 for the relevant timing diagrams. In 4FSK transmit mode, the MSB of the transmit symbol is clocked into the ADF7021 on the first rising edge of the data clock from the TxRxCLK pin. In 4FSK receive mode, the MSB of the first payload symbol is clocked out on the first negative edge of the data clock after the SWD, and should be clocked into the microcontroller on the following rising edge. Refer to Figure 6 and Figure 7 for the relevant timing diagrams. ADF7021 MISO RSCLK1 DT1PRI SLE TxRxCLK TxRxDATA DR1PRI RFS1 PF6 SWD CE Figure 61. ADSP-BF533 to ADF7021 Connection Diagram 05876-027 TxRxDATA MISO 05876-076 ADuC84x Data Sheet ADF7021 M3 M2 M1 MUXOUT 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 REGULATOR_READY (DEFAULT) FILTER_CAL_COMPLETE DIGITAL_LOCK_DETECT RSSI_READY Tx_Rx LOGIC_ZERO TRISTATE LOGIC_ONE DB1 DB0 C2 (0) C1 (0) DB3 DB2 DB4 M1 C4 (0) C3 (0) DB5 M2 DB6 DB7 M4 M3 DB8 DB12 M9 M5 DB13 M10 DB9 DB14 M11 DB10 DB15 M6 DB16 M13 M12 M7 DB17 DB11 M15 M14 M13 ... M3 M2 M1 FRACTIONAL DIVIDE RATIO 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 ... ... ... ... ... ... ... ... ... ... 0 0 0 . . . 1 1 1 1 0 0 1 . . . 0 0 1 1 0 1 0 . . . 0 1 0 1 0 1 2 . . . 32764 32765 32766 32767 N8 N7 N6 N5 N4 N3 N2 N1 N COUNTER DIVIDE RATIO 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 1 1 . . . 1 0 1 . . . 1 1 0 . . . 1 1 0 . . . 0 1 0 . . . 1 23 24 . . . 253 1 1 1 1 1 1 1 0 254 1 1 1 1 1 1 1 1 255 05876-030 DISABLED ENABLED M14 N2 UART MODE 0 1 DB18 DB21 DB20 N3 U1 DB19 DB22 N4 TRANSMIT RECEIVE N1 DB23 0 1 M15 DB24 N6 N5 TRANSMIT/ RECEIVE M8 Tx/Rx DB25 DB28 U1 N7 DB29 DB26 TR1 ADDRESS BITS 15-BIT FRACTIONAL_N DB27 DB30 M2 M1 8-BIT INTEGER_N N8 DB31 M3 MUXOUT TR1 UART MODE REGISTER 0—N REGISTER Figure 62. Register 0—N Register Map The RF output frequency is calculated by the following: For the direct output Fractional _ N RFOUT = PFD × Integer _ N + 2 15 For the RF_DIVIDE_BY_2 (DB18) selected Fractional _ N RFOUT = PFD × 0.5 × Integer _ N + 2 15 In UART/SPI mode, the TxRxCLK pin is used to input the Tx data. The Rx Data is available on the TxRxDATA pin. In the MUXOUT map in Figure 62, the FILTER_CAL_COMPLETE indicates when a coarse or coarse plus fine IF filter calibration has finished. The DIGITAL_LOCK_DETECT indicates when the PLL has locked. The RSSI_READY indicates that the RSSI signal has settled and an RSSI readback can be performed. Tx_Rx gives the status of DB27 in this register, which can be used to control an external Tx/Rx switch. Rev. B | Page 47 of 64 ADF7021 Data Sheet VB4 0 0 . 1 VB3 0 0 . 1 VCO VB1 1 0 . 1 DB8 DB7 DB6 DB5 DB4 DB3 CL2 CL1 R3 R2 R1 C4 (0) LOOP CONDITION 0 1 VCO OFF VCO ON INTERNAL L VCO EXTERNAL L VCO D1 0 1 CP2 0 0 1 1 CP1 RSET 0 1 0 1 ICP (mA) 3.6kΩ 0.3 0.9 1.5 2.1 CL1 0 1 0 . . . 1 DB0 DB9 VE1 CL2 0 0 1 . . . 1 C1 (1) DB10 CL4 CL3 3.75mA CL3 0 0 0 . . . 1 DB2 DB11 D1 CL4 0 0 0 . . . 1 DB1 DB12 X1 VCO BIAS CURRENT 0.25mA 0.5mA R1 1 0 . . . 1 C3 (0) DB13 XB1 OFF ON R2 0 1 . . . 1 C2 (0) DB14 XB2 XOSC_ ENABLE XTAL_ DOUBLER DB15 CP1 CP_ CURRENT DB17 DB16 R3 0 0 . . . 1 RFD1 RF DIVIDE BY 2 0 1 ADDRESS BITS R_COUNTER RF R COUNTER DIVIDE RATIO 1 2 . . . 7 CLKOUT DIVIDE RATIO OFF 2 4 . . . 30 XTAL DOUBLER DISABLE ENABLED X1 XTAL OSC OFF 0 ON 1 XB2 XB1 0 0 1 1 0 1 0 1 XTAL BIAS 20µA 25µA 30µA 35µA 05876-031 NOMINAL VCO ADJUST UP 1 VCO ADJUST UP 2 VCO ADJUST UP 3 CLOCKOUT_ DIVIDE VE1 VB1 0 1 0 1 XTAL_ BIAS CP2 DB19 VB2 VA1 0 0 1 1 VB2 0 1 . 1 RF_DIVIDE_ BY_2 VCO_ ENABLE DB20 VB3 VCO CENTER FREQ ADJUST RFD1 DB18 DB22 DB21 VB4 DB23 VA1 VCO_ ADJUST DB24 VCO_BIAS VA2 VCL1 0 1 VA2 VCL1 DB25 VCO_ INDUCTOR REGISTER 1—VCO/OSCILLATOR REGISTER Figure 63. Register 1—VCO/Oscillator Register Map The R_COUNTER and XTAL_DOUBLER relationship is expressed as follows: If XTAL_DOUBLER = 0, PFD = XTAL R _ COUNTER If XTAL_DOUBLER =1, PFD = XTAL × 2 R _ COUNTER The CLOCKOUT_DIVIDE is a divided-down and inverted version of the XTAL and is available on Pin 36 (CLKOUT). Set XOSC_ENABLE high when using an external crystal. If using an external oscillator (such as TCXO) with CMOS-level outputs into Pin OSC2, set XOSC_ENABLE low. If using an external oscillator with a 0.8 V p-p clipped sine wave output into Pin OSC1, set XOSC_ENABLE high. The VCO_BIAS bits should be set according to Table 9. The VCO_ADJUST bits adjust the center of the VCO operating band. Each bit typically adjusts the VCO band up by 1% of the RF operating frequency (0.5% if RF_DIVIDE_BY_2 is enabled). Setting VCO_INDUCTOR to external allows the use of the external inductor VCO, which gives RF operating frequencies of 80 Hz to 650 MHz. If the internal inductor VCO is being used for operation, set this bit low. Rev. B | Page 48 of 64 Data Sheet ADF7021 DI1 TxDATA INVERT 0 0 1 1 0 1 0 1 NORMAL INVERT CLK INVERT DATA INV CLK AND DATA TFD9 ... 0 0 0 0 . 1 ... ... ... ... ... ... NRC1 RAISED COSINE ALPHA 0 1 0.5 (Default) 0.7 0 0 0 0 . 1 0 0 1 1 . 1 0 1 0 1 . 1 MODULATION_ SCHEME DB6 DB5 DB4 DB3 DB2 DB1 DB0 S2 S1 C4 (0) C3 (0) C2 (1) C1 (0) PA2 PA1 PA BIAS PE1 POWER AMPLIFIER 0 0 1 1 0 1 0 1 5µA 7µA 9µA 11µA 0 1 OFF ON PR3 PR2 PR1 PA RAMP RATE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 NO RAMP 256 CODES/BIT 128 CODES/BIT 64 CODES/BIT 32 CODES/BIT 16 CODES/BIT 8 CODES/BIT 4 CODES/BIT P6 . . P2 P1 PA LEVEL 0 0 0 0 . . 1 . . . . . . 1 . . . . . . . 0 0 1 1 . . 1 0 1 0 1 . . 1 0 (PA OFF) 1 (–16.0 dBm) 2 3 . . 63 (13 dBm) ADDRESS BITS S3 PA_ ENABLE DB7 DB8 PE1 PR1 DB9 PR2 DB11 PA1 DB10 DB12 PA2 PR3 DB13 DB14 P1 PA_RAMP P2 DB16 P4 0 1 2 3 . 511 DB15 DB17 P5 TFD3 TFD2 TFD1 fDEV PA_BIAS P3 DB18 P6 TFD1 DB19 TFD2 DB20 TFD4 DB22 TFD3 DB21 POWER_AMPLIFIER S3 S2 S1 MODULATION SCHEME 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2FSK GAUSSIAN 2FSK 3FSK 4FSK OVERSAMPLED 2FSK RAISED COSINE 2FSK RAISED COSINE 3FSK RAISED COSINE 4FSK 05876-032 DI2 TFD5 DB23 TFD6 DB24 TFD8 DB26 DB28 DI1 Tx_FREQUENCY_DEVIATION TFD9 DB27 DB29 DI2 NRC1 DB30 TxDATA_ INVERT TFD7 DB25 R-COSINE_ ALPHA REGISTER 2—TRANSMIT MODULATION REGISTER Figure 64. Register 2—Transmit Modulation Register Map The 2FSK/3FSK/4FSK frequency deviation is expressed by the following: Direct output Frequency Deviation [Hz] = Tx_FREQUENCY_DEVIATION × PFD 2 16 With RF_DIVIDE_BY_2 (R1_DB18) enabled In the case of 4FSK, there are tones at ±3 × the frequency deviation and at ±1 × the deviation. The power amplifier (PA) ramps at the programmed rate (R2_DB[8:10]) until it reaches its programmed level DB[13:18]. If the PA is enabled/disabled by the PA_ENABLE bit (DB7), it ramps up and down. If it is enabled/disabled by the Tx/Rx bit (R0_DB27), it ramps up and turns hard off. R-COSINE_ALPHA sets the roll-off factor (alpha) of the raised cosine data filter to either 0.5 or 0.7. The alpha is set to 0.5 by default, but the raised cosine filter bandwidth can be increased to provide less aggressive data filtering by using an alpha of 0.7. Frequency Deviation [Hz] = Tx_FREQUENCY_DEVIATION × PFD 0. 5 × 2 16 where Tx_FREQUENCY_DEVIATION is set by DB[19:27] and PFD is the PFD frequency. Rev. B | Page 49 of 64 ADF7021 Data Sheet GD4 GD3 GD2 GD1 AGC CLK DIVIDE 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 1 ... 1 INVALID 1 ... 127 DB5 BK2 DB0 DB6 OK1 C1 (1) DB7 OK2 DB1 DB8 OK3 C2 (1) DB9 OK4 DB2 DB10 FS1 DB3 DB11 FS2 C3 (0) DB12 FS3 C4 (0) DB13 FS4 DB4 DB14 FS5 BK1 DB15 FS6 ADDRESS BITS SK3 SK2 SK1 SEQ CLK DIVIDE BK2 BK1 BBOS CLK DIVIDE 0 0 . 1 1 0 1 . 1 1 1 0 . 0 1 1 2 . 254 255 0 0 1 1 0 1 0 1 4 8 16 32 OK4 OK3 OK2 OK1 DEMOD CLK DIVIDE 0 0 ... 1 INVALID 1 ... 15 0 0 ... 1 0 0 ... 1 0 1 ... 1 FS8 FS7 ... FS3 FS2 FS1 CDR CLK DIVIDE 0 0 . 1 1 0 0 . 1 1 ... ... ... ... ... 0 0 . 1 1 0 1 . 1 1 1 0 . 0 1 1 2 . 254 255 05876-033 GD5 DB16 ... ... ... ... ... ... DB17 0 0 . 1 1 FS7 DB22 SK5 DB18 DB23 SK6 SK7 0 0 . 1 1 FS8 DB24 SK7 SK1 DB25 SK8 DB19 DB26 GD1 DB20 DB27 GD2 SK2 DB28 GD3 SK3 DB29 GD4 DB21 DB30 GD5 SK8 GD6 DEM_CLK_ DIVIDE CDR_CLK_DIVIDE SK4 DB31 SEQUENCER_CLK_DIVIDE GD6 AGC_CLK_DIVIDE BBOS_CLK_ DIVIDE REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER Figure 65. Register 3—Transmit/Receive Clock Register Map Baseband offset clock frequency (BBOS CLK) must be greater than 1 MHz and less than 2 MHz, where XTAL BBOS CLK = BBOS _ CLK _ DIVIDE CDR CLK = CDR _ CLK _ DIVIDE The sequencer clock (SEQ CLK) supplies the clock to the digital receive block. It should be as close to 100 kHz as possible. Set the demodulator clock (DEMOD CLK) such that 2 MHz ≤ DEMOD CLK ≤ 15 MHz, where DEMOD CLK = DEMOD CLK XTAL DEMOD _ CLK _ DIVIDE SEQ CLK = XTAL SEQ _ CLK _ DIVIDE The time allowed for each AGC step to settle is determined by the AGC update rate. It should be set close to 10 kHz. For 2FSK/3FSK, the data/clock recovery frequency (CDR CLK) needs to be within 2% of (32 × data rate). For 4FSK, the CDR CLK needs to be within 2% of (32 × symbol rate). Rev. B | Page 50 of 64 AGC Update Rate [Hz] = SEQ CLK AGC _ CLK _ DIVIDE Data Sheet ADF7021 DW10 . POST DEMOD DW6 DW5 DW4 DW3 DW2 DW1 BW 0 0 . . . . 1 0 0 . . . . 1 0 0 . . . . 1 0 0 . . . . 1 CROSS PRODUCT DOT PRODUCT DB4 DB3 DB2 DB1 DB0 DS1 C4(0) C3(1) C2(0) C1(0) DB10 TD1 DB5 DB11 TD2 DS2 DB12 TD3 DB6 DB13 TD4 DB7 DB14 TD5 DS3 DB15 TD6 DP1 DB16 TD7 DB8 PRODUCT 0 1 NORMAL INVERT CLK INVERT DATA INVERT CLK/DATA DS3 DS2 DS1 0 0 0 0 1 1 1 1 1 2 . . . . 1023 TD10 . TD6 TD5 TD4 TD3 TD2 TD1 CORRELATOR DISCRIM BW 0 0 . . . . 1 0 0 . . . . 0 0 0 . . . . 1 0 0 . . . . 0 0 0 . . . . 1 0 1 . . . . 0 1 0 . . . . 0 1 2 . . . . 660 . . . . . . . DP1 ADDRESS BITS INVERT 1 0 . . . . 1 0 1 . . . . 1 RI1 DB17 0 1 0 1 DEMOD_ SCHEME 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DEMODULATOR SCHEME 2FSK LINEAR DEMODULATOR 2FSK CORRELATOR DEMODULATOR 3FSK DEMOD 4FSK DEMOD RESERVED RESERVED RESERVED RESERVED 05876-034 0 0 . . . . 1 0 0 1 1 DB9 DB18 TD9 TD8 RI2 RI1 RI2 DB19 TD10 DW1 DB20 DW2 DB21 DW3 DB22 DW4 DB23 DW5 DB24 DW6 DB25 DW7 DB26 DW8 DB27 DW9 DB28 DB30 IFB1 DW10 DB29 DB31 IFB2 IF FILTER IFB2 IFB1 BW 0 0 12.5kHz 1 0 18.75kHz 0 1 25kHz 1 1 INVALID . . . . . . . Rx_ INVERT DISCRIMINATOR_BW POST_DEMOD_BW IF_BW DOT_PRODUCT REGISTER 4—DEMODULATOR SETUP REGISTER Figure 66. Register 4—Demodulator Setup Register Map To solve for DISCRIMINATOR_BW, use the following equation: DISCRIMINATOR_BW = DEMOD CLK × K where the maximum value = 660. For 2FSK, 100 × 10 3 K = Round f DEV 400 × 10 3 where: Round is rounded to the nearest integer. Round4FSK is rounded to the nearest of the following integers: 32, 31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3. fDEV is the transmit frequency deviation in Hz. For 4FSK, fDEV is the frequency deviation used for the ±1 symbols (that is, the inner frequency deviations). Rx_INVERT (DB[8:9]) and DOT_PRODUCT (DB7) need to be set as outlined in Table 17 and Table 18. POST_DEMOD_BW = For 3FSK, 100 × 10 3 K = Round 2 × f DEV For 4FSK, 100 × 10 3 K = Round 4 FSK 4 × f DEV 211 × π × f CUTOFF DEMOD CLK where the cutoff frequency (fCUTOFF) of the post demodulator filter should typically be 0.75 × the data rate in 2FSK. In 3FSK, it should be set equal to the data rate, while in 4FSK, it should be set equal to 1.6 × symbol rate. Rev. B | Page 51 of 64 ADF7021 Data Sheet 0 0 0 . 1 0 0 1 . 1 IR GAIN ADJUST UP/DN 0 1 GAIN ATTENUATE 0 1 2 ... 31 IFA6 IFA5 ... 0 0 ... 0 0 ... 0 0 ... .. .. ... 0 1 ... 1 0 ... 1 0 ... 1 0 ... 1 . ... 1 1 ... IF_CAL_COARSE DB0 C1 (1) DB3 C4 (0) DB1 DB4 CC1 C2 (0) DB5 IFD1 DB2 DB6 IFD2 C3 (1) DB7 IFD3 CC1 CAL 0 1 NO CAL DO CAL IFD9 . FILTER CLOCK IFD6 IFD5 IFD4 IFD3 IFD2 IFD1 DIVIDE RATIO 0 0 . . . . 1 0 0 . . . . 1 . . . . . . . 0 0 . . . . 1 0 0 . . . . 1 0 0 . . . . 1 0 1 . . . . 1 1 0 . . . . 1 1 2 . . . . 511 IF FILTER IFA2 IFA1 ADJUST 0 0 1 .. 1 0 0 1 . 1 0 1 0 .. 1 0 1 0 . 1 0 +1 +2 ... +31 0 –1 –2 ... –31 05876-035 ADJUST I CH ADJUST Q CH 0 1 0 . 1 DB8 DB20 PM1 0 0 0 . 1 IFD4 DB21 PM2 IR GAIN GM2 GM1 ADJUST DB9 DB22 PM3 GM3 ADDRESS BITS IFD5 DB23 PM4 GM5 GM4 0 1 2 ... 15 IFD7 DB11 DB24 PD1 IR PHASE ADJUST I/Q ADJUST I CH ADJUST Q CH 0 1 0 . 1 IFD8 DB12 DB25 GM1 0 0 1 . 1 IF_FILTER_DIVIDER IFD9 DB13 DB26 GM2 0 0 0 . 1 IFA1 DB14 DB27 GM3 0 0 0 . 1 IFA2 DB15 DB28 GM4 IR PHASE PM1 PM1 ADJUST 0 1 GA1 IFA3 DB16 DB29 GM5 PM2 GQ1 IR GAIN ADJUST I/Q 0 1 IFA4 DB17 DB30 GQ1 PM3 PD1 0 0 0 . 1 IFA6 DB19 DB31 IF_FILTER_ADJUST IFD6 DB10 IR_PHASE_ ADJUST_MAG GA1 IR_GAIN_ ADJUST_MAG IFA5 DB18 IR PHASE ADJUST DIRECTION IR GAIN ADJUST UP/DN IR GAIN ADJUST I/Q REGISTER 5—IF FILTER SETUP REGISTER Figure 67. Register 5—IF Filter Setup Register Map A coarse IF filter calibration is performed when the IF_CAL_COARSE bit (DB4) is set. If the IF_FINE_CAL bit (R6_DB4) has been previously set, a fine IF filter calibration is automatically performed after the coarse calibration. Set IF_FILTER_DIVIDER such that XTAL = 50 kHz IF _ FILTER _ DIVIDER IF_FILTER_ADJUST allows the IF fine filter calibration result to be programmed directly on subsequent receiver power-ups, thereby saving on the need to redo a fine filter calibration in some instances. Refer to the Filter Bandwidth Calibration Readback section for information about using the IF_FILTER_ADJUST bits. DB[20:31] are used for image rejection calibration. Refer to the Image Rejection Calibration section for details on how to program these parameters. Rev. B | Page 52 of 64 Data Sheet ADF7021 IF_FINE_ CAL DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LT6 LT5 LT4 LT3 LT2 LT1 FC1 C4 (0) C3 (1) C2 (1) C1 (0) DB17 UT5 LT7 DB18 UT6 LT8 DB19 UT7 DB13 DB20 UT8 UT1 DB21 CD1 ADDRESS BITS DB14 DB22 CD2 DB15 DB23 CD3 UT3 DB24 CD4 IF_CAL_LOWER_TONE_DIVIDE UT2 DB25 CD5 DB16 DB26 UT4 DB27 IF_CAL_UPPER_TONE_DIVIDE CD6 IF_CAL_DWELL_TIME CD7 DB29 IR_CAL_ SOURCE_ IRC1 DB28 DRIVE_LEVEL IRC2 IRD1 DB30 IR_CAL_ SOURCE ÷2 REGISTER 6—IF FINE CAL SETUP REGISTER IRD1 IR CAL SOURCE ÷2 0 1 SOURCE ÷2 OFF SOURCE ÷2 ON UT8 UT7 ... 0 0 0 . . 0 IR CAL SOURCE IRC2 IRC1 DRIVE LEVEL 0 0 OFF 1 0 LOW 0 1 MED 1 1 HIGH 0 0 0 . . 1 ... ... ... ... ... ... UT3 UT2 UT1 IF CAL UPPER TONE DIVIDE 0 0 0 . . 1 0 1 1 . . 1 1 0 1 . . 1 1 2 3 . . 127 LT8 LT7 ... LT3 CD7 ... IF CAL CD3 CD2 CD1 DWELL TIME 0 0 0 . . 1 ... ... ... ... ... ... 0 0 0 . . 1 1 0 1 . . 1 1 2 3 . . 127 0 0 0 . . 1 ... ... ... ... ... ... 0 0 0 . . 1 IF FINE CAL 0 1 DISABLED ENABLED LT2 LT1 IF CAL LOWER TONE DIVIDE 0 1 1 . . 1 1 0 1 . . 1 1 2 3 . . 255 05876-036 0 1 1 . . 1 0 0 0 . . 1 FC1 Figure 68. Register 6—IF Fine Cal Setup Register Map A fine IF filter calibration is set by enabling the IF_FINE_CAL Bit (R6_DB4). A fine calibration is then carried out only when Register 5 is written to and R5_DB4 is set. Set the IF upper and lower tones used during fine filter calibration as follows: For best practice, is recommended to have the IF tone calibration time be at least 500 µs. IF Tone Calibration Time = IF _ CAL _ DWELL _ TIME SEQ CLK The total time for a fine IF filter calibration is XTAL = 65.8 kHz IF _ CAL _ LOWER _ TONE _ DIVIDE × 2 IF Tone Calibration Time × 10. XTAL = 131.5 kHz IF _ CAL _ UPPER _ TONE _ DIVIDE × 2 The IF tone calibration time is the amount of time that is spent at an IF calibration tone. It is dependent on the sequencer clock. DB[28:30] control the internal source for the image rejection (IR) calibration. The IR_CAL_SOURCE_DRIVE_LEVEL bits (DB[28:29]) set the drive strength of the source, whereas the IR_CAL_SOURCE_÷2 bit (DB30) allows the frequency of the internal signal source to be divided by 2. Rev. B | Page 53 of 64 ADF7021 Data Sheet REGISTER 7—READBACK SETUP REGISTER READBACK SELECT ADC MODE DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RB3 RB2 RB1 AD2 AD1 C4 (0) C3 (1) C2 (1) C1 (1) RB3 READBACK 0 1 CONTROL BITS AD2 AD1 ADC MODE DISABLED ENABLED RB2 RB1 READBACK MODE 0 1 0 1 0 1 0 1 MEASURE RSSI BATTERY VOLTAGE TEMP SENSOR TO EXTERNAL PIN AFC WORD ADC OUTPUT FILTER CAL SILICON REV 05876-037 0 0 1 1 0 0 1 1 Figure 69. Register 7—Readback Setup Register Map Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, temperature sensor, or voltage at the external pin is not valid in Rx mode. For AFC readback, use the following equations (see the Readback Format section): To read back the battery voltage, the temperature sensor, or the voltage at the external pin in Tx mode, users should first power up the ADC using R8_DB8 because it is turned off by default in Tx mode to save power. Rev. B | Page 54 of 64 FREQ RB [Hz] = (AFC_READBACK × DEMOD CLK)/218 VBATTERY = BATTERY_VOLTAGE_READBACK/21.1 VADCIN = ADCIN_VOLTAGE_READBACK/42.1 Temperature [°C] = −40 + (68.4 − TEMP_READBACK) × 9.32 Data Sheet ADF7021 PD6 SYNTH_ ENABLE LE1 RESERVED DB10 SW1 LNA/MIXER_ ENABLE DB11 PD7 FILTER_ ENABLE DB12 ADC_ ENABLE DB13 DEMOD_ ENABLE DB14 CR1 LOG_AMP_ ENABLE DB15 Tx/Rx_SWITCH_ ENABLE Rx_RESET PA_ENABLE_ Rx_MODE COUNTER_ RESET REGISTER 8—POWER-DOWN TEST REGISTER DB9 DB8 DB7 DB6 DB5 DB4 PD5 PD4 PD3 PD1 CR1 COUNTER RESET 0 1 NORMAL RESET CONTROL BITS DB3 DB2 DB1 DB0 C4 (1) C3 (0) C2 (0) C1 (0) PD1 SYNTH STATUS 0 1 SYNTH OFF SYNTH ON CDR RESET DEMOD RESET PD7 PA (Rx MODE) 0 1 PA OFF PA ON SW1 Tx/Rx SWITCH DEFAULT (ON) OFF LE1 LOG AMP ENABLE 0 1 LOG AMP OFF LOG AMP ON PD6 DEMOD ENABLE 0 1 DEMOD OFF DEMOD ON LNA/MIXER ENABLE 0 1 LNA/MIXER OFF LNA/MIXER ON PD4 FILTER ENABLE 0 1 FILTER OFF FILTER ON PD5 ADC ENABLE 0 1 ADC OFF ADC ON 05876-038 0 1 PD3 Figure 70. Register 8—Power-Down Test Register Map It is not necessary to write to this register under normal operating conditions. For a combined LNA/PA matching network, DB11 should always be set to 0, which enables the internal Tx/Rx switch. This is the power-up default condition. Rev. B | Page 55 of 64 ADF7021 Data Sheet 0 1 FILTER CURRENT 0 1 LOW HIGH 0 1 0 1 DB1 DB0 C2 (0) C1 (1) DB9 GL6 DB2 DB10 GL7 DB3 DB12 DB11 DB13 GH3 GH1 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 0 0 0 1 . . . 1 1 1 0 0 0 0 . . . 1 1 1 1 0 1 0 . . . 1 0 1 0 1 1 0 . . . 0 1 1 1 2 3 4 . . . 61 62 63 AGC HIGH GH7 GH6 GH5 GH4 GH3 GH2 GH1 THRESHOLD 0 0 0 0 . . . 1 1 1 FG2 FG1 FILTER GAIN 0 0 1 1 GH2 DB15 DB14 GH5 0 0 0 0 . . . 1 1 1 DEFAULT REDUCED GAIN FI1 C3 (0) DB16 GH6 AUTO AGC MANUAL AGC FREEZE AGC RESERVED LG1 LNA MODE 0 1 C4 (1) DB17 GH7 800µA (DEFAULT) DB4 DB18 GM1 LNA BIAS 0 GL1 DB19 GM2 LI1 0 DB6 DB20 LG1 LI2 DB5 DB21 LG2 0 1 2 3 GL3 DB22 FG1 GH4 AGC LOW GL7 GL6 GL5 GL4 GL3 GL2 GL1 THRESHOLD AGC MODE DEFAULT HIGH ADDRESS BITS AGC_LOW_THRESHOLD GL2 DB23 FG2 ML1 MIXER LINEARITY AGC_HIGH_THRESHOLD DB7 DB24 FI1 AGC_ MODE GL4 DB25 LG1 LNA_ CURRENT LNA_ GAIN DB8 FILTER_ CURRENT DB26 LI1 FILTER_ GAIN GL5 LNA_MODE DB27 LI2 MIXER_ LINEARITY DB28 ML1 REGISTER 9—AGC REGISTER 8 24 72 INVALID 0 0 0 0 . . . 0 0 0 0 0 0 0 . . . 0 0 1 0 0 0 0 . . . 1 1 0 0 0 0 1 . . . 1 1 0 0 1 1 0 . . . 1 1 0 1 0 1 0 . . . 0 1 0 1 2 3 4 . . . 78 79 80 LG2 LG1 LNA GAIN 0 1 0 1 3 10 30 INVALID 05876-039 0 0 1 1 Figure 71. Register 9—AGC Register Map In receive mode, AGC is set to automatic AGC by default on power-up. The default thresholds are AGC_LOW_THRESHOLD = 30 and AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC section for details. It is only necessary to program this register if AGC settings, other than the defaults, are required. AGC high and low settings must be more than 30 apart to ensure correct operation. An LNA gain of 30 is available only if LNA_MODE (DB25) is set to 0. Rev. B | Page 56 of 64 Data Sheet ADF7021 DB6 DB5 M2 M1 KP1 KP KI4 KI3 KI2 KI1 KI AE1 AFC ENABLE 0 0 . 1 0 1 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 1 . 1 2^0 2^1 ... 2^15 0 1 OFF AFC ON 0 0 . 1 2^0 2^1 ... 2^7 ... MAX AFC MA3 MA2 MA1 RANGE M12 ... M3 M2 M1 AFC SCALING FACTOR 0 0 0 0 . . . 1 1 1 ... ... ... ... ... ... ... ... ... ... 0 0 0 1 . . . 1 1 1 0 0 0 0 . . . 1 1 1 ... ... ... ... ... ... ... ... ... ... 0 0 0 1 . . . 1 1 1 0 1 1 0 . . . 0 1 1 1 0 1 0 . . . 1 0 1 1 2 3 4 . . . 4093 4094 4095 1 0 1 0 . . . 1 0 1 1 2 3 4 . . . 253 254 255 05876-040 DB7 DB0 DB8 M4 M3 C1 (0) DB9 M5 DB1 DB10 M6 DB2 DB11 M7 C2 (1) DB12 M8 C3 (0) DB13 M9 DB3 DB14 M10 C4 (1) DB15 M11 DB4 DB16 M12 KP3 KP2 MA8 0 1 1 0 . . . 0 1 1 ADDRESS BITS AE1 DB17 KI1 DB18 DB20 KI4 DB19 DB21 AFC SCALING_FACTOR KI2 DB22 KP2 KP1 KI3 DB23 DB26 MA3 KP3 DB27 MA4 DB24 DB28 MA5 DB25 DB29 MA6 KI MA1 DB30 MA7 KP MA2 DB31 MA8 MAX_AFC_RANGE AFC_EN REGISTER 10—AFC REGISTER Figure 72. Register 10—AFC Register Map To tradeoff between AFC settling time and AFC accuracy, the KI and KP parameters can be adjusted from the recommended settings (staying within the allowable range) such that The AFC_SCALING_FACTOR can be expressed as 2 24 × 500 AFC _ SCALING _ FACTOR = Round XTAL AFC Correction Range = MAX_AFC_RANGE × 500 Hz The settings for KI and KP affect the AFC settling time and AFC accuracy. The allowable range of each parameter is KI > 6 and KP < 7 The recommended settings to give optimal AFC performance are KI = 11 and KP = 4. When the RF_DIVIDE_BY_2 (R1_DB18) is enabled, the programmed AFC correction range is halved. The user accounts for this halving by doubling the programmed MAX_AFC_RANGE value. Signals that are within the AFC pull-in range but outside the IF filter bandwidth are attenuated by the IF filter. As a result, the signal can be below the sensitivity point of the receiver and, therefore, not detectable by the AFC. Rev. B | Page 57 of 64 ADF7021 Data Sheet DB0 C1 (1) DB6 MT1 DB1 DB7 MT2 C2 (1) DB8 SB1 DB2 DB9 SB2 DB3 DB10 SB3 C3 (0) DB11 SB4 C4 (1) DB12 SB5 DB4 DB13 SB6 CONTROL BITS PL1 DB14 SB7 PL2 DB15 SB8 DB5 MATCHING_ TOLERANCE DB16 SB9 SB10 DB17 SB11 DB18 SB12 DB19 SB13 DB20 SB14 DB21 SB15 DB22 SB16 DB23 SB17 DB24 SB18 DB25 SB19 DB26 SB20 DB27 SB21 DB28 SB22 DB29 SB23 DB30 SYNC_BYTE_SEQUENCE SB24 DB31 SYNC_BYTE_ LENGTH REGISTER 11—SYNC WORD DETECT REGISTER PL2 PL1 SYNC BYTE LENGTH 0 0 1 1 0 1 0 1 12 BITS 16 BITS 20 BITS 24 BITS 0 0 1 1 0 1 0 1 ACCEPT 0 ERRORS ACCEPT 1 ERROR ACCEPT 2 ERRORS ACCEPT 3 ERRORS 05876-041 MATCHING MT2 MT1 TOLERANCE Figure 73. Register 11—Sync Word Detect Register Map SWD_MODE LOCK_ THRESHOLD_ MODE REGISTER 12—SWD/THRESHOLD SETUP REGISTER DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DP7 DP6 DP5 DP4 DP3 DP2 DP1 IL2 IL1 LM2 LM1 C4 (1) C3 (1) C2 (0) C1 (0) CONTROL BITS DP8 DATA_PACKET_LENGTH DATA PACKET LENGTH 0 1 ... 255 INVALID 1 BYTE ... 255 BYTES SWD MODE 0 1 2 3 SWD PIN LOW SWD PIN HIGH AFTER NEXT SYNCWORD SWD PIN HIGH AFTER NEXT SYNCWORD FOR DATA PACKET LENGTH NUMBER OF BYTES INTERRUPT PIN HIGH 3 THRESHOLD FREE RUNNING LOCK THRESHOLD AFTER NEXT SYNCWORD LOCK THRESHOLD AFTER NEXT SYNCWORD FOR DATA PACKET LENGTH NUMBER OF BYTES LOCK THRESHOLD 05876-042 LOCK THRESHOLD MODE 0 1 2 Figure 74. Register 12—SWD/Threshold Setup Register Map Lock threshold locks the threshold of the envelope detector. This has the effect of locking the slicer in linear demodulation and locking the AFC and AGC loops when using linear or correlator demodulation. Rev. B | Page 58 of 64 Data Sheet ADF7021 REGISTER 13—3FSK/4FSK DEMOD REGISTER 0 0 1 1 0 1 0 1 DB3 DB1 DB0 C2 (0) C1 (1) DB4 ST1 DB2 DB5 C3 (1) DB6 ST3 ST2 C4 (1) DB7 CONTROL BITS ST4 DB9 ST6 DB8 DB10 ST7 ST5 DB11 3FSK/4FSK_ SLICER_THRESHOLD VD1 DB12 PC1 PHASE_ CORRECTION 3FSK_VITERBI_ DETECTOR DB13 VM1 VT4 DB19 VT5 VM2 VM1 DB14 OFF 1 2 3 . . 127 DB15 0 1 0 1 . . 1 VT1 0 0 1 1 . . 1 VM2 0 0 0 0 . . 1 DB17 ... ... ... ... ... ... ... DB16 0 0 0 0 . . 1 VT2 3FSK CDR THRESHOLD VT3 VT1 DB18 VT2 DB20 VT3 VT6 ... DB21 VT7 VT7 PTV1 DB22 3FSK_CDR_THRESHOLD PTV2 DB23 PTV3 DB24 PTV4 DB25 3FSK_PREAMBLE_ TIME_VALIDATE VITERBI_ PATH_ MEMORY Refer to the Receiver Setup section for information about programming these settings. 3FSK VITERBI VD1 DETECTOR 0 DISABLED 1 ENABLED PHASE PC1 CORRECTION 0 DISABLED 1 ENABLED VITERBI PATH MEMORY 4 BITS 6 BITS 8 BITS 32 BITS ST7 ... ST3 ST2 ST1 SLICER THRESHOLD 0 0 0 0 . . 1 ... ... ... ... ... ... ... 0 0 0 0 . . 1 0 0 1 1 . . 1 0 1 0 1 . . 1 OFF 1 2 3 . . 127 3FSK PREMABLE PTV4 PTV3 PTV2 PTV1 TIME VALIDATE 0 0 0 0 . . 1 0 0 1 1 . . 1 0 1 0 1 . . 1 0 1 2 3 . . 15 05876-043 0 0 0 0 . . 1 Figure 75. Register 13—3FSK/4FSK Demod Register Map Rev. B | Page 59 of 64 ADF7021 Data Sheet 0 1 2 3 4 5 6 7 ED PEAK RESPONSE TEST DAC GAIN 0 1 2 3 0 1 ... 15 FULL RESPONSE TO PEAK 0.5 RESPONSE TO PEAK 0.25 RESPONSE TO PEAK 0.125 RESPONSE TO PEAK TEST TDAC EN DB6 DB5 DB4 DB3 DB2 DB1 DB0 TO2 TE1 C4 (1) C3 (1) C2 (1) C1 (0) DB7 TO3 ADDRESS BITS TO1 DB9 DB8 TO6 TO4 DB10 TO7 TO5 DB12 DB11 TO8 DB13 TO9 TO11 DB15 TO10 DB14 TO12 DB16 TO14 DB18 DB21 TG1 TO13 DB17 DB22 TG2 TO15 DB19 DB23 TEST DAC OFFSET TO16 DB20 DB24 DB25 ER1 LEAKAGE = 2^–8 2^–9 2^–10 2^–11 2^–12 2^–13 2^–14 2^–15 TG3 DB26 ED LEAK FACTOR TEST_DAC_GAIN TG4 PULSE_ EXTENSION DB27 EF1 ER2 DB29 EF3 DB28 DB30 PE1 EF2 DB31 PE2 ED_LEAK_ FACTOR ED_PEAK_ RESPONSE REGISTER 14—TEST DAC REGISTER NO GAIN × 2^1 ... × 2^15 PULSE EXTENSION NO PULSE EXTENSION EXTENDED BY 1 EXTENDED BY 2 EXTENDED BY 3 05876-044 0 1 2 3 Figure 76. Register 14—Test DAC Register Map The demodulator tuning parameters, PULSE_EXTENSION, ED_LEAK_FACTOR, and ED_PEAK_RESPONSE, can only be enabled by setting R15_DB[4:7] to 0x9. Using the Test DAC to Implement Analog FM DEMOD and Measuring SNR The test DAC allows the post demodulator filter out for both linear and correlator demodulators to be viewed externally. The test DAC also takes the 16-bit filter output and converts it to a high frequency, single-bit output using a second-order, error feedback Σ-Δ converter. The output can be viewed on the SWD pin. This signal, when filtered appropriately, can then be used to do the following: • Monitor the signals at the FSK post demodulator filter output. This allows the demodulator output SNR to be measured. Eye diagrams of the received bit stream can also be constructed to measure the received signal quality. • Provide analog FM demodulation. While the correlators and filters are clocked by DEMOD CLK, CDR CLK clocks the test DAC. Note that although the test DAC functions in regular user mode, the best performance is achieved when the CDR_CLK is increased to or above the frequency of DEMOD CLK. The CDR block does not function when this condition exists. Programming Register 14 enables the test DAC. Both the linear and correlator/demodulator outputs can be multiplexed into the DAC. Register 14 allows a fixed offset term to be removed from the signal (to remove the IF component in the ddt case). It also has a signal gain term to allow the usage of the maximum dynamic range of the DAC. Rev. B | Page 60 of 64 Data Sheet ADF7021 DB0 C1 (1) DB5 RT2 DB1 DB6 RT3 DB2 DB7 RT4 C2 (1) DB8 TM1 C3 (1) DB9 TM2 DB3 DB10 ADDRESS BITS DB4 DB11 Rx_TEST_ MODES SD1 Tx_TEST_ MODES TM3 Σ-Δ_TEST_ MODES RT1 DB12 CLK_-MUX C4 (1) DB13 SD2 DB19 SD3 DB20 PM1 CM3 DB14 DB21 PM2 PC1 DB22 PM3 DB15 PFD/CP_TEST_ MODES DB23 PM4 PC2 DB24 AM1 DB16 DB25 AM2 DB17 DB26 AM3 PC3 DB27 AM4 DB18 DB28 FH1 PLL_TEST_ MODES CM1 DB29 RD1 ANALOG_TEST_ MODES CM2 REG 1_PD FORCE_LD HIGH DB30 CO1 CAL_ OVERRIDE DB31 CO2 REGISTER 15—TEST MODE REGISTER CAL OVERRIDE AUTO CAL OVERRIDE GAIN OVERRIDE BW OVERRIDE BW AND GAIN PFD/CP TEST MODES 0 1 2 3 4 5 6 7 REG1 PD 0 1 NORMAL PWR DWN DEFAULT, NO BLEED (+VE) CONSTANT BLEED (–VE) CONSTANT BLEED (–VE) PULSED BLEED (–VE) PULSE BLD, DELAY UP? CP PUMP UP CP TRI-STATE CP PUMP DN FORCE LD HIGH 0 1 Σ-Δ TEST MODES NORMAL FORCE 0 1 2 3 4 5 6 7 ANALOG TEST MODES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BAND GAP VOLTGE 40µA CURRENT FROM REG4 FILTER I CHANNEL: STAGE 1 FILTER I CHANNEL: STAGE 2 FILTER I CHANNEL: STAGE 1 FILTER Q CHANNEL: STAGE 1 FILTER Q CHANNEL: STAGE 2 FILTER Q CHANNEL: STAGE 1 ADC REFERENCE VOLTAGE BIAS CURRENT FROM RSSI 5µA FILTER COARSE CAL OSCILLATOR O/P ANALOG RSSI I CHANNEL OSET LOOP +VE FBACK V (I CH) SUMMED O/P OF RSSI RECTIFIER+ SUMMED O/P OF RSSI RECTIFIER– BIAS CURRENT FROM BB FILTER DEFAULT, 3RD ORDER SD, NO DITHER 1ST ORDER SD 2ND ORDER SD DITHER TO FIRST STAGE DITHER TO SECOND STAGE DITHER TO THIRD STAGE DITHER × 8 DITHER × 32 Tx TEST MODES 0 1 2 3 4 5 6 NORMAL OPERATION Tx CARRIER ONLY Tx +VE TONE ONLY Tx –VE TONE ONLY Tx "1010" PATTERN Tx PN9 DATA, AT PROGRAMED RATE Tx SYNC BYTE REPEATEDLY Rx TEST MODES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PLL TEST MODES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NORMAL OPERATION R DIV N DIV RCNTR/2 ON MUXOUT NCNTR/2 ON MUXOUT ACNTR TO MUXOUT PFD PUMP UP TO MUXOUT PFD PUMP DN TO MUXOUT SDATA TO MUXOUT (OR SREAD?) ANALOG LOCK DETECT ON MUXOUT END OF COARSE CAL ON MUXOUT END OF FINE CAL ON MUXOUT FORCE NEW PRESCALER CONFIG. FOR ALL N TEST MUX SELECTS DATA LOCK DETECT PERCISION RESERVED NORMAL SCLK, SDATA -> I, Q REVERSE I,Q I,Q TO TxRxCLK, TxRxDATA 3FSK SLICER ON TxRxDATA CORRELATOR SLICER ON TxRxDATA LINEAR SLICER ON RXDATA SDATA TO CDR ADDITIONAL FILTERING ON I, Q ENABLE REG 14 DEMOD PARAMETERS POWER DOWN DDT AND ED IN T/4 MODE ENVELOPE DETECTOR WATCHDOG DISABLED RESERVED PROHIBIT CALACTIVE FORCE CALACTIVE ENABLE DEMOD DURING CAL CLK MUXES on CLKOUT pin 0 1 2 3 4 5 6 7 NORMAL, NO OUTPUT DEMOD CLK CDR CLK SEQ CLK BB OFFSET CLK SIGMA DELTA CLK ADC CLK TxRxCLK Figure 77. Register 15—Test Mode Register Map Rev. B | Page 61 of 64 05876-045 0 1 2 3 ADF7021 Data Sheet OUTLINE DIMENSIONS 0.30 0.23 0.18 PIN 1 INDICATOR 48 37 36 1 0.50 BSC TOP VIEW 0.80 0.75 0.70 0.45 0.40 0.35 4.25 4.10 SQ 3.95 EXPOSED PAD 12 25 24 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD. 08-16-2010-B 7.00 BSC SQ Figure 78. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 7 mm × 7 mm Body, Very Very Thin Quad (CP-48-5) Dimensions shown in millimeters ORDERING GUIDE Model1 ADF7021BCPZ ADF7021BCPZ-RL ADF7021BCPZ-RL7 EVAL-ADF70XXMBZ EVAL-ADF70XXMBZ2 EVAL-ADF7021DBJZ EVAL-ADF7021DBZ2 EVAL-ADF7021DBZ3 EVAL-ADF7021DBZ5 EVAL-ADF7021DBZ6 EVAL-ADF7021DB9Z 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Control Mother Board Evaluation Platform 426 MHz to 429 MHz Daughter Board 860 MHz to 870 MHz Daughter Board 431 MHz to 470 MHz Daughter Board 80 MHz to 650 MHz Daughter Board 608 MHz to 614 MHz Daughter Board 169 MHz Daughter Board Z = RoHS Compliant Part. Rev. B | Page 62 of 64 Package Option CP-48-5 CP-48-5 CP-48-5 Data Sheet ADF7021 NOTES Rev. B | Page 63 of 64 ADF7021 Data Sheet NOTES ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05876-0-4/13(B) Rev. B | Page 64 of 64