Octal, 12-/14-/16-Bit SPI Voltage Output denseDAC with 5 ppm/°C On-Chip Reference Data Sheet AD5628/AD5648/AD5668 FEATURES FUNCTIONAL BLOCK DIAGRAM VREFIN/VREFOUT VDD AD5628/AD5648/AD5668 LDAC INPUT REGISTER INPUT REGISTER INPUT REGISTER SCLK SYNC INTERFACE LOGIC INPUT REGISTER INPUT REGISTER DIN INPUT REGISTER 1.25V/2.5V REF DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER STRING DAC B STRING DAC C STRING DAC D STRING DAC E STRING DAC F INPUT REGISTER DAC REGISTER STRING DAC G INPUT REGISTER DAC REGISTER STRING DAC H BUFFER VOUTA BUFFER VOUTB BUFFER VOUTC BUFFER VOUTD BUFFER VOUTE BUFFER VOUTF BUFFER VOUTG BUFFER VOUTH POWER-DOWN LOGIC POWER-ON RESET GND LDAC1 CLR1 APPLICATIONS STRING DAC A 1RU-16 PACKAGE ONLY 05302-001 Low power, small footprint, pin-compatible octal DACs AD5668: 16 bits AD5648: 14 bits AD5628: 12 bits 14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-lead WLCSP On-chip 1.25 V/2.5 V, 5 ppm/°C reference Power down to 400 nA @ 5 V, 200 nA @ 3 V 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale or midscale 3 power-down functions Hardware LDAC and LDAC override function CLR function to programmable code Rail-to-rail operation Figure 1. Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5628/AD5648/AD5668 devices are low power, octal, 12-/14-/16-bit, buffered voltage-output DACs. All devices operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design. The AD5668 and AD5628 are available in both a 4 mm × 4 mm LFCSP and a 16-lead TSSOP, while the AD5648 is available in both a 14-lead and 16-lead TSSOP. The AD5628/AD5648/AD5668 have an on-chip reference with an internal gain of 2. The AD5628-1/AD5648-1/AD5668-1 have a 1.25 V 5 ppm/°C reference, giving a full-scale output range of 2.5 V; the AD5628-2/AD5648-2/AD5668-2 and AD5668-3 have a 2.5 V 5 ppm/°C reference, giving a full-scale output range of 5 V. The on-board reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write. The part incorporates a power-on reset circuit that ensures that the DAC output powers up to 0 V (AD5628-1/AD5648-1/AD5668-1, AD5628-2/AD5648-2/AD5668-2) or midscale (AD5668-3) and remains powered up at this level until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 400 nA at 5 V and provides softwareRev. G selectable output loads while in power-down mode for any or all DAC channels. The outputs of all DACs can be updated simultaneously using the LDAC function, with the added functionality of user-selectable DAC channels to simultaneously update. There is also an asynchronous CLR that updates all DACs to a userprogrammable code—zero scale, midscale, or full scale. The AD5628/AD5648/AD5668 utilize a versatile 3-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The on-chip precision output amplifier enables rail-to-rail output swing. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Octal, 12-/14-/16-bit DAC. On-chip 1.25 V/2.5 V, 5 ppm/°C reference. Available in 14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-lead WLCSP. Power-on reset to 0 V or midscale. Power-down capability. When powered down, the DAC typically consumes 200 nA at 3 V and 400 nA at 5 V. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5628/AD5648/AD5668 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 D/A Section ................................................................................. 21 Applications ....................................................................................... 1 Resistor String ............................................................................. 21 Functional Block Diagram .............................................................. 1 Internal Reference ...................................................................... 21 General Description ......................................................................... 1 Output Amplifier ........................................................................ 22 Product Highlights ........................................................................... 1 Serial Interface ............................................................................ 22 Revision History ............................................................................... 2 Input Shift Register .................................................................... 23 Specifications..................................................................................... 3 SYNC Interrupt .......................................................................... 23 AC Characteristics ........................................................................ 6 Internal Reference Register ....................................................... 24 Timing Characteristics ................................................................ 7 Power-On Reset .......................................................................... 24 Absolute Maximum Ratings ............................................................ 8 Power-Down Modes .................................................................. 24 ESD Caution .................................................................................. 8 Clear Code Register ................................................................... 24 Pin Configurations and Function Descriptions ........................... 9 LDAC Function .......................................................................... 26 Typical Performance Characteristics ........................................... 11 Power Supply Bypassing and Grounding ................................ 26 Terminology .................................................................................... 19 Outline Dimensions ....................................................................... 27 Theory of Operation ...................................................................... 21 Ordering Guide .......................................................................... 29 REVISION HISTORY 1/13—Rev. F to Rev. G Added WLCSP Reference TC of 15 ppm/°C, Table 2 .................. 5 Changes to Ordering Guide .......................................................... 29 8/11—Rev. E to Rev. F Added 16-Lead WLCSP ..................................................... Universal Added Figure 6 and Table 7; Renumbered Sequentially ........... 10 Changes to Figure 32 and Figure 33............................................. 15 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 28 1/11—Rev. D to Rev. E Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset Error, and Reference TC Parameters, Table 1 ............................... 3 Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset Error, and Reference TC Parameters, Table 2 ............................... 5 Changes to Output Voltage Settling Time, Table 3 ...................... 6 Added Figure 53; Renumbered Sequentially .............................. 17 Change to Output Amplifier Section ........................................... 21 Changes to Ordering Guide .......................................................... 28 9/10—Rev. C to Rev. D Change to Title .................................................................................. 1 Added 16-Lead LFCSP Throughout ................................ Universal Changes to Table 1 ............................................................................ 3 Changes to Table 2.............................................................................5 Changes to Table 3.............................................................................6 Changes to Table 4.............................................................................7 Deleted SnPb from Table 5 ...............................................................8 Added Figure 5; Renumbered Sequentially ...................................9 Changes to Table 6.............................................................................9 Replaced Typical Performance Characteristics Section ............ 10 Changes to Power-On Reset Section ........................................... 23 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 28 1/10—Rev. B to Rev. C Changes to Figure 3 ........................................................................ 10 Changes to Ordering Guide .......................................................... 28 2/09—Rev. A to Rev. B Changes to Reference Current Parameter, Table 1........................3 Changes to IDD (Normal Mode) Parameter, Table 1......................4 Changes to Reference Current Parameter, Table 2........................5 Changes to IDD (Normal Mode) Parameter, Table 2......................6 11/05—Rev. 0 to Rev. A Change to Specifications ..................................................................3 10/05—Revision 0: Initial Version Rev. G | Page 2 of 32 Data Sheet AD5628/AD5648/AD5668 SPECIFICATIONS VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE 2 AD5628 Resolution Relative Accuracy Differential Nonlinearity A Grade 1 Min Typ Max B Grade1 Min Typ Max 12 12 ±0.5 ±1 ±0.25 Bits LSB LSB ±2 ±4 ±0.5 Bits LSB LSB ±32 ±1 ±8 ±16 ±1 Bits LSB LSB 19 6 ±2 −0.2 19 ±0.5 ±4 ±0.25 ±2 ±8 ±0.5 ±8 Zero-Code Error Zero-Code Error Drift Full-Scale Error 6 ±2 −0.2 Gain Error Gain Temperature Coefficient Offset Error DC Power Supply Rejection Ratio DC Crosstalk (External Reference) ±2.5 ±6 –80 10 AD5648 Resolution Relative Accuracy Differential Nonlinearity AD5668 Resolution Relative Accuracy Differential Nonlinearity 14 OUTPUT CHARACTERISTICS Output Voltage Range Capacitive Load Stability 14 16 16 −1 ±1 DC Crosstalk (Internal Reference) Unit −1 ±1 ±2.5 ±6 –80 10 ±19 ±19 mV µV/°C % FSR % FSR ppm mV dB µV 5 10 25 5 10 25 µV/mA µV µV 10 10 µV/mA Conditions/Comments See Figure 9 Guaranteed monotonic by design (see Figure 12) See Figure 8 Guaranteed monotonic by design (see Figure 11) See Figure 7 Guaranteed monotonic by design (see Figure 10) All 0s loaded to DAC register (see Figure 26) All 1s loaded to DAC register (see Figure 27) Of FSR/°C VDD ± 10% Due to full-scale output change, RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) Due to full-scale output change, RL = 2 kΩ to GND or VDD Due to load current change 3 DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT Output Voltage AD56x8-2, AD56x8-3 Reference TC3 Reference Output Impedance 0 VDD 0 2 10 0.5 30 4 40 0 55 VDD 40 0 14.6 2.495 5 15 7.5 VDD 2 10 0.5 30 4 2.495 5 5 7.5 Rev. G | Page 3 of 32 RL = ∞ RL = 2 kΩ VDD = 5 V Coming out of power-down mode, VDD = 5 V 55 VDD µA V kΩ VREF = VDD = 5.5 V (per DAC channel) 2.505 10 10 V ppm/°C ppm/°C kΩ At ambient TSSOP LFCSP 14.6 2.505 10 V nF nF Ω mA µs AD5628/AD5648/AD5668 Parameter LOGIC INPUTS3 Input Current Input Low Voltage, VINL Input High Voltage, VINH Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V IDD (All Power-Down Modes) 5 VDD = 4.5 V to 5.5 V Data Sheet A Grade 1 Min Typ Max B Grade1 Min Typ Max ±3 0.8 2 Unit Conditions/Comments ±3 0.8 µA V V pF All digital inputs VDD = 5 V VDD = 5 V 5.5 V 2 3 4.5 3 5.5 4.5 1.0 1.8 1.5 2.25 1.0 1.7 1.5 2.25 mA mA All digital inputs at 0 or VDD, DAC active, excludes load current VIH = VDD and VIL = GND Internal reference off Internal reference on 0.4 1 0.4 1 µA VIH = VDD and VIL = GND Temperature range is −40°C to +105°C, typical at 25°C. Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16,256), and AD5668 (Code 512 to 65,024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. 1 2 Rev. G | Page 4 of 32 Data Sheet AD5628/AD5648/AD5668 VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE 2 AD5628 Resolution Relative Accuracy Differential Nonlinearity AD5648 Resolution Relative Accuracy Differential Nonlinearity AD5668 Resolution Relative Accuracy Differential Nonlinearity A Grade 1 Min Typ Max B Grade1 Min Typ Max 12 12 Reference Output Impedance ±2 ±8 ±0.5 ±0.5 ±1 ±0.25 Bits LSB LSB ±2 ±4 ±0.5 Bits LSB LSB Bits LSB LSB 14 16 16 ±8 ±32 ±1 ±8 ±16 ±1 6 ±2 −0.2 19 6 ±2 −0.2 19 ±2.5 ±6 –80 DC Crosstalk 3 (Internal Reference) DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT Output Voltage AD5628/AD5648/AD5668-1 Reference TC3 ±4 ±0.25 14 Zero-Code Error Zero-Code Error Drift Full-Scale Error Gain Error Gain Temperature Coefficient Offset Error DC Power Supply Rejection Ratio3 DC Crosstalk 3 (External Reference) OUTPUT CHARACTERISTICS 3 Output Voltage Range Capacitive Load Stability ±0.5 −1 ±1 ±2.5 ±6 –80 ±19 Unit −1 ±1 ±19 mV µV/°C % FSR % FSR ppm mV dB 10 10 µV 5 10 25 5 10 25 µV/mA µV µV 10 10 µV/mA 0 VDD 0 VDD 2 10 0.5 30 4 40 0 2 10 0.5 30 4 55 VDD 40 0 14.6 1.247 5 15 7.5 55 VDD 14.6 1.253 15 1.247 5 5 15 7.5 Conditions/Comments See Figure 9 Guaranteed monotonic by design (see Figure 12) See Figure 8 Guaranteed monotonic by design (see Figure 11) See Figure 7 Guaranteed monotonic by design (see Figure 10) All 0s loaded to DAC register (see Figure 26) All 1s loaded to DAC register (see Figure 27) Of FSR/°C VDD ± 10% Due to full-scale output change, RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) Due to full-scale output change, RL = 2 kΩ to GND or VDD Due to load current change V nF nF Ω mA µs VDD = 3 V Coming out of power-down mode, VDD = 3 V µA VREF = VDD = 5.5 V (per DAC channel) RL = ∞ RL = 2 kΩ kΩ 1.253 15 15 Rev. G | Page 5 of 32 V ppm/°C ppm/°C ppm/°C kΩ At ambient TSSOP LFCSP WLCSP AD5628/AD5648/AD5668 Parameter LOGIC INPUTS3 Input Current Input Low Voltage, VINL Input High Voltage, VINH Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 2.7 V to 3.6 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) 5 VDD = 2.7 V to 3.6 V Data Sheet A Grade 1 Min Typ Max B Grade1 Min Typ Max ±3 0.8 2 Unit Conditions/Comments ±3 0.8 µA V V pF All digital inputs VDD = 3 V VDD = 3 V 3.6 V 2 3 2.7 3 3.6 2.7 1.0 1.8 1.5 2.25 1.0 1.7 1.5 2.25 mA mA All digital inputs at 0 or VDD, DAC active, excludes load current VIH = VDD and VIL = GND Internal reference off Internal reference on 0.2 1 0.2 1 µA VIH = VDD and VIL = GND Temperature range is −40°C to +105°C, typical at 25°C. Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16256), and AD5668 (Code 512 to 65024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. 1 2 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1, 2 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise Min Typ 2.5 1.2 4 Max 7 19 0.1 0.2 0.4 0.8 320 −80 120 100 12 Unit µs V/µs nV-s nV-s nV-s nV-s nV-s nV-s kHz dB nV/√Hz nV/√Hz μV p-p Conditions/Comments 3 ¼ to ¾ scale settling to ±2 LSB (16-bit resolution) 1 LSB(16-bit resolution) change around major carry (see Figure 42) From code 0xEA00 to code 0xE9FF (16-bit resolution) VREF = 2 V ± 0.2 V p-p VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz DAC code = 0x8400(16-bit resolution), 1 kHz DAC code = 0x8400(16-bit resolution), 10 kHz 0.1 Hz to 10 Hz, DAC code = 0x0000 Guaranteed by design and characterization; not production tested. See the Terminology section. 3 Temperature range is −40°C to +105°C, typical at 25°C. 1 2 Rev. G | Page 6 of 32 Data Sheet AD5628/AD5648/AD5668 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX VDD = 2.7 V to 5.5 V 20 8 8 13 4 4 0 15 13 0 10 15 5 0 300 Parameter t1 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge set-up time Data set-up time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to SCLK fall ignore SCLK falling edge to SYNC fall ignore LDAC pulse width low SCLK falling edge to LDAC rising edge CLR pulse width low SCLK falling edge to LDAC falling edge CLR pulse activation time Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested. t10 t1 t9 SCLK t8 t3 t4 t2 t7 SYNC t6 t5 DIN DB31 DB0 t14 t11 LDAC1 t12 LDAC2 CLR VOUT t13 t15 05302-002 1 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns typ 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Serial Write Operation Rev. G | Page 7 of 32 AD5628/AD5648/AD5668 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND Digital Input Voltage to GND VOUT to GND VREFIN/VREFOUT to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ MAX) TSSOP Package Power Dissipation θJA Thermal Impedance Reflow Soldering Peak Temperature Pb Free Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +105°C −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION (TJ MAX − TA)/θJA 150.4°C/W 260°C Rev. G | Page 8 of 32 Data Sheet AD5628/AD5648/AD5668 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 13 DIN 14 SCLK 16 SYNC 15 LDAC AD5628/AD5668 VDD 1 13 DIN VOUTA 3 VOUTC 4 VOUTE 5 VOUTG 6 VREFIN/VREFOUT 7 TOP VIEW (Not to Scale) DIN VOUTE 4 14 GND VDD 3 AD5628/ AD5648/ AD5668 12 GND VOUTA 4 11 VOUTB VOUTC 5 10 VOUTD VOUTE 6 11 VOUTF 9 VOUTF VOUTG 7 10 VOUTH 8 VOUTH 8 9 05302-003 AD5628/ AD5648/ 15 VREFIN/VREFOUT TOP VIEW (Not to Scale) 13 VOUTB 12 VOUTD CLR Figure 4. 16-Lead TSSOP (RU-16) Figure 3. 14-Lead TSSOP (RU-14) 10 VOUTD 9 VOUTF NOTES 1. EXPOSED PAD MUST BE TIED TO GND. 05302-005 2 SYNC 2 TOP VIEW (Not to Scale) CLR 7 VDD VOUTC 3 11 VOUTB VOUTH 8 14 SCLK SCLK VOUTG 5 1 16 05302-004 SYNC LDAC 1 12 GND VREFIN/VREFOUT 6 VOUTA 2 Figure 5. 16-Lead LFCSP(CP-16-17) Table 6. Pin Function Descriptions Pin No. 14-Lead TSSOP 16-Lead TSSOP Mnemonic Description 1 16-Lead LFCSP 15 N/A LDAC 1 2 16 SYNC 2 3 1 VDD 3 11 4 10 7 4 13 5 12 8 2 11 3 10 6 VOUTA VOUTB VOUTC VOUTD VREFIN/ VREFOUT N/A 9 7 CLR 5 9 6 8 12 13 6 11 7 10 14 15 4 9 5 8 12 13 VOUTE VOUTF VOUTG VOUTH GND DIN 14 16 14 SCLK EPAD EPAD Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. The AD5628/AD5648/AD5668 have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V. Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. It is recommended that the exposed paddle be soldered to the ground plane. Rev. G | Page 9 of 32 AD5628/AD5648/AD5668 Data Sheet BALL A1 INDICATOR 2 1 GND SCL 3 4 DIN SYNC A VOUTB LDAC VDD VOUTA B VOUTF VOUTD VOUTE VOUTC VOUTH CLR VREF VOUTG D 05302-006 C TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 6. 16-Lead WLCSP Table 7. 16-Lead WLCSP Pin Function Descriptions Pin. No. B2 Mnemonic Description LDAC A4 SYNC B3 VDD B4 B1 C4 C2 D3 VOUTA VOUTB VOUTC VOUTD VREFIN/VREFOUT D2 CLR C3 C1 D4 D1 A1 A3 VOUTE VOUTF VOUTG VOUTH GND DIN A4 SCLK Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. The AD5628/AD5648/AD5668 have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V. Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Rev. G | Page 10 of 32 Data Sheet AD5628/AD5648/AD5668 TYPICAL PERFORMANCE CHARACTERISTICS 8 0.6 4 0.4 2 0.2 DNL (LSB) 6 0 –2 0 –0.2 –4 –0.4 –6 –0.6 –8 –0.8 –10 0 10k 20k 30k 40k 50k 60k 65535 CODES VDD = 5V EXT REF = 5V TA = 25°C 0.8 –1.0 05302-106 INL (LSB) 1.0 VDD = 5V EXT REF = 5V TA = 25°C 0 30k 40k 50k 60k 65535 Figure 10. DNL AD5668—External Reference 0.5 VDD = 5V EXT REF = 5V TA = 25°C 3 20k CODES Figure 7. INL AD5668—External Reference 4 10k 05302-109 10 VDD = 5V 0.4 EXT REF = 5V TA = 25°C 0.3 2 0.2 INL (LSB) INL (LSB) 1 0 –1 0.1 0 –0.1 –0.2 –2 –0.3 –3 5k 10k 15k 16384 CODES –0.5 05302-107 0 0 15k 16384 Figure 11. DNL AD5648—External Reference 0.20 VDD = 5V EXT REF = 5V TA = 25°C 0.8 10k CODES Figure 8. INL AD5648—External Reference 1.0 5k 05302-110 –0.4 –4 VDD = 5V EXT REF = 5V 0.15 TA = 25°C 0.6 0.10 DNL (LSB) 0.2 0 –0.2 0.05 0 –0.05 –0.4 –0.10 –0.6 –1.0 0 500 1000 1500 2000 2500 3000 3500 CODES 4095 Figure 9. INL AD5628—External Reference –0.20 0 500 1000 1500 2000 2500 3000 3500 CODES Figure 12. DNL AD5628—External Reference Rev. G | Page 11 of 32 4095 05302-111 –0.15 –0.8 05302-108 INL (LSB) 0.4 AD5628/AD5648/AD5668 10 Data Sheet 1.0 VDD = 5V INT REF = 2.5V TA = 25°C 0.5 DNL (LSB) 5 0 –5 0 –0.5 0 10k 20k 30k 40k 50k 60k 65535 CODES –1.0 05302-112 –10 0 20k 10k 30k 40k 50k 60k 65535 CODES Figure 13. INL AD5668-2/AD5668-3 05302-115 INL (LSB) VDD = 5V INT REF = 2.5V TA = 25°C Figure 16. DNL AD5668-2/AD5668-3 4 0.5 VDD = 5V EXT REF = 5V 3 T = 25°C A VDD = 5V 0.4 EXT REF = 2.5V TA = 25°C 0.3 2 0.2 DNL (LSB) INL (LSB) 1 0 –1 0.1 0 –0.1 –0.2 –2 –0.3 –3 5k 10k 15k 16383 CODES –0.5 05302-113 0 0 5k Figure 14. INL AD5648-2 15k 16383 Figure 17. DNL AD5648-2 0.20 1.0 VDD = 5V INT REF = 2.5V 0.15 TA = 25°C VDD = 5V INT REF = 2.5V TA = 25°C 0.10 DNL (LSB) 0.5 0 0.05 0 –0.05 –0.10 –0.5 –1.0 0 500 1000 1500 2000 2500 CODES 3000 3500 4095 –0.20 0 500 1000 1500 2000 2500 3000 CODES Figure 18. DNL AD5628-2 Figure 15. INL AD5628-2 Rev. G | Page 12 of 32 3500 4095 05302-117 –0.15 05302-114 INL (LSB) 10k CODES 05302-116 –0.4 –4 Data Sheet AD5628/AD5648/AD5668 10 1.0 VDD = 3V INT REF = 1.25V TA = 25°C 8 VDD = 3V INT REF = 1.25V TA = 25°C 6 0.5 2 DNL (LSB) INL (LSB) 4 0 –2 0 –4 –0.5 –6 0 10k 20k 30k 40k 50k 60k 65535 CODES –1.0 05302-118 –10 0 10k 20k 30k 40k 50k 60k 65535 CODES Figure 19. INL AD5668-1 05302-121 –8 Figure 22. DNL AD5668-1 4 0.5 VDD = 3V EXT REF = 1.25V 3 T = 25°C A VDD = 3V 0.4 EXT REF = 1.25V TA = 25°C 0.3 2 0.2 DNL (LSB) INL (LSB) 1 0 –1 0.1 0 –0.1 –0.2 –2 –0.3 –3 5k 10k 15k 16383 CODES –0.5 05302-119 0 0 5k Figure 20. INL AD5648-1 1.0 Figure 23. DNL AD5648-1 0.20 VDD = 3V INT REF = 1.25V TA = 25°C VDD = 3V INT REF = 1.25V TA = 25°C 0.15 0.5 DNL (LSB) 0.10 0 0.05 0 –0.05 –0.5 –0.10 –1.0 0 500 1000 1500 2000 2500 CODES 3000 3500 4095 Figure 21. INL AD5628-1 –0.20 0 500 1000 1500 2000 2500 3000 CODES Figure 24. DNL AD5628-1 Rev. G | Page 13 of 32 3500 4095 05302-123 –0.15 05302-120 INL (LSB) 15k 16383 10k CODES 05302-122 –0.4 –4 AD5628/AD5648/AD5668 Data Sheet 0 1.95 VDD = 5V TA = 25°C 1.90 –0.05 OFFSET ERROR ERROR (mV) ERROR (% FSR) 1.85 –0.10 FULL-SCALE ERROR –0.15 1.80 1.75 1.70 ZERO-SCALE ERROR –0.20 GAIN ERROR 1.65 –0.25 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 1.55 2.7 05302-124 –0.30 –40 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) Figure 25. Gain Error and Full-Scale Error vs. Temperature 05302-127 1.60 Figure 28. Zero-Scale Error and Offset Error vs. Supply Voltage 21 6 VDD = 5V 18 5 OFFSET ERROR 15 NUMBER OF HITS ERROR (mV) 4 ZERO-SCALE ERROR 3 2 12 9 6 1 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 0 0.85 Figure 26. Zero-Scale Error and Offset Error vs. Temperature 0.90 0.95 1.00 IDD WITH EXTERNAL REFERENCE (mA) 1.05 05302-128 –25 05302-125 0 –40 3 Figure 29. IDD Histogram with External Reference 18 –0.16 TA = 25°C FULL-SCALE ERROR –0.17 16 –0.18 14 NUMBER OF HITS –0.20 –0.21 –0.22 –0.23 10 8 6 GAIN ERROR 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) 0 1.65 1.70 1.75 1.80 1.85 IDD WITH INTERNAL REFERENCE (mA) Figure 30. IDD Histogram with Internal Reference Figure 27. Gain Error and Full-Scale Error vs. Supply Voltage Rev. G | Page 14 of 32 1.190 05302-129 2 –0.25 –0.26 2.7 12 4 –0.24 05302-126 ERROR (% FSR) –0.19 Data Sheet AD5628/AD5648/AD5668 1.8 0.4 TA = 25°C TA = 25°C 1.7 0.3 1.6 0 VDD = 5V 1.5 0.1 VDD = 3V, INT REF = 1.25V IDD (mA) –0.1 1.4 VDD = 3V 1.3 1.2 –0.2 1.1 –0.3 1.0 VDD = 5V, INT REF = 2.5V –0.4 0.9 –8 –6 –4 –2 0 2 4 6 8 10 SOURCE/SINK CURRENT (mA) 0.8 05302-130 –0.5 –10 0 10k 20k 30k 40k 50k 05302-133 ERROR VOLTAGE (V) 0.2 60k DIGITAL CODES (Decimal) Figure 34. Supply Current vs. Code Figure 31. Headroom at Rails vs. Source and Sink 6 2.0 VDD = 5V INT REF = 2.5V T 5 A = 25°C FULL SCALE 1.9 1.8 3/4 SCALE 3 1.7 IDD (mA) VOUT (V) 4 MIDSCALE 2 VDD = 5.5V 1.6 1.5 VDD = 3.6V 1.4 1/4 SCALE 1.3 1 1.2 0 –0.02 –0.01 0 0.01 0.02 0.03 CURRENT (A) 1.0 –40 05302-131 –1 –0.03 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 32. AD5668-2/AD5668-3 Source and Sink Capability 05302-134 1.1 ZERO SCALE Figure 35. Supply Current vs. Temperature 1.48 4.0 VDD = 3V 3.5 INT REF = 1.25V TA = 25°C TA = 25°C 1.46 3.0 FULL SCALE 1.44 1.5 IDD (mA) 3/4 SCALE 2.0 MIDSCALE 1.42 1.40 1.0 1/4 SCALE 1.38 0.5 ZERO SCALE 0 1.36 –1.0 –0.03 –0.02 –0.01 0 0.01 0.02 CURRENT (A) 0.03 1.34 2.7 3.1 3.5 3.9 4.3 4.7 5.1 VDD (V) Figure 36. Supply Current vs. Supply Voltage Figure 33. AD5668-1 Source and Sink Capability Rev. G | Page 15 of 32 5.5 05302-135 –0.5 05302-132 VOUT (V) 2.5 AD5628/AD5648/AD5668 2.3 Data Sheet 5.5 TA = 25°C 2.1 VDD = 5V 5.0 EXT REF = 5V TA = 25°C 4.5 1.9 4.0 VOLTAGE (V) IDD (mA) VDD 3.5 1.7 VDD = 5V 1.5 1.3 3.0 2.5 VOUTA 2.0 1.5 1.1 1.0 VDD = 3V 0.9 0.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VLOGIC (V) 05302-136 0 –0.5 –0.0010 5 –0.0002 0.0002 0.0006 0.0010 TIME (s) Figure 37. Supply Current vs. Logic Input Voltage 6 –0.0006 05302-139 0 0.7 Figure 40. Power-On Reset to Midscale 5.5 VDD = 5V EXT REF = 5V TA = 25°C 5.0 4.5 24TH CLK RISING EDGE VDD = 5V EXT REF = 5V TA = 25°C 4.0 3.5 VOLTAGE (V) VOUT (V) 4 3 3.0 2.5 VOUTA 2.0 2 1.5 1.0 1 0.5 2 4 6 8 TIME (µs) 05302-137 0 –0.5 –10 5.0 4.5 5 10 Figure 41. Exiting Power-Down to Midscale VDD = 5V EXT REF = 5V TA = 25°C 4.0 0 TIME (µs) Figure 38. Full-Scale Settling Time, 5 V 5.5 –5 T VDD = 5V EXT REF = 5V TA = 25°C VDD 3.0 VOUTA 2.5 3 2.0 1.5 1.0 24TH CLK RISING EDGE 0.5 VOUTA –0.0006 –0.0002 0.0002 0.0006 TIME (s) 0.0010 Figure 39. Power-On Reset to 0 V 4 CH3 10.0mV B W CH4 5.0V M400ns T 17.0% A CH4 1.50V Figure 42. Digital-to-Analog Glitch Impulse (Negative) Rev. G | Page 16 of 32 05302-141 0 –0.5 –0.0010 05302-138 VOLTAGE (V) 3.5 05302-140 0 0 –2 Data Sheet 0.0010 AD5628/AD5648/AD5668 0.20 VDD = 5V EXT REF = 5V TA = 25°C EXT REF = 2.5V 0.15 0.10 OUTPUT NOISE (V) GLITCH AMPLITUDE (V) 0.0005 0 –0.0005 0.05 0 –0.05 –0.10 –0.0010 –0.15 1 2 3 4 5 6 7 8 9 TIME (µs) –0.20 0 3 4 5 6 7 8 9 10 Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, External Reference 0.0020 0.20 VDD = 5V EXT REF = 5V TA = 25°C 0.0015 INT REF = 1.25V 0.15 0.10 0.0010 OUTPUT NOISE (V) 0.0005 0 –0.0005 0.05 0 –0.05 –0.10 –0.0010 –0.15 1 2 3 4 5 6 7 8 TIME (µs) –0.20 0 2 3 4 5 6 7 8 9 10 TIME (s) Figure 44. DAC-to-DAC Crosstalk 0.06 1 05302-146 0 05302-143 –0.0015 Figure 47. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference 800 EXT REF = 5V 700 OUTPUT NOISE (nV/ Hz) 0.04 0.02 0 –0.02 –0.04 –0.06 600 500 400 VREF = 2.5V 300 200 100 0 1 2 3 4 5 6 7 8 9 10 TIME (s) 05302-144 VREF = 1.25V –0.08 Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, External Reference 0 100 1k 10k 100k FREQUENCY (Hz) Figure 48. Noise Spectral Density, Internal Reference Rev. G | Page 17 of 32 1M 05302-147 GLITCH AMPLITUDE (V) 2 TIME (s) Figure 43. Analog Crosstalk OUTPUT VOLTAGE (V) 1 05302-145 0 05302-142 –0.0015 AD5628/AD5648/AD5668 Data Sheet 10 0 VDD = 5.5V EXT REF = 5V –20 TA = 25°C VREF = 2V ± 0.1V p-p FREQUENCY = 10kHz –40 0 –10 –80 –30 –40 –50 –100 –60 –120 –70 0 2000 4000 6000 8000 10,000 FREQUENCY (Hz) –80 10 05302-148 –140 CH A CH B CH C CH D CH E CH F CH G CH H –3dB 100 VDD = 5.5V EXT REF = 5V TA = 25°C VREF = 2V ± 0.2V p-p 1k 1k0 100k 1M Figure 52. Multiplying Bandwidth 1.2510 TA = 25°C VDD = 5.5V 1.2508 8 1.2506 VDD = EXTERNAL REFERENCE = 5V REFERENCE (ppm/°C) 7 SETTLING TIME (µs) 100M FREQUENCY (Hz) Figure 49. Total Harmonic Distortion 9 10M 05302-151 VOUT (dBm) THD (dB) –20 –60 6 5 4 3 1.2504 1.2502 1.2500 1.2498 1.2496 VDD = EXTERNAL REFERENCE = 3V 1.2494 2 1.2492 1 1 2 3 4 5 6 7 8 9 10 CAPACITIVE LOAD (nF) –40 05302-149 0 25 05302-152 1.2490 0 105 TEMPERATURE (°C) Figure 53. 1.25 V Reference Temperature Coefficient vs. Temperature Figure 50. Settling Time vs. Capacitive Load 2.503 5.5 EXT REF = 5V 5.0 2.502 4.5 2.501 REFERENCE (ppm/°C) 4.0 3.0 VOUTA 2.5 2.0 1.5 CLR PULSE 2.500 2.499 2.498 2.497 1.0 0.5 2.496 –0.5 –10 –5 0 TIME (µs) 5 10 Figure 51. Hardware CLR 2.495 105 25 TEMPERATURE (°C) –40 05302-154 0 05302-150 VOLTAGE (V) 3.5 Figure 54. 2.5 V Reference Temperature Coefficient vs. Temperature Rev. G | Page 18 of 32 Data Sheet AD5628/AD5648/AD5668 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. Figure 7 to Figure 9, Figure 13 to Figure 15, and Figure 19 to Figure 21 show plots of typical INL vs. code. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Figure 10 to Figure 12, Figure 16 to Figure 18, and Figure 22 to Figure 24 show plots of typical DNL vs. code. Offset Error Offset error is a measure of the difference between the actual VOUT and the ideal VOUT, expressed in millivolts in the linear region of the transfer function. Offset error is measured on the AD5668 with Code 512 loaded into the DAC register. It can be negative or positive and is expressed in millivolts. Zero-Code Error Zero-code error is a measure of the output error when zero code (0x0000) is loaded into the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5628/AD5648/AD5668, because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in millivolts. Figure 28 shows a plot of typical zerocode error vs. temperature. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. Zero-Code Error Drift Zero-code error drift is a measure of the change in zero-code error with a change in temperature. It is expressed in µV/°C. Gain Error Drift Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be VDD – 1 LSB. Full-scale error is expressed as a percentage of the full-scale range. Figure 25 shows a plot of typical full-scale error vs. temperature. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 42. DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in decibels. VREF is held at 2 V, and VDD is varied ±10%. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in microvolts. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in microvolts per milliamp. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (that is, LDAC is high). It is expressed in decibels. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device, but is measured when the DAC is not being written to (SYNC held high). It is specified in nV-s and measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s. Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s or vice versa) while keeping LDAC high, and then pulsing LDAC low and monitoring the output of the DAC whose digital code has not changed. The area of the glitch is expressed in nV-s. Rev. G | Page 19 of 32 AD5628/AD5648/AD5668 Data Sheet DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Total Harmonic Distortion (THD) Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Rev. G | Page 20 of 32 Data Sheet AD5628/AD5648/AD5668 THEORY OF OPERATION D/A SECTION R The AD5628/AD5648/AD5668 DACs are fabricated on a CMOS process. The architecture consists of a string of DACs followed by an output buffer amplifier. Each part includes an internal 1.25 V/2.5 V, 5 ppm/°C reference with an internal gain of 2. Figure 55 shows a block diagram of the DAC architecture. R TO OUTPUT AMPLIFIER R VDD VREFIN REF OUTPUT AMPLIFIER (GAIN = ×2) DAC REGISTER VOUT R R 05302-053 GND 05302-153 RESISTOR STRING Figure 55. DAC Architecture Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by Figure 56. Resistor String INTERNAL REFERENCE D VOUT VREFIN N 2 The ideal output voltage when using the internal reference is given by D VOUT 2 V REFOUT N 2 where: D = decimal equivalent of the binary code that is loaded to the DAC register. 0 to 4095 for AD5628 (12 bits). 0 to 16,383 for AD5648 (14 bits). 0 to 65,535 for AD5668 (16 bits). N = the DAC resolution. The AD5628/AD5648/AD5668 have an on-chip reference with an internal gain of 2. The AD5628/AD5648/AD5668-1 have a 1.25 V, 5 ppm/°C reference, giving a full-scale output of 2.5 V; the AD5628/AD5648/AD5668-2, -3 have a 2.5 V, 5 ppm/°C reference, giving a full-scale output of 5 V. The on-board reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a write to the control register (see Table 8). The internal reference associated with each part is available at the VREFOUT pin. A buffer is required if the reference output is used to drive external loads. When using the internal reference, it is recommended that a 100 nF capacitor be placed between the reference output and GND for reference stability. Individual channel power-down is not supported while using the internal reference. RESISTOR STRING The resistor string section is shown in Figure 56. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Rev. G | Page 21 of 32 AD5628/AD5648/AD5668 Data Sheet Table 8. Command Definitions OUTPUT AMPLIFIER The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. The amplifier is capable of driving a load of 2 kΩ in parallel with 200 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 32 and Figure 33. The slew rate is 1.5 V/μs with a ¼ to ¾ scale settling time of 7 μs. SERIAL INTERFACE The AD5628/AD5648/AD5668 have a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 32-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5628/AD5648/AD5668 compatible with high speed DSPs. On the 32nd falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in DAC register contents and/or a change in the mode of operation. At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 15 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. SYNC should be idled low between write sequences for even lower power operation of the part. As is mentioned previously, however, SYNC must be brought high again just before the next write sequence. C3 0 0 0 0 0 0 0 0 1 1 – 1 Command C2 C1 0 0 0 0 0 1 0 1 1 1 1 0 0 – 1 1 0 0 1 1 0 0 – 1 C0 0 1 0 1 0 1 0 1 0 1 – 1 Description Write to Input Register n Update DAC Register n Write to Input Register n, update all (software LDAC) Write to and update DAC Channel n Power down/power up DAC Load clear code register Load LDAC register Reset (power-on reset) Set up internal REF register Reserved Reserved Reserved Table 9. Address Commands A3 0 0 0 0 0 0 0 0 1 Rev. G | Page 22 of 32 Address (n) A2 A1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 A0 0 1 0 1 0 1 0 1 1 Selected DAC Channel DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H All DACs Data Sheet AD5628/AD5648/AD5668 INPUT SHIFT REGISTER SYNC INTERRUPT The input shift register is 32 bits wide. The first four bits are don’t cares. The next four bits are the command bits, C3 to C0 (see Table 8), followed by the 4-bit DAC address, A3 to A0 (see Table 9) and finally the 16-/14-/12-bit data-word. The dataword comprises the 16-/14-/12-bit input code followed by four, six, or eight don’t care bits for the AD5668, AD5648, and AD5628, respectively (see Figure 57 through Figure 59). These data bits are transferred to the DAC register on the 32nd falling edge of SCLK. In a normal write sequence, the SYNC line is kept low for 32 falling edges of SCLK, and the DAC is updated on the 32nd falling edge and rising edge of SYNC. However, if SYNC is brought high before the 32nd falling edge, this acts as an interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 60). DB31 (MSB) X X DB0 (LSB) X X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X COMMAND BITS 05302-054 DATA BITS ADDRESS BITS Figure 57. AD5668 Input Register Contents DB31 (MSB) X X DB0 (LSB) X X C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X COMMAND BITS 05302-055 DATA BITS ADDRESS BITS Figure 58. AD5648 Input Register Contents DB31 (MSB) X X X C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X COMMAND BITS 05302-056 DATA BITS ADDRESS BITS Figure 59. AD5628 Input Register Contents SCLK SYNC DIN DB31 DB0 INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 32ND FALLING EDGE DB31 DB0 VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 32ND FALLING EDGE Figure 60. SYNC Interrupt Facility Rev. G | Page 23 of 32 05302-057 X DB0 (LSB) AD5628/AD5648/AD5668 Data Sheet INTERNAL REFERENCE REGISTER The on-board reference is off at power-up by default. This allows the use of an external reference if the application requires it. The on-board reference can be turned on or off by a user-programmable internal REF register by setting Bit DB0 high or low (see Table 10). Command 1000 is reserved for setting the internal REF register (see Table 8). Table 12 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device. POWER-ON RESET The AD5628/AD5648/AD5668 family contains a power-on reset circuit that controls the output voltage during power-up. The AD5628/AD5648/AD5668-1, -2 DAC output powers up to 0 V, and the AD5668-3 DAC output powers up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. There is also a software executable reset function that resets the DAC to the power-on reset code. Command 0111 is reserved for this reset function (see Table 8). Any events on LDAC or CLR during power-on reset are ignored. POWER-DOWN MODES The AD5628/AD5648/AD5668 contain four separate modes of operation. Command 0100 is reserved for the power-down function (see Table 8). These modes are software-programmable by setting two bits, Bit DB9 and Bit DB8, in the control register. Table 12 shows how the state of the bits corresponds to the mode of operation of the device. Any or all DACs (DAC H to DAC A) can be powered down to the selected mode by setting the corresponding eight bits (DB7 to DB0) to 1. See Table 13 for the contents of the input shift register during power-down/powerup operation. When using the internal reference, only all channel power-down to the selected modes is supported. When both bits are set to 0, the part works normally with its normal power consumption of 1.3 mA at 5 V. However, for the three power-down modes, the supply current falls to 0.4 µA at 5 V (0.2 µA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected internally to GND through either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited (three-state). The output stage is illustrated in Figure 61. The bias generator of the selected DAC(s), output amplifier, resistor string, and other associated linear circuitry are shut down when the power-down mode is activated. The internal reference is powered down only when all channels are powered down. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 µs for VDD = 5 V and for VDD = 3 V. See Figure 41 for a plot. Any combination of DACs can be powered up by setting PD1 and PD0 to 0 (normal operation). The output powers up to the value in the input register (LDAC low) or to the value in the DAC register before powering down (LDAC high). CLEAR CODE REGISTER The AD5628/AD5648/AD5668 have a hardware CLR pin that is an asynchronous clear input. The CLR input is falling edge sensitive. Bringing the CLR line low clears the contents of the input register and the DAC registers to the data contained in the user-configurable CLR register and sets the analog outputs accordingly. This function can be used in system calibration to load zero scale, midscale, or full scale to all channels together. These clear code values are user-programmable by setting two bits, Bit DB1 and Bit DB0, in the CLR control register (see Table 14). The default setting clears the outputs to 0 V. Command 0101 is reserved for loading the clear code register (see Table 8). The part exits clear code mode on the 32nd falling edge of the next write to the part. If CLR is activated during a write sequence, the write is aborted. The CLR pulse activation time—the falling edge of CLR to when the output starts to change—is typically 280 ns. However, if outside the DAC linear region, it typically takes 520 ns after executing CLR for the output to start changing (see Figure 51). See Table 15 for contents of the input shift register during the loading clear code register operation. Rev. G | Page 24 of 32 Data Sheet AD5628/AD5648/AD5668 Table 10. Internal Reference Register Internal REF Register (DB0) 0 1 Action Reference off (default) Reference on Table 11. 32-Bit Input Shift Register Contents for Reference Set-Up Command MSB DB31 to DB28 X Don’t cares DB27 DB26 DB25 DB24 1 0 0 0 Command bits (C3 to C0) DB23 DB22 DB21 DB20 X X X X Address bits (A3 to A0)—don’t cares DB19 to DB1 X Don’t cares LSB DB0 1/0 Internal REF register Table 12. Power-Down Modes of Operation DB9 0 DB8 0 0 1 1 1 0 1 Operating Mode Normal operation Power-down modes 1 kΩ to GND 100 kΩ to GND Three-state Table 13. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function DB27 DB26 DB25 DB24 DB23 DB22 DB21 X 0 1 0 0 X X X Don’t cares LSB Command bits (C3 to C0) DB20 DB19 to DB10 DB9 DB8 DB7 X X PD1 PD0 Don’t cares Powerdown mode DAC DAC DAC DAC DAC DAC DAC DAC H G F E D C B A Power-down/power-up channel selection—set bit to 1 to select Address bits (A3 to A0)— don’t cares RESISTOR STRING DAC AMPLIFIER POWER-DOWN CIRCUITRY DB6 DB5 DB4 DB3 DB2 DB1 DB0 VOUT RESISTOR NETWORK 05302-058 MSB DB31 to DB28 Figure 61. Output Stage During Power-Down Table 14. Clear Code Register DB1 CR1 0 0 1 1 Clear Code Register DB0 CR0 0 1 0 1 Clears to Code 0x0000 0x8000 0xFFFF No operation Table 15. 32-Bit Input Shift Register Contents for Clear Code Function MSB DB31 to DB28 X Don’t cares DB27 DB26 DB25 DB24 0 1 0 1 Command bits (C3 to C0) DB23 DB22 DB21 DB20 X X X X Address bits (A3 to A0)—don’t cares Rev. G | Page 25 of 32 DB19 to DB2 X Don’t cares LSB DB1 DB0 CR1 CR0 Clear code register AD5628/AD5648/AD5668 Data Sheet pin. See Table 17 for the contents of the input shift register during the load LDAC register mode of operation. LDAC FUNCTION The outputs of all DACs can be updated simultaneously using the hardware LDAC pin. POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5628/AD5648/ AD5668 should have separate analog and digital sections. If the AD5628/AD5648/AD5668 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5628/AD5648/AD5668. Synchronous LDAC: After new data is read, the DAC registers are updated on the falling edge of the 32nd SCLK pulse. LDAC can be permanently low or pulsed as in Figure 2. Asynchronous LDAC: The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register. The power supply to the AD5628/AD5648/AD5668 should be bypassed with 10 µF and 0.1 µF capacitors. The capacitors should physically be as close as possible to the device, with the 0.1 µF capacitor ideally right up against the device. The 10 µF capacitors are the tantalum bead type. It is important that the 0.1 µF capacitor has low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic types of capacitors. This 0.1 µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. Alternatively, the outputs of all DACs can be updated simultaneously using the software LDAC function by writing to Input Register n and updating all DAC registers. Command 0011 is reserved for this software LDAC function. An LDAC register gives the user extra flexibility and control over the hardware LDAC pin. This register allows the user to select which combination of channels to simultaneously update when the hardware LDAC pin is executed. Setting the LDAC bit register to 0 for a DAC channel means that this channel’s update is controlled by the LDAC pin. If this bit is set to 1, this channel updates synchronously; that is, the DAC register is updated after new data is read, regardless of the state of the LDAC pin. It effectively sees the LDAC pin as being tied low. (See Table 16 for the LDAC register mode of operation.) This flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. Writing to the DAC using command 0110 loads the 8-bit LDAC register (DB7 to DB0). The default for each channel is 0, that is, the LDAC pin works normally. Setting the bits to 1 means the DAC channel is updated regardless of the state of the LDAC Table 16. LDAC Register Load DAC Register LDAC Bits (DB7 to DB0) LDAC Pin LDAC Operation 0 1 Determined by LDAC pin. DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0. 1/0 X—don’t care Table 17. 32-Bit Input Shift Register Contents for LDAC Register Function MSB DB31 to DB28 X Don’t cares LSB DB27 0 DB26 1 DB25 1 DB24 0 Command bits (C3 to C0) DB23 X DB22 X DB21 X DB20 X Address bits (A3 to A0)— don’t cares DB19 to DB8 X Don’t cares Rev. G | Page 26 of 32 DB7 DAC H DB6 DB5 DB4 DB3 DB2 DB1 DAC DAC DAC DAC DAC DAC G F E D C B Setting LDAC bit to 1 overrides LDAC pin DB0 DAC A Data Sheet AD5628/AD5648/AD5668 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.20 0.09 SEATING PLANE 0.30 0.19 8° 0° 0.75 0.60 0.45 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 62. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 63. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. G | Page 27 of 32 AD5628/AD5648/AD5668 PIN 1 INDICATOR Data Sheet 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC PIN 1 INDICATOR 16 13 12 1 EXPOSED PAD 2.70 2.60 SQ 2.50 4 9 0.80 0.75 0.70 0.45 0.40 0.35 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.20 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 08-16-2010-C TOP VIEW 5 8 COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters 2.645 2.605 SQ 2.565 4 3 2 1 A BALL A1 IDENTIFIER B 1.50 REF C D 0.50 REF SEATING PLANE BOTTOM VIEW (BALL SIDE UP) SIDE VIEW COPLANARITY 0.05 0.340 0.320 0.300 0.270 0.240 0.210 Figure 65. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-16) Dimensions shown in millimeters Rev. G | Page 28 of 32 10-23-2012-A 0.650 0.595 0.540 TOP VIEW (BALL SIDE DOWN) Data Sheet AD5628/AD5648/AD5668 ORDERING GUIDE Model 1 AD5628BRUZ-1 AD5628BRUZ-1REEL7 AD5628BRUZ-2 AD5628BRUZ-2REEL7 AD5628ARUZ-2 AD5628ARUZ-2REEL7 AD5628ACPZ-1-RL7 AD5628ACPZ-2-RL7 AD5628BCPZ-2-RL7 AD5628BCBZ-1-RL7 AD5648BRUZ-1 AD5648BRUZ-1REEL7 AD5648BRUZ-2 AD5648BRUZ-2REEL7 AD5648ARUZ-2 AD5648ARUZ-2REEL7 AD5668BRUZ-1 AD5668BRUZ-1REEL7 AD5668BRUZ-2 AD5668BRUZ-2REEL7 AD5668BRUZ-3 AD5668BRUZ-3REEL7 AD5668ARUZ-2 AD5668ARUZ-2REEL7 AD5668ARUZ-3 AD5668ARUZ-3REEL7 AD5668BCPZ-1-RL7 AD5668BCPZ-1500RL7 AD5668BCPZ-2-RL7 AD5668BCPZ-2500RL7 AD5668ACPZ-2-RL7 AD5668ACPZ-3-RL7 AD5668BCBZ-1-RL7 EVAL-AD5668SDCZ EVAL-AD5668SDRZ 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 14-Lead TSSOP 14-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead WLCSP 14-Lead TSSOP 14-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead WLCSP LFCSP Evaluation Board TSSOP Evaluation Board Z = RoHS Compliant Part. Rev. G | Page 29 of 32 Package Option RU-14 RU-14 RU-16 RU-16 RU-16 RU-16 CP-16-17 CP-16-17 CP-16-17 CB-16-16 RU-14 RU-14 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 CP-16-17 CP-16-17 CP-16-17 CP-16-17 CP-16-17 CP-16-17 CB-16-16 Power-On Reset to Code Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Zero Midscale Midscale Zero Zero Midscale Midscale Zero Zero Zero Zero Zero Midscale Zero Accuracy ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±2 LSB INL ±2 LSB INL ±2 LSB INL ±2 LSB INL ±1 LSB INL ±1 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±8 LSB INL ±8 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±32 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±32 LSB INL ±32 LSB INL ±16 LSB INL Internal Reference 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 2.5 V 2.5 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V AD5628/AD5648/AD5668 Data Sheet NOTES Rev. G | Page 30 of 32 Data Sheet AD5628/AD5648/AD5668 NOTES Rev. G | Page 31 of 32 AD5628/AD5648/AD5668 Data Sheet NOTES ©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05302-0-1/13(G) Rev. G | Page 32 of 32