CAT504 8-Bit Quad DACpot FEATURES APPLICATIONS ■ Output settings retained without power ■ Automated product calibration. ■ Output range includes both supply rails ■ Remote control adjustment of equipment ■ 4 independently addressable outputs ■ Offset, gain and zero adjustments in Self- Calibrating and Adaptive Control systems. ■ 1 LSB Accuracy ■ Serial µP interface ■ Tamper-proof calibrations. ■ Single supply operation: 2.7V-5.5V ■ Setting read-back without effecting outputs DESCRIPTION The CAT504 is a quad 8-Bit Memory DAC designed as an electronic replacement for mechanical potentiometers and trim pots. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for systems capable of self calibration, and applications where equipment which is either difficult to access or in a hazardous environment, requires periodic adjustment. Control of the CAT504 is accomplished with a simple 3 wire serial interface. A Chip Select pin allows several CAT504s to share a common serial interface and communication back to the host controller is via a single serial data line thanks to the CAT504’s Tri-Stated Data Output pin. The CAT504 operates from a single 3–5 volt power supply drawing just a few milliwatts of power. When storing data in EEPROM memory an additional 20 volt low current supply is required. The 4 independently programmable DAC's have an output range which includes both supply rails. Output settings, stored in non-volatile EEPROM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each output can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the DAC’s output. The CAT504 is available in the 0 to 70° C Commercial and –40° C to + 85° C Industrial operating temperature ranges and offered in 14-pin plastic DIP and Surface mount packages. FUNCTIONAL DIAGRAM PIN CONFIGURATION PROG 7 VPP VDD 3 1 VREF H DIP Package (P) PROGRAM CONTROL DAC 1 DI CLK CS 5 DAC 2 2 SERIAL CONTROL SOIC Package (J) 14 13 12 VDD CLK VPP V 1 OUT CS DI DO VOUT 2 DATA REGISTER & EEPROM DAC 3 4 DAC 4 SERIAL DATA OUTPUT REGISTER 11 10 6 PROG 1 14 2 13 VREFH VOUT1 12 CAT 4 11 504 5 10 6 9 VOUT2 VOUT3 VOUT4 VREFL 3 7 8 GND VDD CLK VPP CS DI DO PROG 1 14 2 13 VREFH VOUT1 12 4 CAT 11 504 5 10 6 9 VOUT2 VOUT3 VOUT4 VREFL 7 GND 3 8 VOUT 3 V 4 OUT DO CAT504 8 GND © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 VREF L 1 Doc. No. 25048-0A 2/98 M-1 CAT504 ABSOLUTE MAXIMUM RATINGS* Operating Ambient Temperature Commercial (‘C’ suffix) .................... 0°C to +70°C Industrial (‘I’ suffix) ...................... – 40°C to +85°C Junction Temperature ..................................... +150°C Storage Temperature ....................... –65°C to +150°C Lead Soldering (10 sec max) .......................... +300°C Supply Voltage VDD to GND ...................................... –0.5V to +7V VPP to GND ..................................... –0.5V to +22V Inputs CLK to GND ............................ –0.5V to VDD +0.5V CS to GND .............................. –0.5V to VDD +0.5V DI to GND ............................... –0.5V to VDD +0.5V PROG to GND ........................ –0.5V to VDD +0.5V VREFH to GND ........................ –0.5V to VDD +0.5V VREFL to GND ......................... –0.5V to VDD +0.5V Outputs D0 to GND ............................... –0.5V to VDD +0.5V VOUT 1– 4 to GND ................... –0.5V to VDD +0.5V * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. RELIABILITY CHARACTERISTICS Symbol Parameter Min VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up 2000 100 Max Units Test Method Volts mA MIL-STD-883, Test Method 3015 JEDEC Standard 17 NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V. DC ELECTRICAL CHARACTERISTICS: VDD = 2.7V to 5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max 8 — — Bits ILOAD = 250 nA, TR = C TR = I ILOAD = 1 µA, TR = C TR = I ILOAD = 250 nA, TR = C TR = I ILOAD = 1 µA, TR = C TR = I — — — — — — — — — — — — — — — — ±1 ±1 ±2 ±2 ± 0.5 ± 0.5 ± 1.5 ± 1.5 LSB LSB LSB LSB LSB LSB LSB LSB VIN = VDD VIN = 0V — — 2 0 — — — — 10 –10 VDD 0.8 µA µA V V 2.7 GND — — — 7k VDD VDD -2.7 — V V Ω VDD –0.3 — — — — — — 0.4 0.4 V V V Resolution Units Accuracy INL Integral Linearity Error DNL Differential Linearity Error Logic Inputs IIH IIL VIH VIL Input Leakage Current Input Leakage Current High Level Input Voltage Low Level Input Voltage References VRH VRL ZIN VREFH Input Voltage Range VREFL Input Voltage Range VREFH–VREFL Resistance Logic Outputs VOH VOL High Level Output Voltage Low Level Output Voltage Doc. No. 25048-0A 2/98 M-1 IOH = – 40 µA IOL = 1 mA, VDD = +5V IOL = 0.4 mA, VDD = +3V 2 CAT504 DC ELECTRICAL CHARACTERISTICS (Cont.): VDD = 2.7V to 5.5V, VREFH = +VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units 0.99 VR — — — — — 0.995 VR 0.005 VR — — — — — 0.10 VR 1 20k 40k 1 V V µA Ω Ω LSB / V — — 200 µV/ °C — 700 — — — 2.7 18 — 200 — 19 50 500 5.5 20 µA µA V V Min Typ Max Units 150 100 0 50 50 — — — — 3 150 500 300 DC — — — — — — — 400 400 5 — — — — — — — — — 150 150 — — — — — — 1 ns ns ns ns ns ns ns ns ns ms ns ns ns MHz CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V — — 3 6 10 10 µs µs VIN = 0V, f = 1 MHz(2) VOUT = 0V, f = 1 MHz(2) — — 8 6 — — pF pF Analog Output FSO ZSO IL ROUT Full-Scale Output Voltage Zero-Scale Output Voltage DAC Output Load Current DAC Output Impedance PSSR Power Supply Rejection VR = VREFH–VREFL VR = VREFH–VREFL VDD = +5V VDD = +3V ILOAD = 250 nA Temperature TCO VOUT Temperature Coefficient TCREF Temperature Coefficient of VREF Resistance VREFH = +5V, VREFL = 0V VDD = +5V, ILOAD = 250nA VREFH to VREFL ppm / °C Power Supply IDD IPP VDD VPP Supply Current Programming Current Operating Voltage Range Programing Voltage Range Excludes VREF VPP = +19V AC ELECTRICAL CHARACTERISTICS: VDD = 2.7V to 5.5V, VREFH = +VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tPROG tPS tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Pulse Width PROG Setup Time Minimum CLK High Time Minimum CLK Low Time Clock Frequency CL = 100 pF see note 1 Analog tDS DAC Settling Time to 1/2 LSB Pin Capacitance CIN COUT Input Capacitance Output Capacitance NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. 3 Doc. No. 25048-0A 2/98 M-1 Doc. No. 25048-0A 2/98 M-1 4 PROG DO DI CS CLK to to t LZ t DIS t CSS 1 1 t DO1 t DIH 2 2 t CLK H t PS 3 t CLK L 3 t DO0 4 t PROG t CSH 4 t HZ t CSMIN 5 5 FROM TIMING TO Rising CS edge to D0 becoming high low impedance (active output) t LZ Rising PROG edge to next rising CLK edge t PS t PROG Rising PROG edge to falling PROG edge Falling CS edge to D0 becoming high impedance (Tri-State) t HZ Rising CLK edge to D0 = high Rising CLK edge to D0 = low t DO0 t DO1 Rising CLK edge to end of data valid t DIH Min Min (Max) Max (Max) Max Min Min Data valid to first rising CLK edge after CS = high t DIS Min Min Rising CS edge to next rising CLK edge t CSMIN Falling CS edge to rising CS edge t CSS Min t CSH Falling CLK edge for last data bit (DI) to falling CS edge Min Min MIN/MAX t CLK L Falling CLK edge to CLK rising edge t CLK H Rising CLK edge to falling CLK edge PARAM NAME CAT504 A. C. TIMING DIAGRAM CAT504 PIN DESCRIPTION DAC addressing is as follows: Pin Name Function 1 2 3 4 5 6 7 VDD CLK VPP CS DI DO PROG 8 9 10 11 12 13 14 GND VREFL VOUT4 VOUT3 VOUT2 VOUT1 VREFH Power supply positive. Clock input pin EEPROM Programming Voltage Chip Select Serial data input pin. Serial data output pin. EEPROM Programming Enable Input Power supply ground. Minimum DAC output voltage. DAC output channel 4. DAC output channel 3. DAC output channel 2. DAC output channel 1. Maximum DAC output voltage. DEVICE OPERATION DAC OUTPUT A0 A1 VOUT1 0 0 VOUT2 1 0 VOUT3 0 1 VOUT4 1 1 read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DAC control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DAC outputs to the settings stored in EEPROM memory and switches DO to its high impedance Tri-State mode. The CAT504 is a quad 8-bit Digital to Analog Converter (DAC) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile EEPROM memory and will not be lost when power is removed from the chip. Upon power up the DACs return to the settings stored in EEPROM memory. Each DAC can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be temporarily adjusted without changing the stored output setting, which is useful for testing new output settings before storing them in memory. Because CS functions like a reset the CS pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT504’s clock controls both data flow in and out of the IC and EEPROM memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to EEPROM memory, even though the data being saved may already be resident in the DAC control register. DIGITAL INTERFACE The CAT504 employs a standard 3 wire serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DAC address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. No clock is necessary upon system power-up. The CAT504’s internal power-on reset circuitry loads data from EEPROM to the DACs without using the external clock. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. CHIP SELECT Chip Select (CS) enables and disables the CAT504’s read and write operations. When CS is high data may be 5 Doc. No. 25048-0A 2/98 M-1 CAT504 VREF CS high, a start bit followed by a two bit DAC address and eight data bits are clocked into the DAC control register via the DI pin. Data enters on the clock’s rising edge. The DAC output changes to its new setting on the clock cycle following D7, the last data bit. VREF, the voltage applied between pins VREFH andVREFL, sets the DAC’s Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH andVREFL are connected across the power supply rails. When using less than the full supply voltage VREFH is restricted to voltages between VDD and VDD/2 and VREFL to voltages between GND and VDD/2. Programming is achieved by bringing PROG high for a minimum of 3 ms while supplying 18 to 20 volts to the VPP pin. PROG must be brought high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DAC control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of ramping the programming voltage for data transfer to the EEPROM cells. The CAT504’s EEPROM memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. VPP When saving data to non-volatile EEPROM memory an external voltage of 18–20 volts must be applied to the VPP pin. This voltage need only be present during the programming cycle and may be removed or turned off the remainder of the time. While it is not necessary to remove or power down VPP between programming cycles, some power sensitive applications may choose to do so. In such cases, the VPP supply must be given sufficient time to come up and stabilize before issuing the PROG command. READING DATA Each time data is transferred into a DAC control register currently held data is shifted out via the DI pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DAC’s output. This feature allows µPs to poll DACs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in EEPROM so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the EEPROM’s setting is reloaded into the DAC control register. Since this value is the same as that which had been there previously no change in the DAC’s output is noticed. Had the value held in the control register been different from that stored in EEPROM then a change would occur at the read cycle’s conclusion. DATA OUTPUT Data is output serially by the CAT504, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 504s to share a single serial data line and simplifies interfacing multiple 504s to a microprocessor. WRITING TO MEMORY Programming the CAT504’s EEPROM memory is accomplished through the application of an externally generated programming voltage, VPP, and the control signals: Chip Select (CS) and Program (PROG). With Figure 1. Writing to Memory to 1 2 3 4 5 6 7 8 9 Figure 2. Reading from Memory 10 11 12 N to N+1 N+2 1 2 3 4 5 6 7 8 9 10 11 12 CS CS NEW DAC DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 DI D6 D7 DO 1 A0 A1 CURRENT DAC DATA CURRENT DAC DATA DO D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5 PROG PROG Vpp DON'T CARE DAC OUTPUT CURRENT DAC VALUE NON-VOLATILE Doc. No. 25048-0A 2/98 M-1 Vpp NEW DAC VALUE VOLATILE NEW DAC VALUE NON-VOLATILE DAC OUTPUT DON'T CARE CURRENT DAC VALUE NON-VOLATILE 6 D6 D7 CAT504 TEMPORARILY CHANGE OUTPUT Figure 3. Temporary Change in Output The CAT504 allows temporary changes in DAC’s output to be made without disturbing the settings retained in EEPROM memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS NEW DAC DATA DI 1 A0 A1 D0 D1 D0 D1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DAC DATA Figure 3 shows the control and data signals needed to effect a temporary output change. DAC settings may be changed as many times as required and can be made to any of the four DACs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all four DACs will return to the output values stored in EEPROM memory. DO D2 D3 D4 D5 PROG Vpp DON'T CARE DAC OUTPUT CURRENT DAC VALUE NON-VOLATILE NEW DAC VALUE VOLATILE CURRENT DAC VALUE NON-VOLATILE When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DAC control register prior to programming. This is because the CAT504’s internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no PROG signal is received. APPLICATION CIRCUITS +5V +5V Ri RF +15V +15V VDD CONTROL & DATA VREF H – CAT504 OPT 504 GND + VDD VOUT CONTROL & DATA OP 07 -15V VREF L VREF H – CAT504 OPT 504 GND + RF VOUT = (1 + –––) V DAC RI Buffered DAC Output Amplified DAC Output DAC INPUT DAC OUTPUT ANALOG OUTPUT +5V Ri CODE (V - V VDAC = ——— FS ZERO ) + VZERO 255 RF VFS = 0.99 VREF VZERO = 0.01 VREF VREF = 5V R I = RF 1111 255 (.98 V —— REF ) + .01 VREF = .990 VREF 255 VOUT = +4.90V 1000 0000 V = +0.02V OUT 0111 1111 0000 0001 128 (.98 V —— ) + .01 V = .502 V REF REF REF 255 127 (.98 V —— ) + .01 V = .498 V 255 REF REF REF 1 —— (.98 V ) + .01 V = .014 V 255 REF REF REF 0000 0000 0 (.98 V —— ) + .01 V = .010 V REF REF REF 255 V = -4.90V OUT +15V VDD CONTROL & DATA VREF H CAT504 OPT 504 GND VREF L OP 07 -15V VREF L VOUT = VDAC Vi VOUT VOUT – + MSB LSB 1111 OP 07 -15V VOUT = VDAC ( R i+ RF) -Vi R F Ri For R i = RF VOUT = 2VDAC -Vi V = -0.02V OUT V = -4.86V OUT Bipolar DAC Output 7 Doc. No. 25048-0A 2/98 M-1 CAT504 APPLICATION CIRCUITS (Cont.) +5V VREF RC = ————— 256 * 1 µA +5V VDD VREF VREFH +VREF VDD Fine adjust gives ± 1 LSB change in V OFFSET VREF when VOFFSET = ——— 2 VREFH 127RC FINE ADJUST DAC + (+VREF ) - (VOFFSET ) RC = ——————————— 1 µA 127RC FINE ADJUST DAC (-VREF ) + (VOFFSET+ ) Ro = ——————————— 1 µA +V RC COARSE ADJUST DAC V OFFSET RC COARSE ADJUST DAC + GND VREF L +V Ro – GND VOFFSET -VREF VREF L + – -V Coarse-Fine Offset Control by Averaging DAC Outputs for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DAC Outputs for Dual Power Supply Systems 28 - 32V V+ I > 2 mA 15K 10 µF VDD VREF H 1N5231B VREF = 5.000V VDD VREF H 5.1V 10K CONTROL & DATA CAT504 OPT 504 GND CONTROL & DATA LT 1029 CAT504 OPT 504 GND VREF L VREF L + – MPT3055EL LM 324 OUTPUT 4.02 K 1.00K Digitally Trimmed Voltage Reference Doc. No. 25048-0A 2/98 M-1 Digitally Controlled Voltage Reference 8 10 µF 35V 0 - 25V @ 1A CAT504 APPLICATION CIRCUITS (Cont.) +5V VIN VREF 1.0 µF LM 339 + 10K – VDD +5V VREF H WINDOW 1 + OPT 504 CAT504 V REF – VPP WINDOW 1 DAC 1 + 10K – +5V WINDOW 2 VOUT 1 + CS WINDOW 2 – + DAC 2 DI VOUT 2 10K – +5V WINDOW 3 WINDOW 3 + DO – DAC 3 PROG VOUT 3 + WINDOW 4 10K – +5V WINDOW 4 VOUT 4 + CLK – DAC 4 WINDOW 5 + GND 10K – +5V WINDOW 5 + VREF L GND WINDOW STRUCTURE – Staircase Window Comparator +5V VIN VREF 1.0 µF VDD VREF H OPT 504 CAT504 VPP LM 339 + 10K – +5V WINDOW 1 + DAC 1 – VREF H CS DI WINDOW 1 VOUT 2 + DAC 2 VOUT 1 10K – +5V WINDOW 2 + DO WINDOW 2 – VOUT 4 PROG DAC 3 VOUT 3 WINDOW 3 CLK GND DAC 4 + 10K – +5V WINDOW 3 WINDOW STRUCTURE + GND VREF L – Overlapping Window Comparator 9 Doc. No. 25048-0A 2/98 M-1 CAT504 APPLICATION CIRCUITS (Cont.) +5V 2.2K VDD VREF 4.7 µA LM385-2.5 ISINK = 2 - 255 mA +15V DAC + +5V CONTROL & DATA 10K OPT 504 CAT504 1 mA steps 2N7000 – 10K 39Ω1W 39Ω 1W DAC + 5 µA steps 2N7000 – VREF L GND 5 meg 5 meg 3.9K 10K 10K – TIP 30 + -15V Current Sink with 4 Decades of Resolution +15V 51K + TIP 29 – 10K 10K +5V VDD VREF H 5 meg 5 meg 39Ω 1W DAC 39Ω 1W CONTROL & DATA – OPT 504 CAT504 5 meg DAC GND BS170P + 5 meg 1 mA steps 3.9K – VREF L BS170P 5 µA steps + LM385-2.5 -15V ISOURCE = 2 - 255 mA Current Source with 4 Decades of Resolution Doc. No. 25048-0A 2/98 M-1 10 CAT504 APPLICATION CIRCUITS (Cont.) +12V 10K 1N914 1.0 µF +12V 74C14 .005 µF VCC 1N914 13 0.1 µF 2.5 µF TREB CAP 0.47 µF 2 INPUT 1 IN 1 BASS CAP 4 0.01 µF 8 0.39 µF 20V IN5250B 3 Vpp VDD 1 CAT504 OPT 504 CHIP SELECT. PROGRAM DATA IN DATA OUT CLOCK 4 7 5 6 2 VREFH 14 PROG VOUT 1 VOUT 2 DO CLK VOUT 3 VOUT 4 VREFL GND 13 12 11 10 VZ OUTPUT 1 10 OUT 1 LM1040 1.0 µF 9 CS DI 19 47K 14 47K 11 47K 5 47K 16 0.22 µF 0.22 µF 0.22 µF 0.22 µF LOUDNESS VOLUME BALANCE TREBLE BYPASS BASS 1 47 µF 7 10 µF 18 10 µF 9 8 OUTPUT 2 0.47 µF 23 INPUT 2 3 IN 2 BASS CAP STEREO TREB CAP 15 17 22 ENHANCE 4.7K GND GND 0.39 µF 21 24 0.1 µF OUT 2 0.01 µF 12 Digital Stereo Control 11 Doc. No. 25048-0A 2/98 M-1 CAT504 ORDERING INFORMATION Prefix Device # Suffix CAT 504 J Optional Company ID Product Number Package P: PDIP J: SOIC I Tape & Reel TE13: 2000/Reel Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) Notes: (1) The device used in the above example is a CAT504JI-TE13 (SOIC, Industrial Temperature, Tape & Reel) Doc. No. 25048-0A 2/98 M-1 -TE13 12