MAXIM MAX4731EUA

19-2645; Rev 2 12/06
50Ω, Dual SPST Analog Switches in UCSP
The MAX4731/MAX4732/MAX4733 low-voltage, dual,
single-pole/single-throw (SPST) analog switches operate from a single +2V to +11V supply and handle railto-rail analog signals. These switches exhibit low
leakage current (0.1nA) and consume less than 0.5nW
(typ) of quiescent power, making them ideal for batterypowered applications.
When powered from a +3V supply, these switches feature 50Ω (max) on-resistance (RON) with 3.5Ω (max)
matching between channels, and 9Ω (max) flatness
over the specified signal range.
The MAX4731 has two normally open (NO) switches,
the MAX4732 has two normally closed (NC) switches,
and the MAX4733 has one NO and one NC switch. The
MAX4731/MAX4732/MAX4733 are available in 9-bump
chip-scale packages (UCSP™), along with 8-pin TDFN
and 8-pin µMAX® packages. The tiny UCSP occupies a
1.52mm ✕ 1.52mm area and significantly reduces the
required PC board area.
Features
♦ 1.52mm ✕ 1.52mm UCSP Package
♦ Guaranteed On-Resistance (RON)
25Ω (max) at +5V
50Ω (max) at +3V
♦ On-Resistance Matching
3Ω (max) at +5V
3.5Ω (max) at +3V
♦ Guaranteed < 0.1nA Leakage Current at
TA = +25°C
♦ Single-Supply Operation from +2.0V to +11V
♦ TTL/CMOS-Logic Compatible
♦ -108dB Crosstalk (1MHz)
♦ -72dB Off-Isolation (1MHz)
♦ Low Power Consumption: 0.5nW (typ)
♦ Rail-to-Rail Signal Handling
Ordering Information
MAX4731EUA
TEMP
RANGE
-40°C to +85°C
MAX4731ETA
-40°C to +85°C
8 TDFN-EP**
ALG
MAX4731EBL-
-40°C to +85°C
9 UCSP-9
ABV
MAX4732EUA
-40°C to +85°C
8 µMAX
-40°C to +85°C
8 TDFN-EP**
ALH
Communications Circuits
MAX4732ETA
MAX4732EBL-
-40°C to +85°C
9 UCSP-9
ABT
PDAs
MAX4733EUA
-40°C to +85°C
8 µMAX
—
MAX4733ETA
MAX4733EBL-
-40°C to +85°C
8 TDFN-EP**
ALI
-40°C to +85°C
9 UCSP-9
ABS
PART
Applications
Battery-Powered Systems
Audio/Video-Signal Routing
Low-Voltage Data-Acquisition Systems
Cell Phones
UCSP is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
PIN/BUMPPACKAGE
8 µMAX
TOP
MARK
—
—
*Future product—contact factory for availability.
**EP = Exposed pad.
Pin Configurations/Functional Diagrams/Truth Tables
TOP VIEW
(BUMPS
ON BOTTOM)
TOP VIEW
(BUMPS
ON BOTTOM)
MAX4731
MAX4731
COM1
NO1
A1
IN1
B1
V+
C1
A2
C2
A3
GND
B3
IN2
C3
1
8
V+
COM1
2
7
IN1
IN2
3
6
COM2
NO1
NO2
MAX4732
A1
IN1
B1
V+
GND
4
COM2
UCSP
5
TDFN
MAX4732
COM1
NC1
C1
A2
C2
A3
GND
B3
IN2
C3
1
8
V+
COM1
2
7
IN1
IN2
3
6
COM2
GND
4
5
NC2
NC2
NO2
COM2
UCSP
TDFN
MAX4731
Pin Configurations/Functional
Diagrams/Truth Tables
continued at end of data sheet.
NC1
MAX4732
IN_
NO_
IN_
0
OFF
0
ON
1
ON
1
OFF
SWITCHES SHOWN
FOR LOGIC "0" INPUT
NC_
SWITCHES SHOWN
FOR LOGIC "0" INPUT
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX4731/MAX4732/MAX4733
General Description
MAX4731/MAX4732/MAX4733
50Ω, Dual SPST Analog Switches in UCSP
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
V+ ...........................................................................-0.3V to +12V
IN_, COM_, NO_, NC_ (Note 1)....................-0.3V to (V+ + 0.3V)
Continuous Current (any pin) ...........................................±10mA
Peak Current (any pin, pulsed at 1ms, 10% duty cycle) ...±20mA
Continuous Power Dissipation (TA = +70°C)
8-Pin µMAX (derate 4.5mW/°C above +70°C) .............362mW
8-Pin TDFN (derate 24.4mW/°C above +70°C) .........1951mW
9-Bump UCSP (derate 4.7mW/°C above +70°C).........379mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Bump Temperature (soldering, Note 2)
Infrared (15s) ...............................................................+220°C
Vapor Phase (60s) .......................................................+215°C
Note 1: Signals on IN_, NO_, NC_, or COM_ exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to
maximum current rating.
Note 2: This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device
can be exposed to during board level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and Convection reflow. Preheating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(V+ = +3V ±10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3V, TA = +25°C.)
(Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
TA
MIN
TYP
MAX
UNITS
V+
V
ANALOG SWITCH
Analog Signal Range
On-Resistance
On-Resistance Matching
Between Channels (Notes 5, 6)
VCOM_,
VNO_, VNC_
0
RON
V+ = +2.7V,
ICOM_ = 5mA;
VNO_ or VNC_ = +1.5V
∆RON
V+ = +2.7V,
ICOM_ = 5mA;
VNO_ or VNC_ = +1.5V
On-Resistance Flatness
(Note 7)
RFLAT(ON)
V+ = +2.7V,
ICOM_ = 5mA;
VNO_ or VNC_ = +1V, +1.5V, +2V
NO_ or NC_ Off-Leakage Current
(Note 8)
INO_(OFF)
INC_(OFF)
V+ = +3.6V,
VCOM_ = +0.3V, +3V;
VNO_ or VNC_ = +3V, +0.3V
COM_ Off-Leakage Current
(Note 8)
COM_ On-Leakage Current
(Note 8)
2
V+ = +3.6V,
ICOM_(OFF) VCOM_ = +0.3V, +3V;
VNO_ or VNC_ = +3V, +0.3V
ICOM_(ON)
V+ = +3.6V,
VCOM_ = +0.3V, +3.0V;
VNO_ or VNC_ = +0.3V, +3V, or
floating
+25°C
19
TMIN to
TMAX
50
60
+25°C
0.8
TMIN to
TMAX
3.5
4.5
+25°C
2.3
TMIN to
TMAX
Ω
9
11
+25°C
-0.1
+0.1
TMIN to
TMAX
-2
+2
+25°C
-0.1
+0.1
TMIN to
TMAX
-2
+2
+25°C
-0.2
+0.2
TMIN to
TMAX
-4
+4
_______________________________________________________________________________________
Ω
Ω
nA
nA
nA
50Ω, Dual SPST Analog Switches in UCSP
(V+ = +3V ±10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3V, TA = +25°C.)
(Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
TA
MIN
TYP
MAX
70
150
UNITS
DYNAMIC CHARACTERISTICS
Turn-On Time
tON
VNO_ or VNC_ = +1.5V,
RL = 300Ω,
CL = 35pF, Figure 2
Turn-Off Time
tOFF
VNO_ or VNC_ = +1.5V,
RL = 300Ω, CL = 35pF,
Figure 2
Break-Before-Make
(MAX4733 Only, Note 8)
tBBM
VNO_ or VNC_ = +1.5V,
RL = 300Ω, CL = 35pF,
Figure 3
+25°C
TMIN to
TMAX
170
+25°C
30
TMIN to
TMAX
TMIN to
TMAX
60
70
+25°C
ns
ns
40
ns
1
VGEN = 0V, RGEN = 0, CL = 1.0nF,
Figure 4
+25°C
7.5
pC
BW
Signal = 0dBm, 50Ω in and out
+25°C
300
MHz
Off-Isolation (Note 9)
VISO
f = 1MHz, VCOM_ = 1VRMS,
RL = 50Ω, CL = 5pF,
Figure 5
+25°C
-72
dB
Crosstalk (Note 10)
VCT
f = 1MHz, VCOM_ = 1VRMS,
RL = 50Ω, CL = 5pF,
Figure 6
+25°C
-108
dB
Charge Injection
Q
On-Channel -3dB Bandwidth
NO_ or NC_ Off-Capacitance
f = 1MHz, Figure 7
+25°C
20
pF
COM_ Off-Capacitance
CCOM_(OFF) f = 1MHz, Figure 7
COFF
+25°C
20
pF
COM_ On-Capacitance
CCOM_(ON) f = 1MHz, Figure 7
+25°C
40
pF
LOGIC INPUT
Input Logic High
VIH
Input Logic Low
VIL
Input Leakage Current
IIN
1.4
VIN_ = 0V or V+
-1
V
+0.005
0.8
V
+1
µA
11
V
1
µA
SUPPLY
Power-Supply Range
Positive Supply Current
V+
I+
2.0
V+ = +5.5V, VIN_ = 0V or V+,
all switches on or off
0.0001
_______________________________________________________________________________________
3
MAX4731/MAX4732/MAX4733
ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)
MAX4731/MAX4732/MAX4733
50Ω, Dual SPST Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V+ = +5V ±10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5V, TA = +25°C.)
(Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
TA
MIN
TYP
MAX
UNITS
V+
V
ANALOG SWITCH
Analog Signal Range
On-Resistance
On-Resistance Matching
Between Channels (Notes 5, 6)
VCOM_,
VNO_, VNC_
0
RON
V+ = +4.5V,
ICOM_ = 5mA,
VNO_ or VNC_ = +3.5V
∆RON
V+ = +4.5V,
ICOM_ = 5mA,
VNO_ or VNC_ = +3.5V
On-Resistance Flatness
(Note 7)
RFLAT(ON)
V+ = +4.5V,
ICOM_ = 5mA,
VNO_ or VNC_ = +1V, +2V, +3V
NO_ or NC_ Off-Leakage Current
(Note 8)
INO_(OFF)
INC_(OFF)
V+ = +5.5V,
VCOM_ = +1V, +4.5V;
VNO_ or VNC_ = +4.5V, +1V
COM_ Off-Leakage Current
(Note 8)
COM_ On-Leakage Current
(Note 8)
V+ = +5.5V,
ICOM_(OFF) VCOM_ = +1V, +4.5V;
VNO_ or VNC_ = +4.5V, +1V
ICOM_(ON)
V+ = +5.5V,
VCOM_ = +1V, +4.5V;
VNO_ or VNC_ = +1V, +4.5V, or
floating
+25°C
8.5
TMIN to
TMAX
25
30
+25°C
0.2
TMIN to
TMAX
3
4
+25°C
2
TMIN to
TMAX
Ω
Ω
5
7
+25°C
-0.1
+0.1
TMIN to
TMAX
-2
+2
+25°C
-0.1
+0.1
TMIN to
TMAX
-2
+2
+25°C
-0.2
+0.2
TMIN to
TMAX
-4
+4
Ω
nA
nA
nA
DYNAMIC CHARACTERISTICS
+25°C
47
85
Turn-On Time
tON
VNO_ or VNC_ = +3.0V,
RL = 300Ω, CL = 35pF,
Figure 2
Turn-Off Time
tOFF
VNO_ or VNC_ = +3.0V,
RL = 300Ω, CL = 35pF,
Figure 2
Break-Before-Make
(MAX4733 Only, Note 8)
tBBM
VNO_ or VNC_ = +3.0V,
RL = 300Ω, CL = 35pF,
Figure 3
Q
VGEN = 0V, RGEN = 0,
CL = 1.0nF, Figure 4
+25°C
7.5
pC
Charge Injection
TMIN to
TMAX
95
+25°C
23
TMIN to
TMAX
TMIN to
TMAX
45
55
+25°C
ns
ns
25
ns
1
On-Channel Bandwidth
BW
Signal = 0dBm,
50Ω in and out
+25°C
300
MHz
Off-Isolation (Note 9)
VISO
f = 1MHz, VCOM_ = 1VRMS,
RL = 50Ω, CL = 5pF,
Figure 5
+25°C
-72
dB
4
_______________________________________________________________________________________
50Ω, Dual SPST Analog Switches in UCSP
(V+ = +5V ±10%, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5V, TA = +25°C.)
(Notes 3, 4)
PARAMETER
Crosstalk (Note 10)
SYMBOL
VCT
NO_ or NC_ Off-Capacitance
COFF
CONDITIONS
TA
MIN
TYP
MAX
UNITS
f = 1MHz, VCOM_ = 1VRMS,
RL = 50Ω, CL = 5pF,
Figure 6
+25°C
-108
dB
f = 1MHz, Figure 7
+25°C
20
pF
COM_ Off-Capacitance
CCOM_(OFF) f = 1MHz, Figure 7
+25°C
20
pF
COM_ On-Capacitance
CCOM_(ON) f = 1MHz, Figure 7
+25°C
40
pF
LOGIC INPUT
Input Logic High
VIH
Input Logic Low
VIL
Input Leakage Current
IIN
2.0
VIN_ = 0V or V+
-1
V
+0.005
0.8
V
+1
µA
11
V
1
µA
SUPPLY
Power-Supply Range
V+
Positive Supply Current
I+
2.0
V+ = +5.5V, VIN_ = 0V or V+,
all switches on or off
0.0001
The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in
this data sheet.
Note 4: UCSP and TDFN parts are 100% tested at +25°C only, and guaranteed by design over temperature. µMAX parts are
100% tested at +85°C and +25°C and guaranteed by design over temperature.
Note 5: ∆RON = RON(MAX) - RON(MIN).
Note 6: UCSP on-resistance matching between channels and on-resistance flatness guaranteed by design.
Note 7: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal range.
Note 8: Guaranteed by design.
Note 9: Off-Isolation = 20 log10 (VNO_/VCOM_), VNO_ = output, VCOM_ = input to off switch.
Note 10: Between any two switches.
Note 3:
_______________________________________________________________________________________
5
MAX4731/MAX4732/MAX4733
ELECTRICAL CHARACTERISTICS—Single +5V Supply
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
ON-RESISTANCE
vs. VCOM (V+ = +3.0V)
ON-RESISTANCE
vs. VCOM (V+ = +2.5V)
V+ = +2.0V
40
TA = +85°C
25
30
MAX4731-33 toc02
30
MAX4731-33 toc01
50
25
MAX4731-33 toc03
ON-RESISTANCE vs. VCOM
TA = +85°C
V+ = +3.0V
V+ = +5.0V
4
6
8
1.0
1.5
8
TA = +25°C
ON/OFF-LEAKAGE CURRENT (pA)
MAX4731-33 toc04
TA = +85°C
V+ = +5V
100
ON-LEAKAGE
10
1
1
2
3
4
5
2.0
2.5
V+ = +5.0V
35
30
25
20
V+ = +3.0V
15
10
5
0
-40
-20
0
20
40
60
0
80
1
2
3
4
TEMPERATURE (°C)
VCOM (V)
SUPPLY CURRENT vs. TEMPERATURE
LOGIC THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
TURN-ON/OFF TIME
vs. SUPPLY VOLTAGE
2.5
2.0
1.5
1.0
0.5
2.5
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
100
2.0
80
1.5
tON
60
1.0
40
0.5
20
0
0
120
5
MAX4731-33 toc09
3.0
VIN RISING OR
FALLING
tON/OFF (ns)
3.5
3.0
MAX4731-33 toc08
V+ = +5V, +3V
LOGIC THRESHOLD VOLTAGE (V)
MAX4731-33 toc07
VCOM (V)
4.0
3.0
40
0
0
1.5
45
OFF-LEAKAGE
TA = -40°C
0
1.0
CHARGE INJECTION vs. VCOM
MAXZ4731-33 toc05
ON/OFF-LEAKAGE CURRENT
vs. TEMPERATURE
12
0.5
VCOM (V)
ON-RESISTANCE
vs. VCOM (V+ = +5.0V)
1000
0
2.5
2.0
VCOM (V)
16
4
0.5
VCOM (V)
20
TA = -40°C
0
0
10
CHARGE INJECTION (pC)
2
TA = +25°C
5
5
0
RON (Ω)
TA = +25°C
10
10
6
10
TA = -40°C
V+ = +10.0V
0
15
15
MAX4731-33 toc06
20
20
RON (Ω)
30
RON (Ω)
RON (Ω)
20
SUPPLY CURRENT (nA)
MAX4731/MAX4732/MAX4733
50Ω, Dual SPST Analog Switches in UCSP
tOFF
0
2
4
6
8
10
2
4
V+ (V)
_______________________________________________________________________________________
6
V+ (V)
8
10
50Ω, Dual SPST Analog Switches in UCSP
-20
tON,
V+ = +5.0V
50
LOSS (dB)
tON/OFF (ns)
60
0
40
1
ON-LOSS
-40
OFF-ISOLATION
-60
0.1
RL = 1kΩ
V+ = +5.0V
0.01
RL = 100kΩ
V+ = +3.0V
30
-80
20
tOFF,
V+ = +3.0V
10
0
0.001
CROSSTALK
-100
tOFF,
V+ = +5.0V
-20
0
20
40
60
80
RL = 100kΩ
V+ = +5.0V
V+ = +3V
-120
-40
VCOM = 2VP-P
BW = 30kHz
RL = 1kΩ
V+ = +3.0V
THD (%)
tON,
V+ = +3.0V
MAX4731-33 toc11
MAX4731-33 toc10
80
70
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
FREQUENCY RESPONSE
MAX4731-33 toc12
TURN-ON/OFF TIME
vs. TEMPERATURE
10k
100k
TEMPERATURE (°C)
1M
10M
100M
0.0001
1G
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Pin Description
PIN
MAX4731
MAX4732
UCSP
µMAX/
TDFN
A1
MAX4733
NAME
FUNCTION
UCSP
µMAX/
TDFN
UCSP
µMAX/
TDFN
1
—
—
A1
1
NO1
A2
2
A2
2
A2
2
COM1
A3
4
A3
4
A3
4
GND
B1
7
B1
7
B1
7
IN1
Logic-Control Digital Input
Analog-Switch Normally Open Terminal
Analog-Switch Common Terminal
Ground. Connect to digital ground.
B3
3
B3
3
B3
3
IN2
Logic-Control Digital Input
C1
8
C1
8
C1
8
V+
Positive Supply Voltage Input
C2
6
C2
6
C2
6
COM2
Analog-Switch Common Terminal
C3
5
—
—
—
—
NO2
Analog-Switch Normally Open Terminal
—
—
A1
1
—
—
NC1
Analog-Switch Normally Closed Terminal
—
—
C3
5
C3
5
NC2
Analog-Switch Normally Closed Terminal
—
EP (TDFN
only)
—
EP (TDFN
only)
—
EP (TDFN
only)
EP
Applications Information
Operating Considerations for
High-Voltage Supply
The MAX4731/MAX4732/MAX4733 operate to +11V
with some precautions. The absolute maximum rating
for V+ is +12V (referenced to GND). When operating
near this region, bypass V+ with a minimum 0.1µF
capacitor to ground as close to the IC as possible.
Exposed Pad. Connect to V+.
Logic Levels
The MAX4731/MAX4732/MAX4733 are TTL compatible
when powered from a single +5V supply. When powered from other supply voltages, the logic inputs should
be driven rail-to-rail. For example, with a +11V supply,
IN1 and IN2 should be driven low to 0V and high to
11V. With a +3.3V supply, IN1 and IN2 should be driven low to 0V and high to 3.3V. Driving IN1 and IN2 railto-rail minimizes power consumption.
_______________________________________________________________________________________
7
MAX4731/MAX4732/MAX4733
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX4731/MAX4732/MAX4733
50Ω, Dual SPST Analog Switches in UCSP
Analog Signal Levels
Analog signals that range over the entire supply voltage
(GND to V+) pass with very little change in RON (see
Typical Operating Characteristics). The bidirectional
switches allow NO_, NC_, and COM_ connections to be
used as either inputs or outputs.
Power-Supply Sequencing and
Overvoltage Protection
CAUTION: Do not exceed the absolute maximum
ratings. Stresses beyond the listed ratings can
cause permanent damage to the devices.
Proper power-supply sequencing is recommended for
all CMOS devices. Always apply V+ before applying
analog signals, especially if the analog signal is not
current limited. If this sequencing is not possible, and if
the analog inputs are not current limited to < 20mA,
add a small-signal diode, D1, as shown in Figure 1. If
the analog signal can dip below GND, add D2. Adding
protection diodes reduces the analog signal range to a
diode drop (about 0.7V) below V+ (for D1), and to a
diode drop above ground (for D2). Leakage is unaffected by adding the diodes. On-resistance increases
slightly at low supply voltages. Maximum supply voltage (V+) must not exceed +11V.
Adding protection diodes causes the logic thresholds to
be shifted relative to the power-supply rails. The most
significant shift occurs when using low supply voltages
(+5V or less). With a +5V supply, TTL compatibility is not
guaranteed when protection diodes are added. Driving
IN1 and IN2 all the way to the supply rails (i.e., to a
diode drop higher than the V+ pin, or to a diode drop
lower than the GND pin) is always acceptable.
Protection diodes D1 and D2 also protect against some
overvoltage situations. Using the circuit in Figure 1, no
damage results if the supply voltage is below the
absolute maximum rating (+12V) and if a fault voltage
up to the absolute maximum rating (V+ + 0.3V) is
applied to an analog signal terminal.
8
UCSP Applications Information
For the latest application details on USCP construction,
dimensions, tape carrier information, printed circuit
board techniques, bump-pad layout, and recommended reflow temperature profile as well as the latest information on reliability testing results, go to the Maxim
web site at www.maxim-ic.com/ucsp to find the
Application Note: UCSP—A Wafer-Level Chip-Scale
Package.
Test Circuits/Timing Diagrams
V+
D1
EXTERNAL BLOCKING DIODE
MAX4731
MAX4732
MAX4733
V+
*
*
NO_
COM_
*
*
GND
EXTERNAL BLOCKING DIODE
D2
GND
*INTERNAL PROTECTION DIODES.
Figure 1. Overvoltage Protection Using External Blocking Diodes
_______________________________________________________________________________________
50Ω, Dual SPST Analog Switches in UCSP
MAX4731
MAX4732
MAX4733
V+
VN_
V+
COM_
NO_
OR NC_
50%
VIL
VOUT
CL
35pF
RL
300Ω
tOFF
IN_
VOUT
SWITCH
OUTPUT
GND
LOGIC
INPUT
tr < 5ns
tf < 5ns
VIH
LOGIC
INPUT
0.9 x VOUT
0.9 x VOUT
0V
tON
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
RL
VOUT = VN_ ( R + R )
L
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
ON
Figure 2. Switching Time
V+
MAX4733
V+
VN_
NO1
COM1
NC2
COM2
VOUT1
IN2
tr < 5ns
tf < 5ns
V+
50%
0V
VOUT2
RL2
300Ω
IN1
LOGIC
INPUT
LOGIC
INPUT
RL1
300Ω
CL1
35pF
SWITCH
OUTPUT 1
(VOUT1)
CL2
35pF
0.9 x V0UT1
0V
SWITCH
OUTPUT 2
(VOUT2)
GND
0.9 x VOUT2
0V
tBBM
tBBM
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 3. Break-Before-Make Interval (MAX4733 only)
V+
MAX4731
MAX4732
MAX4733
∆VOUT
V+
RGEN
V GEN
NC_
OR NO_
GND
VOUT
COM
CL
1nF
VOUT
IN
OFF
ON
OFF
IN_
VIL TO VIH
IN
OFF
ON
OFF
Q = (∆V OUT )(C L )
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 4. Charge Injection
_______________________________________________________________________________________
9
MAX4731/MAX4732/MAX4733
Test Circuits/Timing Diagrams (continued)
MAX4731/MAX4732/MAX4733
50Ω, Dual SPST Analog Switches in UCSP
Test Circuits/Timing Diagrams (continued)
10nF
SIGNAL
GENERATOR 0dBm
10nF
V+
MAX4731
MAX4732
MAX4733
V+
COM_
IN_
VIL OR VIH
NC_
OR NO_
ANALYZER
SIGNAL
GENERATOR 0dBm
0 OR 2.4V
V+
V+
COM1
0 OR 2.4V
RL
V-
10nF
NOTE: DUAL SUPPLIES USED TO ACCOMODATE GROUND-REFERENCED INSTRUMENTS.
Figure 6. Crosstalk
V+
MAX4731
MAX4732
MAX4733
V+
COM_
IN_
NC_ OR
NO_
Chip Information
VIL OR VIH
TRANSITOR COUNT: 68
PROCESS: CMOS
GND
Figure 7. Channel Off/On-Capacitance
10
N.C.
V-
Figure 5. Off-Isolation/On-Channel Bandwidth
f = 1MHz
COM2
GND
NOTE: DUAL SUPPLIES USED TO ACCOMODATE GROUND-REFERENCED INSTRUMENTS.
CAPACITANCE
METER
50Ω
IN2
NO2/NC2
ANALYZER
10nF
10nF
NO1/NC1
IN1
GND
RL
MAX4731
MAX4732
MAX4733
______________________________________________________________________________________
50Ω, Dual SPST Analog Switches in UCSP
TOP VIEW
(BUMPS
ON BOTTOM)
MAX4733
MAX4733
COM1
NO1
A1
IN1
B1
V+
C1
A2
A3
GND
B3
IN2
C3
C2
EP
NO1
1
8
V+
COM1
2
7
IN1
IN2
3
6
COM2
GND
4
5
NC2
NC2
COM2
UCSP
MAX4733
IN_
NO1
NC2
0
OFF
ON
1
ON
OFF
SWITCHES SHOWN FOR LOGIC "0" INPUT
TDFN
EP = EXPOSED PAD
TOP VIEW
MAX4732
MAX4731
NO1 1
8
V+
NC1 1
COM1 2
7
IN1
IN2
3
6
GND
4
5
µMAX
COM2
NO2
MAX4733
8
V+
NO1 1
COM1 2
7
IN1
IN2 3
6
GND 4
5
µMAX
COM2
NC2
8
V+
COM1 2
7
IN1
IN2 3
6
COM2
GND 4
5
NC2
µMAX
______________________________________________________________________________________
11
MAX4731/MAX4732/MAX4733
Pin Configurations/Functional Diagrams/Truth Tables (continued)
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
9LUCSP, 3x3.EPS
MAX4731/MAX4732/MAX4733
50Ω, Dual SPST Analog Switches in UCSP
PACKAGE OUTLINE, 3x3 UCSP
21-0093
12
______________________________________________________________________________________
K
1
1
50Ω, Dual SPST Analog Switches in UCSP
6, 8, &10L, DFN THIN.EPS
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
21-0137
COMMON DIMENSIONS
MIN.
MAX.
PKG. CODE
N
D2
E2
e
JEDEC SPEC
b
[(N/2)-1] x e
A
0.70
0.80
T633-1
6
1.50–0.10
2.30–0.10
0.95 BSC
MO229 / WEEA
0.40–0.05
1.90 REF
D
2.90
3.10
T633-2
6
1.50–0.10
2.30–0.10
0.95 BSC
MO229 / WEEA
0.40–0.05
1.90 REF
E
2.90
3.10
T833-1
8
1.50–0.10
2.30–0.10
0.65 BSC
MO229 / WEEC
0.30–0.05
1.95 REF
A1
0.00
0.05
T833-2
8
1.50–0.10
2.30–0.10
0.65 BSC
MO229 / WEEC
0.30–0.05
1.95 REF
L
0.20
0.40
T833-3
8
1.50–0.10
2.30–0.10
0.65 BSC
MO229 / WEEC
0.30–0.05
1.95 REF
T1033-1
10
1.50–0.10
2.30–0.10
0.50 BSC
MO229 / WEED-3
0.25–0.05
2.00 REF
0.25 MIN.
A2
0.20 REF.
1
2
PACKAGE VARIATIONS
SYMBOL
k
H
T1033-2
10
1.50–0.10
2.30–0.10
0.50 BSC
MO229 / WEED-3
0.25–0.05
2.00 REF
T1433-1
14
1.70–0.10
2.30–0.10
0.40 BSC
----
0.20–0.05
2.40 REF
T1433-2
14
1.70–0.10
2.30–0.10
0.40 BSC
----
0.20–0.05
2.40 REF
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
-DRAWING NOT TO SCALE-
21-0137
H
2
2
______________________________________________________________________________________
13
MAX4731/MAX4732/MAX4733
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
4X S
8
8
INCHES
DIM
A
A1
A2
b
E
fl0.50–0.1
H
c
D
e
E
H
0.6–0.1
L
1
1
α
0.6–0.1
S
BOTTOM VIEW
D
MIN
0.002
0.030
MAX
0.043
0.006
0.037
0.014
0.010
0.007
0.005
0.120
0.116
0.0256 BSC
0.120
0.116
0.198
0.188
0.026
0.016
6¡
0¡
0.0207 BSC
8LUMAXD.EPS
MAX4731/MAX4732/MAX4733
50Ω, Dual SPST Analog Switches in UCSP
MILLIMETERS
MAX
MIN
0.05
0.75
1.10
0.15
0.95
0.25
0.36
0.13
0.18
2.95
3.05
0.65 BSC
2.95
3.05
4.78
5.03
0.41
0.66
0¡
6¡
0.5250 BSC
TOP VIEW
A1
A2
A
α
c
e
b
FRONT VIEW
L
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
21-0036
REV.
J
1
1
Revision History
Pages changed at Rev 2: 1, 2, 7, 8, 11, 14
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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is a registered trademark of Maxim Integrated Products, Inc.