19-2119; Rev 2; 9/02 Standard Definition Video Reconstruction Filters and Buffers Features ♦ Ideal for CVBS, Y/C (S-Video), and RGB (Y Pb Pr) Outputs for NTSC, PAL, and SDTV ♦ 6th-Order Lowpass Filter ♦ Drives Two 150Ω Video Loads ♦ Four Levels of Passband High-Frequency Boost Control ♦ Input 2 to 1 Multiplexer ♦ Output Disable ♦ Filter Bypassing ♦ +5V Single-Supply Voltage ♦ Tiny 8-Pin SOT23 Package (MAX7428), 10-Pin µMAX Package (MAX7430), and 14-Pin TSSOP Package (MAX7432) Ordering Information TEMP RANGE PINPACKAGE TOP MARK MAX7428EKA-T -40°C to +85°C 8 SOT23-8 AAIU MAX7430EUB -40°C to +85°C 10 µMAX — MAX7432EUD -40°C to +85°C 14 TSSOP — PART Applications Set-Top Boxes DVD Players MSPB is a trademark of Maxim Integrated Products, Inc. Hard-Disk Recorders Pin Configurations appear at end of data sheet. Camcorders Functional Diagrams VCC SYNCIO SYNC MAX7428 SERIAL INTERFACE AND CONTROL CIN D/A DATA 75Ω INA * +6dB 6TH-ORDER FILTER OUT 75Ω ENCODER LEVEL SHIFT CIN BIAS GENERATOR INB AUX INPUT REXT GND * *OPTIONAL Functional Diagrams continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX7428/MAX7430/MAX7432 General Description The MAX7428/MAX7430/MAX7432 filters are low-cost, high-performance replacements for standard discrete filter and buffer solutions. The MAX7428/MAX7430/ MAX7432 are ideal for anti-aliasing and DAC smoothing video applications, when analog video is reconstructed from a digital data stream. These devices require a single +5V supply and the filters have a cutoff frequency optimized for NTSC, PAL, and standard definition digital TV (SDTV) video signals. The MAX7428/MAX7430/ MAX7432 feature Maxim’s Single Pin Bus (MSPB™) interface to digitally control channel selection (IN_A or IN_B), adjust high-frequency boost, bypass the filter, configure luma vs. chroma operation, and control the output disable. The MAX7428 single-channel filter is ideal for composite (CVBS) video signals. The MAX7430 dual filter is optimized for S-Video (Y/C) applications. The MAX7432 triple filter is optimized for component (YPbPr or embedded synchronous RGB) video signals. The MAX7428 is available in a tiny 8-pin SOT23 package, the MAX7430 is available in a miniature 10-pin µMAX package, and the MAX7432 is available in a 14-pin TSSOP package. The MAX7428/MAX7430/MAX7432 are fully specified over the -40°C to +85°C extended temperature range. MAX7428/MAX7430/MAX7432 Standard Definition Video Reconstruction Filters and Buffers ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................................+6V All Other Pins to GND .................................-0.3V to (VCC + 0.3V) Maximum Current Into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 8-Pin SOT23 (derate 9.71mW/°C above +70°C)..........777mW 10-Pin µMAX (derate 6.94mW/°C above +70°C) ......555.5mW 14-Pin TSSOP (derate 9.1mW/°C above +70°C) .........727mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +5V ±10%, RREXT = 300kΩ ±1%, CIN = 0.1µF, CREXT = (1nF to 1µF) ±1%, CLOAD = 0 to 20pF; BOOST0_, BOOST1_ = 0, 0; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL Passband Response Stopband Attenuation Asb HF Boost Relative Step Size, 4 Levels Differential Gain Differential Phase Harmonic Distortion Signal-to-Noise Ratio Group Delay Deviation CONDITIONS MIN TYP f = 100kHz to 4.2MHz relative to 100kHz -0.5 +0.5 f = 100kHz to 5MHz relative to 100kHz -1.0 +1.0 f > 27MHz 48 f = 4.2MHz to 5MHz 0.2 UNITS dB dB 0.4 dG 5-step modulated staircase 0.2 dθ 5-step modulated staircase 0.2 THD f = 100kHz to 5MHz 0.1 SNR Peak signal (2Vp-p) to RMS noise, f = 100Hz to 50MHz ∆tg MAX 0.6 dB % degrees 0.5 72 % dB Deviation from 100kHz to 3.58 (4.43)MHz 20 Line-Time Distortion Hdist 18µs, 100 IRE bar 0.3 % Field-Time Distortion Vdist 130 lines, 18µs, 100 IRE bar 0.5 % Clamp Settling Time tclamp 100 Lines Output DC Clamp Level Low-Frequency Gain AV to ±1% (Note 1) CLEVEL = 0 0.8 1.3 CLEVEL = 1 1.35 1.85 Gain at 100kHz 1.9 Group Delay Matching tg(MATCH) Low frequency channel-to-channel matching f = 100kHz Low-Frequency Gain Matching AV(MATCH) Channel-to-channel gain matching, f = 100kHz Channel-to-Channel Crosstalk XTALK Output Short-Circuit Current ISC Input Leakage Current IIN Input Dynamic Swing VCC Supply Range 2 1.975 2 Channel-to-channel crosstalk, f = 100kHz to 5.5MHz -60 OUT_ shorted to ground or VCC 50 1.4 CINp-p CLEVEL = 1 0.9 4.5 _______________________________________________________________________________________ V/V % dB mA 10 CLEVEL = 0 V ns 5 YINp-p VCC 2.05 ns µA Vp-p 5.5 V Standard Definition Video Reconstruction Filters and Buffers (VCC = +5V ±10%, RREXT = 300kΩ ±1%, CIN = 0.1µF, CREXT = (1nF to 1µF) ±1%, CLOAD = 0 to 20pF; BOOST0_, BOOST1_ = 0, 0; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER Supply Current SYMBOL ICC Power-Supply Rejection Ratio PSRR IN_A/IN_B Crosstalk CONDITIONS No load MIN TYP MAX MAX7428 24 32 MAX7430 45 62 MAX7432 68 86 UNITS mA VIN = 100mVp-p, f = 0 to 5.5MHz 40 dB VIN = 100mVp-p, f = 100kHz to 5.5MHz -60 dB LOGIC CHARACTERISTICS Logic Input High Voltage VIH Logic Input Low Voltage VIL 2 Logic Input Current IIH/IIL VIL = 0 (source), VIH = VCC (sink) Logic Output High Voltage VOH I(SOURCE) = 500µA Logic Output Low Voltage VOL I(SINK) = 500µA V 0.8 V 10 µA VCC 0.5 V 0.4 V MSPB INTERFACE TIMING SPECIFICATIONS (VCC = +5V ±10%, RREXT = 300kΩ ±1%, CREXT = (1nF to 1µF) ±1%, CLOAD = 0 to 20pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Figures 4 through 9) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS t0, tP 1 5 8 µs Logic-One Pulse Width t1 24 30 36 µs Transaction Pulse Width tT 80 100 120 tWAIT 0.5 MSPB TIMING Logic-Zero/Prompt Pulse Width Separation Between Pulses Bus Release Time by Host After Prompt Pulse tRELEASE Bus Reclaim Time by Host After Prompt Pulse tRECLAIM 13 Read Back Data Valid Window After the Prompt Pulse tREAD 2.3 µs µs 1 µs µs 4.7 µs Note 1: One horizontal line = 63.5µs. Note 2: MAX7428 devices are 100% production tested at TA = +25°C and are guaranteed by design from TA = TMIN to TMAX. _______________________________________________________________________________________ 3 MAX7428/MAX7430/MAX7432 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = +5V, RREXT = 300kΩ; BOOST0_, BOOST1_ = 0, 0; VIN_ = 1Vp-p, TA = +25°C, unless otherwise noted.) PASSBAND AMPLITUDE vs. FREQUENCY 0 -30 -40 D -4 -6 A: BOOST1, BOOST0 = 1, 1 B: BOOST1, BOOST0 = 1, 0 C: BOOST1, BOOST0 = 0, 1 D: BOOST1, BOOST0 = 0, 0 -8 -50 0.1 1 10 0 -60 -180 0.1 100 60 -120 -10 -60 1 10 0.1 1 10 FREQUENCY (MHz) GROUP DELAY vs. FREQUENCY 2T RESPONSE (1IRE = 7.14mV) MODULATED 12.5T RESPONSE (1IRE = 7.14mV) MAX7428/30/32 toc04 100 80 INA_ 200mV/div MAX7428/30/32 toc06 FREQUENCY (MHz) MAX7428/30/32 toc05 FREQUENCY (MHz) 120 GROUP DELAY (ns) C -2 120 PHASE (DEGREES) AMPLITUDE (dB) -20 B A PHASE RESPONSE vs. FREQUENCY 180 MAX7428/30/32 toc03 MAX7428/30/32 toc01 -10 AMPLITUDE (dB) 2 MAX7428/30/32 toc02 AMPLITUDE vs. FREQUENCY 0 INA_ 200mV/div 60 OUT_ 200mV/div OUT_ 200mV/div 40 20 0 0.1 1 400ns/div 200ns/div 10 FREQUENCY (MHz) 25 24 23 -0.01 -0.04 -0.08 -0.10 -0.06 0.1 0 -0.1 -0.2 MAX7428/30/32 toc08 0 DIFFERENTIAL PHASE (DEGREES) 26 DIFFERENTIAL GAIN (%) MAX7428/30/32 toc07 27 DIFFERENTIAL PHASE DIFFERENTIAL GAIN 0.2 0 0.04 0.06 0.06 0.04 0.02 1st. 2nd. 3rd. 4th. 5th. 6th. 0.20 0.15 0.10 0.05 0 NO LOAD 22 -0.3 -40 -15 10 35 60 85 -0.05 1st. 2nd. 3rd. 4th. 5th. 6th. TEMPERATURE (°C) 4 _______________________________________________________________________________________ MAX7428/30/32 toc09 SUPPLY CURRENT vs. TEMPERATURE 28 SUPPLY CURRENT (mA) MAX7428/MAX7430/MAX7432 Standard Definition Video Reconstruction Filters and Buffers Standard Definition Video Reconstruction Filters and Buffers OUTPUT TRANSIENT DUE TO INPUT MUX SWITCHING IMPEDANCE (Ω) 3.0 2.5 2.0 OUT_ 500mV/div 1.5 1.0 MAX7428/30/32 toc12 3.5 -70 -75 CROSSTALK (dB) MAX7428/30/32 toc10 4.0 PASSBAND CHANNEL-TO-CHANNEL CROSSTALK vs. FREQUENCY MAX7428/30/32 toc11 OUTPUT IMPEDANCE vs. FREQUENCY -80 -85 -90 0.5 BOOST = CODE 00 -95 0 0.1 1 200ns/div 10 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) Pin Description PIN NAME FUNCTION MAX7432 MAX7430 MAX7428 1 1 — IN1A Video Input 1A. Master channel, sync signal required. Use a 0.1µF series input capacitor for proper operation. 2 2 — IN2A Video Input 2A. Slave channel, clamping controlled by master channel sync. Use a 0.1µF series input capacitor for proper operation. 3 — — IN3A Video Input 3A. Slave channel, clamping controlled by master channel sync. Use a 0.1µF series input capacitor for proper operation. 4, 10 8 4 GND Ground 5 4 — IN1B Video Input 1B. Master channel, sync signal required. Use a 0.1µF series input capacitor for proper operation. 6 5 — IN2B Video Input 2B. Slave channel, clamping controlled by master channel sync. Use a 0.1µF series input capacitor for proper operation. 7 — — IN3B Video Input 3B. Slave channel, clamping controlled by master channel sync. Use a 0.1µF series input capacitor for proper operation. Serial Data Interface 8 6 6 DATA 9 — — OUT3 Buffer Output 3 11 7 — OUT2 Buffer Output 2 12 3 7 REXT External Resistor. Connect a 300kΩ resistor from REXT to GND for internal biasing. Connect a 1nF to 1µF capacitor from REXT to GND for chip-address programming (see Table 3). _______________________________________________________________________________________ 5 MAX7428/MAX7430/MAX7432 Typical Operating Characteristics (continued) (VCC = +5V, RREXT = 300kΩ; BOOST0_, BOOST1_ = 0, 0; VIN = 1Vp-p, TA = +25°C, unless otherwise noted.) Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432 Pin Description (continued) PIN NAME FUNCTION MAX7432 MAX7430 MAX7428 13 9 — OUT1 14 10 2 VCC +5V Supply Voltage — — 1 INA Video Input A. Use a 0.1µF series input capacitor for proper operation. — — — — — — 3 5 8 INB SYNCIO OUT Video Input B. Use a 0.1µF series input capacitor for proper operation. Sync Pulse Input or Output Buffer Output Buffer Output 1 **220µF 75Ω Z0 = 75Ω 5V VCC 0.1µF D/A 75Ω **220µF 75Ω OUT INA C1 Z0 = 75Ω 75Ω *1MΩ MAX7428 300kΩ REXT 0.1µF INB D/A DATA SERIAL I/O *** *1MΩ 5V ENCODER 10kΩ GND SYNCIO SYNC PULSE IN OR OUT C1 = 1nF TO 1µF (SEE TABLE 3) *NEEDED ONLY IN FILTER BYPASS MODE **OPTIONAL CAPACITOR ***ONLY ONE PULLUP RESISTOR NEEDED PER BUS Figure 1. MAX7428 Typical Application Circuit Detailed Description The MAX7428/MAX7430/MAX7432 filter and buffer the outputs of DAC encoder chipsets that process digital video information in applications such as set-top boxes, hard-disk recorders, DVD players, recorders, and digital VCRs. These devices also filter and “clean-up” analog video signals. Each channel in the MAX7428/ MAX7430/MAX7432 includes an input mux to select the input channel, a 6th-order Sallen-Key filter with four adjustable high-frequency boost levels, an output buffer with a 6dB gain, a sync detector and clamp, and an external resistor to set internal bias levels. Output disable adds additional multiplexing in a wired-OR configuration. Filter bypass, in conjunction with the two inputs, can be used to provide filtered and unfiltered video signal processing. Maxim’s Single Pin Bus 6 (MSPB) interface controls all of the above features. An external capacitor is used to assign each device a unique address that allows control of up to 16 devices on the same bus. Typical application circuits for the MAX7428/MAX7430/MAX7432 are shown in Figures 1, 2, and 3. Input Considerations Use a 0.1µF ceramic capacitor to AC-couple the input to the MAX7428/MAX7430/MAX7432. This input capacitor stores a DC level to level-shift the input signal to an optimal point between VCC and GND. The ABSEL bit on the Control Register sets which channel (IN_A or IN_B) is selected (Control Register section). The IN_A and IN_B inputs have a typical input resistance of 50kΩ. _______________________________________________________________________________________ Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432 200µF** 75Ω +5V Z0 = 75Ω 75Ω VCC 0.1µF 200µF** 75Ω Z0 = 75Ω OUT1 IN1A AUX IN *** +5V 75Ω 10kΩ *1MΩ DATA 0.1µF SERIAL I/O 200µF** 75Ω Z0 = 75Ω IN1B D/A ENCODER *1MΩ 75Ω MAX7430 0.1µF 200µF** 75Ω IN2A AUX IN Z0 = 75Ω OUT2 *1MΩ 75Ω 300kΩ 0.1µF REXT IN2B D/A ENCODER *1MΩ C1 GND C1 = 1nF TO 1µF (SEE TABLE 3) *NEEDED ONLY IN FILTER BYPASS MODE **OPTIONAL OUTPUT CAPACITOR ***ONLY ONE PULLUP RESISTOR NEEDED PER BUS Figure 2. MAX7430 Typical Application Circuit _______________________________________________________________________________________ 7 MAX7428/MAX7430/MAX7432 Standard Definition Video Reconstruction Filters and Buffers 75Ω 220µF** Z0 = 75Ω +5V 75Ω VCC 0.1µF 75Ω 220µF** Z0 = 75Ω OUT1 IN1A AUX IN *** *1MΩ +5V 75Ω SERIAL I/O DATA 0.1µF IN1B D/A ENCODER 75Ω 220µF** Z0 = 75Ω *1MΩ 75Ω 0.1µF MAX7432 IN2A AUX IN 75Ω 220µF** Z0 = 75Ω OUT2 *1MΩ 75Ω 0.1µF IN2B D/A ENCODER 75Ω *1MΩ 220µF** Z0 = 75Ω 0.1µF 75Ω IN3A AUX IN 75Ω *1MΩ 220µF** Z0 = 75Ω OUT3 0.1µF 75Ω IN3B D/A ENCODER *1MΩ REXT GND 300kΩ C1 C1 = 1nF TO 1µF (SEE TABLE 3) *NEEDED ONLY IN FILTER BYPASS MODE **OPTIONAL OUTPUT CAPACITOR ***ONLY ONE PULLUP RESISTOR NEEDED PER BUS Figure 3. MAX7432 Typical Application Circuit 8 _______________________________________________________________________________________ Standard Definition Video Reconstruction Filters and Buffers SYNCIO ABSEL BYPASS CLEVEL BOOST1 BOOST0 OUTDISABLE FIRST BIT (LSB) — 0 1 1 0 0 0 0 0 (MSB) NAME DEFAULT Filter Serial Interface Filter Response The reconstruction filter consists of a 6th-order Butterworth filter in three second-order stages. The Butterworth filter features a maximally flat passband for NTSC and PAL bandwidths. The stopband offers typically 50dB of attenuation at sampling frequencies of 25MHz and above (see Typical Operating Characteristics). The corner frequency is not critical since the response of the filter meets both the stopband and passband specifications. The MAX7428/MAX7430/MAX7432 incorporate an autotrimming feature that reduces the corner frequency variation digitally. It is possible, although not likely, that a discrete shift in the corner frequency may occur due to an external environmental change. The autotrimming operates continuously so that the corner frequency remains centered over the full operating temperature range. Maxim’s Single Pin Bus (MSPB) interface uses DATA to transfer data to and from the microprocessor (µP) and the MAX7428/MAX7430/MAX7432. This negative logic protocol uses three different pulse widths to represent a logic “1”, logic “0”, and control commands. MSPB allows up to 16 devices to be connected on the same bus by assigning a unique 4-bit identification address to each device. The µP can communicate to each device individually or by sending a “broadcast” message to all the devices. The unique address for each device is set by means of the time constant set by the external capacitor connected in parallel with the external 300kΩ resistor (see Initializing the MAX7428/ MAX7430/MAX7432 section). High-Frequency Boost The high-frequency boost compensates for signal degradation and roll-off in the signal path prior to the MAX7428/ MAX7430/MAX7432. High-frequency boost is programmable in four steps to increase image sharpness. Output Buffer The output buffer is able to drive two 150Ω video loads with a 2Vp-p signal. The +6dB gain of the output buffer is independent of the filter bypass or input selection. The output buffer drives the 75Ω backmatch resistors and series capacitor (typically 220µF). The MAX7428/ MAX7430/MAX7432 are able to drive the video load directly without using the 220µF capacitor. This feature is common in SCART applications. The OUTDISABLE bit of the control register disables the output (mute) (see Control Register section). Filter Bypass The MAX7428/MAX7430/MAX7432 offer selectable filter bypassing that allows either of the video inputs to be filtered or unfiltered. The 1MΩ optional input resistors are needed only in filter bypass mode to provide a discharge path for the input coupling capacitors. MAX7428 Control Register Table 1 defines the structure of the MAX7428 8-bit control register programmed by MSPB. This register controls the selection of INA or INB, SYNCIO functionality, filter bypassing, clamp-level selection, high-frequency boost control, and output disable. See Maxim’s Single Pin Bus Interface (MSPB) section for detailed programming instructions. SYNCIO: SYNCIO Select bit. A logic 0 sets the SYNCIO pin to function as an output while a logic 1 sets SYNCIO to function as an input. ABSEL: Channel Select bit. A logic 0 selects the input at INB to be processed while a logic 1 selects the input at INA to be processed. BYPASS: Filter Bypass Select bit. A logic 1 selects the filter while a logic 0 bypasses the filter. Table 2. Boost Level Programming RELATIVE HIGH-FREQUENCY BOOST BOOST1 BOOST0 0 0 0 0 1 0.45dB 1 0 0.90dB 1 1 1.35dB _______________________________________________________________________________________ 9 MAX7428/MAX7430/MAX7432 Table 1. MAX7428 Control Register MAX7428/MAX7430/MAX7432 Standard Definition Video Reconstruction Filters and Buffers Table 3. MAX7430 Control Register (MSB) NAME — ABSEL2 BYPASS2 CLEVEL2 BOOST1(2) BOOST0(2) OUT DISABLE2 — DEFAULT 0 1 1 0 0 0 0 0 NAME — ABSEL1 BYPASS1 CLEVEL1 BOOST1(1) BOOST0(1) DEFAULT 0 1 1 0 0 0 OUT DISABLE1 0 — 0 FIRST BIT (LSB) CLEVEL: Clamp Level bit. A logic 0 selects a clamp level of 1V while a logic 0 selects a clamp level of 1.5V at the output. [BOOST1, BOOST0]: High-Frequency Boost Control bits. The adjust bits select the amount of high-frequency boost for the filter. Table 2 defines four levels of adjustment. OUTDISABLE: Output Disable bit. A logic 0 selects normal operation while a logic 1 places the output in a high-impedance state. Table 4. Boost Level Programming RELATIVE HIGHFREQUENCY BOOST BOOST1_ BOOST0_ 0 0 0 0 1 0.45dB 1 0 0.90dB 1 1 1.35dB MAX7430 Control Register MAX7432 Control Register Table 3 defines the structure of the MAX7430 16-bit control register programmed by MSPB. This register controls the selection of IN_A or IN_B, selection of filter 1 or 2, filter bypassing, clamp-level selection, high-frequency boost control, and output disable. See Maxim’s Single Pin Bus Interface (MSPB) section for detailed programming instructions. ABSEL_: Channel Select bit. A logic zero selects the input at IN_B to be processed while a logic 1 selects the input at IN_A to be processed. Table 5 defines the structure of the MAX7432 24-bit control register programmed by MSPB. This register controls the selection of IN_A or IN_B, selection of filter 1, 2, or 3, filter bypassing, clamp-level selection, highfrequency boost control, and output disable. See Maxim’s Single Pin Bus Interface (MSPB) section for detailed programming instructions. BYPASS_: Filter Bypass Select bit. A logic 1 selects the channel filter while a logic 0 bypasses the channel filter. CLEVEL_: Clamp Level bit. A logic 0 selects a channel clamp level of 1V while a logic 0 selects a channel clamp level of 1.5V at the output. [BOOST1_, BOOST0_]: High-Frequency Boost Control bits. The adjust bits select the amount of high-frequency boost for the channel filter. Table 4 defines four levels of adjustment. OUTDISABLE_: Output Disable bit. A logic 0 selects normal channel output operation while a logic 1 puts the channel output in a high-impedance state. BYPASS_: Filter Bypass Select bit. A logic 1 selects the channel filter while a logic 0 bypasses the channel filter. CLEVEL_: Clamp Level bit. A logic 0 selects a channel clamp level of 1V while a logic 0 selects a channel clamp level of 1.5V at the output. [BOOST1_, BOOST0_]: High-Frequency Boost Control bits. The adjust bits select the amount of high-frequency boost for the channel filter. Table 6 defines four levels of adjustment. OUTDISABLE_: Output Disable Bit. A logic 0 selects normal channel output operation while a logic 1 puts the channel output in high-impedance state. 10 ABSEL_: Channel Select bit. A logic zero selects the input at IN_B to be processed while a logic 1 selects the input at IN_A to be processed. ______________________________________________________________________________________ Standard Definition Video Reconstruction Filters and Buffers (MSB) NAME — ABSEL3 BYPASS3 CLEVEL3 BOOST1(3) BOOST0(3) OUT DISABLE3 — DEFAULT 0 1 1 0 0 0 0 0 NAME — ABSEL2 BYPASS2 CLEVEL2 BOOST1(2) BOOST0(2) OUT DISABLE2 — DEFAULT 0 1 1 0 0 0 0 0 NAME — ABSEL1 BYPASS1 CLEVEL1 BOOST1(1) BOOST0(1) OUT DISABLE1 — DEFAULT 0 1 1 0 0 0 0 0 FIRST BIT (LSB) Applications Information Maxim’s Single Pin Bus (MSPB) Serial Interface The MSPB interface uses three pulses of different widths to represent commands and data bits. Figure 4 shows the set of pulses that the single pin interface uses to communicate with the device. A combination of the one pulse (t1), zero pulse (t0), transaction pulse (tT), and prompt pulse (tP), writes to, reads back from, and sends broadcast data to the devices on the bus. Note: The zero pulse and prompt pulse are the same. Initialization pulses are significantly longer and are used only on power-up or software reset. ZERO/PROMPT PULSE ONE PULSE TRANSACTION PULSE t0 tP = t0 = 5µs t1 t1 = 30µs tT Figure 4. MSPB Interface Pulses tT = 100µs Table 6. Boost Level Programming RELATIVE HIGHFREQUENCY BOOST BOOST1_ BOOST0_ 0 0 0 0 1 0.45dB 1 0 0.90dB 1 1 1.35dB Initializing the MAX7428/MAX7430/MAX7432 Initialization is performed only after power-up or software reset. It assigns a unique address to each device on the bus. The time constant of the capacitor connected to REXT in parallel with the 300kΩ resistor determines the order in which the devices are initialized (address assigned). The device with the largest time constant is initialized first and so on, in descending order. Table 7 shows the “Initialize Wait” and “Initialize Time” pulse widths needed for a specific capacitor value and tolerance. Program each device on the bus with this command sequence starting with the device with the biggest capacitor. To reinitialize a device, cycle the power or use a software reset. The following is the command sequence and timing diagram (Figure 5) for initialization as shown below. Chip ID is entered LSB first. Note: If there is only one device on the bus, no initialization is needed. Communicate to the device using the broadcast command described on page 13. ______________________________________________________________________________________ 11 MAX7428/MAX7430/MAX7432 Table 5. MAX7432 Control Register MAX7428/MAX7430/MAX7432 Standard Definition Video Reconstruction Filters and Buffers Table 7. Initialization Capacitor Values and Pulse Widths (CREXT = ±10% Tolerance, RREXT = ±1% Tolerance) CAPACITOR VALUE (nF) INITIALIZING WAIT PERIOD (ms) (tINTWAIT) INITIALIZING TIME PERIOD (ms) WITH RREXT = 300kΩ (tINT) MIN TYP MAX 179 (151.2) 1000 20.000 162 (136.8) 171 (144) 680 13.600 112 118 123 470 9.400 52.6 (44.1) 55.4 (46.4) 58.2 (48.72) 220 4.400 35.90 37.80 39.70 150 3.000 23.90 (13.7) 25.20 (14.4) 26.50 (15.1) 100 2.000 16.25 17.10 17.95 68 1.360 11.21 (4.4) 11.80 (4.64) 12.39 (4.9) 47 0.940 5.26 5.54 5.82 22 0.440 3.59 3.78 3.97 15 0.300 2.39 2.52 2.65 10 0.200 1.625 (1.37) 1.710 (1.44) 1.795 (1.51) 6.8 0.136 1.121 1.180 1.239 4.7 0.094 0.526 (0.441) 0.554 (0.464) 0.582 (0.487) 2.2 0.044 0.359 0.378 0.397 1.5 0.030 0.239 0.252 0.265 1 0.020 0.162 (0.137) 0.171 (0.144) 0.179 (0.151) Note: ( ) Indicates the time periods associated with 20% capacitors. This limits the maximum number of devices on the bus to seven. Initialization Command Sequence: Initialize wait T011 Initialize Time Address ID = 4-bits T111 Programming the MAX7428/MAX7430/MAX7432 An address sequence precedes a write or read operation to determine with which device to communicate. If the address transmitted in this mode matches with a device’s address, the device and µP can initiate data transfer. When entering the four address bits, ensure that the LSB is entered first. The following is the command sequence and timing diagram (Figure 6) for an address sequence. Address Command Sequence: T010 Address = 4-bits T111 Use a write sequence to load data into the data register of the device. It must follow an address sequence. Transmit a minimum of eight data bits for the MAX7428, 16 data bits for the MAX7430, or 24 data bits for the MAX7432 to make this transaction valid starting with the LSB first. The last 8/16/24 data bits are used if more 12 than 8/16/24 bits are loaded into the register. The following is the command sequence and timing diagram (Figure 7) for a write sequence. Write Command Sequence: T001 Data ≥ 8-bits (MAX7428, See Table 1) Data ≥ 16-bits (MAX7430, See Table 3) Data ≥ 24-bits (MAX7432, See Table 5) T111 During the read sequence, the µP sends a prompt pulse causing the device to output the data word LSB first. Similar to the write transaction, the read transaction must be preceded by an address sequence. If more than 8 prompts (MAX7428), 16 prompts (MAX7430), or 24 prompts (MAX7432) are available, the device outputs the same data starting with the LSB again. The following is the command sequence and timing diagram (Figure 8) for a read sequence. ______________________________________________________________________________________ Standard Definition Video Reconstruction Filters and Buffers T101 Prompts ≥ 8 (MAX7428) Prompts ≥ 16 (MAX7430) Prompts ≥ 24 (MAX7432) T111 T000 8 or more 1s (MAX7428) 16 or more 1s (MAX7430) 24 or more 1s (MAX7432) T010 Address = 4-bits T111 T001 8 or more 1s (MAX7428) 16 or more 1s (MAX7430) 24 or more 1s (MAX7432) T111 OR The broadcast sequence writes data to the control registers of all the devices on the bus at the same time. Write data with the LSB first. The following is the command sequence and timing diagram (Figure 9) for the broadcast transaction. No address sequence is required. Use the broadcast command when there is only one device on the bus. more ones for the MAX7430, or 24 or more ones for the MAX7432 to that device register. Broadcast Command Sequence: Composite Video Filtering Data ≥ 8-bits (MAX7428) Data ≥ 16-bits (MAX7430) Data ≥ 24-bits (MAX7432) T000 T111 The MAX7428 is ideally suited for filtering composite video signals. Program the SYNCIO as an output when processing composite video signals. In the rare occasion that an external sync pulse is needed to process the composite video, program the SYNCIO as an input. T111 Executing a software reset serves the same function as a power-on reset and is achieved by transmitting all data bits (eight or more) for the MAX7428, sixteen or tWAIT ADDRESS: 0001 tINTWAIT tINT tT t0 t1 t1 t1 t0 t0 LSB t0 tT t1 t1 t1 t1 t1 t1 MSB Figure 5. Initialization Timing Diagram tWAIT tT ADDRESS: 0001 t0 t1 t0 t1 t0 LSB t0 t0 tT MSB Figure 6. Address Timing Diagram tWAIT tT DATA: 1***000 t0 t0 t1 t0 LSB t0 t0 t1 tT t1 t1 t1 MSB Figure 7. Write Timing Diagram ______________________________________________________________________________________ 13 MAX7428/MAX7430/MAX7432 Software Reset Command Sequence: Read Command Sequence: tO A tWAIT tT t1 t0 t1 B HIGH-Z MAX7428/MAX7430/MAX7432 Standard Definition Video Reconstruction Filters and Buffers tP t0 C D A B tP 0 OR 1 C D tP 00 OR OR 11 READS 2ND BIT READS 1ST BIT (LSB) tT t1 t1 t1 REPEAT TO READ 6 MORE BITS A: µP WILL RELEASE BUS BY TIME A C: µP HAS UNTIL TIME C TO FINISH READING BIT B: µP CAN START READING BIT AT TIME B D: DEVICE WILL RELEASE BUS BY TIME D NOTE: TIME A, B, C, D ARE REFERENCED TO t0. Figure 8. Read Timing Diagram tWAIT tT DATA: 1***000 t0 t0 t0 t0 t0 t0 LSB t1 tT t1 t1 t1 MSB Figure 9. Broadcast Timing Diagram When processing composite video set the clamp level to +1V (CLEVEL = 0). Use the MAX7430 to process two synchronous composite signals simultaneously. Use the MAX7432 to process three synchronous composite signals simultaneously. Y/C Video Filtering The MAX7430 is ideally suited for processing S-Video (Y/C) signals (Figure 10). Ensure that IN1_ filters the signal that contains the sync information (Y) since the clamping on IN2_ is internally controlled by the master channel (IN1_) sync. Set the clamp level for IN1_ to +1V (CLEVEL1 = 0) and set the clamp level for IN2_ to +1.5V (CLEVEL2 = 1). Use two MAX7428s for Y/C video filtering. Since only the Y signal contains the sync, a typical Y/C video-filtering application requires a master-slave configuration of the SYNCIO. The MAX7428 processing the Y signal should have SYNCIO configured as an output, which in turn drives the SYNCIO of the second MAX7428, processing the C signal that has its SYNCIO configured as an input (Figure 11). Clamping level for the Y signal should be set for +1V (CLEVEL = 0), and clamping level for the C signal should be set for +1.5V (CLEVEL = 1). Use the MAX7432 to filter one Y/C and one composite video signal that are synchronous. 14 Component Video (RGB or Y Pb Pr) Filtering Component video consists of three separate signals. Typically the three signals are separate red, green, and blue (RGB) signals or Y (luma) and two color difference signals: B-Y (Pb) which is blue minus luma and R-Y (Pr), which is red minus luma. Sync information is included with the Y signal of Y Pb Pr component video, or in the case of RGB, sync is usually carried on the G or on a separate H sync line. The MAX7432 is ideally suited for filtering component video signals. Ensure that the sync signal (Y for Y Pb Pr signals and usually G for RGB signals) is filtered by IN1_ since IN2_ and IN3_ are internally synced to IN1_. Set the clamp level for IN1_ to +1V (CLEVEL1 = 0) and set the clamp levels for IN2_ and IN3_ to +1.5V (CLEVEL2, 3 = 1) for Y Pb Pr filtering (Figure 12) and set all clamp levels to 1V (CLEVEL_ = 0) for RGB filtering (Figure 13). A Y Pb Pr component video-filter application requires three MAX7428s with SYNCIO master-slave configuration. The MAX7428 processing the Y signal has its SYNCIO configured as an output, which in turn drives the SYNCIO inputs of the other MAX7428s (Figure 14). For RGB video signal filtering with a separate horizontal sync signal, configure all MAX7428s for SYNCIO as an input (Figure 15). ______________________________________________________________________________________ Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432 Y (LUMA) OUT INA SYNCIO MAX7430 Y (LUMA) IN1A [CLEVEL = 0] (CLEVEL = 0) OUT1 MAX7248 C (CHROMA) C (CHROMA) IN2A [CLEVEL = 1] OUT INA SYNCIO OUT2 (CLEVEL = 1) MAX7248 Figure 10. MAX7430 Y/C Video Filter Application Figure 11. Y/C Video Filter Application MAX7432 MAX7432 Y (LUMA) (INCLUDES SYNC SIGNAL) IN1A [CLEVEL = 0] OUT1 G (MUST CONTAIN SYNC SIGNAL) IN1A [CLEVEL = 0] OUT1 Pb IN2A [CLEVEL = 1] OUT2 R IN2A [CLEVEL = 0] OUT2 Pr IN3A [CLEVEL = 1] OUT2 B IN3A [CLEVEL = 0] OUT3 Figure 12. MAX7432 Y Pb Pr Video Filter Application Set the clamping levels for component video so the MAX7428 processing Y clamps at +1V (CLEVEL = 0). The remaining two MAX7428s should have clamp levels set to +1.5V (CLEVEL = 1). For RGB video with external sync (H), all three MAX7428s should have clamp levels set to +1V (CLEVEL = 0). Figure 13. MAX7432 RGB Video Filter with Embedded Sync Application Power-Supply Bypassing and Layout The MAX7428/MAX7430/MAX7432 operate from a single +5V supply. Bypass V CC to GND with a 0.1µF capacitor. Place all external components as close to the devices as possible. Refer to the MAX7428EVKIT for a proven PC board layout example. ______________________________________________________________________________________ 15 MAX7428/MAX7430/MAX7432 Standard Definition Video Reconstruction Filters and Buffers Y (LUMA) (INCLUDES SYNC SIGNAL) OUT INA INB R INB SYNCIO SYNCIO (CLEVEL = 0) (CLEVEL = 0) MAX7248 MAX7248 G Pb OUT INA INA OUT INB SYNCIO INA OUT INB SYNCIO (CLEVEL = 0) (CLEVEL = 1) MAX7248 MAX7248 B Pr INA OUT INB SYNCIO Figure 14. Y Pb Pr Video Filter Application OUT INB SYNCIO (CLEVEL = 0) (CLEVEL = 1) MAX7248 INA MAX7248 EXTERNAL H SYNC Figure 15. RGB Video Filter with External Sync Application Chip Information TRANSISTOR COUNT: MAX7428 = 4955 MAX7430 = 7413 MAX7432 = 9873 PROCESS: BiCMOS 16 ______________________________________________________________________________________ Standard Definition Video Reconstruction Filters and Buffers TOP VIEW INA 1 VCC 2 INB 8 OUT IN1A 1 7 REXT IN2A MAX7428 3 6 DATA GND 4 5 SYNCIO 2 REXT 3 IN1B 4 IN2B MAX7430 10 VCC IN1A 1 14 VCC 9 OUT1 IN2A 2 13 OUT1 8 GND IN3A 3 12 REXT 7 OUT2 GND 4 DATA IN1B 5 10 GND IN2B 6 9 OUT3 IN3B 7 8 DATA 6 5 µMAX SOT23 MAX7432 11 OUT2 TSSOP Functional Diagrams (continued) * VCC IN1A * D/A 6TH-ORDER FILTER +6dB OUT1 IN1B LEVEL SHIFT AUX INPUT SYNC SERIAL INTERFACE AND CONTROL DATA * IN2A D/A * 6TH-ORDER FILTER ENCODER +6dB OUT2 IN2B LEVEL SHIFT AUX INPUT BIAS GENERATOR MAX7430 GND REXT *OPTIONAL OUTPUT CAPACITOR ______________________________________________________________________________________ 17 MAX7428/MAX7430/MAX7432 Pin Configurations Standard Definition Video Reconstruction Filters and Buffers MAX7428/MAX7430/MAX7432 Functional Diagrams (continued) * VCC IN1A * D/A 6TH-ORDER FILTER +6dB OUT1 IN1B LEVEL SHIFT AUX INPUT SYNC SERIAL INTERFACE AND CONTROL DATA * IN2A D/A * 6TH-ORDER FILTER +6dB OUT2 IN2B LEVEL SHIFT AUX INPUT * IN3A D/A * 6TH-ORDER FILTER ENCODER +6dB OUT3 IN3B LEVEL SHIFT AUX INPUT MAX7432 GND BIAS GENERATOR REXT *OPTIONAL OUTPUT CAPACITOR 18 ______________________________________________________________________________________ Standard Definition Video Reconstruction Filters and Buffers SOT23, 8L.EPS ______________________________________________________________________________________ 19 MAX7428/MAX7430/MAX7432 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) e 10LUMAX.EPS MAX7428/MAX7430/MAX7432 Standard Definition Video Reconstruction Filters and Buffers 4X S 10 INCHES 10 H ÿ 0.50±0.1 0.6±0.1 1 1 0.6±0.1 BOTTOM VIEW TOP VIEW D2 MILLIMETERS MAX DIM MIN A 0.043 A1 0.002 0.006 A2 0.030 0.037 D1 0.116 0.120 D2 0.114 0.118 E1 0.116 0.120 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S α 0∞ 6∞ MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0∞ 6∞ E2 GAGE PLANE A2 c A b D1 FRONT VIEW A1 α E1 L L1 SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 10L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. 21-0061 20 ______________________________________________________________________________________ REV. I 1 1 Standard Definition Video Reconstruction Filters and Buffers TSSOP4.40mm.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX7428/MAX7430/MAX7432 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)