SEMICONDUCTOR TECHNICAL DATA The MC10160 consists of nine Exclusive-OR gates in a single package, internally connected to provide odd parity checking or generation. Output goes high when an odd number of inputs are high. Unconnected inputs are pulled to low logic levels allowing parity detection and generation for less than 12 bits. PD = 320 mW typ/pkg (No Load) tpd = 5.0 ns typ tr, tf = 2.0 ns typ (20%–80%) L SUFFIX CERAMIC PACKAGE CASE 620–10 LOGIC DIAGRAM P SUFFIX PLASTIC PACKAGE CASE 648–08 3 4 5 6 7 PIN ASSIGNMENT 9 10 2 11 12 13 14 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 15 INPUT OUTPUT Sum of High Level Inputs Pin 2 Even Low Odd High 9/96 Motorola, Inc. 1996 3–69 REV 6 VCC1 1 16 VCC2 OUT 2 15 IN12 IN1 3 14 IN11 IN2 4 13 IN10 IN3 5 12 IN9 IN4 6 11 IN8 IN5 7 10 IN7 VEE 8 9 IN6 MC10160 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Power Supply Drain Current Input Current Symbol Pin Pi Under Test IE 8 86 IinH (Note 1.) 3 4 425 350 IinL 3 0.5 –30°C Min +25°C Max Min +85°C Max Unit 78 86 mAdc 265 220 265 220 µAdc Typ Max 62 0.5 Min µAdc 0.3 Output Voltage Logic 1 VOH 2 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc Output Voltage Logic 0 VOL 2 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc Threshold Voltage Logic 1 VOHA 2 –1.080 Logic 0 VOLA 2 Threshold Voltage Switching Times –0.980 –0.910 –1.655 –1.630 Vdc –1.595 (50Ω Load) Propagation Delay ns t3+2+ t3+2– t3–2– t3–2+ t4+2+ t4+2– t4–2– t4–2+ 2 2 2 2 2 2 2 2 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 8.1 8.1 8.1 8.1 8.1 8.1 8.1 8.1 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 7.5 7.5 7.5 7.5 7.5 7.5 7.5 7.5 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 t2+ 2 1.1 3.5 1.1 2.0 3.3 1.0 3.5 Fall Time (20 to 80%) t2– 2 1.1 3.5 1. Pins 3, 6, 7, 11, 12, 15 are similar. Pins 4, 5, 9, 10, 13, 14 are similar. 1.1 2.0 3.3 1.0 3.5 Rise Time MOTOROLA (20 to 80%) Vdc 3–70 MECL Data DL122 — Rev 6 MC10160 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic Power Supply Drain Current Input Current @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Pin Under Test IE 8 IinH (Note 1.) 3 4 IinL 3 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VEE (VCC) Gnd 4,5,9, 10,13,14 8 1,16 3 4 8 8 1,16 1,16 3 8 1,16 4,5,6,7,9,10, 11,12,13,14,15 8 1,16 8 1,16 8 1,16 4 8 1,16 Pulse In Pulse Out –3.2 V +2.0 V 3 3 3 3 4 4 4 4 2 2 2 2 2 2 2 2 8 8 8 8 8 8 8 8 1,16 1,16 1,16 1,16 1,16 1,16 1,16 1,16 3 2 8 1,16 3 2 8 1,16 VIHmax Output Voltage Logic 1 VOH 2 Output Voltage Logic 0 VOL 2 3,4,5,6,7,9,10, 11,12,13,14,15 Threshold Voltage Logic 1 VOHA 2 4,5,6,7,9,10, 11,12,13,14,15 Threshold Voltage Logic 0 VOLA 2 3,5,6,7,9,10, 11,12,13,14,15 t3+2+ t3+2– t3–2– t3–2+ t4+2+ t4+2– t4–2– t4–2+ 2 2 2 2 2 2 2 2 t2+ 2 Switching Times (50Ω Load) Propagation Delay Rise Time (20 to 80%) Fall Time (20 to 80%) 3 VILmin +1.11V 4 4 3 3 t2– 2 1. Pins 3, 6, 7, 11, 12, 15 are similar. Pins 4, 5, 9, 10, 13, 14 are similar. VIHAmin VILAmax 3 Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. MECL Data DL122 — Rev 6 3–71 MOTOROLA MC10160 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M –A– 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ MOTOROLA 3–72 *MC10160/D* MC10160/D MECL Data DL122 — Rev 6