Revised February 2002 74ALVCH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold General Description Features The ALVCH16244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ALVCH16244 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74ALVCH16244 is designed for low voltage (1.65V to 3.6V) VCC applications with output capability up to 3.6V. The 74ALVCH16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ 1.65V to 3.6V VCC supply operation ■ 3.6V tolerant control inputs and outputs ■ Bushold on data inputs eliminating the need for external pull-up/pull-down resistors ■ tPD 3 ns max for 3.0V to 3.6V VCC 3.7 ns max for 2.3V to 2.7V VCC 6.0 ns max for 1.65V to 1.95V VCC ■ Uses patented noise/EMI reduction circuitry ■ Latch-up conforms to JEDEC JED78 ■ ESD performance: Human body model > 2000V Machine model > 200V Ordering Code: Order Number 74ALVCH16244T Package Number Package Description MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names © 2002 Fairchild Semiconductor Corporation DS500625 Description OEn Output Enable Input (Active LOW) I0–I15 Bushold Inputs O0–O15 Outputs www.fairchildsemi.com 74ALVCH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold September 2001 74ALVCH16244 Connection Diagram Truth Tables Inputs Outputs OE1 I0–I3 L L L L H H H X Z Inputs O0–O3 Outputs OE3 I8-I11 L L L L H H H X Z Inputs O8–O11 Outputs OE2 I4-I7 O4-O7 L L L L H H H X Z Inputs Outputs OE4 I12-I15 O12-O15 L L L L H H H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Functional Description puts are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs. The 74ALVCH16244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE out- Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 3) −0.5V to +4.6V Supply Voltage (VCC) −0.5V to 4.6V DC Input Voltage (VI) Output Voltage (VO) (Note 2) Power Supply −0.5V to VCC +0.5V Operating DC Input Diode Current (IIK) VI < 0V −50 mA 0V to VCC Output Voltage (VO) DC Output Diode Current (IOK) 0V to VCC Free Air Operating Temperature (TA) VO < 0V −50 mA −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V DC Output Source/Sink Current ±50 mA (IOH/IOL) ±100 mA Supply Pin (ICC or GND) 10 ns/V Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC VCC or GND Current per Storage Temperature Range (TSTG) 1.65V to 3.6V Input Voltage (VI) −65°C to +150°C Note 2: IO Absolute Maximum Rating must be observed, limited to 4.6V. Note 3: Floating or unused control inputs must be held HIGH or LOW. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage IOH = −100 µA VCC (V) Min 1.65 - 1.95 0.65 x VCC 2.3 - 2.7 1.7 2.7 - 3.6 2.0 0.35 x VCC 2.3 - 2.7 0.7 2.7 - 3.6 0.8 1.65 - 3.6 Units V 1.65 - 1.95 V VCC - 0.2 IOH = −4 mA 1.65 1.2 IOH = −6 mA 2.3 2.0 IOH = −12 mA 2.3 1.7 2.7 2.2 V 3.0 2.4 IOH = −24 mA 3.0 2 IOL = 100 µA 1.65 - 3.6 0.2 1.65 0.45 IOL = 4 mA IOL = 6 mA 2.3 0.4 IOL = 12 mA 2.3 0.7 2.7 0.4 IOL = 24 mA 3.0 0.55 II Input Leakage Current 0 ≤ VI ≤ 3.6V 3.6 II(HOLD) Bushold Input Minimum VIN = 0.58V 1.65 25 −25 Drive Hold Current Max ±5.0 VIN = 1.07V 1.65 VIN = 0.7V 2.3 45 VIN = 1.7V 2.3 −45 VIN = 0.8V 3.0 75 −75 V µA µA VIN = 2.0V 3.0 0 < VO ≤ 3.6V 3.6 ±500 IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V 3.6 ±10 µA ICC Quiescent Supply Current VI = V CC or GND, IO = 0 3.6 40 µA ∆ICC Increase in ICC per Input VIH = VCC − 0.6V 3 - 3.6 750 µA 3 www.fairchildsemi.com 74ALVCH16244 Absolute Maximum Ratings(Note 1) 74ALVCH16244 AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol CL = 50 pF Parameter VCC = 3.3V ± 0.3V CL = 30 pF VCC = 2.7V Min VCC = 2.5V ± 0.2V VCC = 1.8V ± 0.15V Units Min Max Max Min Max Min Max tPHL, tPLH Propagation Delay 1.0 3 3.6 1.0 3.7 1.5 6.0 tPZL, tPZH Output Enable Time 1.0 4.4 5.4 1.0 5.7 1.5 8.2 ns tPLZ, tPHZ Output Disable Time 1.0 4.1 4.6 1.0 5.2 1.5 6.8 ns ns Capacitance Symbol CIN Parameter Input Capacitance COUT Output Capacitance CPD Power Dissipation Capacitance www.fairchildsemi.com Conditions TA = +25°C Units VCC Typical Control VI = 0V or VCC 3.3 3 Data VI = 0V or VCC 3.3 6 VI = 0V or VCC 3.3 7 Outputs Enabled f = 10 MHz, CL = 50 pF 3.3 19 2.5 16 Outputs Disabled f = 10 MHz, CL = 50 pF 3.3 5 2.5 4 4 pF pF pF TABLE 1. Values for Figure 1 TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VL tPZH, tPHZ GND FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω) Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V 1.5V VCC/2 VCC/2 Vmo 1.5V 1.5V VCC/2 VCC/2 VX VOL + 0.3V VOL + 0.3V VOL + 0.15V VOL + 0.15V VY VOH − 0.3V VOH − 0.3V VOH − 0.15V VOH − 0.15V VL 6V 6V VCC*2 VCC*2 FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic 5 www.fairchildsemi.com 74ALVCH16244 AC Loading and Waveforms 74ALVCH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6