19-4771; Rev 1; 10/98 ANUAL N KIT M EET IO T A U EVAL TA SH WS DA FOLLO 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC ____________________________Features ♦ Regulated Step-Up/Step-Down Operation ♦ 80mA Output from 3 Cells ♦ 85% Efficiency ♦ 13µA Idle Mode™ (coast) Current ♦ Selectable Low-Noise PWM or Low-Current PFM Operation ♦ PWM Operating Frequency Synchronized to Seven Times an External Clock Source ♦ Operates at 270kHz with No External Clock ♦ Automatic Backup-Battery Switchover Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX769EEI -40°C to +85°C 28 QSOP ________________________Applications Two-Way Pagers GPS Receivers 2 or 3-Cell Powered, Hand-Held Equipment Pin Configuration appears at end of data sheet. ___________________________________________________Typical Operating Circuit INPUT 2 OR 3 AA ALKALINE BATTERIES 1.5V TO 5.5V BATT LX1 LOW-BATTERY IN/OUT LBI LBO LX2 OUT REJECT IN/OUT RSIN RSO PGND SERIAL I/O CS SCL SD1 SD03 1.8Ω DRIVERS A/D INPUT OPTIONAL REG2IN MAX769 OFS DR1 DR2 DR2IN DRGND CH0 SYNC FILT REF AGND REG2 OUTPUT 2 2.85V ANALOG REG1 OUTPUT 1 3V LOGIC REG3 OUTPUT 3 1V RECEIVER NICD TO RF PA NiCd STORAGE BATTERY OR CAPACITOR STACK Idle Mode is a trademark of Maxim Integrated Products. SPI is a trademark of Motorola, Inc. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX769 ________________General Description The MAX769 is a complete buck/boost power supply and monitoring system for two-way pagers or other lowpower digital communications devices. Few external components are required. Included on-chip are: • An 80mA output, synchronous-rectified, buck/boost DC-DC converter with a digitally controlled +1.8V to +4.9V output. The DC-DC converter is unique, since it provides a regulated output for battery inputs that are both less than and greater than the output voltage, without using transformers. • Three low-noise linear-regulator outputs • Three DAC-controlled comparators for softwaredriven, 3-channel A/D conversion • SPI™-compatible serial interface • Reset and low-battery (LBO) warning outputs • Charger for NiCd/NiMH, lithium battery, or storage capacitor for RF PA power or system backup • Two 1.8Ω (typical), serial-controlled, open-drain MOSFET switches for beeper or vibrator drive An evaluation kit for the MAX769 (MAX769EVKIT) is available to aid in design and prototyping. MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC ABSOLUTE MAXIMUM RATINGS BATT, OUT, NICD, LBO, RSO to AGND...................-0.3V to +6V REG1, REG2, OFS, REF, R2IN to AGND .....-0.3V to (OUT + 0.3V) SCL, SDO, SDI, CS, SYNC, FILT, DR2IN, CH0, LBI, RSIN to AGND......................-0.3V to (REG1 + 0.3V) REG3 .......................................................-0.3V to (REG2 + 0.3V) DR1, DR2 to DRGND ...............................-0.3V to (BATT + 0.3V) PGND, DRGND to AGND ......................................-0.3V to +0.3V LX1 to PGND .............................................-0.3V to (OUT + 0.3V) LX2 to PGND ............................................-0.3V to (BATT + 0.3V) Continuous Power Dissipation (TA = +70°C) QSOP (derate 8mW/°C above +70°C) ..........................640mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +165°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (OUT = 3.0V, BATT = 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS 5.5 V GENERAL PERFORMANCE BATT Typical Operating Range (Note 2) Run or Coast Mode BATT Minimum Start-Up Voltage (Note 3) TA = +25°C 1.6 2.0 V Coast Mode Supply Current (Note 4) REG2, REG3 and CH DAC off, VOUT = 2.8V 13 25 µA Run Mode Supply Current (Note 4) REG2, REG3 and CH DAC on 875 1350 µA BATT Supply Current (Note 5) Coast Mode 4 10 µA NICD Input Current, Standby (Note 6) Charger and Backup Modes off, NICD = 3.6V 1.2 3 µA NICD Input Supply Current, Backup (Note 7) Backup Mode, NICD = 3.6V, OUT = 3V 20 40 µA NICD Input Current, Power Fail (Note 8) Charger and Backup Modes off, BATT = 0V, OUT = 0V 1.2 3 µA REG2 Supply Current (Note 4) Incremental supply current when on 50 µA REG3 Supply Current (Note 4) Incremental supply current when on 20 µA CH DAC Supply Current (Note 4) Incremental supply current when on 30 µA Reference Voltage DR1, DR2 Leakage Current IREF = 0 to 20µA, OUT = 1.8V to 4.9V TA = +25°C IDR = 120mA TA = -40°C to +85°C VDR = 5V SDO Output Low ISDO = 100µA SDO Output High ISDO = -100µA, from REG1 Logic Input Level Low Includes CS, SDI, SCL, DR2IN, and SYNC Logic Input Level High Includes CS, SDI, SCL, DR2IN, and SYNC Logic Input Current Logic Input = 0 to 3.3V; includes CS, SDI, SCL, DR2IN, and SYNC DR1, DR2 On-Resistance 2 1.5 -1.5% 1.28 1.8 1 1.5% 2.8 3.6 250 V nA 200 mV Ω VREG1 - 0.2 V 0.4 V -1 _______________________________________________________________________________________ VREG1 - 0.4 V 1 µA 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC MAX769 ELECTRICAL CHARACTERISTICS (continued) (OUT = 3.0V, BATT = 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS SERIAL-INTERFACE TIMING SPECIFICATIONS (Note 9) SCL Maximum Clock Rate 5 MHz SDI Setup Time (tDS) 50% duty cycle 100 ns SDI Hold Time (tDH) 50 ns SCL to SDO Output Valid (tDO) 70 ns CS to SDO Output Valid (tDV) 70 ns 70 ns CS to SDO Disable (tTR) CS to SCL Setup Time (tCSS) 50 ns CS to SCL Hold Time (tCSH) 50 ns CS Pulse Width High (tCSW) 100 ns SCL Pulse Width High or Low (tCH, tCL) 50 ns DC-DC CONVERTER Output Current, Run Mode (Note 10) Circuit of Figure 2, OUT = 3.0V, BATT = 3.0V 80 115 mA Output Current, Coast Mode (Note 10) Circuit of Figure 2, OUT = 3.0V, BATT = 3.0V 15 40 mA OUT Error, Coast Mode (Note 11) Coast Mode, OUT = 1.8V to 4.9V -3.5 OUT Error, Run Mode (Note 12) Run Mode, OUT = 1.8V to 4.9V -3.5 OUT DAC Step Size (Note 13) Coast or Run Mode, OUT = 1.8V to 4.9V OUT Load Regulation IOUT = 1mA to 80mA, Run Mode OUT Line Regulation BATT = 1.6V to 4.5V Maximum LX Duty Cycle 76 OUT Voltage Ripple OUT = 3.0V IOUT = 80mA, COUT = 47µF with ESR < 0.25Ω LX Switch Current Limit During the inductor charge cycle 300 LX On-Resistance (Note 14) LX1, LX2, BATT = 3.0V 30 3.5 100 % 3.5 % 170 mV 25 mV 25 mV 83 % 70 mVp-p 350 400 mA NMOS 0.9 1.8 PMOS 1.3 2.6 Ω 270 325 PHASE-LOCKED LOOP (PLL) Frequency, Free-Run TA = +25°C, FILT connected to REF Frequency, Locked 268.8 kHz Jitter (Note 15) fSYNC = 38.4kHz fSYNC = 38.4kHz, FILT Network = 1nF (22nF + 10kΩ) 210 kHz ±15 kHz Capture Time (Note 15) fSYNC = 38.4kHz, FILT Network = 1nF (22nF + 10kΩ) 1 25 ms NICD CHARGER Current High 0.2V < (OUT - NICD) < 2V, 15mA_CHG = 1 7 25 mA Current Low 0.2V < (OUT - NICD) < 2V, 1mA_CHG = 1 0.45 1.5 mA OUT Error, Backup Regulator OUT = 2.8V, IOUT = 20mA, NICD = 3.3V -3.5 3.5 % Backup-Regulator On-Resistance (Note 16) Backup Mode, NICD = 3.3V 10 Ω 5 _______________________________________________________________________________________ 3 MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC ELECTRICAL CHARACTERISTICS (continued) (OUT = 3.0V, BATT = 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS 1.5 3.1 Ω LINEAR REGULATORS REG1 PMOS On-Resistance OUT = 3.0V, IREG1 = 65mA REG1 Supply Rejection (Note 16) f = 268.8kHz, CREG1 = 10µF ceramic REG1 Clamp Voltage IOUT = 1mA, OUT = 4.9V TA = +25°C REG2 Voltage Drop TA = -40°C to +85°C IREG2 = 0 to 24mA, OUT = 3.0V, ROFS = 15kΩ REG2 Load Regulation IREG2 = 0.1mA to 24mA REG2 Supply Rejection (Note 16) f = 268.8kHz, CREG1 = 10µF, ceramic, ROFS = 15kΩ, COFS = 0.1µF, IREG2 = 15mA REG3 Output Voltage IREG3 = 0 to 2mA REG3 Supply Rejection (Note 16) f = 268.8kHz, CREG1 = 1µF ceramic 15 25 3.2 3.3 3.15 120 dB 3.4 3.45 155 190 V V mV 9 mV 30 40 dB 0.96 1.0 40 50 1.04 V dB DATA-ACQUISITION AND VOLTAGE MONITORS LBI/RSIN Input Threshold 0.58 0.60 0.63 V LBI/RSIN Input Hysteresis (Note 16) Falling input 7.5 16 30 mV LBI/RSIN Input Current -50 -3 50 nA LBO/RSO Output Low IOUT = 1mA 30 400 mV LBO/RSO Output Leakage Output = 5.5V 1 250 nA LBO/RSO Response Time (Note 16) 10mV overdrive 15 50 µs CH0 Threshold Range (Note 16) 0.2 1.27 V CH1 Threshold Range (Note 16) Measures NICD 1.2 5.08 V CH2 Threshold Range (Note 16) Measures BATT 1.2 5.08 V CH0 Threshold Resolution (Note 16) 10 mV CH1 Threshold Resolution (Note 16) Measures NICD 40 mV CH2 Threshold Resolution (Note 16) Measures BATT 40 mV CH0 Error At thresholds of 200mV, 800mV, and 1270mV -2.0 - 15mV 2.0 + 15mV % CH1 Error At thresholds of 1200mV, 3200mV, and 5080mV -3.0 - 60mV 3.0 + 60mV % CH2 Error At thresholds of 1200mV, 3200mV, and 5080mV -3.0 - 60mV 3.0 + 60mV % CH0 Input Hysteresis (Note 16) 1 2 4 mV CH1 Input Hysteresis (Note 16) 4 8 16 mV 4 _______________________________________________________________________________________ 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC (OUT = 3.0V, BATT = 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER CONDITIONS CH2 Input Hysteresis (Note 16) CH0 Input Current CH0 = 0.2V to 1.27V CH Comparator Response Time (Note 16) 10mV overdrive Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: MIN TYP MAX UNITS 4 8 16 mV 100 nA 1.0 µs -100 0.6 Specifications to -40°C are guaranteed by design, not production tested. This is not a tested parameter, since the IC is powered from OUT, not BATT. Minimum start-up voltage is tested by determining when the LX pins can draw at least 15mA for 0.5µs (min) at a 285kHz (min) repetition rate. This guarantees that the IC will deliver at least 200µA at the OUT pin. This supply current is drawn from the OUT pin. Current drain from the battery depends on voltages at BATT and OUT and on the DC-to-DC converter’s efficiency. Current into BATT pin in addition to the supply current at OUT. This current is roughly constant from Coast to Run Mode. Current into NICD pin when NICD isn’t being charged and isn’t regulating OUT. Current into NICD pin when NICD is regulating OUT. Doesn’t include current drawn from OUT by the rest of the circuit. Measured by setting the OUT regulation point to 2.8V and holding OUT at 3.0V. Current into the NICD pin when BATT and OUT are both at 0V. This test guarantees that NICD won’t draw significant current when the main battery is removed and backup is not activated. Serial-interface timing specifications are not tested and are provided for design guidance only. Serial-interface functionality is tested by clocking data in at 5MHz with a 50% duty-cycle clock and checking for proper operation. With OUT set below 2.5V, the serial-interface clock frequency should be reduced to 1MHz to ensure proper operation. This specification is not directly tested but is guaranteed by correlation to LX on-resistance and current-limit tests. Measured by using the internal feedback network and Coast-Mode error comparator to regulate OUT. Doesn’t include ripple voltage due to inductor currents. Measured by using the internal feedback network and Run-Mode error comparator to regulate OUT. Doesn’t include ripple voltage due to inductor currents. Uses the OUT measurement techniques described for the OUT error, Coast Mode, and OUT error Run Mode specifications. The on-resistance is for either LX1 or LX2. PLL acquisition characteristics depend on the impedance at the FILT pin. The specification is not tested and is provided for design guidance only. The limits in this specification are not guaranteed and are provided for design guidance only. Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) 90 EFFICIENCY (%) EFFICIENCY (%) 90 80 70 VIN = 5.0V VIN = 3.5V 60 80 100 MAX769-02 100 VIN = 5.0V VIN = 3.5V VIN = 2.5V VIN = 2.0V VIN = 1.5V VIN = 5.0V VIN = 3.5V VIN = 2.5V VIN = 2.0V VIN = 1.5V 90 EFFICIENCY (%) VIN = 1.5V VIN = 2.0V MAX769-01 100 EFFICIENCY vs. LOAD CURRENT (COAST MODE, VOUT = 2.4V) EFFICIENCY vs. LOAD CURRENT (COAST MODE, VOUT = 3.0V) 70 MAX769-03 EFFICIENCY vs. LOAD CURRENT (RUN MODE, VOUT = 3.0V) 80 70 60 60 VIN = 2.5V 50 50 50 1 10 LOAD CURRENT (mA) 100 0.01 0.1 1 LOAD CURRENT (mA) 10 100 0.01 0.1 1 10 100 LOAD CURRENT (mA) _______________________________________________________________________________________ 5 MAX769 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) START-UP BATTERY VOLTAGE vs. LOAD CURRENT MAXIMUM LOAD CURRENT vs. BATTERY VOLTAGE VOUT = 3.0V 140 120 RUN MODE 100 80 COAST MODE 60 40 6 MAX769-06 160 MAX769-05 VOUT = 3.0V COAST MODE MAXIMUM LOAD CURRENT (mA) MAX769-04 100 VOUT = 3.0V COAST MODE START-UP BATTERY VOLTAGE (V) NO-LOAD BATTERY CURRENT vs. BATTERY VOLTAGE BATTERY CURRENT (µA) 5 4 3 2 20 1 0 10 2 3 4 5 1 6 2 3 4 5 10 NICD CHARGING CURRENT vs. NICD VOLTAGE DR1 OR DR2 ON-RESISTANCE vs. VOUT 3 MAX769-07 25 100 LOAD CURRENT (mA) BATTERY VOLTAGE (V) BATTERY VOLTAGE (V) 20 2 15 RON (Ω) NICD CHARGING CURRENT (mA) 1 6 MAX769-08 1 10 1 5 15mA MODE VOUT = 4.9V 0 0 1 2 3 4 5 0 6 2 3 4 VOUT VOLTAGE (V) LX NOISE SPECTRUM (RUN MODE, SYNC OPERATION) REG2 NOISE SPECTRUM (RUN MODE) 100 MAX769-09 20 5 80 NOISE (dBµV) 0 -20 -40 60 40 20 -60 -80 0 100 200 300 400 FREQUENCY (kHz) 6 1 NICD VOLTAGE (V) MAX769-10 0 NOISE (dBV) MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC 500 600 0.1 1 10 100 1000 FREQUENCY (kHz) _______________________________________________________________________________________ 10,000 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC PIN NAME FUNCTION LX1 Connect LX1 to the inductor. LX1 is internally connected to an NFET that switches to PGND and a PFET that switches to OUT. 2 SDI Serial Data Input for SPI Interface 3 SDO Serial Data Output for SPI Interface 4 PGND 1 Power Ground. Source of LX1 and LX2 NFETs. 5 SCL Serial Clock for SPI Interface 6 LBO Open-Drain Output for LBI Comparator 7 RSO Reset Output. Open drain goes low when RSIN drops below 0.6V. All serial registers are reset (or set) to POR state as well. 8 REF 1.28V Reference. Bypass with a 1µF capacitor. 9 CH0 CH0 is compared to a 7-bit DAC that adjusts from 0.2V to 1.27V. The comparison result is sent to the CH0 OUT register. 10 RSIN Reset Input. Triggers RSO and resets IC when input is below 0.6V. Comparator with hysteresis (18mV). 11 LBI Low-Battery Input. Triggers LBO and internal serial bit. 12 FILT An external RC network sets the PLL loop response to adjust frequency lock time versus jitter: 1nF || (22nF + 10kΩ). 13 SYNC Sync Input for PWM Switch Rate. A 38.4kHz input results in a 268.8kHz PWM rate (seven times the SYNC frequency). 14 OFS Resistor sets offset between OUT (or REG1 or any other point) and REG2. ROFS = 15kΩ results in 150mV. 15 AGND 16 DRGND 17 DR1 18 DR2IN Analog Ground Ground for DR1 and DR2 FET Sources Open-Drain FET Switch. Activated via the serial-interface bit. Logic Input. ANDed with the DR2ON bit to control the DR2 switch. 19 DR2 20 REG3 Open-Drain FET Switch. On via AND of the DR2ON bit and the DR2IN pin. 1V, 2mA Regulator Output. On via the serial interface. Low noise. 21 REG2 24mA REG2 Output. Linearly regulated to the voltage at the OFS pin (voltage difference = 10µA x ROFS). REG2 isolates noise. 22 R2IN REG2 Input. Connect to OUT, REG1, or another voltage source. 23 NICD 15mA or 1mA Settable Charge Current from OUT to 3-Cell NiCd Stack. When the NICD_REG_ON bit is set (Table 1), NICD becomes an input to the linear regulator at OUT, and the DC-DC converter is off. 24 REG1 PFET Output Connected to OUT. Output is clamped such that it cannot rise above 3.3V, regardless of the voltage set at OUT. 25 OUT DC-DC Converter Output and Feedback Point. Digitally controlled from 1.8V to 4.9V in 100mV steps (Table 5). 26 BATT Positive Connection to Battery. The IC is powered from OUT. 27 CS Chip Select for SPI Serial Interface 28 LX2 Connect LX2 to the other inductor terminal. LX2 is internally connected to an NFET that switches to PGND and a PFET that switches to BATT. _______________________________________________________________________________________ 7 MAX769 Pin Description MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC 2- OR 3-CELL BATTERY IN SCL SDI SDO CS 5 2 3 27 22µF 26 BATT P 28 N LBO 6 11 – 0.6V CPLB + CH0 9 + CP0 – FROM NICD S1 X7 PLL TO S1 AND S2 SERIAL I/O 12 5 FILT OUT 25 CH2 3.3V CLAMP DAC0–DAC7 – AR1 + 47µF P REG1 24 10µF BACKUP REGULATOR AOUT + 5 10k SYNC CLAMP ON WHEN OV4 = 1 CONTROL REF LX1 13 RESET 7-BIT CH DAC L1 68µH 22nF CH1 7 PGND P OV0–OV4 + CP2 – S2 1 CH0 + CP1 – FROM BATTERY 4 N RUN/ COAST LB0 N PWM (PFM IN COAST) MAX769 LBI LX2 CHARGE NICD OR BACKUP REGULATOR V FEEDBACK 8 ROFS 15k 23 NICD 1µF 1.28V REFERENCE 0.6V RSIN 10 1mA/15mA CHG/REG 14 22 + CPRS – 10µA – AR2 + 3.3V OFS R2IN COFS 0.1µF P REG2 21 REG2 ON RSO 7 10µF N REG3 ON 1.8Ω 1.0V – AR3 + REG3 1.8Ω N 20 N 17 18 19 DR1 DR2IN DR2 16 P 1.0V 1µF 15 DRGND AGND Figure 1. MAX769 Block Diagram 8 _______________________________________________________________________________________ 1nF 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC The MAX769 contains several functional blocks that simplify the integration of power-supply and monitoring functions within a 2 or 3-cell powered system. They are described in the following subsections. Voltage Regulators Regulator outputs include the following: • OUT: Main switch-mode buck/boost output • REG1: 1.5Ω switch and output voltage clamp. Switches REG1 to OUT and clamps REG1 at 3.3V when OUT is set to 3.4V or more. • REG2: Linear-regulated, 24mA low-noise output that regulates so that VOUT - VREG2 is a set difference voltage (10µA x ROFS). Output peak-to-peak ripple is typically 2mV with a 10µF bypass capacitor at REG2. REG2 clamps the output at 3.3V when OUT is set to 3.4V or more. • REG3: Low-noise, 1V linear regulator that supplies 2mA. Main DC-DC Boost Converter (OUT) OUT is the main DC-DC converter’s output. It supplies current from the internal synchronous-rectified buck/ boost regulator and needs no external FETs or voltagesetting resistors. The output voltage (VOUT) is adjusted from 1.8V to 4.9V in 100mV steps (Tables 1 and 5) by internal DAC control using a serial-data command. OUT can supply up to 80mA, less the current supplied to the other regulators (REG1, REG2, and REG3). OUT can also be put into a low-current, pulse-skipping Coast Mode (13µA typical quiescent current) by resetting the RUN/COAST serial input bit. OUT supplies up to 40mA in Coast Mode. Typically, when changing from Run to Coast Mode, a lower OUT voltage is also set (Table 4) to further reduce system operating current. The extent of this reduction depends on the minimum operating voltage of the system components when they are in standby or sleep states. OUT can be set as low as 1.8V; however, some Run Mode functions are limited when VOUT is below 2.5V: • The allowed serial-interface clock rate is reduced. • Internal LX FET and DR1 and DR2 on-resistance increases. Logic Supply (REG1) REG1 is not a regulator in the conventional sense, but rather a 1.5Ω PFET that acts as either a switch or a voltage clamp, depending on the programmed OUT voltage. When OUT is set to 3.3V or less, REG1 operates as a switch. When OUT is set to 3.4V or more, the REG1 output clamps at 3.3V. This arrangement limits VREG1 to an acceptable voltage for logic when OUT is programmed to a higher voltage (typically >4V) for charging (see Charger Circuit and Backup Linear Regulator sections). Low-Noise Analog Supply (REG2) REG2 is a linear, 24mA low-dropout regulating circuit whose input is R2IN. The REG2 output (VREG2) is set by ROFS. ROFS does not set an absolute voltage, but rather an offset level from R2IN (Figure 2). VREG2 is set by: VREG2 = VR2IN - 10µA x ROFS Typically R2IN and R OFS are tied to OUT, in which case: VOUT - VREG2 = 10µA x ROFS ROFS adjusts V REG1 - V REG2 to allow REG2 noise rejection to be traded for voltage drop and consequent efficiency loss. A 15kΩ (typical) R OFS value sets a 150mV voltage difference. R2IN is typically supplied from OUT or REG1, but can be connected elsewhere as long as the voltage applied to R2IN does not exceed VOUT. For lowest output noise on REG2, connect R2IN to REG1. Note that the REG2 output also clamps at 3.3V when OUT is set to 3.4V or higher. Low-Noise, 1V Analog Supply (REG3) REG3 is a 1V, low-noise linear regulator that supplies up to 2mA. REG3’s input is internally connected to REG2. PWM Frequency Synchronization The DC-DC converter switching frequency in pulsewidth-modulation (PWM) mode is nominally 270kHz if no synchronization clock is supplied and FILT is tied to REF. If the PLL is used, a filter network is connected to FILT, a clock is applied to SYNC, and the internal oscillator locks to seven times the input clock rate. The MAX769 is designed for a 38.4kHz SYNC input and hence a 268.8kHz operating frequency. PWM switching frequency is unaffected by the serial-data clock rate. Voltage Detectors (LBO and Reset) The MAX769 contains two voltage-detector inputs: LBI and RSIN. The LBI and RSIN comparator outputs are open-drain pins (LBO and RSO) for a real-time hardware output. LBO is also readable via the serial interface. Both LBI and RSIN trigger at a 0.6V input threshold and have about 18mV hysteresis. RSO also triggers the MAX769 internal power-on reset (POR). _______________________________________________________________________________________ 9 MAX769 _______________Detailed Description MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC 2 OR 3-CELL AA ALKALINE BATTERY C5 22µF R1 1M 11 REG1 L1 68µH 26 1 BATT LX1 LX2 OUT LBI R2 250k R5 270k PGND 6 9 A/D IN SERIAL I/O 27 5 2 3 1.8Ω DRIVERS 17 19 18 16 38.4kHz C10 22nF CH0 13 12 C9 1nF 10k LBO 8 REG1 MAX769 CS SCL SDI SDO R2IN DR1 DR2 DR2IN DRGND REG2 OFS 28 25 C1 47µF 4 REG3 RSIN RSO NICD REF AGND 15 C6 0.1µF 3.0V LOGIC 24 C2 10µF 22 14 COFS 0.1µF ROFS, 15k 21 2.85V ANALOG C3 10µF SYNC FILT C8 1µF D1 MBR0520L 1V RCVR 20 C4 1µF 100k 10 7 R3 1.3M R4 470k 23 TO RF PA TO µC RESET 3-CELL NiCd Figure 2. Standard Application Circuit 7-Bit ADC (CH0 Input and CH1, CH2) Three analog channels are compared to a 7-bit, serially programmed digital-to-analog converter (CH DAC). The CH DAC voltage can be varied in 10mV steps from 200mV to VREF - 1LSB (or 1.27V) (Table 1). CH0 is an external input, while CH1 and CH2 are signals internally generated from the NICD and BATT pins. NICD and BATT are internally divided by four before being compared to CH DAC. The comparison threshold voltages for each channel are described in the following equations: VTH (CH0: pin 9) = D x 10mV VTH (CH1: NICD) = D x 40mV VTH (CH2: BATT) = D x 40mV 10 where D is the decimal equivalent of the binary code DAC0–DAC6 (Table 1). DAC0 is the LSB. A DAC code of 1111111 equates to D = 127. When all zeros are programmed, the CH DAC and CH_ comparators turn off. CH0, CH1, and CH2 comparison results reside in the three MSB locations of the output serial data (Table 4). The CH_ OUT data is delayed by one read cycle. In other words, each CH_ OUT bit is the result of the comparison made against the CH DAC voltage programmed during the previous serial-write operation. An analog-to-digital (A/D) conversion can be performed on a channel by using the system software to step through a successive-approximation routine or, if the input is partially known, by setting the CH DAC to a voltage near the estimated point and checking successive CH_ OUT bits. ______________________________________________________________________________________ 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC The A/D circuitry can be invoked in both Run and Coast Modes. Open-Drain Drivers Two open-drain drivers (DR1 and DR2) are activated via the serial interface. DR1 and DR2 are grounded 1.8Ω (typical) NFETs that can sink up to 120mA. The maximum sink current is limited by on-resistance and package dissipation to about 240mA total sink current for both switches. Note that DR1 and DR2 are designed to sink current only from the main battery (BATT) and cannot be pulled above BATT. DR2 is controlled by an external input (DR2IN) as well as a serial input bit. DR2IN is ANDed with the DR2ON serialcontrol bit, allowing DR2 to drive an audio beeper. The audio-frequency clock is applied to DR2IN, and ON/OFF gating is applied to DR2ON. Both DR2IN (pin 18) and DR2ON (serial bit) must be high for DR2 to switch on. Coast Mode/Voltage Selection Reduce the operating current by setting the RUN/COAST bit low via the serial input. This shifts the DC-DC boost converter from low-noise PWM operation (Run Mode) to a very low operating current mode (Coast Mode) in which switching pulses are only provided as needed to satisfy the load. To further reduce operating current in Coast Mode, lower VOUT using the OV0–OV4 serial bits. The MAX769 starts up in Coast Mode. Select Run Mode with the serial interface after power-up. Various circuit functions can be disabled as follows: Functions that always remain on in Coast Mode are: • • • • • Serial I/O Reference (REF) OUT REG1 LBI, RSIN (and LBO, RSO) Functions that can be programmed on or off in Coast Mode are (Table 1): • DR1 and DR2 • REG2 and REG3 • NICD charger (Note: This may overload OUT if turned on in Coast Mode when other loads are present) • Backup regulator • CH0, CH1, CH2, and CH DAC Functions that always turn off in Coast Mode are: • SYNC and PLL circuits • DC-DC PWM control circuits Power-On Reset The MAX769 has an internal POR circuit (VOUT < 1.6V) to ensure an orderly power-up when a battery is first applied. This feature is separate from the RSO comparator; however, if RSO goes low during operation, all serial registers are set to the same predetermined states as on power-up. The POR states for each register are listed in Table 2. Note that the MAX769 always comes out of reset in Coast Mode; consequently, it cannot supply full power until Run Mode is selected by serial command. System software cannot exercise full load current until Run Mode is enabled. Charger Circuit A charger current source from OUT to NICD is activated via a serial bit (Table 1). The current source can charge a small 3-cell NiCd or NiMH battery (typically a coin cell) or a 1-cell lithium battery. The charge current can be set to either 15mA or 1mA. OUT sets the maximum charge (or float) voltage. When charging is implemented, VOUT must also be set high enough to allow sufficient headroom for the charger current source. The VOUT - VNICD difference should normally be between 0.2V and 0.5V. Charger current vs. NICD voltage is graphed in the Typical Operating Characteristics. Note also that charging current reduces the OUT current available for other loads. Backup Linear Regulator The BACKUP serial input bit turns on the backup regulator, which sources current from NICD to OUT. This regulator backs up OUT by using the rechargeable battery (at NICD) when the main battery (at BATT) is depleted or removed. The backup regulator pass device’s resistance is typically 5Ω, so it can typically supply 20mA with only 100mV of dropout. ______________________________________________________________________________________ 11 MAX769 A faster A/D shortcut can be used for battery measurements when the goal is a “go, no go” determination. For this type of test, the CH DAC can simply be set to the desired limit, and CH_ OUT supplies the result on the next serial-write operation. One instance in which this shortcut saves time is during a battery-impedance check. The unloaded battery voltage can first be measured, if time allows, using one of the techniques described in the previous paragraph. Then the magnitude of the loaded voltage drop can be quickly checked with a single comparison to see if it is within the desired limit. MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC Table 1. Serial-Bit Assignments R2 (MSB) R1 R0 D4 D3 D2 D1 D0 0 0 0 DR2_ON DR1_ON REG3_ON REG2_ON RUN/ COAST 0 0 1 X LBO_Sets_ BACKUP BACKUP 15mA_CHG 1mA_CHG 0 1 0 OV4 OV3 OV2 OV1 OV0 0 1 1 X X X X X 1 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 Table 2. Serial-Bit Power-On Reset (POR) States R2 R1 R0 D4 D3 D2 D1 D0 0 0 0 POR = 0 POR = 0 POR = 0 POR = 0 POR = 0 0 0 1 X POR = 0 POR = 0 POR = 0 POR = 0 0 1 0 POR = 0 POR = 1 POR = 1 POR = 0 POR = 0 0 1 1 X X X X X 1 POR = 0 POR = 0 POR = 0 POR = 0 POR = 0 POR = 0 POR = 0 Table 3. Input-Bit Function Description INPUT BIT RUN/COAST FUNCTION 1 = Run Mode, 0 = Coast Mode (POR state is Coast Mode). REG2_ON, REG3_ON 1 = Turns on the selected regulator (POR state is off). DR1, DR2 1 = Turns on the selected switch (POR state is off). 1mA_CHG, 15mA_CHG 1 = Turns on the selected charge current to NICD. If both are set, the charge current is 15mA (POR state is off). BACKUP 1 = Turns on the backup linear regulator from NICD to OUT and disables the DC-DC converter (POR state is BACKUP off). Setting this bit overrides 1mA_CHG, 15mA_CHG, and LBO_Sets_BACKUP (Figure 1). LBO_Sets_BACKUP 1 = Allows LBO to turn on the backup regulator and disable the DC-DC converter (POR state is no connection between LBO and BACKUP). OV0–OV4 Sets OUT Output Voltage (POR state is VOUT = 3.0V). DAC0–DAC6 Sets 7-bit CH DAC voltage for A/D conversion (POR state is all zeros with DAC and comparators off). Table 4. Serial Output Data D7 (MSB) CH2_OUT 12 D6 CH1_OUT D5 CH0_OUT D4 LBO D3–D0 FUNCTION X CH_OUT and LBO output bits. A 1 indicates that the selected channel (CH_) voltage is greater than the CH DAC voltage or that LBI is less than 0.6V. ______________________________________________________________________________________ 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC SERIAL-DATA BIT VOUT (V) All DC-DC converter and charging circuitry is disabled when the backup regulator is turned on, but all other functions remain active. Activate BACKUP manually or by serial command, or set it to trigger automatically via LBO. OV4 OV3 OV2 OV1 OV0 0 0 0 0 0 1.8 0 0 0 0 1 1.9 0 0 0 1 0 2.0 0 0 0 1 1 2.1 0 0 1 0 0 2.2 0 0 1 0 1 2.3 0 0 1 1 0 2.4 0 0 1 1 1 2.5 0 1 0 0 0 2.6 0 1 0 0 1 2.7 0 1 0 1 0 2.8 0 1 0 1 1 2.9 0 1 1 0 0 3.0 0 1 1 0 1 3.1 0 1 1 1 0 3.2 0 1 1 1 1 3.3 1 0 0 0 0 3.4 Serial Interface 1 0 0 0 1 3.5 1 0 0 1 0 3.6 1 0 0 1 1 3.7 1 0 1 0 0 3.8 1 0 1 0 1 3.9 1 0 1 1 0 4.0 1 0 1 1 1 4.1 1 1 0 0 0 4.2 The MAX769 has an SPI-compatible serial interface. The serial-interface lines are Chip Select (CS), Serial Clock (SCL), Serial Data In (SDI), and Serial Data Out (SDO). Serial input data is arranged in 8-bit bytes. Most bytes contain a 3-bit address pointer (R2, R1, R0) along with 5 bits of input data (D4–D0). For common operations such as selecting Run or Coast Mode, activating REG2 or REG3, or turning on DR1 or DR2, only the 000 (R2, R1, R0) address register needs to be written. The serial input data format for all MAX769 operations is outlined in Tables 1, 2, and 3. 1 1 0 0 1 4.3 1 1 0 1 0 4.4 1 1 0 1 1 4.5 1 1 1 0 0 4.6 1 1 1 0 1 4.7 1 1 1 1 0 4.8 1 1 1 1 1 4.9 Automatic Backup Setting the LBO_Sets_BACKUP serial bit (Table 1) programs the IC so that when LBO goes low, the backup regulator automatically turns on without instructions from the microprocessor (µP). When the LBO_Sets_BACKUP bit is 0, the backup regulator is turned on only by setting the BACKUP bit. The BACKUP bit also overrides the LBO_Sets_BACKUP bit. Figure 3 shows the logic for this function. If the main battery is depleted and the NiCd battery is drained during backup, RSO goes low while the backup regulator is supplying OUT (if RSI is used to monitor OUT or REG1). When RSO falls, the serial registers reset to their POR states (with the DC-DC converter on in Coast Mode and the backup regulator off, see Tables 1, 2, and 3). This prevents the IC from getting hung up with the DC-DC converter off when a new main battery is inserted. This sequence is required because if the MAX769 did not default to “DC-DC converter on” when coming out of reset, the µP (still reset by RSO) would not be able to provide the device with serial instructions to turn on. 15mA_CHG TO CHARGER CONTROL 1mA_CHG LBO LBO_SETS_BACKUP TO BACKUP REGULATOR BACKUP Figure 3. Logic for Charger Control and BACKUP and for LBO_Sets_BACKUP Serial Input Bits ______________________________________________________________________________________ 13 MAX769 Table 5. VOUT Output Voltage MAX769 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC Serial data is clocked in and out MSB first. Input data is latched on the CLK rising edge, and output data is shifted out on the CLK falling edge. When CS goes low, DO immediately contains the MSB output bit (D7). D6 is not clocked out until the falling clock edge that follows the first rising clock edge after a Chip Select. See the timing diagrams in Figures 4 and 5. SPI writes and reads concurrently, so it may be necessary to perform dummy writes in order to read output data. Four output data bits (D7–D4, Table 4) are sent from SDO each time a serial operation occurs. When R2 = 0, R0 and R1 are address pointers. However, when R2 = 1, the 7 remaining bits (R1, R0 and D4–D0) become DAC programming bits. This violation of programming etiquette (R1 and R0 are sometimes address bits and other times data bits) allows the CH DAC to be loaded with only one write operation. Writing all zeros to the CH DAC turns it, the CH0, CH1, and CH2 comparators, and the NICD and BATT voltage-sensing resistors off to minimize current consumption. This reduces current drain from OUT by about 30µA. ••• CS tCSH tCSS tCH tCL tCSH SCLK ••• tDS tDH ••• DIN tDV tDO tTR ••• DOUT Figure 4. Detailed Serial-Interface Timing CS SCL SCO SDI D7 R2 D6 D5 D4 0 0 R1 R0 D4 D3 D2 0 0 D1 D0 Figure 5. CS, SCL, SDO, and SDI Serial Timing 14 ______________________________________________________________________________________ 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC from external logic (or a µP) powered from REG1, or by open-drain logic devices that are pulled up to REG1. Component Selection The MAX769 requires minimal design calculation and is optimized for the component values shown in Figure 2. However, some flexibility in component selection is still allowed, as described in the following text. A list of suitable components is provided in Table 6. Inductor L1 is nominally 68µH, but values from 47µH to 100µH should be satisfactory. The inductor current rating should be 300mA or more if full output current (80mA) is needed. If less output current is required, the inductor current rating can be reduced proportionally but should never be less than 150mA. Inductor resistance should be minimized for best efficiency, but since the MAX769 N-channel switch resistance is typically 0.9Ω, efficiency does not improve significantly for coil resistances below 0.4Ω. Filter capacitors C1–C4 should be low-ESR types (tantalum or ceramic) for lowest ripple and best noise rejection. The values shown in Figure 2 are optimized for each output’s rated current. Lower required output current allows smaller capacitance values. Resistors at the LBI and RSIN inputs set the voltage at which the LBO and RSO outputs trigger. The voltage threshold for both LBI and RSI is 0.6V. The resistors required to set a desired trip voltage, (Figure 2) VTRIP, are calculated by: R1 = R2[(VTRIP(LBO) / 0.6) - 1] R3 = R4[(VTRIP(LBO) / 0.6) - 1] To minimize battery drain, use large values for R2 and R4 (>100kΩ) in the above equations; 470kΩ is a good starting value. See the Low-Noise Analog Supply (REG2) section for information on selecting ROFS. Since LBO and RSO are open-drain outputs, pull-up resistors are usually required. Normally these will be pulled up to REG1. 100kΩ is recommended as a compromise between response time and current drain, although other values can be used. Since LBI and RSO are high (open circuit) during normal operation, current normally does not flow in the pull-up resistors until a low-battery or reset event occurs. Logic Levels Note that since the MAX769’s internal logic is powered from REG1, the input logic levels at the digital inputs (DR2IN, RUN, SYNC, CS, and SDI) as well as the logic output level of SDO are governed by the voltage at REG1. Logic-high inputs at these pins should not exceed VREG1. Digital inputs should either be driven Board Layout and Noise Reduction The MAX769 makes every effort in its internal design to minimize noise and EMI. Nevertheless, prudent layout practices are still suggested for best performance. Recommendations are as follows: 1) Keep trace lengths at L1, LX1, and LX2, as well as at PGND, as short and wide as possible. Since LX1 and LX2 toggle between VBATT and VOUT at a fast rate, minimizing the trace length serves to reduce excess PC board area that might act as an antenna. 2) Place the filter capacitors at OUT, REG1, REG2, and REG3 as close to their respective pins as possible (no more than 0.5mm away). 3) Consider using an inductor at L1. A shielded inductor at L1 will minimize radiated noise, but may not be essential. Toroids will also exhibit EMI performance similar to that of shielded coils. 4) Keep the power components at the uppermost part of the IC to minimize coupling to other parts of the circuit. The LX1, LX2, OUT, and PGND pins are located at the uppermost part of the IC to facilitate PC board layout. Other pins in this area are digital and are not affected by close proximity to switching nodes. 5) Use a separate short, wide ground trace for PGND and the ground side of the BATT and OUT filter capacitors. Tie this trace to the ground plane. Table 6. External Components SUPPLIER PART NO. COMMENTS INDUCTORS (68µH) Coilcraft DT1608C-223, DT1608C-683 0.58Ω, 3.18mm high, shielded Murata LQH4N680K 1.9Ω, 2.6mm high, low current, low cost CD54-680 0.46Ω, 4.5mm high CDR74B-680 0.33Ω, 4.5mm high, shielded CD73-680 0.33Ω, 3.5mm high AVX TPS series Tantalum Marcon THCR series Ceramic Sprague 595D series Tantalum TDK C3216 series Ceramic Sumida CAPACITORS STORAGE CAPACITOR (optional at NICD pin) Polystor A-10300 1.5 Farads ______________________________________________________________________________________ 15 MAX769 Applications Information 2 or 3-Cell, Step-Up/Down, Two-Way Pager System IC MAX769 Pin Configuration TOP VIEW LX1 1 28 LX2 SDI 2 27 CS SDO 3 26 BATT PGND 4 25 OUT SCL 5 LBO 6 24 REG1 MAX769 23 NICD RSO 7 22 R2IN REF 8 21 REG2 CH0 9 20 REG3 RSIN 10 19 DR2 LBI 11 18 DR2IN FILT 12 17 DR1 SYNC 13 16 DRGND 15 AGND OFS 14 QSOP QSOP.EPS ________________________________________________________Package Information 16 ______________________________________________________________________________________