19-3936; Rev 0; 2/06 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference The MAX5650/MAX5651/MAX5652 are available in a 32pin, 5mm x 5mm TQFN package and are guaranteed over the extended temperature range (-40°C to +85°C). For 14-bit, pin-compatible versions of the MAX5650/ MAX5651/MAX5652, refer to the MAX5653/MAX5654/ MAX5655 datasheet. ♦ 16-Bit Resolution ♦ Parallel 16-Bit or 2-Byte Double Buffered Interface ♦ Guaranteed Monotonic ♦ Maximum INL: ±4 LSB ♦ Fast 2µs Settling Time ♦ Clear Input (CLR) Sets Output to Zero-Scale or Midscale ♦ Integrated Precision Resistors for Bipolar Operation ♦ Integrated Precision Bandgap Reference: +4.096V (MAX5650) +2.048V (MAX5651) Ordering Information MAX5650ETJ 32 TQFN-EP* (5mm x 5mm) PACKAGE CODE T3255-4 MAX5651ETJ** 32 TQFN-EP* (5mm x 5mm) T3255-4 MAX5652ETJ** 32 TQFN-EP* (5mm x 5mm) T3255-4 PART Note: All devices specified over the -40°C to +85°C temperature range. *EP = Exposed paddle. Connect to AGND or leave unconnected. **Future product—contact factory for availability. Functional Diagram For 12-bit, pin-compatible versions of the MAX5650/ MAX5651/MAX5652, refer to the MAX5656/MAX5657/ MAX5658 datasheet. Applications Automatic Test Equipment Process Control Digital Calibration Actuator Control Servo Loops Waveform Generators Motor Control Selector Guide PART SUPPLY VOLTAGE (V) REFERENCE (V) INL (LSB, max) MAX5650ETJ +4.75 to +5.25 Internal, +4.096 ±4 MAX5651ETJ +2.7 to +5.25 Internal, +2.048 — MAX5652ETJ +2.7 to +5.25 External — PIN-PACKAGE REF INA D15 BANDGAP REFERENCE (MAX5650/ MAX5651 ONLY) 8-BIT MSB INPUT REGISTER D8 16-BIT DAC REGISTER R MTAP R D7 INB 8-BIT LSB INPUT REGISTER 16-BIT DAC OUT D0 GND CSMSB WR MAX5650 MAX5651 MAX5652 CSLSB LDAC POWER-ON RESET CLR Pin Configuration appears at end of data sheet. AVDD DVDD DGND MID/ZERO AGND ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5650/MAX5651/MAX5652 Features General Description The MAX5650/MAX5651/MAX5652 parallel-input, voltage-output, 16-bit, digital-to-analog converters (DACs) provide monotonic 16-bit output voltage over the full extended operating temperature range. The MAX5650/ MAX5651 include an internal precision low drift (10ppm/°C) bandgap voltage reference, while the MAX5652 requires an external reference. The MAX5650 operates from a +5V single supply and has a +4.096V internal reference. The MAX5651 operates from either a +3V or +5V single supply and has a +2.048V internal reference. The MAX5652 operates from either a +3V or +5V single supply and accepts an input reference voltage between +2V and AV DD . TheMAX5650/MAX5651/ MAX5652 parallel inputs are double buffered and configurable as a single 16-bit wide input or a 2-byte input. The MAX5650/MAX5651/MAX5652 unbuffered DAC voltage output ranges from 0 to VREF. The MAX5650/MAX5651/MAX5652 feature an active-low hardware clear input (CLR) that clears the registers and the output to zero-scale (0000 hex) or midscale (8000 hex), depending on the state of the MID/ZERO input. These devices include matched scaling resistors for use with a precision external op amp (such as the MAX400) to generate a bipolar output-voltage swing. MAX5650/MAX5651/MAX5652 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference ABSOLUTE MAXIMUM RATINGS AVDD to DVDD……………………………………………...........±6V AVDD to AGND, GND…………………………...…… -0.3V to +6V DVDD to DGND…..…………………………………… -0.3V to +6V DGND to GND……………………………………… -0.3V to +0.3V DGND, GND to AGND…………………………….. -0.3V to +0.3V D0–D15, CSLSB, CSMSB, WR, LDAC, CLR, MID/ZERO, to DGND…………………………………-0.3V to (DVDD + 0.3V) REF to AGND……………………………….-0.3V to (AVDD + 0.3V) OUT, MTAP, INA to AGND, GND...........................-0.3V to AVDD INB to AGND ..……………………………………………-6V to +6V INB to MTAP………………………………………………-6V to +6V Maximum Current into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 32-Pin TQFN (derate 20.8mW/°C above +70°C)….2758.6mW Operating Temperature Range …………………..-40°C to +85°C Storage Temperature Range…………………….-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX5650 (AVDD = DVDD = +4.75V to +5.25V, AGND = DGND = GND = 0V, VREF = internal, RL = ∞, CL = 10pF, CREF = 1µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE—ANALOG SECTION Resolution N Differential Nonlinearity DNL Integral Nonlinearity Zero-Code Offset Error Zero-Code Temperature Coefficient Gain Error LSB INL ±4 LSB ZSE ±80 µV ±10 ppmFS/ °C LSB ZSTC Guaranteed monotonic Bits ±1 ±0.5 (Note 2) ±0.05 (Note 3) Gain-Error Temperature Coefficient DAC Output Resistance 16 ROUT Bipolar Resistor Ratio (Note 2) ±0.1 (Note 4) 6.2 kΩ 1 Ω/Ω RINB / RINA Bipolar Resistor Ratio Error ppm/°C ±0.05 Bipolar Resistor Ratio Temperature Coefficient Bipolar Resistor Value % (Note 2) ±0.5 ppm/°C RINB and RINA (Note 4) 12.4 kΩ VOLTAGE REFERENCE (RREF = 10kΩ, CREF(MIN) = 1µF) Voltage Reference VREF TA = +25°C 4.081 4.106 Reference Voltage Temperature Coefficient TCVREF (Note 2) 10 Reference Load Regulation VOUT / IOUT 0 ≤ IOUT ≤ VREF / 10kΩ 0.1 Short-Circuit Current Reference Load IREF 2 0.6 PSRR 4 AVDD = DVDD = 4.75V to 5.25V (FS code) _______________________________________________________________________________________ µV/µA mA 400 Settle to 0.5 LSB V ppm/°C 6 Reference Power-Up Time Power-Supply Rejection Ratio 4.111 µA ms 0.5 mV/V 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference MAX5650/MAX5651/MAX5652 ELECTRICAL CHARACTERISTICS—MAX5650 (continued) (AVDD = DVDD = +4.75V to +5.25V, AGND = DGND = GND = 0V, VREF = internal, RL = ∞, CL = 10pF, CREF = 1µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE—ANALOG SECTION Output Settling Time 7F60H to 80A0H or 80A0H to 7F60H to 0.5 LSB 2 µs DAC Glitch Impulse Major carry transition 10 nV·s Digital Feedthrough Code = 0000 hex; CSLSB = CSMSB = DVDD, D0–D15 transition from 0 to DVDD 3 nV·s DYNAMIC PERFORMANCE—VOLTAGE REFERENCE SECTION Noise Voltage (Note 6) VREF Glitch Impulse Frequency = 0.1Hz to 10Hz 15 µVP-P Frequency = 10Hz to 1kHz 12 µVRMS For zero-scale to full-scale or full-scale to zero-scale transition 10 nV·s STATIC PERFORMANCE—DIGITAL INPUTS Input High Voltage VIH (Note 8) Input Low Voltage VIL (Note 8) Input Current IIN Input Capacitance CIN 2.4 V 0.8 ±1 5 V µA pF POWER SUPPLY Analog Supply Range Digital Supply Range Positive Supply Current AVDD 4.75 5.25 V DVDD AVDD 0.3 AVDD + 0.3 V 2 mA IAVDD + IDVDD (Note 9) All digital inputs at DVDD or 0V, AVDD = DVDD TIMING CHARACTERISTICS (Figure 4) CSMSB and CSLSB Pulse Width tCS 40 ns WR Pulse Width tWR 40 ns CSMSB or CSLSB to WR Setup Time tCWS 0 ns CSMSB or CSLSB to WR Hold Time tCWH 0 ns Data Valid to WR Setup Time tDWS 40 ns Data Valid to WR Hold Time tDWH 0 ns LDAC Pulse Width tLDAC 40 ns tCLR 40 ns CLR Pulse Width Note 1: 100% production tested at TA = +25°C and TA = +85°C. Guaranteed by design at TA = -40°C. Note 2: Temperature coefficient is determined by the box method in which the maximum change over the temperature range is divided by ∆T. Note 3: Gain error is measured at the full-scale code and is calculated with respect to the reference voltage (REF). Note 4: Resistor tolerance is typically ±20%. Note 5: Guaranteed by design, not production tested. Note 6: Noise is measured at the reference output. Note 7: Min/max range guaranteed by gain-error test. Operation outside min/max limits results in degraded performance. Note 8: The devices draw higher supply current when the digital inputs are driven between (DVDD - 0.5V) and (DGND + 0.5V). See Digital Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics. Note 9: For optimal performance AVDD = DVDD. _______________________________________________________________________________________ 3 Typical Operating Characteristics (AVDD = DVDD = +5V, AGND = DGND = GND = 0V, RL = ∞, CL = 10pF, CREF = 1µF for the MAX5650/MAX5651, TA = +25°C, unless otherwise noted.) -0.5 15 10 5 -INL -15 10 35 60 -15 REFERENCE VOLTAGE vs. TEMPERATURE (MAX5650) 35 60 85 -40 -15 10 35 60 TEMPERATURE (°C) REFERENCE-VOLTAGE NOISE (MAX5650) TOTAL SUPPLY CURRENT vs. TEMPERATURE (MAX5650) MAX5650 toc04 f = 0.1Hz TO 10Hz 4.098 10µV/div 4.097 4.096 85 1.2 1.1 SUPPLY CURRENT (mA) REFERENCE VOLTAGE (V) 4.099 10 TEMPERATURE (°C) TEMPERATURE (°C) 4.100 MAX5650 toc03 -3 -40 85 MAX5650 toc05 -40 -1 -2 0 -1.0 0 MAX5650 toc06 0 1 FS GAIN ERROR (LSB) 20 OFFSET ERROR (µV) 0.5 2 MAX5650 toc02 +INL INL (LSB) 25 MAX5650 toc01 1.0 GAIN ERROR vs. TEMPERATURE (MAX5650) ZERO-CODE OFFSET ERROR vs. TEMPERATURE (MAX5650) INTEGRAL NONLINEARITY vs. TEMPERATURE 1.0 0.9 0.8 CODE = FFFF 4.095 0.7 -40 -15 10 35 60 85 REFERENCE VOLTAGE vs. DIGITAL INPUT CODE 4.09697 4.09696 4.09695 4.09694 10000 20000 30000 40000 50000 60000 70000 CODE 4 60 85 FULL-SCALE STEP RESPONSE (MAX5650) D1 5V/div 0 1 0.1 0.01 0.001 VOUT 2V/div 0 ALL DIGITAL INPUTS CONNECTED TOGETHER 0.0001 0 35 MAX5650 toc08 10 AVDD = DVDD = 5.25V 4.09693 10 MAX5650 toc09 100 DIGITAL SUPPLY CURRENT (mA) 4.09698 -15 TEMPERATURE (°C) DIGITAL SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE (MAX5650) MAX5650 toc07 4.09699 -40 1s/div TEMPERATURE (°C) REFERENCE VOLTAGE (V) MAX5650/MAX5651/MAX5652 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference CODE FFFF TO OOOO STEP 0.00001 0 1 2 3 4 5 6 400ns/div DIGITAL INPUT VOLTAGE (V) _______________________________________________________________________________________ 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference FULL-SCALE STEP RESPONSE (MAX5650) MAJOR-CARRY GLITCH MAX5650 toc10 MAJOR-CARRY GLITCH MAX5650 toc11 D1 5V/div 0V VOUT 2V/div MAX5650 toc12 D15 5V/div D15 5V/div 0V 0V VOUT 20mV/div VOUT 20mV/div 0V 0V 0V CODE 0000 TO FFFF STEP CODE 7FFF TO 8000 STEP CODE 8000 TO 7FFF STEP 400ns/div 1µs/div 1µs/div DIGITAL FEEDTHROUGH (MAX5650) SMALL-SIGNAL SETTLING TIME SMALL-SIGNAL SETTLING TIME MAX5650 toc15 MAX5650 toc13 MAX5650 toc14 D1 5V/div VOUT 10mV/div VOUT 10mV/div 0V 0V VOUT 20mV/div CODE 0000 TO 00A2 STEP CODE 00A2 TO 0000 STEP 400ns/div 1µs/div 400ns/div REFERENCE FEEDTHROUGH (MAX5652) REFERENCE BANDWIDTH (MAX5652) 0 VREF = 3.5V + 0.5VP-P -15 -20 -25 -30 CODE = 0000h -20 VOUT/VREF (dB) -5 -10 VOUT/VREF (dB) 0 MAX5650 toc16 5 MAX5650 toc17 FS TRANSITION -40 -60 -80 -35 -40 CODE = FFFFh -45 VREF = 3.5V + 0.5VP-P -100 -120 -50 10 100 1000 FREQUENCY (kHz) 10,000 0.01 0.1 1 10 100 1000 10,000 FREQUENCY (kHz) _______________________________________________________________________________________ 5 MAX5650/MAX5651/MAX5652 Typical Operating Characteristics (continued) (AVDD = DVDD = +5V, AGND = DGND = GND = 0V, RL = ∞, CL = 10pF, CREF = 1µF for the MAX5650/MAX5651, TA = +25°C, unless otherwise noted.) 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference MAX5650/MAX5651/MAX5652 Pin Description PIN NAME 1 D0 Data Input Bit 0 (LSB) 2 D1 Data Input Bit 1 3 D2 Data Input Bit 2 4 D3 Data Input Bit 3 5 D4 Data Input Bit 4 6 D5 Data Input Bit 5 7 D6 Data Input Bit 6 8 D7 Data Input Bit 7 9 D8 Data Input Bit 8 10 D9 Data Input Bit 9 11 D10 Data Input Bit 10 12 D11 Data Input Bit 11 13 D12 Data Input Bit 12 14 D13 Data Input Bit 13 15 D14 Data Input Bit 14 16 D15 Data Input Bit 15 (MSB) 17 DGND Digital Ground 18 DVDD Digital Supply. Bypass DVDD to DGND with a 0.1µF capacitor as close to the device as possible. 19 CSLSB Lower 8-Bit Active-Low Chip Select. When CSLSB is driven low the data inputs D0–D7 are loaded to the input and DAC registers depending on the state of WR and LDAC (see Table 1). 20 CSMSB Upper 8-Bit Active-Low Chip Select. When CSMSB is driven low the data inputs D8–D15 are loaded to the input and DAC registers depending on the state of WR and LDAC (see Table 1). 21 WR Active-Low Write Input. While chip select (CSLSB and/or CSMSB) is low, the data on D0–D7 and/or D8–D15 is presented to the input register when WR is low. A rising edge on WR then latches the data to the input register (see Table 1). Hold WR low to make the input register transparent. 22 LDAC Asynchronous Active-Low Load DAC Input. When LDAC is low, the data in the input register is presented to the DAC register. A rising edge on LDAC then latches the data to the DAC register (see Table 1). Hold WR and LDAC low to perform a write-through operation. 23 CLR 24 MID/ZERO 25 MTAP Asynchronous Active-Low Clear DAC Input. Pull CLR low to clear the input and DAC registers and set the DAC output to midscale (8000 hex), if MID/ZERO is high, or zero scale (0000 hex), if MID/ZERO is low. Midscale/Zero-Scale Clear Output Value Select. Pull MID/ZERO low for zero-scale clear output (0000 hex) or high for midscale clear output (8000 hex). Internal Scaling Resistor Midpoint Tap. Connect to the inverting input of an external op amp. INB Internal Resistor Input B. Free end of internal resistor (RINB). Connect to the output of an external output buffer for bipolar operation. 27 AVDD Analog Supply. Bypass AVDD to AGND with a 0.1µF capacitor as close to the device as possible. 28 AGND 29 INA 26 6 FUNCTION Analog Ground Internal Resistor Input A. Free end of internal resistor (RINA). Connect to REF for bipolar operation. _______________________________________________________________________________________ 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference PIN NAME 30 REF FUNCTION Internal Reference Voltage Output (MAX5650/MAX5651). Connect a 1µF < CREF < 47µF between REF and AGND as close to the device as possible. The internal reference voltage of the MAX5650 is +4.096V and +2.048V for the MAX5651. External Reference Voltage Input (MAX5652). Connect to an external voltage reference source between +2V and AVDD. 31 OUT 32 GND — EP DAC Output DAC Ground Exposed paddle. Connect to AGND or leave unconnected. Typical Application Circuits DVDD D15 BANDGAP REFERENCE (MAX5650/ MAX5651 ONLY) 8-BIT MSB INPUT REGISTER 8-BIT BUS REF AVDD D8 16-BIT DAC REGISTER INA R MTAP R D7 INB 8-BIT LSB INPUT REGISTER µC 16-BIT DAC OUT 0 TO VREF D0 CSMSB GND CONTROL LINES WR MAX5650 MAX5651 MAX5652 CSLSB LDAC POWER-ON RESET CLR DGND MID/ZERO AGND Figure 1. Typical Application Circuit for µC Byte-Wide Interface _______________________________________________________________________________________ 7 MAX5650/MAX5651/MAX5652 Pin Description (continued) 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference MAX5650/MAX5651/MAX5652 Typical Application Circuits (continued) ACTUATOR DRIVE CIRCUIT DVDD AVDD REF INA R D15 BANDGAP REFERENCE (MAX5650/ MAX5651 ONLY) 8-BIT MSB INPUT REGISTER 16-BIT BUS D8 16-BIT DAC REGISTER R INB MTAP +12V D7 8-BIT LSB INPUT REGISTER ASIC 16-BIT DAC 0 TO VREF OUT 0 TO VREF D0 CSMSB GND CONTROL LINES WR MAX5650 MAX5651 MAX5652 CSLSB LDAC POWER-ON RESET CLR DGND MID/ZERO AGND Figure 2. Typical Application Circuit for Unipolar Configuration 8 _______________________________________________________________________________________ 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference AVDD DVDD REF INA R D15 BANDGAP REFERENCE (MAX5650/ MAX5651 ONLY) 8-BIT MSB INPUT REGISTER 8-BIT BUS D8 16-BIT DAC REGISTER R INB MTAP +5V D7 8-BIT LSB INPUT REGISTER FPGA 16-BIT DAC +/- VREF OUT -5V 0 TO VREF D0 CSMSB GND CONTROL LINES WR MAX5650 MAX5651 MAX5652 CSLSB LDAC POWER-ON RESET CLR DGND MID/ZERO AGND Figure 3. Typical Application Circuit for Bipolar Configuration _______________________________________________________________________________________ 9 MAX5650/MAX5651/MAX5652 Typical Application Circuits (continued) MAX5650/MAX5651/MAX5652 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference tCS CSLSB tCS CSMSB tCWH tCWS tCWS tWR tCWH tWR WR tLDAC LDAC tDWS tDWS tDWH D0–D15 VALID DATA tDWH VALID DATA Figure 4. Timing Diagram Detailed Description The MAX5650/MAX5651/MAX5652 parallel-input, voltage-output DACs offer full 16-bit performance with less than ±4 LSB integral nonlinearity and less than ±1 LSB differential nonlinearity, ensuring monotonic performance over the full operating temperature range. The DAC is composed of an inverted R2R ladder with the unbuffered output available directly at OUT, allowing 16-bit performance from the reference voltage to the DAC ground (GND). The parallel inputs are doublebuffered and configurable as a single 16-bit wide input or a 2-byte input. The MAX5650/MAX5651 include internal precision low-drift (10ppm/°C) bandgap voltage references of +4.096V and +2.048V, respectively. The MAX5652 accepts an external reference voltage between +2V and AVDD. The MAX5650 operates with a supply voltage range of +4.75V to +5.25V, while the MAX5651/MAX5652 operate with a supply voltage range of +2.7V to +5.25V. Voltage Reference The MAX5650/MAX5651 provide a 10ppm/°C (typ) internal precision bandgap voltage reference with a load regulation specification of less than 0.6µV/µA (maximum) over the entire operating temperature range. The reference voltage for the MAX5650 is +4.096V, while the reference voltage for the MAX5651 is +2.048V. Connect a capacitor ranging between 1µF and 47µF from REF to ground as close to the device as possible. Use a low-ESR ceramic capacitor such as the GRM series from Murata. 10 The MAX5652 accepts an external reference with a voltage range extending from +2V to AVDD. The output voltage of the DAC is determined as follows: VOUT = VREF x N / 65536 where N is the numeric value of the DAC’s binary input code (0 to 65535) and VREF is the reference voltage. At a full-scale transition, the instantaneous charge demand from the external reference is about 550pC. For a reference with a 1µF load capacitor, the charge demand causes an instantaneous reference voltage drop of 550µV. A 10µF load capacitor causes a voltage drop of 55µV. This glitch recovers in a time inversely proportional to the bandwidth of the voltage reference, which should be sufficiently fast to recover before the next DAC transition to avoid accumulation of the glitch energy and a shift in the average reference voltage. For a +4.096V reference with 1µF bypass capacitor, it takes three time constants to recover to 0.5 LSB accuracy. Therefore, a 96kHz bandwidth reference recovers in 5µs while a 960kHz bandwidth reference recovers in 0.5µs. For further voltage-reference selection assistance, visit www.maxim-ic.com/appnotes.cfm/appnote_number/754. ______________________________________________________________________________________ 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference while CSLSB is low, latches the lower byte (D0–D7) into the input register. The rising edge of WR, while CSMSB is low, latches the upper byte (D8–D15) into the input register. The sequence of loading the MSB and LSB does not matter. See Figure 1 for byte-wide interface circuit. The DAC register is transparent when LDAC is low. The rising edge of LDAC latches data into the DAC register. The DAC’s analog output reflects the data held in the DAC register. Both the input register and DAC register are transparent when CSLSB, CSMSB, WR, and LDAC are driven low. In this case, any change at D0–D15 appears at the output instantly. See Table 1 for the truth table. Table 1. Truth Table CLR CSLSB CSMSB WR LDAC 1 0 1 0 1 Loads least significant byte into the input register. DAC output remains unchanged. 1 0 1 1 Latches least significant byte into the input register. DAC output remains unchanged. 1 1 0 1 Loads most significant byte into the input register. DAC output remains unchanged. 1 1 0 1 Latches most significant byte into the input register. DAC output remains unchanged. 1 X X 1 0 Transfers data from the input register into the DAC register and updates the DAC output. 1 X X 1 1 1 0 0 0 Most significant input and DAC registers are transparent. DAC output updates immediately with the most significant input data and least significant input register data. 1 X X 1 1 No operation. 1 0 0 0 0 Both most significant and least significant input registers and DAC register are transparent. DAC output updates immediately with the most significant and least significant input data. 1 0 0 0 1 Loads all 16 bits into the input register. DAC output remains unchanged. 1 0 1 0 0 Least significant input and DAC registers are transparent. DAC output updates immediately with the least significant input data and most significant register data. 1 1 1 X 0 Transfers data held in the input register to the DAC register and updates the DAC output. 1 1 1 X 1 No operation. 0 X X X X Sets the input and DAC registers and DAC output to midscale (if MID/ZERO = 1) or zero-scale (if MID/ZERO = 0). 0 FUNCTION Latches data from the input register into the DAC register. DAC output remains unchanged. 0 = Low state. 1 = High state. X = Don’t care. = Rising edge. ______________________________________________________________________________________ 11 MAX5650/MAX5651/MAX5652 Digital Interface The MAX5650/MAX5651/MAX5652 accept a single 16bit wide input or an 8 plus 8-bit wide input. Data latches or transfers directly to the DAC depending on the state of the control inputs CLR, CSLSB, CSMSB, LDAC, MID/ZERO, and WR. All digital inputs are compatible with both TTL and CMOS logic. The double buffered input consists of an input register and a DAC register (see the Functional Diagram). Data is loaded into the input register using CSLSB, CSMSB, and WR. The input register is transparent when WR and CSLSB and/or CSMSB are low. The rising edge of WR, MAX5650/MAX5651/MAX5652 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference The MAX5650/MAX5651/MAX5652 provide an asynchronous clear input (CLR). Asserting CLR resets the input and DAC registers and DAC output to midscale if the MID/ZERO input is high and to zero scale when MID/ZERO is low. Power-On Reset (POR) The MAX5650/MAX5651/MAX5652 provide an internal POR circuit. On power-up, the input and DAC registers and DAC output are set to 0000 hex if MID/ZERO is low or 8000 hex if MID/ZERO is high. Wait 10µs after power-up before pulling CSMSB or CSLSB low. Internal Scaling Resistors The MAX5650/MAX5651/MAX5652 include two internal scaling resistors of 12.4kΩ (typ) each that are matched to 0.05% or better. Use these resistors with a precision external op amp to generate a bipolar output swing (see the Bipolar Operation section). The free ends of these resistors are accessible at INA and INB while the midpoint is accessible at MTAP. Connect INB to the output of the op amp and INA to REF for bipolar operation. Negative voltages are only allowed at INB (see the Absolute Maximum Ratings section). Applications Information Unipolar Buffered/Unbuffered Operation Unbuffered operation reduces power consumption as well as the offset error contributed by the external output buffer (see Figure 1). The R2R DAC output is available directly at OUT, allowing 16-bit performance from +VREF to GND without degradation at zero scale. The typical application circuit (Figure 2) shows the MAX5650/MAX5651/MAX5652 configured for a buffered unipolar voltage-output operation. Use the integrated precision matched resisters for op-amp input impedance matching. Table 2 shows digital codes and corresponding output voltages for unipolar buffered or unbuffered operation. Bipolar Operation For bipolar voltage-output operation, use an external op amp (such as the MAX400) in conjunction with the internal scaling resistors (see Figure 3). Connect the free end of the internal resistor (INB) to the output of the external op amp and the free end of the other resistor (INA) to REF. Connect the midpoint of the resistors to the inverting input of the op amp. Connect the output of the DAC to the noninverting input of the external op amp. The resulting transfer function is as follows: where D is the decimal value of the DACs binary input code. Table 3 shows digital codes and corresponding output voltages for bipolar operation. Table 2. Unipolar Code Table DAC LATCH CONTENTS MSB ANALOG OUTPUT, VOUT LSB 1111 1111 1111 1111 VREF x (65,535 / 65,536) 1000 0000 0000 0000 VREF x (32,768 / 65,536) = 0.5VREF 0000 0000 0000 0001 VREF x (1 / 65,536) 0000 0000 0000 0000 0V Table 3. Bipolar Code Table DAC LATCH CONTENTS MSB ANALOG OUTPUT, VOUT LSB 1111 1111 1111 1111 +VREF x (32,767 / 32,768) 1000 0000 0000 0001 +VREF x (1 / 32,768) 1000 0000 0000 0000 0V 0111 1111 1111 1111 -VREF (1 / 32,768) 0000 0000 0000 0000 -VREF x (32,768 / 32,768) = -VREF Power-Supply and Layout Considerations Careful PC board layout is important for optimal system performance. Wire-wrapped boards, sockets, and breadboards are not recommended. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Connect AGND and DGND to the highest quality ground available. Star-connect all ground return paths back to AGND or use a multilayer board with a low-inductance ground plane. Connect analog and digital ground planes together at a lowimpedance power-supply source. For the MAX5652, keep the trace between the reference source to the reference input short and low impedance. Bypass each supply with a 0.1µF capacitor as close as possible to the IC for optimal 16-bit performance. Chip Information PROCESS: BiCMOS VOUT = VREF [(2D / 65, 536) − 1] 12 ______________________________________________________________________________________ 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference MID/ZERO CLR LDAC WR CSMSB CSLSB DVDD DGND TOP VIEW 24 23 22 21 20 19 18 17 MTAP 25 16 D15 INB 26 15 D14 14 D13 13 D12 12 D11 REF 30 11 D10 OUT 31 10 D9 9 D8 AVDD 27 MAX5650 MAX5651 MAX5652 AGND 28 INA 29 6 7 8 D7 D2 5 D6 D1 4 D5 3 D4 2 D3 1 D0 GND 32 + MAX5650/MAX5651/MAX5652 Pin Configuration TQFN 5mm x 5mm ______________________________________________________________________________________ 13 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) QFN THIN.EPS MAX5650/MAX5651/MAX5652 16-Bit, Parallel-Input, Voltage-Output DACs with Internal Reference D2 D b CL 0.10 M C A B D2/2 D/2 k L MARKING AAAAA E/2 E2/2 CL (NE-1) X e E DETAIL A PIN # 1 I.D. E2 PIN # 1 I.D. 0.35x45° e/2 e (ND-1) X e DETAIL B e L1 L CL CL L L e e 0.10 C A C 0.08 C A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm -DRAWING NOT TO SCALE- COMMON DIMENSIONS A1 A3 b D E e 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 1 2 EXPOSED PAD VARIATIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A I 21-0140 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.40 BSC. 0.50 BSC. - 0.25 - 0.25 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 - 0.30 0.40 0.50 16 40 N 20 28 32 ND 4 10 5 7 8 4 10 5 7 8 NE WHHB ----WHHC WHHD-1 WHHD-2 JEDEC k L L1 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. PKG. CODES T1655-2 T1655-3 T1655N-1 T2055-3 D2 L E2 exceptions MIN. NOM. MAX. MIN. NOM. MAX. ±0.15 3.00 3.00 3.00 3.00 3.00 T2055-4 T2055-5 3.15 T2855-3 3.15 T2855-4 2.60 T2855-5 2.60 3.15 T2855-6 T2855-7 2.60 T2855-8 3.15 T2855N-1 3.15 T3255-3 3.00 T3255-4 3.00 T3255-5 3.00 T3255N-1 3.00 T4055-1 3.20 3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 2.60 3.15 2.60 3.15 3.15 33.00 33.00 3.00 3.00 3.20 3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40 ** ** ** ** ** 0.40 ** ** ** ** ** 0.40 ** ** ** ** ** ** DOWN BONDS ALLOWED YES NO NO YES NO YES YES YES NO NO YES YES NO YES NO YES NO YES ** SEE COMMON DIMENSIONS TABLE 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05. PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm 21-0140 -DRAWING NOT TO SCALE- I 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Inc.