19-3855; Rev 1; 4/06 2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN The MAX13202E/MAX13204E/MAX13206E/MAX13208E low-capacitance ±30kV ESD-protection diode arrays are designed to protect sensitive electronics attached to communication lines. Each channel consists of a pair of diodes that steer ESD current pulses to VCC or GND. The MAX13202E/MAX13204E/MAX13206E/MAX13208E protect against ESD pulses up to ±15kV Human Body Model (HBM) and ±30kV Air-Gap Discharge, as specified in IEC 61000-4-2. These devices have a 6pF oncapacitance per channel, making them ideal for use on high-speed data I/O interfaces. The MAX13204E is a quad-ESD structure designed for Ethernet and FireWire® applications. The MAX13202E/ MAX13206E/MAX13208E are 2-channel, 6-channel, and 8-channel devices. They are designed for cellphone connectors and SVGA video connections. These devices are available in 6-, 8-, and 10-pin µDFN packages and are specified over the -40°C to +125°C automotive operating temperature range. Applications USB Ethernet USB 2.0 Video PDAs Cell Phones FireWire GND N.C. I/O2 Pin Configurations 6 5 4 Features ♦ High-Speed Data-Line ESD Protection ±15kV—Human Body Model ±30kV—IEC 61000-4-2, Air-Gap Discharge ♦ Tiny µDFN Package MAX13202E (1mm x 1.5mm) MAX13204E (2mm x 2mm) MAX13206E (2mm x 2mm) MAX13208E (2mm x 2mm) ♦ Low 6pF Input Capacitance ♦ Low 1nA (max) Leakage Current ♦ +0.9V to +16V Supply Voltage Range Ordering Information PART PINPKG PROTECTED I/O PORTS TOP MARK PKG CODE MAX13202EALT+ 6 µDFN 2 BV L611-1 MAX13204EALT+ 6 µDFN 4 AAO L622-1 MAX13206EALA+ 8 µDFN 6 AAL L822-1 MAX13208EALB+ 10 µDFN 8 AAD L1022-1 Note: All devices are specified over the -40°C to +125°C automotive operating temperature range. +Denotes lead-free package Typical Operating Circuit VCC VCC MAX13202E 0.1µF + 3 I/O1 VCC 2 N.C. 0.1µF 1 µDFN (1mm x 1.5mm) PROTECTED CIRCUIT I/0 I/0_ MAX13202E MAX13204E MAX13206E MAX13208E Pin Configurations continued at end of data sheet. FireWire is a registered trademark of Apple Computer, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX13202E/MAX13204E/MAX13206E/MAX13208E General Description MAX13202E/MAX13204E/MAX13206E/MAX13208E 2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN ABSOLUTE MAXIMUM RATINGS VCC to GND ............................................................-0.3V to +18V I/O_ to GND ................................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70°C) 6-Pin, 1mm x 1.5mm µDFN (derate 2.1mW/°C above +70°C)................................................................168mW 6-Pin, 2mm x 2mm µDFN (derate 4.5mW/°C above +70°C)................................................................358mW 8-Pin, 2mm x 2mm µDFN (derate 4.8mW/°C above +70°C)................................................................381mW 10-Pin, 2mm x 2mm µDFN (derate 5.0mW/°C above +70°C)................................................................403mW Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature .....................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +5V ±5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25°C.) (Note 1) PARAMETER SYMBOL Supply Voltage VCC Supply Current ICC Diode Forward Voltage VF Channel Clamp Voltage (Note 2) VC CONDITIONS MIN TYP MAX 0.9 1 IF = 10mA 0.65 TA = +25°C, ±15kV, Human Body Model, IF = 10A Positive transients TA = +25°C, ±14kV, Contact Discharge (IEC 61000-4-2), IF = 42A Positive transients TA = +25°C, ±30kV, Air-Gap Discharge (IEC 61000-4-2), IF = 90A Positive transients UNITS 16.0 V 100 nA 0.95 V VCC + 25 Negative transients -25 VCC + 80 V Negative transients -80 VCC + 120 Negative transients -120 Channel Leakage Current (Note 3) TA = -40°C to +50°C -1 TA = -40°C to +125°C -1 Channel Input Capacitance VCC = 5V, bias of VCC/2, f = 1MHz (Note 3) 6 +1 nA +1 µA 7 pF ESD PROTECTION Human Body Model IEC 61000-4-2 Contact Discharge IEC 61000-4-2 Air-Gap Discharge ±15 MAX13204E/MAX13206E/MAX13208E ±14 MAX13202E ±12 ±30 Note 1: Limits over temperature are guaranteed by design, not production tested. Note 2: Idealized clamp voltages (L1 = L2 = L3 = 0) (Figure 1); see the Applications Information section for more information. Note 3: Guaranteed by design. Not production tested. 2 _______________________________________________________________________________________ kV kV kV 2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN CLAMP VOLTAGE vs. DC CURRENT 1 VCC = 12V 0.1 1.0 I/O TO VCC 0.9 I/O TO GND 0.8 MAX13204E//6E/8E toc03 MAX13204E//6E/8E toc02 10 1 VCC = 12V VCC = 5V 0.1 VCC = 3.3V 0.01 0.01 VCC = 3.3V 0.001 0.001 0.7 30 -40 -25 -10 5 20 35 50 65 80 95 110 125 50 70 90 110 130 DC CURRENT (mA) TEMPERATURE (°C) TEMPERATURE (°C) INPUT CAPACITANCE vs. INPUT VOLTAGE INPUT CAPACITANCE vs. INPUT VOLTAGE 13 12 11 VCC = 3.3V 9 8 VCC = 5.0V 7 10 VCC = 12V 9 INPUT CAPACITANCE (pF) MAX13204E/6E/8E toc04 14 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 150 8 7 MAX13204E/6E/8E toc05 VCC = 5V INPUT CAPCITANCE (pF) SUPPLY CURRENT (nA) 10 1.1 CLAMP VOLTAGE (V) MAX13204E//6E/8E toc01 100 I/O LEAKAGE CURRENT vs. TEMPERATURE I/O LEAKAGE CURRENT (nA) SUPPLY CURRENT vs. TEMPERATURE 6 5 4 3 6 2 5 1 0 4 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 10 11 12 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Pin Description PIN MAX13202E MAX13204E MAX13206E MAX13208E 1 1 1 1 VCC Power-Supply Input. Bypass VCC to GND with a 0.1µF ceramic capacitor. Place the capacitor as close as possible to the device. 2, 5 — — — N.C. No Connection. Not internally connected. 3, 4 2–5 2–7 2–9 I/O_ ESD-Protected Channel 6 6 8 10 GND Ground NAME FUNCTION _______________________________________________________________________________________ 3 MAX13202E/MAX13204E/MAX13206E/MAX13208E Typical Operating Characteristics (VCC = +5V, TA = +25°C, unless otherwise noted.) MAX13202E/MAX13204E/MAX13206E/MAX13208E 2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN Detailed Description The MAX13202E/MAX13204E/MAX13206E/MAX13208E are diode arrays designed to protect sensitive electronics against damage resulting from ESD conditions or transient voltages. The low input capacitance makes these devices ideal for high-speed data lines. The MAX13202E/MAX13204E/MAX13206E/MAX13208E protect two, four, six, and eight channels, respectively. d(IESD ) d(IESD ) VC = − VF(D2) + L1 x + L3 x dt dt where IESD is the ESD current pulse. POSITIVE SUPPLY RAIL The MAX13202E/MAX13204E/MAX13206E/MAX13208E are designed to work in conjunction with a device’s intrinsic ESD protection. The MAX13202E/MAX13204E/ MAX13206E/MAX13208E limit the excursion of the ESD event to below ±25V peak voltage when subjected to the Human Body Model waveform. When subjected to the IEC 61000-4-2 waveform, the peak voltage is limited to ±80V (Contact Discharge) and ±120V (Air-Gap Discharge). The device that is being protected by the MAX13202E/MAX13204E/ MAX13206E/MAX13208E must be able to withstand these peak voltages plus any additional voltage generated by the parasitic board. L2 D1 L1 I/O_ PROTECTED LINE D2 L3 Applications Information GROUND RAIL Design Considerations Maximum protection against ESD damage results from proper board layout (see the Layout Recommendations section and Figure 2). A good layout reduces the parasitic series inductance on the ground line, supply line, and protected signal lines. The MAX13202E/MAX13204E/MAX13206E/MAX13208E ESD diodes clamp the voltage on the protected lines during an ESD event and shunt the current to GND or VCC. In an ideal circuit, the clamping voltage, VC, is defined as the forward voltage drop, VF, of the protection diode plus any supply voltage present on the cathode. For positive ESD pulses: VC = VCC + VF For negative ESD pulses: VC = -VF In reality, the effect of the parasitic series inductance on the lines must also be considered (Figure 1). For positive ESD pulses: Figure 1. Parasitic Series Inductance L2 VCC L1 PROTECTED LINE NEGATIVE ESD CURRENT PULSE PATH TO GROUND D1 VC I/O_ D2 GND L3 d(IESD ) d(IESD ) VC = VCC + VF(D1) + L1 x + L2 x dt dt Figure 2. Layout Considerations For negative ESD pulses: 4 _______________________________________________________________________________________ PROTECTED CIRCUIT 2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN A low-ESR 0.1µF capacitor must be used between VCC and GND. This bypass capacitor absorbs the charge transferred by a +14kV (MAX13204E/MAX13206E/ MAX13208E) and ±12kV (MAX13202E) IEC61000-4-2 Contact Discharge ESD event. Ideally, the supply rail (VCC) would absorb the charge caused by a positive ESD strike without changing its regulated value. In reality, all power supplies have an effective output impedance on their positive rails. If a power supply’s effective output impedance is 1Ω, then by using V = I × R, the clamping voltage of VC increases by the equation V C = I ESD x R OUT . An ±8kV IEC 61000-4-2 ESD event generates a current spike of 24A, so the clamping voltage increases by VC = 24A × 1Ω, or VC = 24V. Again, a poor layout without proper bypassing increases the clamping voltage. A ceramic chip capacitor mounted as close to the MAX13202E/ MAX13204E/MAX13206E/MAX13208E V CC pin is the best choice for this application. A bypass capacitor should also be placed as close to the protected device as possible. ±30kV ESD Protection ESD protection can be tested in various ways. The MAX13202E/MAX13204E/MAX13206E/MAX13208E are characterized for protection to the following limits: • ±15kV using the Human Body Model • ±14kV (MAX13204E/MAX13206E/MAX13208E) and ±12kV (MAX13202E) using the Contact Discharge method specified in IEC 61000-4-2 • ±30kV using the IEC 61000-4-2 Air-Gap Discharge method ESD Test Conditions ESD performance depends on a number of conditions. Contact Maxim for a reliability report that documents test setup, methodology, and results. RC 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 100pF RD 1.5kΩ DISCHARGE RESISTANCE DEVICE UNDER TEST STORAGE CAPACITOR Figure 4. Human Body ESD Test Model I 100% 90% IPEAK IP 100% 90% Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) AMPERES 36.8% 10% 0 10% tR = 0.7ns to 1ns t 30ns 60ns Figure 3. IEC 61000-4-2 ESD Generator Current Waveform 0 tRL TIME tDL CURRENT WAVEFORM Figure 5. Human Body Model Current Waveform _______________________________________________________________________________________ 5 MAX13202E/MAX13204E/MAX13206E/MAX13208E During an ESD event, the current pulse rises from zero to peak value in nanoseconds (Figure 3). For example, in a ±15kV IEC-61000-4-2 Air-Gap Discharge ESD event, the pulse current rises to approximately 45A in 1ns (di/dt = 45 x 109). An inductance of only 10nH adds an additional 450V to the clamp voltage. An inductance of 10nH represents approximately 0.5in of board trace. Regardless of the device’s specified diode clamp voltage, a poor layout with parasitic inductance significantly increases the effective clamp voltage at the protected signal line. MAX13202E/MAX13204E/MAX13206E/MAX13208E 2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN Layout Recommendations RC 50Ω to 100Ω CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 150pF RD 330Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 6. IEC 61000-4-2 ESD Test Model Human Body Model Figure 4 shows the Human Body Model, and Figure 5 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the device through a 1.5kΩ resistor. IEC 61000-4-2 The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. The MAX13202E/ MAX13204E/MAX13206E/MAX13208E help users design equipment that meets Level 4 of IEC 61000-4-2. The main difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2. Because series resistance is lower in the IEC 61000-4-2 ESD test model (Figure 6), the ESD-withstand voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 3 shows the current waveform for the ±8kV IEC 61000-4-2 Level 4 ESD Contact Discharge test. The Air-Gap Discharge test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized. 6 Proper circuit-board layout is critical to suppress ESDinduced line transients. The MAX13202E/MAX13204E/ MAX13206E/MAX13208E clamp to ±120V; however, with improper layout, the voltage spike at the device is much higher. A lead inductance of 10nH with a 45A current spike at a dv/dt of 1ns results in an ADDITIONAL 450V spike on the protected line. It is essential that the layout of the PC board follows these guidelines: 1) Minimize trace length between the connector or input terminal, I/O_, and the protected signal line. 2) Use separate planes for power and ground to reduce parasitic inductance and to reduce the impedance to the power rails for shunted ESD current. 3) Ensure short ESD transient return paths to GND and VCC. 4) Minimize conductive power and ground loops. 5) Do not place critical signals near the edge of the PC board. 6) Bypass VCC to GND with a low-ESR ceramic capacitor as close to VCC and ground terminals as possible. 7) Bypass the supply of the protected device to GND with a low-ESR ceramic capacitor as close to the supply pin as possible. Chip Information PROCESS: BiCMOS _______________________________________________________________________________________ 2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN MAX13202E MAX13204E MAX13206E VCC VCC VCC I/O1 I/O2 I/O4 I/O3 I/O2 I/O1 GND I/O1 I/O2 I/O4 I/O3 GND I/O5 I/O6 GND MAX13208E VCC I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 GND GND I/O4 I/O3 GND I/O6 I/O5 I/O4 GND I/O8 I/O7 I/O6 I/O5 Pin Configurations (continued) 6 5 4 8 7 6 5 10 9 8 7 6 MAX13204E MAX13208E MAX13206E 1 8 µDFN (2mm x 2mm) 2 3 4 5 I/O4 4 I/O3 VCC 3 VCC I/O2 6 µDFN (2mm x 2mm) 2 I/O3 1 I/O2 3 I/O1 2 I/O1 VCC 1 I/O2 + + I/O1 + 10 µDFN (2mm x 2mm) _______________________________________________________________________________________ 7 MAX13202E/MAX13204E/MAX13206E/MAX13208E Functional Diagrams Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 6L UDFN.EPS MAX13202E/MAX13204E/MAX13206E/MAX13208E 2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN Translation Table for Calendar Year Code TABLE1 Calendar Year Legend: 2005 2006 Marked with bar 2007 2008 2009 2010 2011 2012 2013 42-47 48-51 52-05 2014 Blank space - no bar required Translation Table for Payweek Binary Coding TABLE2 Payweek Legend: 06-11 12-17 Marked with bar 18-23 24-29 30-35 36-41 Blank space - no bar required TITLE: PACKAGE OUTLINE, 6L uDFN, 1.5x1.0x0.8mm APPROVAL -DRAWING NOT TO SCALE- 8 DOCUMENT CONTROL NO. 21-0147 REV. D 2 2 _______________________________________________________________________________________ 2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN XXXX XXXX XXXX b e 6, 8, 10L UDFN.EPS A D N SOLDER MASK COVERAGE E PIN 1 0.10x45∞ L L1 1 SAMPLE MARKING PIN 1 INDEX AREA A A (N/2 -1) x e) 7 CL CL b L A A2 L e EVEN TERMINAL A1 e ODD TERMINAL PACKAGE OUTLINE, 6, 8, 10L uDFN, 2x2x0.80 mm 21-0164 -DRAWING NOT TO SCALE- A 1 2 COMMON DIMENSIONS SYMBOL MIN. NOM. A 0.70 0.75 0.80 A1 0.15 0.20 0.25 A2 0.020 0.025 D 1.95 2.00 E 1.95 2.00 L 0.30 0.40 L1 MAX. 0.035 - 2.05 2.05 0.50 0.10 REF. PACKAGE VARIATIONS PKG. CODE N e b (N/2 -1) x e L622-1 6 0.65 BSC 0.30±0.05 1.30 REF. L822-1 8 0.50 BSC 0.25±0.05 1.50 REF. L1022-1 10 0.40 BSC 0.20±0.03 1.60 REF. PACKAGE OUTLINE, 6, 8, 10L uDFN, 2x2x0.80 mm 21-0164 -DRAWING NOT TO SCALE- A 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX13202E/MAX13204E/MAX13206E/MAX13208E Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)