ETC PCT1789N

PRELIMINARY
!
PCT1789N DATA SHEET
303DL FEATURES
303DL FUNCTIONAL DESCRIPTION
Complete DAA includes:
The 303DL chip set is an integrated direct digital access
arrangement (DAA) chip set that provides a digital, lowcost, solid-state interface to a telephone line. Available in
two 16-pin small outline packages, it eliminates the need
for an analog front end (AFE), an isolation transformer,
relays, opto-isolators, and a 2- to 4-wire hybrid. The
303DL dramatically reduces the number of discrete
components and cost required to achieve compliance
with FCC Part 68. The 303DL interfaces directly to
standard modem DSPs and supports all U.S. FCC and
JATE out-of-band noise requirements.
• 3.3 V to 5 V digital/analog power supplies
• JATE filter option
• 86 dB dynamic range TX/RX paths
• Daisy-chaining for up to eight devices
• Integrated ring detector
• 2000 V isolation
• Support for Caller ID
• Low-profile SOIC packages
• Direct interface to DSPs
• Integrated modem CODEC
• Compliant with FCC Part 68
• Low-power standby mode
• Proprietary ISOcap™ technology
• Optional IIR digital filter
303DL APPLICATIONS
• Modems
303DL Chip Set
• Phone line interface systems
303DL FUNCTIONAL BLOCK DIAGRAM
MCLK
SCLK
FSYNC
SDI
SDO
FC/RGDT
RGDT/FSD
OFHK
MODE
RESET
Out
Hybrid
Digital
In
TX
RX
RX
Interface
Isolation
Isolation
DC
Interface
Interface
Termination
Ring Detect
Control
Interface
Off-hook
VREG
DCT
REXT
IGND
RNG1
RNG2
QB
QE
AOUT
PCT303D
PCT303L
PRELIMINARY
PC-TEL, Inc.
2
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
303DL APPLICATION CIRCUITS
303DL APPLICATION CIRCUITS
Typical Application
3.3 or
+5V
R3*
C10
C3
C4
NC
R1
To
DSP
VD VA
MCLK
SCLK
FSYNC
C1A
SDI
SDO
FC/RGDT
Q1
TX
RV1
R5
+
PCT303L
Z1
RV1 M0 GND
R6
C9
C6
C12
R9
R22
Tip
RNG1
RNG2
QB
QE
IGND TSTB
Ring
FB2
R2
REXT
RGDT/FSD
OFHK
RESET
AOUT
D4
C5
RX
HYBD
D2
Q2
C13
C1
VREG
Tip
D3
R21
R4
PCT303D
To ASIC or
Controller
D1
TSTA DCT
C1B
FB1
C11
C7
Ring
C8 R10
R23
Q3
C2
NC
NOTE: R3 is not required when VD = 3.3 V and the charge pump is enabled (CPE = 1). If JATE support is not required,
R21, C12, and C13 may be removed and R4 should be changed to a 604 Ω, 1/4 W, ±1%.
Figure 2 Typical Application Circuit
Table 1 Typical Application Component Values
Symbol
Value
Symbol
Value
C1
150 pF, 2 kV, X7R, ±20%
R4,R21
301 Ω, 1/4 W, ±1%
C2, C4
1000 pF, 2 kV, X7R, ±20%
R5, R6
36 kΩ, 1/10 W ±5%
C3, C6, C10
0.1 µF, 16 V, ±20%
R9, R10
2 kΩ, 1/4 W ±5%
C5
1 µF, 16 V, Tant., ±20%
R22,R23
20 kΩ, 1/10 W ±5%
C7,C8,C9
15 nF, 250 V, X7R, ±20%
Z1
Zener diode, 18 V
C11
39 nF, 16 V, X7R, ±20%
Q1, Q3
Motorola MMBTA42LT1
C12
2.7 nF, 16 V, ±20%
Q2
Motorola MMBTA92LT1
C13
0.1 µF, 35 V, Tantalum, ±20%
RV1
Sidactor, 270V, 100A
R1
51 Ω, 1/2 W ±5%
D1–D4
1N4004
R2
15 Ω, 1/4 W ±5%
FB1, FB2
Ferrite Bead
R3
10 Ω, 1/10 W, ±5%
PRELIMINARY
PC-TEL, Inc.
6
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
303DL APPLICATION CIRCUITS
Analog Output
Figure 3 illustrates an optional application circuit to support the analog output capability of the 303DL chip set for
call progress monitoring purposes. The AOUT level can be set to 0, –6, –12, and mute for both transmit and receive
paths through the ATM/ARM bits in register 6.
+5V
C3
C2
R3
3
AOUT
C6
C1
R1
2
6
+
5
–
U1
C4
C5
+
4
R2
Speaker
Figure 3 Optional Connection to AOUT For a Call Progress Speaker
‘
Table 2 Optional Connection Component Values
Symbol
Value
C1
2200 pF, 16 V, ±20%
C2, C3, C5
0.1 µF, 16 V, ±20%
C4
100 µF, 16 V, Elec. ±20%
C6
820 pF, 16 V, ±20%
R1
10 kΩ, 1/10 W, ±5%
R2
10 Ω, 1/10 W, ±5%
R3
47 kΩ, 1/10 W, ±5%
U1
LM386
PRELIMINARY
PC-TEL, Inc.
7
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
PRELIMINARY
303DL PINOUTS
!
303DL PINOUTS
PCT303D Pinout
MCLK
FSYNC
SCLK
VD
SDO
SDI
FC/RGDT
RESET
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OFHK
RGDT/FSD
M0
VA
GND
C1A
M1
AOUT
Figure 5 PCT303D 16-Pin SOIC
PCT303L Pinout
TSTA
TSTB
IGND
C1B
RNG1
RNG2
QB
QE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TX
NC
RX
REXT
DCT
HYBD
NC
VREG
Figure 6 PCT303L 16-Pin SOIC
PRELIMINARY
PC-TEL, Inc.
13
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
303DL PIN DESCRIPTIONS
303DL PIN DESCRIPTIONS
PCT303D Pin Description
Table 5 PCT303D Pin Description
Name
Number
I/O Description
Serial Interface
MCLK
1
I
Master clock input. High speed master clock input. Generally supplied by the system
crystal clock or modem/DSP.
SCLK
3
O
Serial port bit clock output. Controls the serial data on SDOUT and latches the data on
SDIN.
SDI
6
I
Serial port data in. Serial communication and control data that is generated by the
modem/DSP and presented as an input to the PCT303D.
SDO
5
O
Serial port data out. Serial communication data that is provided by the PCT303D to the
Modem/DSP.
FSYNC
2
I/O Frame sync output/input (master/slave). Data framing signal that is used to indicate
the start and stop of a communication data frame.
FC/
RGDT
7
O
Secondary transfer request input/Ring detect. As FC, this pin is an optional signal to
instruct the PCT303D that control data is being requested in a secondary frame. When
daisy-chain is enabled, this pin becomes the ring detect output, RGDT, which produces an active-low, half-wave rectified version of the ring signal.
Control Interface
RGDT/
FSD
15
O
Ring detect/Delayed frame sync. As RGDT, this pin is an output signal that indicates
the status of a ring signal, which produces an active-low, half-wave rectified version of
the ring signal. When daisy-chain is enabled, this signal becomes a delayed frame
sync, FSD, to drive a slave device.
OFHK
16
I
Off hook. Input control signal that provides a termination across tip and ring for line
seizing and pulse dialing, active-low. This pin must be enabled by the OHE bit of register 5.
RESET
8
I
Reset input. An active-low input that is used to reset all control registers to a defined,
initialized state. Also used to bring the 303DL out of sleep mode.
M0
14
Mode select 0. One of two mode select pins that is used to select the operation of the
serial port/DSP interface.
M1
10
Mode select 1. The second of two mode select pins that is used to select the operation
of the serial port/DSP interface.
Miscellaneous Signals
AOUT
9
C1A
11
O
Analog speaker output. Provides an analog output signal for driving a call progress
speaker.
Isolation capacitor 1A. Connects to one side of the isolation capacitor C1.
Power Signals
VD
4
Digital supply voltage. Provides the digital supply voltage to the PCT303D. Nominally
either 5V or 3.3V.
VA
13
Analog supply voltage. Provides the analog supply voltage for the PCT303D. Nominally either 5V. If the internal charge pump is used, this pin should simply be bypassed
with a 0.1 µF capacitor.
GND
12
Ground. Connects to the system digital ground.
PRELIMINARY
PC-TEL, Inc.
14
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
303DL PIN DESCRIPTIONS
PCT303L Pin Descriptions
Table 6 PCT303L Pin Descriptions
Name
Number
I/O Description
Line Interface
TX
16
O
Transmit output. Provides the output, through an AC termination impedance, to the
telephone network.
RX
14
I
Receive input. Serves as the receive side input from the telephone network.
DCT
12
DC termination. Provides DC termination to the telephone network.
REXT
13
External resistor. Connects to an external resistor.
RNG1
5
I
Ring 1 input. Connects through a capacitor to the “Tip” lead of the telephone line. Provides the ring and caller ID signals to the 303DL.
RNG2
6
I
Ring 2 input. Connects through a capacitor to the “Ring” lead of the telephone line. Provides the ring and caller ID signals to the 303DL.
QB
7
Transistor base. Connects to the base of the hookswitch transistor.
QE
8
Transistor emitter. Connects to the emitter of the hookswitch transistor.
HYBD
11
O
Hybrid node output. Balancing capacitor connection used for JATE out-of-band noise
support.
Isolation
C1B
4
Isolation capacitor 1B. Connects to one side of isolation capacitor C1.
IGND
3
Isolated ground. Connects to ground on the line-side interface. Also connects to capacitor C2.
Miscellaneous Signals
VREG
9
Voltage regulator. Connects to an external capacitor to provide bypassing for an internal voltage regulator.
TSTA
1
I
Test input A. Allows access to test modes, which are reserved for factory use. This pin
has an internal pull-up and should be left as a no-connect for normal operation.
TSTB
2
I
Test input B. Allows access to test modes, which are reserved for factory use. This pin
has an internal pull-up and should be left as a no-connect for normal operation.
NC
10
No connection. This is an unused pin and must be left floating.
PRELIMINARY
PC-TEL, Inc.
15
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
303DL FUNCTIONAL DESCRIPTION
303DL FUNCTIONAL DESCRIPTION
PCT303L can occur until this bit is cleared. The clock
generator must be programmed to an acceptable
sample rate prior to clearing the PDL bit.
The 303DL is an integrated chip-set that provides a lowcost, isolated, silicon-based interface to the telephone
line. The 303DL saves cost and board area by
eliminating the need for a modem AFE or serial CODEC.
It also eliminates the need for an isolation transformer,
relays, opto-isolators, and a 2- to 4-wire hybrid. The
303DL solution requires only a few low-cost, discrete
components to achieve full compliance with FCC
Part 68 and JATE out-of-band noise requirements. See
Figure 2 on page 6 for a typical application circuit.
Off-Hook
The communication system generates an off-hook
command by applying logic 0 to the OFHK pin or writing
a logic 1 to bit 0 of control register 5. The OFHK pin must
be enabled by setting bit 1 (OHE) of register 5. With
OFHK at logic 0, the system is in an off-hook state. This
state is used to seize the line for incoming/outgoing calls
and can also be used for pulse dialing. With OFHK at
logic 1, negligible DC current flows through the
hookswitch. When a logic 0 is applied to the OFHK pin,
the hookswitch transistor pair, Q1 & Q2, turn on. The net
effect of the off-hook signal is the application of a
termination impedance across tip and ring and the flow
of DC loop current. The termination impedance has both
an AC and DC component.
The 303DL North America/Japan DAA offers a number
of new features. These include operation from a single
3.3 V power supply, JATE (Japan) filter option, finer
resolution for both transmit and receive levels on AOUT
(call progress output), daisy-chaining for up to eight
devices, and an optional IIR filter. Table 7 summarizes
the new 303DL features.
Table 7 New 303DL Features
Category
303DL
Daisy-Chaining
Up to 8 Devices
Optional IIR Filter
Yes
Receive Gain
0, +3, +6, +9, +12 dB
Transmit Attenuation
0, –3, –6 –9, –12 dB
VA
3.3 V a or 5 V
VD
3.3 V or 5 V
JATE Support
Yes
AOUT Levels (dB)
0, –6, –12, mute
a.
The AC termination impedance is a 604-ohm resistor,
which is connected to the TX pin. The DC termination is
a 51-ohm resistor, which is connected to the DCT pin.
When executing an off-hook sequence, the 303DL
requires 4620/Fs clock cycles to complete the off-hook
and provide phone line data on the serial link. This
includes the 12/Fs filter group delay. If necessary, for
the shortest delay, a higher Fs may be established prior
to executing the off-hook, such as an Fs of 10.286 kHz.
Ring Detect
The 3.3 V supply is internally generated by
an on-chip charge pump.
The ring signal enters the 303DL through low value
capacitors connected to Tip and Ring. RGDT is a
clipped, half-wave rectified version of the ringing
waveform. See Figure 7 on page 17 for a timing diagram
of the RGDT pin.
Isolation Barrier
The 303DL achieves an isolation barrier through a lowcost, high-voltage capacitor in conjunction with Silicon
Laboratories’ proprietary ISOcap signal processing
techniques. These techniques eliminate any signal
degradation due to capacitor mismatches, common
mode interference, or noise coupling. As shown in
Figure 2 on page 6, the C1, C2, and C4 capacitors
isolate the PCT303D (DSP side) from the PCT303L (line
side). All transmit, receive, control, and caller ID data
are communicated through this barrier.
The integrated ring detect of the 303DL allows the
device to present the ring signal to the DSP, through the
serial port, with no additional signaling required. The
signal sent to the DSP is a clipped version of the original
ring signal. In addition, the 303DL passes through the
caller ID data unaltered.
The system can also detect an occurring ring by the
status of the RDT bit of register 5. This bit is a read-only
bit that is set when the line side device detects a ring
signal at RNG1 and RNG2. The RDT bit clears when the
system either goes off-hook or 4.5 to 9 seconds after the
last ring is detected.
The ISOcap inter-chip communication is disabled by
default. To enable it, the PDL bit in register 6 must be
cleared. No communication between the PCT303D and
PRELIMINARY
PC-TEL, Inc.
16
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
303DL FUNCTIONAL DESCRIPTION
If Caller ID is supported in the system, the designer can
enable the 303DL to pass this information to the SDO
output. Following the completion of the first ring, the
system should set the ONHM bit (register 5, bit 3). This
bit must be cleared at the conclusion of the receipt of the
caller ID data and prior to the next ring burst.
Table 8 Serial Modes
The PCT303D can support a wake-up-on-ring function
using the RGDT signal. Refer to “Power Management”
on page 22 for more details.
M1
M0
Description
0
0
0
FSYNC frames data
1
0
1
FSYNC pulse starts data frame
2
1
0
Slave mode
3
1
1
Reserved
The digital interface consists of a single, synchronous
serial link which communicates both telephony and
control data.
Improved JATE Support
The HYBD pin connects to a node on the internal hybrid
cancellation circuit providing a pin for balancing
capacitor C12. C13 adds the necessary transmit out-ofband filtering required to meet JATE out-of-band noise
specifications. The addition of C13 alters the transmit
path frequency response which must be balanced with
capacitor C12 to obtain maximum hybrid cancellation.
In serial mode 0 or 1, the PCT303D operates as a
master, where the master clock (MCLK) is an input, the
serial data clock (SCLK) is an output, and the frame
sync signal, (FSYNC) is an output. The MCLK frequency
and the value of the sample rate control registers 7, 8, 9
and 10 determine the sample rate (Fs). The serial port
clock, SCLK, runs at 256 bits per frame, where the frame
rate is equivalent to the sample rate. Refer to “Clock
Generation Subsystem” on page 19 for more details on
programming sample rates.
Digital Interface
The 303DL has two serial interface modes that support
most standard modem DSPs. The M0 and M1 mode
pins select the interface mode. The key difference
between these two serial modes is the operation of the
FSYNC signal. Table 8 summarizes the serial mode
definitions.
First Ring
0.2–3.0 seconds
Mode
The 303DL transfers 16-bit or 15-bit telephony data in
the primary timeslot and 16-bit control data in the
secondary timeslot. Figure 8 and Figure 9 on page 18
show the relative timing of the serial frames. Primary
frames occur at the frame rate and are always present.
To minimize overhead in the external DSP, secondary
frames are present only when requested.
0.5–1.5 Sec.
RNG1/
RNG2
> 0.2 Sec.
DATA
RGDT
SDO
DIGITIZED LINE SIGNAL
Figure 7 Ring Detect Timing
PRELIMINARY
PC-TEL, Inc.
17
1789N0DOCDAT01A-0399
PRELIMINARY
!
303DL FUNCTIONAL DESCRIPTION
Communications Frame 1 (CF1)
Secondary
Primary
FSYNC
FC
PCT1789N DATA SHEET
(CF2)
Primary
0
D15–D1
D0=1 (Software FC Bit)
SDI
XMT Data
Secondary
Data
XMT Data
SDO
RCV Data
Secondary
Data
RCV Data
16 SCLKS
128 SCLKs
256 SCLKs
Figure 8 Software FC Secondary Request
Communications Frame 1 (CF1)
FSYNC
Secondary
Primary
(CF2)
Primary
FC 0
D15–D0
SDI
XMT Data
Secondary
Data
XMT Data
SDO
RCV Data
Secondary
Data
RCV Data
16 SCLKS
128 SCLKs
256 SCLKs
Figure 9 Hardware FC Secondary Request
Two methods exist for transferring control information in
the secondary frame. The default power-up mode uses
the LSB of the 16-bit transmit (TX) data word as a flag to
request a secondary transfer. In this mode, only 15-bit
TX data is transferred, resulting in a loss of SNR but
allowing software control of the secondary frames. As
an alternative method, the FC pin can serve as a
hardware flag for requesting a secondary frame. The
external DSP can turn on the 16-bit TX mode by setting
PRELIMINARY
PC-TEL, Inc.
18
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
303DL FUNCTIONAL DESCRIPTION
the SB bit of register 1. In the 16-bit TX mode, the
hardware FC pin must be used to request secondary
transfers.
SDO signal. During a write cycle, the R/W bit is low and
the 5-bit address field contains the address of the
register to be written. The 8-bit data to be written
immediately follows the address on SDI. Only one
register can be read or written during each secondary
frame. See “303DL Control Registers” on page 43 for
the register addresses and functions.
Figure 10 and Figure 11 illustrate the secondary frame
read cycle and write cycle, respectively. During a read
cycle, the R/W bit is high and the 5-bit address field
contains the address of the register to be read. The
contents of the 8-bit control register are placed on the
FSYNC
(mode 0)
FSYNC
(mode 1)
D15 D14 D13 D12 D11 D10 D9
SDI
0
0
1
A
A
A
A
D8
D7
D0
A
D7
D6
D5 D4
D
D
D
D3
D2
D
D
D1 D0
R/W
SDO
D
D
D
Figure 10 Secondary Communication Data Format - Read Cycle
FSYNC
(mode 0)
FSYNC
(mode 1)
D15 D14 D13 D12 D11 D10 D9
SDI
0
0
0
A
A
A
A
D8 D7
A
D
D6
D5 D4
D
D
D
D3
D2
D
D
D1 D0
D
D
R/W
SDO
Figure 11 Secondary Communication Data Format - Write Cycle
Clock Generation Subsystem
In serial mode 2, the PCT303D operates as a slave
device, where the MCLK is an input, the SCLK is a no
connect, and the FSYNC is an input. In addition, the
RGDT/FSD pin operates as a delayed frame sync (FSD)
and the FC/RGDT pin operates as ring detect (RGDT).
Note that in this mode, FC operation is not supported.
For further details on operating the PCT303D as a slave
device, refer to “Multiple Device Support” on page 23.
The 303DL contains an on-chip clock generator. Using
a single MCLK input frequency, the 303DL can generate
all the desired standard modem sample rates, as well as
the common 11.025 kHz rate for audio playback.
The clock generator consists of two phase-locked loops
(PLL1 and PLL2) that achieve the desired sample
frequencies. Figure 12 on page 20 illustrates the clock
generator. The architecture of the dual PLL scheme
PRELIMINARY
PC-TEL, Inc.
19
1789N0DOCDAT01A-0399
PRELIMINARY
!
303DL FUNCTIONAL DESCRIPTION
allows for fast lock time on initial start-up, fast lock time
when changing modem sample rates, high noise
immunity, and the ability to change modem sample rates
with a single register write. A large number of MCLK
frequencies between 1 MHz and 60 MHz are supported.
÷N1
In serial mode 2, the PCT303D operates as a slave
device. The clock generator is configured (by default) to
set the SCLK output equal to the MCLK input. The net
effect is the clock generator multiplies the MCLK input
by 20. For further details of slave mode operation, refer
to “Multiple Device Support” on page 23.
CGM
FUP1
MCLK
PCT1789N DATA SHEET
FPLL1
P
FUP2
0
VCO1
D
÷25
8 bits
÷ N2
1
FPLL2
P
D
÷5
VCO2
1024Fs
4 bits
÷M1
÷M2
0
÷16
1
8 bits
4 bits
PLL1
CGM
PLL2
Figure 12 Clock Generation Subsystem
Programming the Clock Generator
Table 9 N2, M2 Values (CGM = 0, 1)
As noted in Figure 12, the clock generator must output a
clock equal to 1024*Fs, where Fs is the desired sample
rate. The 1024*Fs clock is determined through
programming of the following registers:
Fs (Hz)
N2
M2
7200
2
2
8000
9
10
Register 7—N1 divider, 8 bits.
8229
7
8
Register 8—M1 divider, 8 bits.
8400
6
7
9000
4
5
9600
3
4
10286
7
10
Register 9—N2/M2 dividers, 4 bits/4 bits.
Register 10—CGM, 1 bit.
When using the 303DL for modem applications, the
clock generator can be programmed to allow for a single
register write to change the modem sampling rate.
These standard sample rates are shown in Table 9. The
programming method is described below.
The main design consideration is the generation of a
base frequency, defined as the following:
F
F
F
⋅ M1
MCLK
= ---------------------------------- = 36.864MHz, CGM = 0
Base
N1
Base
F
⋅ M1 ⋅ 16
MCLK
= ---------------------------------------------- = 36.864MHz, CGM = 1
N1 ⋅ 25
N1 (register 7) and M1 (register 8) are 8-bit unsigned
values. FMCLK is the clock provided to the MCLK pin.
Table 10 lists several standard crystal oscillator rates
that could be supplied to MCLK. This list simply
represents a sample of MCLK frequency choices. Many
more are possible.
PRELIMINARY
PC-TEL, Inc.
20
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
303DL FUNCTIONAL DESCRIPTION
After the first PLL has been setup, the second PLL can
be programmed easily. The values for N2 and M2
(register 9) are shown in Table 9. N2 and M2 are 4-bit
unsigned values.
Table 10 MCLK Examples
MCLK
(MHz)
N1
M1
CGM
When programming the registers of the clock generator,
the order of register writes is important. For PLL1
updates, N1 (register 7) must always be written first,
immediately followed by a write to M1 (register 8). For
PLL2, the CGM bit must set as desired prior to writing
N2/M2 (register 9). Changes to CGM only take effect
when N2/M2 are written.
1.8432
1
20
0
4.0000
5
72
1
4.0960
1
9
0
5.0688
11
80
0
6.0000
5
48
1
6.1440
1
6
0
NOTE: The values shown in Table 9 and Table 10
satisfy the equations above. However, when
programming the registers for N1, M1, N2, and M2, the
value placed in these registers must be one less than
the value calculated from the equations. For example,
for CGM = 0 with a MCLK of 48.0 MHz, the values
placed in the N1 and M1 registers would be 7Ch and
5Fh, respectively. If CGM = 1, a non-zero value must be
programmed to register 9 in order for the 16/25 ratio to
take effect.
8.1920
32
225
1
9.2160
1
4
0
10.0000
25
144
1
10.3680
9
32
0
11.0592
3
10
0
12.2880
1
3
0
14.7456
2
5
0
16.0000
5
18
1
PLL Lock Times
18.4320
1
2
0
The 303DL changes sample rates very quickly.
However, lock time varies based on the programming of
the clock generator. The major factor contributing to PLL
lock time is the CGM bit. When the CGM bit is used (set
to one), PLL2 locks slower than when CGM is zero. The
following relationships describe the boundaries on PLL
locking time:
24.5760
32
75
1
25.8048
7
10
0
33.8688
147
160
0
44.2368
96
125
1
46.0800
5
4
0
47.9232
13
10
0
PLL1 lock time < 1 ms (CGM = 0,1)
48.0000
125
96
0
PLL2 lock time <100 µs (CGM = 0)
56.0000
35
36
1
PLL2 lock time <1 ms (CGM = 1)
60.0000
25
24
1
For modem designs, it is recommended that PLL1 be
programmed
during
initialization.
No
further
programming of PLL1 is necessary. The CGM bit and
PLL2 can be programmed for the desired initial sample
rate, typically 7200 Hz. All further sample rate changes
are then made by simply writing to register 9 to update
PLL2.
Setting Generic Sample Rates
The above clock generation description focuses on the
common modem sample rates. An application may
require a sample rate not listed in Table 9, such as the
common audio rate of 11.025 kHz. The restrictions and
equations above still apply; however, a more generic
relationship between MCLK and Fs (the desired sample
rate) is needed. The following equation describes this
relationship:
The final design consideration for the clock generator is
the update rate of PLL1. The following criteria must be
satisfied in order for the PLLs to remain stable:
?M1? ⋅ ?M2?
5 ⋅ 1024 ⋅ Fs
---------------------------------- = ratio • -------------------------------?N1? ⋅ ?N2?
?MCLK?
F UP1 = F MCLK ⁄ ( N1 ) ≥ 144kHz
Where FUP1 is shown in Figure 12 on page 20.
where Fs is the sample frequency, ratio is 1 for CGM=0
and 25/16 for CGM = 1, and all other symbols are shown
in Figure 12 on page 20.
PRELIMINARY
PC-TEL, Inc.
21
1789N0DOCDAT01A-0399
!
PRELIMINARY
PCT1789N DATA SHEET
303DL FUNCTIONAL DESCRIPTION
Knowing the MCLK frequency and desired sample rate
the values for the M1, N1, M2, N2 registers can be
determined. When determining these values, remember
to consider the range for each register as well as the
minimum update rate for the first PLL.
In summary, the power down/up sequence for sleep
mode is as follows:
1. Registers 7, 8, and 9 must have valid non-zero
values.
2. Set the PDN bit (register 6, bit 3) and clear the PDL
bit (register 6, bit 4).
The values determined for M1, N1, M2, and N2 must be
adjusted by minus one when determining the value
written to the respective registers. This is due to internal
logic, which adds one to the value stored in the register.
This addition allows the user to write a zero value in any
of the registers and the effective divide by is one. A
special case occurs when both M1 and N1 and/or M2
and N2 are programmed with a zero value. When Mx
and Nx are both zero, the corresponding PLLx is
bypassed. Note that if M2 and N2 are set to zero, the
ratio of 25/16 is eliminated and cannot be used in the
above equation. In this condition the CGM bit has no
effect.
3. MCLK may stay active or stop.
4. Restore MCLK before initiating the power-up
sequence.
5. Reset the 303DL using RESET pin (after MCLK is
present).
6. Program registers to desired settings.
The 303DL also supports an additional power-down
mode. When both the PDN (register 6, bit 3) and PDL
(register 6, bit 4) are set, the chip-set enters a complete
power-down mode and draws negligible current. Set the
PDL bit either before setting the PDN bit or at the same
time. In this mode, the RGDT pin does not function.
Normal operation may be restored using the same
process for taking the chip-set out of sleep mode.
Power Management
The 303DL supports four basic power management
operation modes. The modes are normal operation,
reset operation, sleep mode, and full power down mode.
The power management modes are controlled by the
PDN and PDL bits of register 6.
Analog Output
The 303DL supports an analog output (AOUT) for
driving the call progress speaker found with most of
today’s modems. AOUT is an analog signal that is
comprised of a mix of the transmit and receive signals.
The receive portion of this mixed signal has a 0 dB gain,
while the transmit signal has a gain of –20 dB.
On power up, or following a reset, the 303DL is in reset
operation. In this mode, the PDL bit is set, while the PDN
bit is cleared. The PCT303D is fully operational, except
for the ISOcap. No communication between the
PCT303D and PCT303L can occur during reset
operation. Note, any bits associated with the PCT303L
are not valid in this mode.
The AOUT level can be adjusted via the ATM and ARM
bits in control register 6. The transmit portion of the
AOUT signal can be set to –20 dB, –26 dB, –32 dB, or
mute. The receive portion of the AOUT signal can be set
to 0 dB, –6 dB, –12 dB, or mute. Figure 3 on page 7
illustrates a recommended application circuit. Note that
in the configuration shown, the LM386 provides a gain
of 26 dB. Additional gain adjustments may be made by
varying the voltage divider created by R1 and R3 of
Figure 3.
The most common mode of operation is the normal
operation. In this mode, the PDL and PDN bits are
cleared. The PCT303D is fully operational and the
ISOcap is communicating information between the
PCT303D and the PCT303L. Note that the clock
generator must be programmed to a valid sample rate
prior to entering this mode.
The 303DL supports a low-power sleep mode. This
mode supports the popular wake-up-on-ring feature of
many modems. The clock generator registers 7, 8, and
9 must be programmed with valid non-zero values prior
to enabling sleep mode. Then, the PDN bit must be set
and the PDL bit cleared. When the 303DL is in sleep
mode, the MCLK signal may be stopped or remain
active, but it must be active before waking up the 303DL.
The PCT303D is non-functional except for the ISOcap
and RGDT signal. To take the 303DL out of sleep mode,
pulse the reset pin (RESET) low.
On-Hook Line Monitor
The 303DL allows the user to detect line activity when
the device is in an on-hook state. When the system is
on-hook, the line data can be passed to the DSP across
the serial port while drawing a small amount of DC
current from the line. This feature is similar to the
passing of line information (such as Caller ID), while onhook, following a ring signal detection. To activate this
feature, set the ONHM bit in register 5.
PRELIMINARY
PC-TEL, Inc.
22
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
303DL FUNCTIONAL DESCRIPTION
Multiple Device Support
The on-hook line monitor can also be used to detect
whether a phone line is physically connected to the
PCT303L and associated circuitry. When the on-hook
line monitor is activated (if no line is connected), the
output of SDO moves towards a negative full scale value
(–32768). The value is guaranteed to be at least 89% of
negative full scale.
The 303DL supports the operation of up to 7 additional
devices on a single serial interface. Figure 17 on page
27 shows the typical connection of the 303DL and one
additional serial CODEC.
The 303DL must be the master in this configuration. The
secondary CODEC should be configured as a slave
device with SCLK and FSYNC as inputs. On power up,
the 303DL master is unaware of the additional CODEC
on the serial bus. The FC/RGDT pin is an input,
operating as the hardware control for secondary frames.
The RGDT/FSD pin is an output, operating as the active
low ring detection signal. It is recommended that the
master device be programmed for master/slave mode
prior to enabling the ISOcap, because a ring signal
causes a false transition to the slave device’s FSYNC.
If a line is present while in on-hook line monitor mode,
SDO has a near zero value. The designer must allow for
the group delay of the receive filter (5/Fs) before making
a decision.
Loop Current Monitor
When the system is in an off-hook state, the LCS bits of
register 12 indicate the approximate amount of DC loop
current that is flowing in the loop. The LCS is a 4-bit
value ranging from zero to fifteen. Each unit represents
approximately 6 mA of loop current from LCS codes
1-14. The typical LCS transfer function is shown in
Figure 13.
Register 14 provides the necessary control bits to
configure the 303DL for master/slave operation. Bit 0
(DCE) sets the 303DL in master/slave mode, also
referred to as daisy-chain mode. When the DCE bit is
set, the FC/RGDT pin becomes the ring detect output
and the RGDT/FSD pin becomes the delay frame sync
output.
15
Bits 7:5 (NSLV2:NSLV0) set the number of slaves to be
supported on the serial bus. For each slave, the 303DL
generates a FSYNC to the DSP. In daisy-chain mode,
the polarity of the ring signal can be controlled by bit 1
(RPOL). When RPOL = 1, the ring detect signal (now
output on the FC/RGDT pin) is active-high.
10
LCS
BIT
5
The 303DL supports the Texas Instruments
TLC320AC01 and the TLC320AD50 CODECs as well
as additional 303DLs. The type of slave CODEC(s) used
is set by bits 4:3 (SSEL1:SSEL0). These bits determine
the type of signalling used in the LSB of SDO. This
assists the DSP in isolating which data stream is the
master and which is the slave. If the LSB is used for
signalling, the master device has a unique setting
relative to the slave devices. The DSP can use this
information to determine which FSYNC marks the
beginning of a sequence of data transfers.
0
0 6 12 18 24 30 36 42 48 54 60 66 72 78 84 90 96
140
Loop Current (mA)
Figure 13 Typical LCS Transfer Function
An LCS value of zero means the loop current is less than
required for normal operation and the system should be
on-hook. Typically, an LCS value of 15 means the loop
current is greater than 140 mA.
The LCS detector has a built-in hysteresis of 2 mA of
current. This allows for a stable LCS value when the
loop current is near a transition level. The LCS value is
a rough approximation of the loop current, and the
designer is advised to use this value in a relative means
rather than an absolute value.
The delayed frame sync (FSD) of each device is
supplied as the FSYNC of each subsequent slave
device in the daisy chain. The master 303DL generates
an FSYNC signal for each device every 16 or 32 SLCK
periods. The delay period is set by register 14, bit 2
(FSD). Figure 15 and Figure 16 on page 26 show the
relative timing for a single slave device. Note that
primary communication frames occur in sequence,
followed by secondary communication frames, if
requested.
This feature enables the modem to determine if an
additional line has “picked up” while the modem is
transferring information. In the case of a second phone
going off-hook, the loop current falls approximately 50%
and is reflected in the value of the LCS bits.
PRELIMINARY
PC-TEL, Inc.
23
1789N0DOCDAT01A-0399
!
PRELIMINARY
PCT1789N DATA SHEET
303DL FUNCTIONAL DESCRIPTION
If FSD is set for 16 SCLK periods between FSYNCs,
only serial mode 1 can be used. In addition, the slave
devices must delay the tri-state to active transition of
their SDO sufficiently from the rising edge of SCLK to
avoid bus contention.
The 303DL supports the operation of up to eight 303DL
devices on a single serial bus. The master 303DL must
be configured in serial mode 1. The slave(s) 303DL is
configured in serial mode 2. Figure 17 on page 27
shows a typical master/slave connection using three
303DL devices.
When in serial mode 2, FSYNC becomes an input,
RGDT/FSD becomes the delay frame sync output, and
FC/RGDT becomes the ring detection output. In
addition, the internal PLLs are fixed to a multiply by 20.
This provides the desired sample rate when the
master’s SCLK is provided to the slave’s MCLK. Note
that the SCLK of the slave is a no connect in this
configuration.
The delay between FSYNC input and delayed frame
sync output (RGDT/FSD) will be 16 SCLK periods. The
RGDT/FSD output has a waveform identical to the
FSYNC signal in serial mode 0. In addition, the LSB of
SDO is set to zero by default for all devices in serial
mode 2.
Gain Control
The 303DL supports multiple gain and attenuation
settings for the receive and transmit paths, respectively,
through register 13. When the ARX bit is set, 6 dB of
gain is applied to the receive path. When the ATX bit is
set, –3 dB of gain is applied to the transmit path.
Register 15 can be used to provide additional gain
control. For register 15 to have an effect on the receive
and transmit paths, the ATX and ARX bits of register 13
must be zero.
The receive path can support gains of 0, 3, 6, 9, and 12
dB. The gain is selected by bits 2:0 (ARX2:ARX0). The
receive path can also be muted by setting bit 3 (RXM).
The transmit path can support attenuations of 0, 3, 6, 9,
and 12 dB. The attenuation is selected by bits 6:4
(ATX2:ATX0). The transmit path can also be muted by
setting bit 7 (TXM).
Filter Selection
The 303DL supports additional filter selections for the
receive and transmit signals. The IIR bit of register 16,
when set, enables the IIR filters defined in Table 28 on
page 59. This filter provides a much lower, however
non-linear, group delay than the default FIR filters.
PRELIMINARY
PC-TEL, Inc.
24
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
303DL FUNCTIONAL DESCRIPTION
MCLK
DSP
PCT303D
MCLK
SCLK
SDI
SDO
FSYNC
SCLK
SDO
SDI
FSYNC
FC/RGDT
RGDT/FSD
INT0
47k
47k
Voice CODEC
MCLK
SCLK
FSYNC
SDI
SDO
M/S
Figure 14 Typical Connection for Master/Slave Operation
PRELIMINARY
PC-TEL, Inc.
25
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
303DL FUNCTIONAL DESCRIPTION
256 SCLKs
FSYNC
master
16 or 32 SCLKs
256 SCLKs
16 SCLKs
FSD
SDO
RCV
Data
Master
RCV
Data
Master
RCV
Data
Slave
RCV
Data
Slave
Figure 15 Single Slave Operation, Serial Mode 1 Primary Communication
256 SCLKs
FSYNC
master
16 or 32
SCLKs
128 SCLKs
FSD
SDO
RCV RCV
Data Data
Master Slave
Control Control
Data
Data
Master Slave
RCV
Data
Master
RCV
Data
Slave
Figure 16 Single Slave Operation, Serial Mode 1 Secondary Communication
PRELIMINARY
PC-TEL, Inc.
26
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
303DL FUNCTIONAL DESCRIPTION
MCLK
PCT303D-Master
DSP
MCLK
SCLK
SDI
SDO
FSYNC
SCLK
SDO
SDI
FSYNC
INT0
VCC
FC/RGDT
RGDT/FSD
M1
M0
47 k
47 k
PCT303D-Slave1
MCLK
SCLK
FSYNC
SDI
SDO
RGDT/FSD
VCC
M1
M0
PCT303D-Slave2
MCLK
SCLK
FSYNC
SDI
SDO
RGDT/FSD
VCC
M1
M0
Figure 17 Typical Connection for Multiple 303DLs
PRELIMINARY
PC-TEL, Inc.
27
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
303DL FUNCTIONAL DESCRIPTION
Revision Identification
1. Power up or reset.
2. Program clock generator to desired sample rate.
The 303DL provides the system designer the ability to
determine the revision of the PCT303D and/or the
PCT303L. Register 11 identifies the revision of the
PCT303D with 4 bits named REVA. Register 13
identifies the revision of the PCT303L with 4 bits named
REVB. Table 11 shows the values for the various
revisions.
3. Enable line side by clearing PDL bit.
4. Issue off-hook
5. Delay 4608/Fs to allow calibration to occur.
6. Set desired test mode.
The ISOcap digital loopback mode allows the data pump
to provide a digital input test pattern on SDI and receive
that digital test pattern back on SDO. To enable this
mode, set the DL bit of register 1. In this mode, the
isolation barrier is actually being tested. The digital
stream is delivered across the isolation capacitor, C1 of
Figure 2 on page 6, to the line side device and returned
across the same barrier. Note in this mode, the 0.9 dB
attenuation and filter group delays also exist.
Table 11 Revision Values
Revision
PCT303D
PCT303W
A
1000
–
B
1001
–
C
–
–
D
–
0100
The analog loopback mode allows an external device to
drive the RX pin of the line side chip and receive the
signal from the TX pin. This mode allows testing of
external components connecting the RJ-11 jack (tip and
ring) to the line side of the 303DL. To enable this mode,
set the AL bit of register 2.
In-Circuit Testing
The 303DL’s advanced design provides the modem
manufacturer with increased ability to determine system
functionality during production line tests, as well as
support for end-user diagnostics. Four loopback modes
allow increased coverage of system components. For
three of the test modes, a line-side power source is
needed. While a standard phone line can be used, the
test circuit in Figure 22 on page 59 is adequate. In
addition, an off-hook sequence must be performed to
connect the power source to the line-side chip.
The final testing mode, internal analog loopback, allows
the system to test the basic operation of the transmit/
receive path of the line side and the external
components R4, R8, and C5 of Figure 2 on page 6. In
this test mode, the data pump provides a digital test
waveform on SDI. This data is passed across the
isolation barrier, looped from the TX to RX pin, passed
back across the isolation barrier, and presented to the
data pump on SDO. To enable this mode, clear the HBE
bit of register 2.
For the start-up test mode, no line-side power is
necessary and no off-hook sequence is required. The
start-up test mode is enabled by default. When the PDL
bit (register 6, bit 4) is set (the default case), the line side
is in a power-down mode and the DSP side is in a digital
loop-back mode. In this mode, data received on SDI is
passed through the internal filters and transmitted on
SDO. This path introduces approximately 0.9 dB of
attenuation on the SDI signal received. The group delay
of both transmit and receive filters exists between SDI
and SDO. Clearing the PDL bit disables this mode and
the SDO data is switched to the receive data from the
line side. Note, when PDL is cleared the FDT bit
(register 12, bit 6) becomes active, indicating the
successful communication between the line side and
DSP side. This can be used to verify that the ISOcap is
operational.
When the HBE bit is cleared, this causes a DC offset
which affects the signal swing of the transmit signal. In
this test mode, it is recommended that the transmit
signal be 12 dB lower than normal transmit levels. This
lower level eliminates clipping caused by the DC offset
which results from disabling the hybrid. It is assumed in
this test that the line AC impedance is nominally 600 Ω.
NOTE: All test modes are mutually exclusive. If more
than one test mode is enabled concurrently, the results
are unpredictable.
Exception Handling
The 303DL provides several mechanisms to determine
if an error occurs during operation. Through the
secondary frames of the serial link, the controlling DSP
can read several status bits. The bit of highest
importance is the frame detect bit (FDT, register 12 bit
6). This bit indicates that the DSP side (PCT303D) and
line side (PCT303L) devices are communicating. During
The remaining test modes require an off-hook sequence
to operate. The following sequence defines the off-hook
requirement:
PRELIMINARY
PC-TEL, Inc.
28
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
PRELIMINARY
303DL FUNCTIONAL DESCRIPTION
!
normal operation, the FDT bit can be checked before
reading any bits that indicate information about the line
side. If FDT is not set, the following bits related to the
line side are invalid—RDT, LCS, CBID, REVB; the
RGDT operation will also be non-functional.
Following power-up and reset, the FDT bit is not set
because the PDL bit (register 6 bit 4) defaults to 1. In this
state, the ISOcap is not operating and no information
about the line side can be determined. The user must
program the clock generator to a valid configuration for
the system and clear the PDL bit to activate the ISOcap.
While the PCT303D and PCT303L are establishing
communication, the 303DL will not generate FSYNC
signals. Establishing communication will take less than
10 ms. Therefore, if the controlling DSP serial interface
is interrupt driven, based on the FSYNC signal, the
controlling DSP does not require a special delay loop to
wait for this event to complete.
The FDT bit can also indicate if the line side executes an
off-hook request successfully. If the line side is not
connected to a phone line (that is, the user fails to
connect a phone line to the modem), the FDT bit
remains cleared. The controlling DSP must allow
sufficient time for the line side to execute the off-hook
request. The maximum time for FDT to be valid following
an off-hook request is 10 ms. At this time, the LCS bits
indicate the amount of loop current flowing. For more
information, see “Loop Current Monitor” on page 23. If
the FDT bit fails to be set following an off-hook request,
the line-side chip must be reset. This is accomplished by
setting the PDL bit for at least 1 ms.
Another useful bit is the communication link error (CLE)
bit (register 12 bit 7). The CLE bit indicates a time-out
error for the ISOcap following a change to either PLL1
or PLL2. For more information, see “Clock Generation
Subsystem” on page 19. When the CLE bit is set, the
DSP side chip has failed to receive verification from the
line side that the clock change has been accepted in an
expected period of time (less than 10 ms). This
condition indicates a severe error in programming the
clock generator or possibly a defective line-side chip.
PRELIMINARY
PC-TEL, Inc.
29
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
303DL CONTROL REGISTERS
303DL CONTROL REGISTERS
Any register not listed here is reserved and should not be written. Undefined/unimplemented registers return 0.
Control 1
(Register 1, R/W)
SR
Reserved
7
6
5
4
3
2
DL
SB
1
0
Reset settings: 00h
Bit Definitions:
Bits
Name
Description
SR
Software reset.
1 = Sets all registers to their reset value.
0 = Enables chip for normal operation.
Reserved
Reserved. Read returns zero.
1
DL
Isolation digital loopback. 1 = Enables digital loopback mode across isolation
barrier.
0
SB
Serial digital interface mode.
1 = The serial port is operating in 16-bit mode and requires use of the secondary
frame sync signal, FC/RGDT, to initiate control data reads/writes.
0 = Operation is in 15-bit mode and the LSB of the data field indicates whether a
secondary frame is required.
7
6:2
Control 2
(Register 2, R/W)
Reserved
7
6
5
4
AL
Reserved
HBE
RXE
3
2
1
0
Reset settings: 03h
Bit Definitions:
Bits
7:4
3
Name
Description
Reserved
Reserved. Read returns zero.
AL
Analog loopback. 1 = Enables analog loopback mode.
2
Reserved
Reserved. Read returns zero.
1
HBE
Hybrid enable. 1 = Connects transmit path in hybrid.
0
RXE
Receive enable. 1 = Enables receive path.
PRELIMINARY
PC-TEL, Inc.
43
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
303DL CONTROL REGISTERS
Control 3
(Register 3, R)
Reserved
7
6
5
4
3
2
1
0
Reset settings: 00h
Bit Definitions:
Bits
7:0
Name
Description
Reserved
Reserved. Read returns zero.
Control 4
(Register 4, R)
Reserved
7
6
5
4
3
2
1
0
Reset settings: 00h
Bit Definitions:
Bits
7:0
Name
Description
Reserved
Reserved. Read returns zero.
DAA Control 1
(Register 5, R/W)
Reserved
7
6
5
OPOL
ONHM
RDT
OHE
OH
4
3
2
1
0
Reset settings: 00h
Bit Definitions:
Bits
Name
Description
Reserved
Reserved. Read returns zero.
4
OPOL
Off-hook polarity.
1 = Off-hook pin is active-high.
0 = Off-hook pin is active-low.
3
ONHM
On-hook line monitor. 1 = Enables low-power monitoring mode allowing the DSP to
receive line activity without going off-hook.
2
RDT
Ring detect. Read-only.
1 = Indicates a ring is occurring.
1
OHE
Off-hook pin enable.
1 = Enables the operation of the off-hook pin.
0 = Off-hook pin is ignored.
0
OH
Off-hook. 1 = Causes the line-side chip to go off-hook. This bit operates independently of OHE and is a logic OR with the off-hook pin when OHE = 1.
7:5
PRELIMINARY
PC-TEL, Inc.
44
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
303DL CONTROL REGISTERS
DAA Control 2
(Register 6, R/W)
CPE
ATM1
ARM1
PDL
PDN
Reserved
ATM0
ARM0
7
6
5
4
3
2
1
0
Reset settings: 70h
Bit Definitions:
Bits
7
6,1
Name
Description
CPE
Charge pump enable.
1 = Charge pump on (the VA pin should not be connected to a supply.
VD = 3.3 V ± 10%).
0 = Charge pump off.
ATM[1:0]
AOUT transmit path level control.
ATM[1:0]
5,0
ARM[1:0]
Description
00
–20dB transmit path attenuation for call progress AOUT pin only.
01
–32dB transmit path attenuation for call progress AOUT pin only.
10
Mutes transmit path for call progress AOUT pin only.
11
–26dB transmit path attenuation for call progress AOUT pin only.
AOUT receive path level control.
ARM[1:0]
Description
00
0dB receive path attenuation for call progress AOUT pin only.
01
–12dB receive path attenuation for call progress AOUT pin only.
10
Mutes receive path for call progress AOUT pin only.
11
–6dB receive path attenuation for call progress AOUT pin only.
4
PDL
Power down line-side chip.
1 = Places the PCT303L in lower power mode.
0 = Normal operation. Program the clock generator before clearing this bit.
3
PDN
Power down. 1 = Powers down the 303DL. A reset pulse on RESET is required
to restore normal operation.
2
Reserved
Reserved. Read returns zero.
PLL1 Divide N1
(Register 7, R/W)
Divider N1
7
6
5
4
3
2
1
0
Reset settings: 00h (serial mode 0, 1, 2)
Bit Definitions:
Bits
7:0
Name
Description
Divider N1
Contains the (value – 1) for determining the output frequency on PLL1.
PRELIMINARY
PC-TEL, Inc.
45
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
303DL CONTROL REGISTERS
PLL1 Multiply M1
(Register 8, R/W)
Multiplier M1
7
6
5
4
3
2
1
0
Reset settings: 00h (serial mode 0,1)
Reset settings: 13h (serial mode 2)
Bit Definitions:
Bits
7:0
Name
Description
Multiplier M1
Contains the (value – 1) for determining the output frequency on PLL1.
PLL2 Divide/Multiply N2/M2
(Register 9, R/W)
Divider N2
7
6
Multiplier M2
5
4
3
2
1
0
Reset settings: 00h (serial mode 0, 1, 2)
Bit Definitions:
Bits
Name
Description
7:4
Divider N2
Contains the (value – 1) for determining the output frequency on PLL2.
3:0
Multiplier M2
Contains the (value – 1) for determining the output frequency on PLL2.
PLL Control
(Register 10, R/W)
Reserved
7
6
5
CGM
4
3
2
1
0
Reset settings: 00h
Bit Definitions:
Bits
7:1
0
Name
Description
Reserved
Reserved. Read returns zero.
CGM
Clock Generation Mode.
1 = A 25/16 ratio is applied to the PLL allowing for a more flexible choice of
MCLK frequencies while slowing down the PLL lock time.
0 = No additional ratio is applied to the PLL and faster lock times are possible.
Chip Revision
(Register 11, R)
Reserved
7
6
REVA
5
4
3
2
1
0
Reset settings: N/A
Bit Definitions:
Bits
Name
Description
7:4
Reserved
Reserved. Read returns zero.
3:0
REVA
Chip revision. Read-only.
Four-bit value indicating the revision of the PCT303D (DSP-side) silicon.
1000 = Revision A
1001 = Revision B
PRELIMINARY
PC-TEL, Inc.
46
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
303DL CONTROL REGISTERS
Line-Side Status
(Register 12, R/W)
CLE
FDT
7
6
Reserved
5
LCS
4
3
2
1
0
Reset settings: N/A
Bit Definitions:
Bits
Name
Description
7
CLE
Com link error.
1 = Indicates a communication problem between the PCT303D and the
PCT303L. When it goes high, it remains high until a logic 0 is written to it.
6
FDT
Frame detect. Read-only.
1 = Indicates ISOcap communication frame lock has been established.
0 = Indicates inter-chip communication has not established frame lock.
5:4
Reserved
Reserved. Read returns zero.
3:0
LCS
Loop current sense. Read-only.
Four-bit value returning the loop current in 6mA increments.
0 = Loop current < 0.4mA typical. 1111 = Loop current > 140mA.
See “Loop Current Monitor” on page 23.
Transmit and Receive Gain
Reserved
CBID
7
6
(Register 13, R/W)
REVB
5
4
3
2
ARX
ATX
1
0
Reset settings: 00h
Bit Definitions:
Bits
Name
Description
7
Reserved
Reserved. Read returns zero.
6
CBID
Chip B ID. Read-only.
1 = Indicates the line-side has international support.
0 = Indicates the line-side is domestic only.
5:2
REVB
Chip revision. Read-only.
Four-bit value indicating the revision of the PCT303L (line-side) silicon.
0100 = Revision D.
1
ARX
Receive gain.a
1 = A +6dB gain is applied to the receive path.
0 = 0dB gain is applied.
0
ATX
Transmit gain.a
1 = A –3dB gain (attenuation) is applied to the transmit path.
0 = 0dB gain is applied.
a.
This bit should be zero if using register 15 to control gain.
PRELIMINARY
PC-TEL, Inc.
47
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
303DL CONTROL REGISTERS
Daisy-Chain Control
(Register 14, R/W)
NSLV[2:0]
7
6
SSEL[1:0]
5
4
3
FSD
RPOL
DCE
2
1
0
Reset settings: 02h (serial mode 0,1)
Reset settings: 3Fh (serial mode 2)
Bit Definitions:
Bits
7:5
Name
Description
NSLV[2:0]
Number of slave devices.
NSLV[2:0]
4:3
SSEL[1:0]
Description
000
0 slave devices. Simply redefines the FC/RGDT and RGDT/FSD pins.
001
1 slave device.
010
2 slave devices.
011
3 slave devices.
100
4 slave devices. For four or more slave devices, the FSD bit MUST be set.
101
5 slave devices.
110
6 slave devices.
111
7 slave devices.
Slave device select.
SSEL[1:0]
Description
00
16-bit SDO receive data.
01
Reserved.
10
15-bit SDO receive data. LSB = 1 for the 303DL device.
11
15-bit SDO receive data. LSB = 0 for the 303DL device.
2
FSD
Delayed frame sync control.
1 = Sets the number of SCLK periods between frame syncs to 16.
0 = Sets the number of SCLK periods between frame syncs to 32.
This bit MUST be set when 303DL devices are used as slaves. For the master
303DL, only serial mode 1 is allowed in this case.
1
RPOL
Ring detect polarity.
1 = The FC/RGDT pin (operating as ring detect) is active-high.
0 = The FC/RGDT pin (operating as ring detect) is active-low.
0
DCE
Daisy-chain enable.
1 = Enables the 303DL to operate with slave devices on the same serial bus. The
FC/RGDT signal (pin 7) becomes the ring detect output and the RGDT/FSD signal (pin 15) becomes the delayed frame sync signal. Note that ALL other bits in
this register are ignored if DCE = 0.
PRELIMINARY
PC-TEL, Inc.
48
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
303DL CONTROL REGISTERS
TX/RX Gain Control
TXM
(Register 15, R/W)
ATX[2:0]
7
6
RXM
5
4
3
ARX[2:0]
2
1
0
Reset settings: 00h
Bit Definitions:
Bits
7
6:4
Name
Description
TXM
Transmit mute. 1 = Mutes the transmit signal.
ATX[2:0]
Analog transmit attenuation.
ATX[2:0]
Description
000
0dB attenuation.
001
3dB attenuation.
010
6dB attenuation.
011
9dB attenuation.
1xx
12dB attenuation.
NOTE: Register 13 bit 0 (ATX) must be 0 for these bits to work as expected.
Unpredictable results can occur if ATX is 1 and these bits are non-zero.
3
2:0
RXM
Receive mute. 1 = Mutes the receive signal.
ARX[2:0]
Analog receive gain.
ATX[2:0]
Description
000
0dB gain.
001
3dB gain.
010
6dB gain.
011
9dB gain.
1xx
12dB gain.
NOTE: Register 13 bit 1 (ARX) must be 0 for these bits to work as expected.
Unpredictable results can occur if ARX is 1 and these bits are non-zero.
IIR Filter Control
(Register 16, R/W)
0
0
0
IIRE
1
0
0
0
7
6
5
4
3
2
1
0
Reset settings: 08h
Bit Definitions:
Bits
7:5
4
3:0
Name
Description
Reserved
Reserved. Read returns zero. Must always be written with zeros.
IIRE
IIR filter enable. When set, the transmit and receive filters are realized with an IIR
filter characteristic. To enable IIR filter write 18h; to disable IIR filter write 08h.
See Table 28 for more details on IIR filter performance.
Reserved
Reserved. Read returns 8h. Must always be written with 8h.
PRELIMINARY
PC-TEL, Inc.
49
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
ELECTRICAL CHARACTERISTICS
303DL Electrical Characteristics
303DL Recommended Operating Conditions
Table 17 303DL Recommended Operating Conditions
Parameter a
Symbol
Test Condition
Min b
Typ
Max b
Unit
Ambient temperature
TA
K-grade
0
25
70
°C
Ambient temperature
TA
B-grade
–40
25
+85
°C
PCT303D supply voltage, analog
VA
3.0
3.3/5.0
5.25
V
PCT303D supply voltage, digital c
VD
3.0
3.3/5.0
5.25
V
a.
b.
c.
The 303DL specifications are guaranteed when the typical application circuit (including component tolerance) and
any PCT303D and PCT303L are used. See Figure 2 on page 6 for a typical application circuit.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.
The digital supply, VD, can operate from either 3.3V or 5.0V. The PCT303D supports interface to 3.3V logic when
operating from 3.3V. The 3.3V operation applies to both the serial port and the digital signals RGDT, OFHK, and
RESET, M0, and M1.
303DL Absolute Maximum Ratings
Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should
be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 18 303DL Absolute Maximum Ratings
Parameter
DC supply voltage
Input current, PCT303D digital input pins
Digital input voltage
Operating temperature range
Storage temperature range
Symbol
Value
Unit
VD, VA
–0.5 to +6.0
V
IIN
±10
mA
VIND
–0.3 to (VD+0.3)
V
TA
–10 to +100
°C
TSTG
–40 to +150
°C
PRELIMINARY
PC-TEL, Inc.
51
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
ELECTRICAL CHARACTERISTICS
303DL Loop Characteristics
Given values are: VA = charge pump, VD = +3.3 V ± 0.3 V; TA = 0 °C to 70 °C for K-grade, –40 °C to +85 °C for
B-grade; refer to Figure 22 on page 59.
Table 19 303DL Loop Characteristics
Parameter
Symbol
Test Condition
DC termination voltage
VDCT
IL = 20mA
DC termination voltage
VDCT
IL = 105mA
DC ring current (with Caller ID)
IRDC
1
mA
DC ring current (without Caller ID)
IRDC
20
µA
AC termination impedance
ZACT
Operating loop current
ILP
Loop current sense bits
LCS
Ring voltage detect
Min
Typ
Max
Unit
7.7
V
12
V
Ω
600
20
LCS = Fh
105
160
140
VRD
13
18
Ring frequency
FR
15
On-hook leakage current
ILK
VBAT = –48V
Ringer equivalence number (with Caller ID)
REN
1.0
Ringer equivalence number (without Caller ID)
REN
0.2
mA
mA
26
VRMS
68
Hz
1
µA
1.67
303DL DC Characteristics
VD = 5V
Given values are: VA = +5 V ±5%; VD = +5 V ± 5%; TA = 0 °C to 70 °C for K-grade, –40 °C to +85 °C for B-grade.
Table 20 303DL DC Characteristics, VD = +5V
Parameter
Symbol
Test Condition
High-level input voltage
VIH
Low-level input voltage
VIL
High-level output voltage
VOH
IO = –2mA
Low-level output voltage
VOL
IO = +2mA
Min
Typ
Max
3.5
Unit
V
0.8
2.4
V
V
0.4
V
±10
µA
Input leakage current
IL
Power supply current, analog
IA
VA pin
0.3
1
mA
Power supply current, digital a
ID
VD pin
14
18
mA
1.3
2.5
mA
Total supply current, sleep mode a
Total supply current, deep sleep
a.
b.
0.5
a,b
mA
All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded
(Static IOUT = 0 mA).
RGDT is not functional in this state.
PRELIMINARY
PC-TEL, Inc.
52
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
ELECTRICAL CHARACTERISTICS
VD = 3.3V
Given values are: VA = charge pump; VD = +3.3 V ± 0.3 V; TA = 0 °C to 70 °C for K-grade, –40 °C to +85 °C for B-grade.
Table 21 303DL DC Characteristics, VD = +3.3V
Parameter
Symbol
Test Condition
High-level input voltage
VIH
Low-level input voltage
VIL
High-level output voltage
VOH
IO = –2mA
Low-level output voltage
VOL
IO = +2mA
Min
Typ
Max
2.4
Unit
V
0.8
2.4
V
V
0.35
V
±10
µA
Input leakage current
IL
Power supply current, analog a
IA
VA pin
0.3
1
mA
Power supply current, digital b
ID
VD pin
9
12
mA
1.2
2.5
mA
Total supply current, sleep mode b
Total supply current, deep sleep
Power supply voltage, analog
a.
b.
c.
d.
a,d
0.5
b,c
VA
Charge pump on
4.5
4.6
mA
4.7
V
Only a decoupling capacitor should be connected to VA when the charge pump is on.
All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded
(Static IOUT = 0 mA).
RGDT is not functional in this state.
The charge pump is recommended to be used only when VDD < 4.5V. When the charge pump is not used, VA
should be applied to the device before VD is applied on power up if driven from separate supplies.
PRELIMINARY
PC-TEL, Inc.
53
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
ELECTRICAL CHARACTERISTICS
303DL AC Characteristics
Given values are: VA = charge pump, VD = +3.3 V ± 0.3 V; TA = 0 °C to 70 °C for K-grade, –40 °C to +85 °C for B-grade.
Table 22 303DL AC Characteristics
Parameter
Symbol
Sample rate
Test Condition
Fs
Min
Typ
7.2
Max
Unit
11.025
kHz
a
FRT
Low –3dB corner
Freq response, transmit a
FRT
300Hz
–0.2
0
dB
Freq response, transmit
FRT
3400Hz
–0.2
0
dB
Transmit full scale level b (0dB gain)
VTX
Freq response, receive a
FRR
Low –3dB corner
Freq response, receive a
FRR
300Hz
–0.01
0
dB
Freq response, receive
FRR
3400Hz
–0.2
0
dB
Receive full scale level b,c (0dB gain)
VRX
Dynamic range d
DR
VIN = 1kHz, –3dB
Dynamic range e
DR
Total harmonic distortion f
Dynamic range (call progress AOUT)
Freq response, transmit
THD (call progress AOUT)
16
e.
f.
16
Hz
86
dB
VIN = 1kHz, –3dB
84
dB
THD
VIN = 1kHz, –3dB
–84
dB
DRAO
VIN = 1kHz
THDAO
VIN = 1kHz
Mute level (call progress AOUT)
a.
b.
c.
d.
Vpeak
Vpeak
81
60
AOUT output impedance
Caller ID full scale level (0dB gain) b
0.98
0.98
AOUT full scale level
Dynamic range (Caller ID mode)
Hz
dB
1.0
%
0.75VD
Vp-p
10
kΩ
–90
DRCID
VIN = 1kHz, –13dB
VCID
dB
60
dB
0.8
Vpeak
These characteristics are determined by external components. See Figure 2 on page 6.
Parameter measured at Tip and Ring of Figure 2 on page 6.
Receive full scale level produces –0.9dBFS at SDO.
DR = 3dB + 20 log (RMS signal/RMS noise). Applies to both the transmit and receive paths. Measurement
bandwidth is 300Hz to 3400Hz. Sample rate = 9.6kHz; Loop current = 40mA.
DR = 3dB + 20 log (RMS signal/RMS noise). Applies to both the transmit and receive paths. Measurement
bandwidth is 15Hz to 3400Hz. Sample rate = 9.6kHz; Loop current = 40mA.
THD = 20 log (RMS distortion/RMS signal). Applies to both the transmit and receive paths. Sample rate = 9.6kHz;
Loop current = 40mA.
PRELIMINARY
PC-TEL, Inc.
54
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
SWITCHING CHARACTERISTICS
SWITCHING CHARACTERISTICS
General Inputs
Given values are: VA = charge pump, VD = 3.0 V to 5.25 V; TA = 0 °C to 70 °C for K-grade, –40 °C to +85 °C for
B-grade; CL = 20 pF.
Table 23 Switching Characteristics—General Inputs
Parameter a
Symbol
Min
Cycle time, MCLK
tmc
16.67
MCLK duty cycle
tdty
40
Rise time, MCLK
Fall time, MCLK
Typ
Max
Unit
ns
50
60
%
tr
5
ns
tf
5
ns
MCLK before RESET ↑
tmr
10
cycles
RESET pulse width b
trl
250
ns
tmxr
150
ns
M0, M1 before RESET ↑ c
a.
b.
c.
All timing (except rise and fall time) is referenced to the 50% level of the waveform. Input test levels are:
VIH = VD – 0.4V, VIL = 0.4V. Rise and fall times are referenced to the 20% and 80% levels of the waveform.
The minimum RESET pulse width is the greater of 250ns or 10 MCLK cycle times.
M0 and M1 are typically connected to VD or GND and should not be changed during normal operation.
tr
tmc
MCLK
tf
VIH
VIL
tmr
RESET
trl
M0, M1
tmxr
Figure 18 General Inputs Timing Diagram
PRELIMINARY
PC-TEL, Inc.
55
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
SWITCHING CHARACTERISTICS
Serial Interface (DCE = 0)
Given values are: VA = charge pump, VD = 3.0 V to 5.25 V; TA = 0 °C to 70 °C for K-grade, –40 °C to +85 °C for
B-grade; CL = 20 pF.
All timing is referenced to the 50% level of the waveform. Input test levels are: VIH = VD – 0.4V, VIL = 0.4V.
Table 24 Switching Characteristics—Serial Interface (DCE = 0)
Parameter
Symbol
Min
Typ
Max
Cycle time, SCLK
tc
354
1/256 Fs
ns
SCLK duty cycle
tdty
50
%
Delay time, SCLK ↑ to FSYNC ↓
td1
Delay time, SCLK ↑ to SDO valid
td2
Delay time, SCLK ↑ to FSYNC ↑
td3
–10
Setup time, SDI before SCLK ↓
tsu
25
ns
Hold time, SDI after SCLK ↓
th
20
ns
Setup time, FC ↑ before SCLK ↑
tsfc
40
ns
Hold time, FC ↑ after SCLK ↑
thfc
40
ns
–10
Unit
20
ns
20
ns
20
ns
tc
VOH
SCLK
VOL
td3
td1
FSYNC
(mode 0)
td3
FSYNC
(mode 1)
td2
16-bit
SDO
D15
D14
tsu
16-bit
SDI
D15
D1
D0
th
D14
D1
D0
tsfc
thfc
FC
Figure 19 Serial Interface Timing Diagram (DCE = 0)
PRELIMINARY
PC-TEL, Inc.
56
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
SWITCHING CHARACTERISTICS
Serial Interface (DCE = 1, FSD = 0)
Given values are: VA = charge pump, VD = 3.0 V to 5.25 V; TA = 0 °C to 70 °C for K-grade, –40 °C to +85 °C for
B-grade; CL = 20 pF.
All timing is referenced to the 50% level of the waveform. Input test levels are: VIH = VD – 0.4V, VIL = 0.4V.
Table 25 Switching Characteristics—Serial Interface (DCE = 1, FSD = 0)
Parameter
Symbol
Min
Typ
Max
50
Unit
SCLK duty cycle
tdty
%
Delay time, SCLK ↑ to FSYNC ↑
td1
Delay time, SCLK ↑ to FSYNC ↓
td2
Delay time, SCLK ↑ to SDO valid
td3
Delay time, SCLK ↑ to SDO Hi-Z
td4
Setup time, SDO before SCLK ↓
tsu
25
ns
Hold time, SDO after SCLK ↓
th
20
ns
Setup time, SDI before SCLK ↓
tsu2
25
ns
Hold time, SDI after SCLK ↓
th2
20
ns
–10
–10
20
ns
20
ns
20
ns
20
ns
SCLK
td1
td2
FSYNC
(mode 1)
td1
FSYNC
(mode 0)
tsu
td3
SDO
th
D14
D15
tsu2
SDI
td4
D15
D13
D0
th2
D14
D1
D0
Figure 20 Serial Interface Timing Diagram (DCE = 1, FSD = 0)
PRELIMINARY
PC-TEL, Inc.
57
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
SWITCHING CHARACTERISTICS
Serial Interface (DCE = 1, FSD = 1)
Given values are: VA = charge pump, VD = 3.0 V to 5.25 V; TA = 0 °C to 70 °C for K-grade, –40 °C to +85 °C for
B-grade; CL = 20 pF.
All timing is referenced to the 50% level of the waveform. Input test levels are: VIH = VD – 0.4V, VIL = 0.4V.
Table 26 Switching Characteristics—Serial Interface (DCE = 1, FSD = 0)
Parameter
Symbol
Min
Typ
Max
Unit
Cycle time, SCLK
tc
354
1/256 Fs
ns
SCLK duty cycle
tdty
50
%
Delay time, SCLK ↑ to FSYNC ↑
td1
–10
20
ns
Delay time, SCLK ↑ to FSYNC ↓
td2
–10
20
ns
Delay time, SCLK ↑ to SDO valid
td3
0.25tc–20
0.25tc+20
ns
Delay time, SCLK ↑ to SDO Hi-Z
td4
20
ns
Delay time, SCLK ↑ before RGDT ↓
td5
20
ns
Setup time, SDO before SCLK ↓
tsu
25
ns
Hold time, SDO after SCLK ↓
th
20
ns
Setup time, SDI before SCLK
tsu2
25
ns
Hold time, SDI after SCLK
th2
20
ns
tc
SCLK
td1
td2
FSYNC
(mode 1)
td3
SDO
(master)
tsu
td4
th
D15
D14
D13
D0
td3
SDO
(slave 1)
D15
td5
FSD
tsu2
SDI
D15
th2
D14
D1
D0
Figure 21 Serial Interface Timing Diagram (DCE = 1, FSD = 1)
PRELIMINARY
PC-TEL, Inc.
58
1789N0DOCDAT01A-0399
PRELIMINARY
PCT1789N DATA SHEET
!
DIGITAL FILTER CHARACTERISTICS
DIGITAL FILTER CHARACTERISTICS
Digital FIR Filter Characteristics
Given values are: VA = charge pump, VD = +5 V ± 5%; sample rate = 8 kHz; TA = 0 °C to 70 °C for K-grade, –40 °C to
+85 °C for B-grade.
Typical FIR filter characteristics for Fs = 8000Hz are shown in Figures 23, 24, 25, and 26.
Table 27 Digital FIR Filter Characteristics—Transmit and Receive
Parameter
Symbol
Min
Passband (0.1dB)
F(0.1dB)
F(3dB)
Passband (3dB)
Passband ripple peak-to-peak
Max
Unit
0
3.3
kHz
0
3.6
kHz
–0.1
0.1
dB
Stopband
Typ
4.4
Stopband attenuation
kHz
–74
Group delay
tgd
dB
12/Fs
sec
Digital IIR Filter Characteristics
Given values are: VA = charge pump, VD = +5 V ± 5%; sample rate = 8 kHz; TA = 0 °C to 70 °C for K-grade, –40 °C to
+85 °C for B-grade.
Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 27, 28, 29, and 30. Figures 31 and 32 show
group delay versus input frequency.
Table 28 Digital IIR Filter Characteristics—Transmit and Receive
Parameter
Symbol
Min
F(3dB)
Passband (3dB)
Passband ripple peak-to-peak
Max
Unit
0
3.6
kHz
–0.2
0.2
dB
Stopband
Typ
4.4
Stopband attenuation
kHz
–40
Group delay
tgd
dB
1.6/Fs
sec
Tip
600 Ω
PCT303L
IL
10 µF
Ring
Note: The remainder of the circuit is identical to the one shown in the typical application circuit.
Figure 22 Test Circuit For Loop Characteristics
PRELIMINARY
PC-TEL, Inc.
59
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
DIGITAL FILTER CHARACTERISTICS
Filter Plot Diagrams
Filter Plot Diagrams
For Figures 23, 24, 25, and 26, all filter plots apply to a sample rate of Fs = 8 kHz. The filters scale with the sample
rate as follows:
F(0.1 dB) = 0.4125 Fs
F(– 3 dB) = 0.45 Fs
Attenuation - dB
Attenuation - dB
where Fs is the sample frequency.
Input Frequency - kHz
Figure 23 FIR Receive Filter Response
Figure 24 FIR Receive Filter Passband Ripple
Attenuation - dB
Attenuation - dB
Input Frequency - kHz
Input Frequency - kHz
Input Frequency - kHz
Figure 26 FIR Transmit Filter Passband Ripple
Figure 25 FIR Transmit Filter Response
PRELIMINARY
PC-TEL, Inc.
60
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
PRELIMINARY
!
DIGITAL FILTER CHARACTERISTICS
For Figures 27, 28, 29, and 30, all filter plots apply to a sample rate of Fs = 8 kHz. The filters scale with the sample
rate as follows:
F(– 3 dB) = 0.45 Fs
Attenuation - dB
Attenuation - dB
where Fs is the sample frequency.
Input Frequency - kHz
Input Frequency - kHz
Figure 28 IIR Receive Filter Passband Ripple
Attenuation - dB
Attenuation - dB
Figure 27 IIR Receive Filter Response
Input Frequency - kHz
Figure 29 IIR Transmit Filter Response
Input Frequency - kHz
Figure 30 IIR Transmit Filter Passband Ripple
PRELIMINARY
PC-TEL, Inc.
61
1789N0DOCDAT01A-0399
PCT1789N DATA SHEET
Delay - µs
DIGITAL FILTER CHARACTERISTICS
Delay - µs
!
PRELIMINARY
Input Frequency - kHz
Figure 31 IIR Receive Group Delay
Input Frequency - kHz
Figure 32 IIR Transmit Group Delay
PRELIMINARY
PC-TEL, Inc.
62
1789N0DOCDAT01A-0399
PRELIMINARY
!
PCT1789N DATA SHEET
MECHANICAL DIMENSIONS
303DL Mechanical Dimensions
16
9
E
H
0.010"
1
0
8
GAUGE PLANE
L
b
DETAIL F
A1
e
c
A
A2
D
L1
Seating Plane
See Detail F
Figure 34 16-pin SOIC Package
Table 30 SOIC Mechanical Dimensions
(Controlling dimension: millimeters)
Symbol
Millimeters
Inches
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
A2
1.30
1.50
0.051
0.059
b
0.330
0.51
0.013
0.020
c
0.19
0.25
0.007
0.010
D
9.80
10.01
0.386
0.394
E
3.80
4.00
0.150
0.157
e
1.27 BSC
H
5.80
6.20
0.228
0.244
L
0.40
1.27
0.016
0.050
L1
1.07 BSC
g
q
0.050 BSC
0.042 BSC
0.10
0°
8°
0.004
0°
8°
PRELIMINARY
PC-TEL, Inc.
64
1789N0DOCDAT01A-0399