PI74LVTCH16245 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 3.3V 16-Bit Bi-Directional Transceiver with 3-State Outputs Product Features Product Description · Advanced low power CMOS design for 2.7V to 3.6V Vcc operation · Supports 5V input/output tolerance in mixed signal mode operation Pericom Semiconductor’s PI74LVTC series of logic circuits are produced using the Company’s advanced submicron CMOS technology, achieving industry leading speed. · Function compatible with LVT family of products · Balanced ±24mA output drive · Typical VOLP (Output Ground Bounce) <0.8V at VCC=3.3V, TA=25°C · Ioff and Power Up/Down 3-State support live insertion · Bus Hold on data inputs eliminates the need for external pull-up/down resistors · Latch-up performance exceeds 200mA Per JESD78 · ESD protection exceeds JESD 22 - 2000V Human-Body Model (A114-B) - 200V Machine Model (A115-A) · Available Packages: - 48-pin 240-mil wide plastic TSSOP (A48) - 48-pin 300-mil wide plastic SSOP (V48) · Industrial Temperature: -40°C to +85°C The PI74LVTCH16245 is a non-inverting 16-bit Bidirectional Transceiver designed for low-voltage 2.7V to 3.6V VCC operation, with the capability of interfacing to the 5V system environment. This tranceiver is designed for asynchronous two-way communication between data buses. The direction control input pin (xDIR) determines the direction of the data flow through the bidirectional transceiver. The Direction and Output Enable controls are designed to operate this device as either two independent 8-bit tranceivers or one 16-bit transceiver. The output enable (xOE) input, when HIGH, disables both A and B ports by placing them in HIGH Z condition. The PI74LVTCH16245 has "Bus Hold" which retains the data input's last valid logic state whenever the data input goes to highimpedance, preventing "floating" inputs and eliminating the need for pull-up/down resistors. When Vcc is between 0 to 1.5V during power up or power down, the outputs of the device are in the high-impedance state. To ensure the high-impedance state above 1.5V, OE should be tied to Vcc through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Logic Block Diagram 1 1DIR 2DIR 48 1A0 47 1A1 46 1A2 44 1A3 43 1A4 41 1A5 40 1A6 38 1A7 37 2 3 5 6 8 9 11 12 25 2OE 1OE 2A0 36 2A1 35 2A2 33 2A3 32 2A4 30 2A5 29 2A6 27 2A7 26 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 The device fully supports live-insertion with its Ioff and power-up/ down 3-state. The Ioff circuitry disables the outputs when the power is off, preventing the backflow of damaging current through the device. Power-up/down 3-state places the outputs in the high-impedance state during power up or power down, preventing driver conflict. 24 13 2B0 14 2B1 16 2B2 17 2B3 19 2B4 20 2B5 22 2B6 23 2B7 1 PS 8649A 05/19/03 PI74LVTCH16245 3.3V, 16-Bit Bi-Directional Tranceivers with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Product Pin Description Pin Name Supply voltage range, VCC .............................. –0.5V to +6.5V Input voltage range, VI(1) ................................ –0.5V to +6.5V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ....... –0.5V to +6.5V Voltage range applied to any output in the active state, VO(1), (2) ................................ –0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ..................................... –50mA Output clamp current, IOK (VO <0) ............................... –50mA Continous Output Current IO ....................................... ±50mA Continous Current through each VCC or GND pin .............. ±100mA Package thermal impedance, θJA(3): package A ........ 104°C/W package V ........... 94°C/W Storage Temperature range, Tstg ..................... –65°C to 150°C xOE 3- State Output Enable Inputs (Active LOW) xDIR Direction Control Inputs (Active HIGH) xAx Side A Inputs or 3- State Outputs xBx Side B Inputs or 3- State Outputs GND Ground VC C Power Product Pin Configuration Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 6.5V maximum 3. The package thermal impedance is calculated in accordance with JESD 51. Truth Table(4) Inputs De s cription Outputs 1DIR 1 48 1OE 1B0 2 47 1A0 1B1 3 46 1A1 GND 4 45 GND 1B2 5 44 1A2 1B3 6 43 1A3 VCC 7 42 VCC 1B4 8 41 1A4 1B5 9 40 1A5 GND 10 39 GND 1B6 11 38 12 48-Pin A, V 37 1A6 1B7 2B0 13 36 2A0 2B1 14 35 2A1 GND 15 34 GND 2B2 16 33 2A2 2B3 17 32 2A3 1A7 xOE xDIR L L Bus B Data to Bus A L H Bus A Data to Bus B VCC 18 31 VCC H X Z 2B4 19 30 2A4 2B5 20 29 2A5 GND 21 28 GND 2B6 22 27 2A6 2B7 23 26 2A7 2DIR 24 25 2OE Notes: 4. H = High Signal Level L = Low Signal Level X = Don’t Care or Irrelevant Z = High Impedance 2 PS 8649A 05/19/03 PI74LVTCH16245 3.3V, 16-Bit Bi-Directional Tranceivers with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Recommended Operating Conditions(5) VC C Supply Voltage M in. M a x. Operating 2.7 3.6 2.0 VIH High- level Input Voltage VC C = 2.7V to 3.6V VIL Low- level Input Voltage VC C = 2.7V to 3.6V VI Input Voltage VO Output Voltage IO H High- level output current IO L Low- level output current 0.8 0 5.5 High or Low State 0 VC C 3- State 0 5.5 VC C = 2.7V – 12 VC C = 3.0V to 3.6V – 24 VC C = 2.7V 12 VC C = 3.0V to 3.6V 24 ∆t/∆v Input transition rise or fall rate V mA 10 ∆t/∆VC C Power- up ramp rate 150 TA – 40 Notes: Units Operating free- air temperature ns/V µs/V +85 °C 5. All unused inputs must be held at VCC or GND to ensure proper device operation. 3 PS 8649A 05/19/03 PI74LVTCH16245 3.3V, 16-Bit Bi-Directional Tranceivers with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C) Parame te rs VIK VO H De s cription Te s t Conditions Clamp Diode Voltage Output High Voltage VC C = 2.7V II = –18mA VC C = 2.7V to 3.6V IO H = –100µA VC C –0.2V VC C = 2.7V IO H = –12mA 2.2 IO H = –12mA 2.4 IO H = –24mA 2.2 VC C = 3V VO L Output Low Voltage II II(HO LD) Input Leakage Current A or B Ports Data Input Hold Current (A or B ports) (6) M a x. V IO L = 100µA 0 .2 VC C = 2.7V IO L = 12mA 0.4 IO L = 12mA 0.4 IO L = 24mA 0.55 VI = 0V to 5.5V ±5 VC C = 0V to 3.6V VC C = 3.6V VC C = 3V VC C = 3.6V(7) VI = 5.5V VI = VC C VI = GND ±5 VI = 0.8V 75 VI = 2V –75 VI = 0 to 3.6V ± 500 IO FF Power Off Output Leakage Current VC C = 0V VI or VO = 0V to 5.5V ±5 IO ZPU Power- Up 3- State Current VC C = 0V to 1.5V VO = 0.5V to 5.5V, OE = don't care ±5 IO ZPD Power- Down 3- State Current VC C = 1.5V to 0V VO = 0.5V to 5.5V, OE = don't care ±5 IC C Quiescent Power Supply Current VC C = 2.7V to 3.6V ∆IC C Increase in IC C VC C = 2.7V to 3.6V VI = VC C or GND 3.6V ≤ VI ≤ 5.5V(8) Units –1.2V VC C = 2.7V to 3.6V VC C = 3V Control Inputs M in. IO = 0 One input at VC C - 0.6V(9) Other inputs at VC C or GND µA 60 500 Notes: 6. For I/O ports, Input Leakage Current (II) includes the 3-state Output Leakage Current. Unused pins are at VCC or GND. 7. This is the maximum bus-hold dynamic current. It is the minimum overdrive current required to switch the input from one state to another. 8. This applies in the diabled stae only. 9. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 PS 8649A 05/19/03 PI74LVTCH16245 3.3V, 16-Bit Bi-Directional Tranceivers with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Capacitance Parame te rs De s cription Typ.(10) Te s t Conditions CI Control Input Capacitance VCC = 3.3V, VI = VCC or GND 3.4 CIO Output Capacitance VCC = 3.3V, VO = VCC or GND 8 C PD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f =10 MHz 23 (11) Units pF Notes: 10. All typical values are measured at VCC = 3.3V, TA =25°C. 11. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output loading, and operating at 50% duty cycle, CPD is related to ICCD dynamic operating current by the expression: ICCD= (CPD)(VCC)(fIN)+(ICCstatic) Switching Characteristics Over Operating Range Parame te rs tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(O) De s cription From (Input) To (Output) Propagation Delay A or B B or A Output Enable Time OE A or B Output Disable Time OE A or B VCC = 3.3V ±0.3V VCC = 2.7V CL = 50pF, RL = 500Ohm CL = 50pF, RL = 500Ohm M in. Typ.(12) M ax. 1.0 2.5 3.5 3.9 1. 0 2.5 3.5 3.9 1. 0 2.8 4.9 5.3 1. 0 2.8 4.9 5.3 1.0 2.7 4.3 4.8 1. 0 2.6 4.3 4.8 Output to Output Skew(13) M in. Units M a x. ns 0.5 Notes: 12. All typical values are measured at VCC = 3.3V, TA = 25°C 13. Skew between any two outputs, switching in the same direction. 5 PS 8649A 05/19/03 PI74LVTCH16245 3.3V, 16-Bit Bi-Directional Tranceivers with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 2.7V and 3.3V ±0.3V 6V 500Ω From Output Under Test CL = 50pF S1 Open GND 500Ω (See Note A) Te s t S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND Load Circuit tW 2.7V 1.5V Input 1.5V 0V Voltage Waveforms Pulse Duration Output Control (Low Level Enabling) 2.7V Input 1.5V Output Waveform 1 S1 at 6V (see Note B) 1.5V 0V tPHL tPLH 1.5V tPZL 1.5V Output Waveform 2 S1 at GND (see Note B) VOL Voltage Waveforms Propagation Delay Times 1.5V 0V tPLZ 3V 1.5V tPZH VOH Output 2.7V 1.5V VOL+0.3V tPHZ 1.5V VOH -0.3V VOL VOH 0V Voltage Waveforms Enable and Disable Times Figure 1. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns. D. The outputs are measured one at a time with one transition per measurement. 6 PS 8649A 05/19/03 PI74LVTCH16245 3.3V, 16-Bit Bi-Directional Tranceivers with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 48-pin TSSOP (A) Package 48 .236 .244 1 6.0 6.2 .488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE .004 0.09 .008 0.20 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS .0197 BSC 0.50 .002 .006 0.05 0.15 .007 .010 0.17 0.27 0.45 .018 0.75 .030 .319 BSC 8.1 48-pin SSOP (V) Package 48 .291 .299 7.39 7.59 .395 .420 10.03 10.67 Gauge Plane .010 0.25 .02 0.51 .04 1.01 1 .620 .630 15.75 16.00 .015 0.381 x 45˚ .025 0.635 .008 0.20 Nom. .110 2.79 Max .025 BSC 0.635 .008 0.20 .0135 0.34 0-8˚ .008 0.20 .016 0.40 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 7 PS 8649A 05/19/03 PI74LVTCH16245 3.3V, 16-Bit Bi-Directional Tranceivers with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Ordering Information Orde ring Data Packaging Code Packaging Type PI74LVTCH16245A A 48- pin, 240- mil wide plastic TSSOP PI74LVTCH16245AE A Pb- free, 48- pin, 240- mil wide plastic TSSOP PI74LVTCH16245V V 48- pin, 300- mil wide plastic SSOP PI74LVTCH16245VE V Pb- free,48- pin, 300- mil wide plastic SSOP Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/mechanicals.php 2. X = Tape/Reel Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 8 PS 8649A 05/19/03