ETC TSB43LV81

IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
TSB43LV81
SLLS403-December 1999
•
•
Fully Interoperable with FireWire™
Implementation of IEEE-1394 (1995) and
IEEE1394.a compliant
Interfaces Directly to Texas Instruments
TSB11LV01,TSB21LV03 and TSB41LV0X
Physical Layer Devices (100/200/400 Mbps) by
AUX I/O for more port or Isolation
•
Automated PageTable Fetch for DataTransfer
•
Automated Status Report to Initiator at End of
DMA
•
8/16Bits asynchronous/synchronous DMA I/F
include SCSI and ATAPI like handshake
•
Asynchronous Transmit Data automatic
Packetizer DMA/Asynchronous Data Fetch and
dePacketizer DMA(Compliant to SBP2
requirements)
•
8/16bits Data/Address multiplex Microcontroler
and 8/16bits separated Data/Address bus
•
3RAM configuration can support High
performance for command exchange and DMA
•
Single 3.3V Supply Operation with 5V Tolerance
using 5V bias pins.
•
400M-PHY One port integrated
•
Automated Read Response for Config-ROM
registers
•
Automated Single Retry Protocol and Split
Transaction control
Asynchronous Command FIFO
: 512 Bytes
Config ROM/LOG FIFO
: 512 Bytes
•
Support up to 4 initiators by automated
Transaction and could support more by
firmware(SBP2 Protocol)
DMA FIFO
: 4720Bytes
•
Management ORB fetch command/Linked
Command ORB fetch protocol command/Auto
address increment DMA both of direct/indirect
addressing(SBP2 Protocol)
1.
Introduction
1.1.
Description
The TSB43LV81 provide a high-performance IEEE1394-1995 and IEEE1394.a interface with capability transfer and
receive up to 400Mbps proper-formatted packet. The TSB43LV81 have high-performance internal SBP-2 Protocol
engine, and it can provide high speed ORB exchange between SBP-2 initiators and own node. That means this
TSB43LV81 act as SBP-2 target node. Data packet FIFO has 4096Byte at maximum and Command FIFO has 512Byte at
maximum.
The TSB43LV81 can be used for another purpose such as DPP (Direct Printer Protocol) by address sorting for received
packet. Address filtering for in coming write request packet can correctly sort data packet that sent by peer DPP devices.
Both two protocols could be existing in this TSB43LV81 in same time, and internal ConfigRom CSR can correctly
response for peer Initiator or DPP device.
By above internal high performance feature, external controller can easily make SBP-2 target device and DPP devices.
This document is not intended to serve as tutorial on the 1394, SBP-2, and DPP protocol. User should refer each
documentation.
PRODUCTION DATA information is current
as of publication date. Products conform to
specifications per the terms of Texas
Instruments standard warranty. Production
processing does not necessarily include testing
of all parameters.
Page 1
Copy right ©1999, Texas Instruments Japan
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Terminal Assignments
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
TSB43LV81
(TOP VIEW)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
AUX[0]
AUX[1]
DVSS
AUX[2]
DVSS
AUX[3]
DVDD
AUX[4]
AUX[5]
DVDD5
AUX[6]
AUX[7]
AUX[8]
DVSS
AUX[9]
DVSS
AUX[10]
AUX[11]
DVDD
CNA
PD
LPS
DVSS
TM
CPS
DVSS
DVDD5
MODE[0]
MODE[1]
M8M16
DVDD
DVSS
MUXMODE
CLKSEL
BDICLK
NCLKOEN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
ALE
XCS
XRESETL
DVDD5
DVSS
AGND
AGND
AVDD
AVDD
TPBTPB+
AGND
TPATPA+
TPBIAS
AGND
AGND
R0
R1
AVDD
AVDD
DVDD
DVSS
DVSS
FLT0
FLT1
PLLV
PLLG
PLLG
DVSS
X0
X1
DVSS
DVDD5
XRESETP
DVDD
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
DVDD
XWR
XRD
WAIT
DVSS
DVDD5
DVSS
DA[15]
DA[14]
DA[13]
DA[12]
DVDD
DA[11]
DVSS
DA[10]
DA[9]
DA[8]
DVSS
DA[7]
DA[6]
DA[5]
DA[4]
DVSS
DVDD
DA[3]
DA[2]
DA[1]
DA[0]
DVSS
XINT
DVSS
BDIO15
BDIO14
DVDD5
BDIO13
BDIO12
1.2.
Figure 1-1. Terminal Assignments
Page 2
DVSS
BDIO11
BDIO10
BDIO9
BDIO8
DVSS
DVDD
BDACK
DVSS
BDIO7
BDIO6
BDIO5
BDIO4
DVSS
BDIO3
BDIO2
BDIO1
BDIO0
DVSS
DVDD5
BDOEN
BDOAVAIL
BDIEN
BDIBSY
DVSS
DVDD
BDOF2
BDOF1
BDOF0
DVSS
BDIF2
BDIF1
BDIF0
DVSS
ATACK
NCLKOUT
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
1.3.
Terminal Functions
1.3.1.
AUX PIN USAGE vs. MODE[1:0]
The Signals in the AUX vs. MODE are defined as follows:
Both internal LINK and PHY work on NORMAL mode. Only PHY functions on PHY-Mode. Link functions under
LINK-Mode.
MODE[1:0]
00
01
10
NAME
PIN
I/O
NORMAL
PHY-MODE
LINK-MODE
(only PHY active)
(only Link active)
AUX[0] (Note-2)
1
I/O
HiZ
CTL0
D7
AUX[1] (Note-2)
2
I/O
HiZ
CTL1
D6
AUX[2] (Note-2)
4
I/O
HiZ
D0
D5
AUX[3] (Note-2)
6
I/O
HiZ
D1
D4
AUX[4] (Note-2)
8
I/O
HiZ
D2
D3
AUX[5] (Note-2)
9
I/O
HiZ
D3
D2
AUX[6] (Note-2)
11
I/O
HiZ
D4
D1
AUX[7] (Note-2)
12
I/O
HiZ
D5
D0
Powerclass/CycleIn (Note-1)
AUX[8] (Note-2)
13
I/O
D6
CTL1
Powerclass/CycleIn (Note-1)
AUX[9] (Note-2)
15
I/O
D7
CTL0
Powerclass/CycleIn (Note-1)
AUX[10] (Note-2)
17
I
LREQ
SCLK
AUX[11] (Note-2)
18
O
OPEN (pull down)
SCLK
LREQ
Note-1) AUX[8:10] input mean PowerClass [2:0], Internal PHY read this value at Power Up Reset. (input)
Note-2) These input has BUS holder circuit for isolation by cap.
1.3.2.
MicroController/MicroProcessor Interface Definition
The Signals in the MicroController/MicroProcessor Interface are defined as follows:
NAME
PIN
I/O
DESCRIPTION
XCS
ALE
XRD
XWR
XINT
XWAIT
ADDR[7:0]
110
109
106
107
79
105
-
I
I
I
I
I/O
O
I/O
DATA[15:0]
M8M16
MUXMODE
30
33
I/O
I
I
Chip select.
Address Latch En. Ignored when not DA mux mode.
Read cycle Enable.
Write cycle Enable.
Interrupt
Wait.
Address
(DA[7:0] for 8bits mode, BDIO[15:8] for 16bits parallel mode)
Data (DA [15:8] for 8bits mode DA[15:0] for 16bit mode)
Bit width select. Set HI is 16bit mode.
Mode selects. Set HI is Data Address multiplex mode.
Page 3
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
1.3.3.
MISC
NAME
MODE[1:0]
XRESETP
XRESETL
TM
1.3.4.
PIN
29,28
143
111
24
I/O
I
I
I
I
DESCRIPTION
Chip mode select. (NORMAL/PHY/LINK)
Phy reset. Reset for LINK block.
Link reset. Reset for PHY block.
Test mode. Should be Low for all time.
Physical Layer Port
The Signals in the Physical Layer Interface are defined as follows:
NAME
CPS
TPBIAS
R1
R0
TPBTPB+
TPATPA+
X0
XI
FLT1
FLT0
PD
CAN
Contend/LPS
PIN
25
123
127
126
118
119
121
122
139
140
134
133
21
20
22
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I
Note: All Pins in this table are reserved for first sample.
Page 4
DESCRIPTION
Cable Power Supply
TPBIAS Output
Current setting resistor
Current setting resistor
Twisted pair cable B negative signal
Twisted pair cable B positive signal
Twisted pair cable A negative signal
Twisted pair cable A positive signal
Crystal oscillator
Crystal oscillator
PLL filter
PLL filter
Power-down input
Cable Not Active output
LPS for PHY Mode, Contend for LINK Mode and Normal
Mode
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
1.3.5.
DMA/BULKY DATA INTERFACE
NAME
BDICLK
BDIBSY/BDREQ(SCSI)
BDIF[2:0]
BDIEN/BDWR(SCSI)
BDIO[15:0]
BDOF[2:0]
BDOEN/BDRD
BDOAVAIL/BDRW(SCSI)
NCLKOEN
CLKSEL
DESCRIPTION
DMA clock (note-1)
DMA input busy / DMA request
DMA input flag (indicate the order of input data on stream)
DMA input enable
DMA data (8bit: BDIO[7:0] )
DMA output flag (indicate the order of output data on stream)
DMA output enable
DMA output avail / (DMA R/W indicator at SCSI mode)
BD clock output enable (hi:enable)
BD clock select, Set Low use BDICLK
Hi : use internal clock (no need to connect BDICLK)
BDACK
65
DMA acknowledge
ATACK
38
O
ATAPI acknowledge
NCLKOUT
37
O
24.576MHz clock output
note-1) Any frequency is OK. Max freq = 40MHz. It’s not required matching same freq to transfer speed.
1.3.6.
PIN
35
49
40,41,42
50
44,45,46
52
51
36
34
I/O
I
O
I
I
I/O
O
I
O
I
I
BDIF
8-bit Bulky
BDIF[2:0]
011
111
101
001
Comment
8-bit data except last block on packet
8-bit data of last on packet
Reset
No data
16-bit Bulky
BDIF[2:0]
011
000
010
111
100
110
101
001
Comment
8-bit data except last block on packet (Upper)
8-bit data except last block on packet (Lower)
16-bit data except last block on packet
8-bit data of last on packet (Upper)
8-bit data of last on packet (Lower)
16-bit data of last block on packet
Reset
No data
1.3.7.
BDOF
BDIF[2:0]
010
110
011
111
100
Page 5
Comment
8-bit data except last block on packet
8-bit data of last on packet
16-bit data except last block on packet
16-bit data of last on packet
No data
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
1.3.8.
POWER SUPPLIES
NAME
PIN
DVSS
DVDD5
3,5,14,16,23,26,32,39,43,48,54,
59,64,67,72,78,80,86,91,95,102
,104,113,131,132,,138,141,
7,19,31,47,66,85,97,108,130,14
4,
10,27,53,75,103,112,142,
AGND
AVDD
PLLV
PLLG
114,115,120,124,125
116,117,128,129,
135
136,137
DVDD
Page 6
I/O
DESCRIPTION
Digital ground
Digital power supply
5VVdd 5V-tolerant
(input 3.3V when not use 5V
control signal to input pin)
Analog ground
Analog power supply
PLL power supply
PLL ground
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
2.
Architecture
2.1.
Block Diagram
AutoResp
MICRO
I/F
Packet
Distributer
ConfigROM
CFR
FOX
TRMgr
1394.a
Link_CORE
Packetizer
PHY
I/F
BDIf
Bdffifo
1394.a
PHY
Figure 2-1. Block Diagram
Page 7
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
2.1.1.
Physical Interface
The Physical (PHY) interface provides Phy-level service to the LINK layer service. In normal usage, this interface is
connected to internal PHY, but this interface module also allows connecting external PHY. This is useful when multiple
port PHY or Isolation is required.
2.1.2.
LINK_Core (1394.a)
The LINK_Core provide LINK layer service such as transmit and receive correctly formatted IEEE1394-1995 and
IEEE1394.a Asynchronous packets. Also generate and inspect the 32-bits cyclic redundancy check (CRC).
This LINK Core doesn’t have capable Isochronous Service.
2.1.3.
ConfigROM
The ConfigROM module support Auto Response service for Config ROM read request. And also record transaction
history. This module has 528byte of random access memory. ConfigROM provide Configuration ROM that required for
IEEE-1212 standard and Host controller can load its data during node initialization. Before all ConfigROM data is
loaded, LINK_Core return Ack_Tardy to all read requests for this address. Once initialized, ConfigROM is accessible by
peer Node read request.
Log module provides transaction history and has loop FIFO architecture.
Hostcontroller can read most recent transaction packet history that transmitted and received by this node.
(Note) Log Mode is disabled when ConfigRom or Status accesses.
Hostcontroller can set each memory size for above two modules. Refer to CFR 0x8C, 0xF8 and 0xFC for more
information.
2.1.4.
AutoResp
The AutoResp module provide auto packet response service for in-coming request packet.
This AutoResp work for ConfigROM read request, Agent State read request, and error response packet for Un-expected
packet. Some sort of auto error response packet could be disable by control bit for various protocols.
2.1.5.
MICRO I/F
The MICRO I/F module provides Hostcontroller interface. This module could be accessed by 8/16-bit access both of data
address multiplex, 8 bit address data parallel access, and also 16 bit data/8 bit address parallel access when using BDOx
line as address line. This interface has Indian programmable access, and allows most MicroController can access CFR
easily. Refer to section 3 for more information.
2.1.6.
CFR
The CFR(Configuration Resistor) provide most of control bits and also hostcontroller monitor for this node.
Refer to section 3 for more information.
2.1.7.
FOX
The FOX module provide Faster ORB exchanger (FOX) function and support Management ORB and also Command
block ORB transaction. In SBP-2 protocol, target has to read ORB packet from initiators.
This FOX module automatically read both of Management ORB and Command block ORB from initiator when Initiator
requested. Once Management Agent address (CFR 0x48) and other information is set, Hostcontroller does not
have to access each packet until getting ORB packet. Linked Command block ORB is automatically fetched each by each
and hardware can emulate up to 4 Agents.
Page 8
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
This module have 2 FIFO modules for Management ORB and Command block ORB for both of transmit and receive
packet. Refer to CFR from 0x44 to 0x6C for more detail.
2.1.8.
Packet Distributor
The Packet Distributor module provides packet routing service for each FIFO module.
When SBP-2 mode, all of request packet and response packet have property and rutting to correct FIFO, and also sent to
corresponding initiators. W hen DPP mode, Packet Distributor filtering request packet by its addressing and save it into
correct receive FIFO. Refer to CFR definition for more detail.
2.1.9.
TRMgr
The TRMgr(Transaction Manager) module provide transaction control service which control packet transmit Priority
between control packet and Data packet. Management is simple first in first type control, so, any packet Transmit request
for cable is sent by its order. This module also control split transaction management and busy retry control. If
acknowledge packet for the sent packet is any busy code, module retry to send packet until the packet succeed to transmit
or busy time out. And also, if acknowledge packet for the sent packet is ack_pending, then module start split transaction
timer and waits response packet. If node did not receive Response packet until split transaction time out limit, then the
module set error code and set interrupt.
See CFR specification for more detail.
2.1.10. Packetizer
The Packetizer module provide packetization for transmit packet. The data stream from BDIF and Bdffifi is split into
small packet that meet SBP-2 requirement. Read request or write request header is attached for each packet and each
header has correctly incremented destination address. These transaction also do busy retry and split transaction timer
control if required. Refer to section for more detail.
The packetizer also provide, AutoPage Table Fetch service, Internal Auto Fetch module send Read Request to page
present address each by each, and DMA automatically send Data to requested address that set by Page Table Element. At
the end of Packetizer, if entire DMA function is completed successfully, then Status Block Packet is automatically sent by
DMA.
2.1.11. Bdffifo
The Bdffifo module provide data packet FIFO for SBP-2 read response packet and also write request packet. FIFO size is
4736 byte max including received header space, and FIFO size for each Tx and Rx is programmable that set by
Hostcontroller via CFR. Refer to CFR definition for more detail.
2.1.12. BDif
The BDif module provides data interface between external host DMA and internal FIFO (Bdfifo).
Data is also could be read by Micro I/F in some condition if required. This interface has several mode such as 8/16 bit
width also asynch/synchronous mode. Refer to Bulky interface section for more detail.
Page 9
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
2.2.
System block diagram
Addr
CPU
AUX
ADDR
Data 8 or 16
external
PHY
DA
WR
WR
RD
RD
43LV81
BDIO
BDIEN
1394
Memory
BDOEN
8 or 16
DMA
controller
Figure 2-2. System block configuration example1 (Async)
Address
decode
CS
ADDR
CPU
AUX
CS
ADDR
1394
43LV81
Data
DA
WR
WR
RD
RD
BDACK
BDIO
BDWR
BDRD
CS
Figure 2-3. System block configuration example2 (SCSI)
Page 10
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
3.
Bit/Byte Order
In this document, the address is big endian and bit 0 is the most significant bit.
MSB
0
1
LSB
2
3
4
5
6
7
8
9
byte0(note)
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
byte1(note)
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
byte2(note)
2
6
2
7
2
8
2
9
3
0
3
1
byte3(note)
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Octlet0(note)
D
A
1
5
3.1.
D
A
1
4
D
A
1
3
D
A
1
2
D
A
1
1
D D D D D D D D D D D D D
A A A A A A A A A A A A A
1 9 8 7 6 5 4 3 2 1 0 1 1
5 4
0
quadlet
Octlet1(note)
D
A
1
3
D
A
1
2
D
A
1
1
D D D D D D D D D D D
A A A A A A A A A A A
1 9 8 7 6 5 4 3 2 1 0
0
Addressing
Addressing in this CFR is in byte. The address is made in the below pin order.
Address[7:0] = ( DA7 , DA6, DA5, DA4, DA3 , DA2, DA1, DA0 )
Note) Write 0xFFFF_FFFF to 0x00 adder to make Byte Endian swap for this address.
3.1.1.
Write access
When the host (MicroController) writes a data on CFR, the quadlet access is only permitted.
It should access with each byte or each octlet but any orders are acceptable.
Example)
Write order for 8 bit access
Write order for 16 bit access
3.1.2.
: byte3 -> byte1 -> byte2 -> byte0
: byte0 -> byte1 -> byte3 -> byte2
: octlet0 -> octlet1
: octlet1 -> octlet0
Read Access
CFR permits the host to read with the byte/octlet access. The host interface brings a quadlet data by the first read of a
byte(octlet) in a quadlet. If the next read by the host is for the other byte (octlet) in the same quadlet, the host interface
shall give the byte (octlet) data in it.
Otherwise, if the next read is for a byte (quadlet) in the other quadlet, the host interface brings the quadlet data newly and
shall give a new byte(octlet) data in it.
Example)
Read order for 8 bit access
: byte3 -> byte1 -> byte2 -> byte0
: byte0 -> byte1 -> byte3 -> byte2
Read order for 8 bit access
: byte1 -> byte1
(These byte1 are read from two different quadlet)
Page 11
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
3.2.
CFR (Configuration Resistor) Definitions
CFR specification in this datasheet is defined as below example.
MSB
LSB
address
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
Name
reg-1
reg-2
Read/Write
R/W
R/O
Default
16’h0000
16’hFFFF
BusReset
16’h0000
U
2
6
2
7
2
8
2
9
Table 3-1. Example CFR Map
Read/Write : "Read or write effect"
R/O : The host can only read. Write by the host is not effective.
R/W : The host can read and write.
W/O : The host can only write. The value read by the host has no meaning.
S/C : It shall be set as soon as the host writes '1' and then be cleared automatically after being proceeded.
N/A : The host shall get a meaningless value when it reads from it or writes on it.
CRW : The host can read or write conditionally.
Default
: "Default value after a power-on reset"
BusReset : "Value set after a bus reset"
U : Unchanged
A : Automatically set to appropriate value.
CC : Conditionally changed.
NOTE: For most registers, the initial value after a power-on reset or bus reset is the same.
When the initial values differ, the two initial values are explicitly illustrated.
NOTE : If RegRW is set, some CFR bits can be written. But it should not be set in the normal operation as it is
test mode for production and other. That shall not be referred to in this specifications.
Page 12
3
0
3
1
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
Root
1
7
1
8
1
9
2
0
Reserved
2
1
2
2
2
3
AckErr
2
4
2
5
2
5
2
6
2
8
2
9
3
0
3
0
3
1
3
1
AckVld
TSB43LV81
2
7
Reserved
Rev
2
9
Prio_Budget
2
8
CFRContID
2
7
PhyRxData
2
6
ATAck
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
5
2
4
Cycle_Offset
2
3
TMODE
4
2
2
NodeSum
2
1
MON
3
2
0
Budget_
Counter
1
9
Reserved
2
1
8
FaGap
TxRdy
CyDne
CyPnd
CyLst
CyArbF
Reserved
ATFEnd
ARFRxd
MOREnd
CORend
DTFEnd
DRFEnd
TxExpr
AgntWr
1
1
7
BRFErr_
Code
1
6
DRHUpdate
FaGap
TxRdy
CyDne
CyPnd
CyLst
CyArbF
Reserved
ATFEnd
ARFRxd
MOREnd
CORend
DTFEnd
DRFEnd
TxExpr
AgntWr
ErrResp
StErpkt
SplTrEn
RetryEn
Ackpnd
Reserved
CyMas
Reserved
CyTmrEn
DMclr
RxUnexp
RUEsel
0
1
5
DRHUpdate
DisAR
Reserved
Reserved
C
LKON
LPS
Reserved
Version
1
4
State_Monitor
1
3
DisAgentID
MAACKconf
Cycle_Count
1
2
NodeNum
1
1
PhyRgData
1
0
SntRj
PhRRx
IFAcc
HdrErr
TCErr
CySec
Cyst
Reserved
Reserved
Ping_Timer
9
SntRj
PhRRx
IFAcc
HdrErr
TCErr
CySec
Cyst
Reserved
0x00
Version
8
Reserved
0x04
Misc.
7
0x08
Control
6
0x0C
Interrupt
5
0x10
Interrupt
Mask
4
BusNumber
3
PhyRxAd
Reserved
IDVal
RxSId
RSIsel
Reserved
Bsy0
TrEn
Reserved
ACArbOn
CncatEn
Reserved
RstTr
Seconds_Count
2
Reserved
Int
PhInt
Breset
CmdSlf
Endslf
Phypkt
IDLIns
IsolDis
BudgEn
Enlghl
regRW
AgntStWr
Reserved
AgRdy0
AgRdy1
AgRdy2
AgRdy3
RstAR
RstTrM
Reserved
0x14
Cycle
Timer
1
PhyRgAd
Int
PhInt
Breset
CmdSlf
Endslf
Phypkt
0x18
0
Reserved
Diagnostics
0x1C
Monitor
0x20
Phy
Access
0x24
BusReset
Page 13
Rdpy
Wrpy
Reserved
Reserved
MRFAEm
MRFEmp
MTQEmp
ARFAEm
ARFEmp
ATFAEm
ATFEmp
5
6
7
CTQ1Av
CTQAem
CTQEmp
8
8
9
9
1
0
1
0
1
1
1
1
ARFThere
MRFThere
Reserved
1
3
1
3
Reserved
1
2
1
2
CRFThere
1
4
1
4
Reserved
CORB_
Size
1
5
ARFCD
Reserved
Reserved
Reserved
ARF_Size
ATF_Size
2
7
2
8
2
8
CTQ_Size
2
6
2
7
CRF_Size
Reserved
2
5
Reserved
2
4
2
6
Reserved
2
3
2
5
Reserved
RtryLmt
2
4
ATFClr
2
2
2
3
ARFClr
2
1
2
2
Reserved
MTQClr
2
0
2
1
Reserved
MRFClr
1
9
2
0
CTQClr
1
8
1
9
CRFClr
RetryInterval
1
8
2
9
2
9
ORBTime
3
0
3
0
CORB_
Prior
MRFCD
1
7
1
7
CAg0Rdy
CAg1Rdy
CAg2Rdy
CAg3Rdy
CRFCD
1
6
1
6
Management_Agent_offset
1
5
CAg0Vld
Cag1Vld
Cag2Vld
Cag3Vld
DrBSnp
DrBFtEn
CnxFtEn
CShtFmt
TSB43LV81
Reserved
4
CRFAEm
CRFEmp
Reserved
3
Reserved
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Reserved
2
7
ATFFul
ATFAFl
1
6
ARFFul
ARFAFl
SplitTimeOut
5
MTQFul
0
4
MRFFul
MRFAFl
0x28
Time Limit
3
0x2C
ATF Status
2
0x30
ARF Status
CTQFul
CTQAFl
0x34
MTQ
status
CRFFul
CRFAFl
0x38
MRF
Status
1
0x3C
CTQ status
0
MORB_
Prior
0x40
CRF status
0x44
ORB Fetch
Control
0x48
Management
Agent
Page 14
Reserved
MagtVld
MagtBsy
Reserved
MShtFmt
3
1
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
1
2
3
4
5
6
7
8
9
1
0
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
USTlEn
AgntVld
Reserved
WrNdID
RdNdID
AgtNmb
0x50
Agent
Control
0x54
ORB
Pointer1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
NodeID
Reserved
ORB_destination_offset_hi
0x58
ORB
Pointer2
TimrNo
TxAbrt
HldTr
RlsTr
Reserved
DrBll3
UnStEn3
Dead3
Rst3
DrBClr3
USEClr3
State3
DrBll2
UnStEn2
Dead2
Rst2
DrBClr2
USEClr2
State2
DrBll1
UnStEn1
Dead1
Rst1
DrBClr1
USEClr1
State1
DTTxEd
DRTxEd
ATTxEd
MTTxEd
CTTxEd
Reserved
ARTxEd
Reserved
DTErr
DRErr
ATErr
MTErr
CTErr
Reserved
ARErr
Reserved
DTRtry
DRRtry
ATRtry
MTRtry
CTRtry
Reserved
ARRtry
Reserved
State0
DrBll0
UnStEn0
Dead0
Rst0
DrBClr0
USEClr0
ORB_destination_offset_lo
0x5C
Agent
Status
0x60
1
2
Agent_Base_offset
Reserved
0x4C
Command
Agent
Transaction
Timer Control
1
1
Reserved
0
0x64
Destination_ID
Transaction
Timer Status1
Destination_offset_hi
0x68
Destination_offset_lo
Transaction
Timer Status2
TCode
0
Page 15
Spd
0x6C
Transaction
Timer Status3
1
2
3
4
5
Retry_
Counter
Tlabel
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
SplitTrTimer
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
0x70
Write
First
Write_First
0x74
Write
Continue
Write_Continue
0x78
Write
Update
Write_Update
0x7C
Reserved
Reserved
0x80
ARF Data
ARFRead
0x84
MRF Data
MRFRead
0x88
CRF Data
CRFRead
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
0x8C
0
Page 16
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
DTHdIs
Dpause
DRStPS
DRHStr
DRDSel
DTDSel
DRFCLr
DTFClr
Dackpnd
Drespcmp
ConfigROM_Size
DTPage
FetchSize
DRPage
FetchSize
Reserved
CheckPg
AutoPg
QuadBndry
LongBlk
QuadSend
DheadSel
DMARW
Reserved
DRFEn
DTFEn
DRpktz
DTpktz
DRSpDis
DTSpDis
0x90
DMA
Control
AR_ConfigROM_Size
RconfSnglpkt
Reserved
Configuration
ROM
Control
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
TSB43LV81
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
Reserved
DRF_Size
DRFThere
Reserved
Reserved
2
9
3
0
3
1
RcvPad
BDORst
BDIRst
BDOTris
1
9
DTAVal
DRxAck
DRAErr
1
8
Reserved
DRFEmpty
DTFAvail
Reserved
1
7
BDIMode
1
6
DTxAck
1
5
Burst
1
4
BDOMode
1
3
DTAErr
1
2
BDIDely
1
1
DTF_Size
Reserved
0xA0
DTF/DRF
Ack
1
0
DRAVal
DTFEmpty
Reserved
9
BDODely
8
MTBufSiz
7
BDOAvail
6
ATAckCtl
5
Reserved
0x98
DTF/DRF
Size
4
BIBsyCtl
BOAvCtl
BOEnCtl
BIEnCtl
BLECtl
AutoPad
3
Reserved
2
MRBufSiz
0x94
Bulky
Interface
Control
0x9C
DTF/DRF
Avail
1
PgBufSiz
0
BDAckCtl
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0xA4
DTF_First & Continue
DTF First
& Continue
0xB4
DTF
Control1
DTF Page
Size
DTF_BlockSize/
DTF_BlockCount
DTF_BlockCount/DTF_BlockSize
0
Page 17
PgTblEn
DTF Max
Payload
DTFSpd
Reserved
0xB0
DTF
Control0
DTFNotify
DRFRead
DTFNdIdval
0xAC
DRF Data
DTFClr/DTFStx
DTF_Update
DTFCTL0
DTFCTl1
0xA8
DTF
Update
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0
1
2
3
0xB8
DTF
Control2
4
5
6
7
8
9
(direct mode)
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
0 0
DRF Page
Size
PgTblEn
DRF Max
Payload
DRFSpd
DRFNotify
Reserved
DRFClr/DRFStx
DRFNdIdval
3
1
DTF_destination_offset_hi
DTF_destination_offset_lo
DRFCT0
DRFCT1
3
0
DRF_BlockSize/
DRF_BlockCount
Reserved
0xC0
DRF
Control0
1
2
DRBIdEn
DRSIdEn
DRAdrEn
(packetizer
mode)
1
1
DTF_destination_ID
0xBC
DTF
Control3
0xC0
DRF
Control0
1
0
0xC4
DRF
Control1
DRF_BlockCount/DRF_BlockSize
(packetizer
mode)
0xC4
DRF
Control1
DRF_destination_Width
(direct mode)
0xC8
DRF
Control2
DRF_destination_ID
0xCC
DRF
Control3
DRF_destination_offset_hi
DRF_destination_offset_lo
0xD0
DRF
Header0
DRF_Header0
0
Page 18
0 0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
1
2
1
3
1
4
1
5
1
6
1
7
1
8
0xD8
DRF
Header2
DRF_Header2
0xDC
DRF
Header3
DRF_Header3
0
1
2
3
4
5
6
8
9
1
0
1
1
2
3
2
4
1
2
1
3
1
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
PRESP
PSTAT
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
DTxPrio
PAck
PSTAT
PRESP
DTxSpd
DRxTlabel
Ack
AckErr
Reserved
7
DTxTlabel
Ack
AckErr
Reserved
Reserved
Reserved
STAT
(DhdSel
=11)
DRx
Header0
Page 19
RESP
STAT
(DhdSel
=10)
DRx
Header0
RESP
0xE8
(DhdSel
=01)
DTx
Header0
2
2
DRFPageCount
DRxSpd
DTFPageCount
(DhdSel
=00)
DTx
Header0
2
1
2
4
2
5
DRxPrio
0xE4
DRF
Expected
Value
Rx_Spd
0xE0
DRF Tailer
2
0
Reserved
DRF_Header1
Reserved
0xD4
DRF
Header1
1
9
DRF_
TxAck
1
1
2
6
2
7
PAck
1
0
PAckErr
9
PAckErr
8
Reserved
7
DtxTCode
6
Reserved
5
DRxTCod
e
4
Reserved
3
Fll0
2
DTxRT
1
DRxRT
0
2
8
2
9
3
0
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0xF4
0xF0
0xEC
0
2
3
(DhdSel
=00)
DTx
Header1
(DhdSel
=01)
DTx
(DhdSel
=10)
DRx
Header1
(DhdSel
=11)
DRx
(DhdSel
=00)
DTx
Header2
(DhdSel
=01)
DTx
Header2
(DhdSel
=10)
DRx
Header2
(DhdSel
=11)
DRx
Header2
(DhdSel
=00)
DTx
Header3
(DhdSel
=01)
DTx
Header3
(DhdSel
=10)
DRx
Header3
(DhdSel
=11)
DRx
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
DTx_destination_ID
DTx_destination_offset_hi
DTx Page Number
Reserved
DRx_destination_ID
DRx_destination_offset_hi
DRx Page Number
Reserved
2
9
3
0
3
1
2
9
3
0
3
1
DTx_destination_offset_lo
DTx Page length
DTx Page table hi
DRx_destination_offset_lo
DRx Page length
DRx Page table hi
DTx_data_length
DTx_extended_tcode
DTx page table lo
DRx_data_length
DRx_extended_tcode
DRx Page table lo
0
Page 20
1
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
1
3
1
4
1
5
Reserved
0xFC
Log ROM
Data
1
6
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
8
2
9
3
0
3
1
Adder
LogRead/RWAccess
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
Table 3-2. CFR List
Page 21
1
7
ROMAddr
1
2
LogThere
OR
1
1
LogCD
LogFull
1
0
Reserved
9
ROMValid
8
XLOG
7
ROMValid
6
LogRetry
ShortLog
LogClr
XLOG
5
LogARROM
4
LogDTFRq
LogDTFRs
LogDRFRq
LogDRFRs
3
LogMTQ
LogMRF
LogAgnt
LogCTQ
LogCRF
0xF8
Log/ROM
Control
(XLOG=1)
2
LogMAgnt
0xF8
Log/ROM
Control
(XLOG=0)
LogATF
LogARF
1
DTFST
DRFST
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0x00
0
1
2
3
4
5
6
7
8
9
1
0
Version
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
Version
R/O
28’h4300_810
U
Read/Write
Default
BusReset
2
9
3
0
3
1
Rev
R/O
4’h2
Table 3-3. CFR map (0x00)
Version: TI device code name of this chip.
: Revision of this chip
Rev
Note) Write 0xFFFF_FFFF to make Endian swap for Micro I/F.
1
1
1
2
1
3
Ping_Timer
N/A
R/O
Default
3’h0
1 0 1 0
9’h0
BusReset
U
U U U U
9’h0
Misc.
Read/Write
1
4
1
5
1
6
1
7
1
8
1
9
2
0
N/A
0
6’h00
A
6’h00
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
AckVld
1
0
R/O
N/A
R/O
9
Reserved
8
ATAck
7
AckErr
6
R/O
5
Reserved
4
Root
3
R/O
2
C
LKON
LPS
Reserved
1
R/O
S/C
R/W
N/A
0
Reserved
0x04
0
4’h0
3’h0
0
0
4’h0
3’h0
0
Table 3-4. CFR map (0x04)
C :Bus Manager Capable for PHY.
Refer PHY specification for more detail. This register is active when PHY is ON; even LINK is in Reset State.
LKON : Link-On output from PHY.
This register is active when PHY generate LINK_ON signal; even LINK is in Reset State. This bit is set when PHY
detect LINK_ON Packet, and cleared when write “1”. This bit will be changed during LPS is off.
LPS :Link Power Status.
Set this bit to one set internal PHY LPS signal to one.
Ping_Timer :The value of Ping Time.
When Ping Packet transmitted by this node, and received Ping Response, this time is updated.
Root
Page 22
:Whether this node is root.
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
When this node is root, Root shows 1.
When this node is not root or a bus reset is being initiated, Root shows 0.
AckErr : "Ack Error"
Whether the last Ack received for the packet transmitted from ATF has any errors.
When the Ack didn't received nor had parity error and length error, AckErr shows 1.
When the Ack has no error or any Ack has not been received yet, AckErr shows 0.
ATAck : "Address transmitter acknowledge received"
The last Ack received for the packet transmitted from ATF.
The value is updated each time the Ack is received.
AckVld : "Ack Valid"
Whether ATAck has been already read.
When ATAck has not read yet, AckVld shows 1.
When ATAck has already read, AckVld shows 0.
BusReset
7
8
9
1
0
1
1
0 1 0 0 0 1 0 0 0 0 0
3’h0
N/A
N/A
A
R/W
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
R/W
2
3
2
4
2
5
0 0 1 1 0 0 1 0 1 0 0 0
U
Table 3-5. CFR map (0x08)
: "ID valid"
IDVal
When the information of 0x24 is valid, IDVal shows 1.
: "Received self-identification(self-ID) packets"
RxSId
When RxSId is set to 1, the self-ID packets generated by Phy during bus
initialization are received and placed into DRF or LOG as a single packet.
When RxSId is set to 0, the self-ID packets are not placed anywhere.
: "Select either Log or DRF to be placed received self-ID packets"
RSIsel
When RSIsel is set to 1 and RxSId is set to 1, the self-ID packets are placed into DRF.
When RSIsel is set to 0 and RxSId is set to 1, the self-ID packets are placed into Log.
: "Busy control"
Bsy0
Whether the receiver sends Ack_Busy_X to all incoming packets.
When Bsy0 is set to 1, Ack_Busy_X is sent.
Page 23
2
2
R/W
6
N/A
R/W
N/A
R/W
S/C
5
ErrResp
StErpkt
SplTrEn
RetryEn
Ackpnd
Reserved
CyMas
Reserved
CyTmrEn
DMclr
RxUnexp
RUEsel
4
Reserved
3
N/A
R/W
R/W
N/A
S/C
Default
2
R/W
Read/Write
1
IDVal
RxSId
RSIsel
Reserved
Bsy0
TrEn
Reserved
ACArbOn
CncatEn
Reserved
RstTr
Control
0
R/O
0x08
U
2
6
2
7
2
8
2
9
3
0
Prio_Budget
R/W
6’h0
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
When Bsy0 is set to 0, Ack_Busy_X is sent only when necessary according to the normal busy/retry protocol.
: "Transaction enable"
TrEn
When TrEn is set to 1, the transmitter arbitrates and sends packets, the receiver receives packets.
When TrEn is set to 0, the transmitter and the receiver is disableed.
AcArbOn : "Accelerated arbitration on"
When AcArbOn is set to 1, the accelerated arbitration is enabled.
When AcArbOn is set to 0, the accelerated arbitration is disabled.
caution) This function is not checked yet.
CncatEn : "Concatenated transaction enable"
When CncatEn is set to 1, concatenated transaction is supported.
When CncatEn is set to 0, concatenated transaction is not supported.
caution) This function is not checked yet.
: "Reset transaction"
RstTr
When RstTr is set to 1, the entire transaction in ATF, ARF and AGENT resets synchronously.
DRF. This bit clears itself to 0 after the reset.
No effect to DTF and
ErrResp : "Response for error packets"
When ErrResp is set to 1, the response packets are returned for packets with any errors.
When ErrResp is set to 0, the acknowledge is returned for packets with any errors.
: "Store error packets"
StErPkt
When StErPkt is set to 1, packets with any errors are stored. Otherwise, packets with any errors
is not stored.
SplTrEn : "Split transaction enable"
When SplTrEn is set to 1, the timer of ATF attempts split transaction for receiving Ack_pending
and can't transmit any packets till the response packet is received or split-timeout occurs.
When SplTrEn is set to 0, the timer does not wait for the response packet.
RetryEn : "Automatic retry enable"
When RetryEn is set to 1, all the transmitter attempts retry automatically for receiving
Ack_Busy_X, Ack_Busy_A or Ack_Busy_B.
When RetryEn is set to 0, any transmitters do not retry automatically.
: "Ack pending enable"
AckPnd
When AckPnd is set to 1, the receiver sends Ack_pending instead of ack_complete to
the write request packets.
When AckPnd is set to 0, the receiver sends ack_complete to the write request packet.
Not effect to DRF function
: "Cycle master"
CyMas
When CyMas is set to 1 and this chip is attached to the root Phy, the cyclemaster function is enable.
When CyMas is set to 0 and this chip is attached to the root Phy, the cyclemaster function is disable.
CyTmrEn : "Cycle-timer enable"
When CyTmEn is set to 1, the cycle_offset field increments.
Page 24
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
When CyTmEn is set to 0, the cycle_offset field does not increment.
: "All the states in DMA block clear"
DMclr
When DMClr is set to 1, all the states in DMA block are reset synchronously. Before to set DMClr, should clear DTF and
DRF also.
This bit clears itself to 0 after that.
RxUnexp : "Received the unexpected response packets"
When RxUnexp is set to 1, the unexpected response packets are received and placed into ARF or DRF.
When RxUnexp is set to 0, the unexpected response packets are not received.
: "Select either ARF or DRF to be placed unexpected response packets"
RUEsel
When RxUnexp is set to 0, RUEsel is invalid.
When RxUnexp is set to 1 and RUEsel is set to 1, the unexpected response packets,
the write request packets to read only registers, the read only request packets to
write register and the write request for configuration ROM is placed into DRF.
When RxUnexp is set to 1 and RUEsel is set to 0, they are placed into ARF.
Prio_Budget : "Priority budget counter"
Prio_Budget value loads priority budget counter.
Default
BusReset
N/A
8
9
1
0
1
1
1
2
1
3
1
4
1
5
S/C
1
6
1
7
1
8
1
9
2
0
2
1
2
2
32’h0000_0000
U
Table 3-6. CFR map (0x0C)
: "Interrupt"
Int
Int contains the value of all interrupt bits and interrupt mask bits ORed logically together.
Inverse of this bit is connected to XINT bit ( pin#70 )
When the logical ORed value of all (INT & MASK) is true, Int shows 1.
When the logical ORed value of all (INT & MASK) is not true, Int shows 0.
PhInt : "Phy chip Interrupt"
When the Phy layer signals an interrupt to this Link chip, PhInt becomes 1.
See physical layer specification in detail.
When the host writes "1" on PhInt, it is cleared to 0.
Page 25
2
3
N/A
7
S/C
S/C
6
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
FaGap
TxRdy
CyDne
CyPnd
CyLst
CyArbF
Reserved
ATFEnd
ARFRxd
MOREnd
CORend
DTFEnd
DRFEnd
TxExpr
AgntWr
5
DRHUpdate
4
SntRj
PhRRx
IFAcc
HdrErr
TCErr
CySec
Cyst
Reserved
3
Reserved
2
N/A
Read/Write
1
Int
PhInt
Breset
CmdSlf
Endslf
Phypkt
Interrupt
0
R/O
0x0C
S/C
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Breset : "Bus reset"
When the Phy layer initializes or detects a bus reset, the Breset becomes 1.
When the host writes "1" on Breset, it is cleared to 0.
CmdSlf : "Command reset received"
When the receiver is sent a quadlet write request addressed to the RESET_START(FFFF_F000_000C) CSR register,
Cmdrst becomes 1.
When the host writes "1" on Cmdrst, it is cleared to 0.
Command Reset Packet also started into ARF.
Endslf : "End of the self-ID process"
When the link layer detects the end of Self-ID process, the Endslf becomes 1.
When the host writes "1" on Endslf, it is cleared to 0.
Phypkt : "Phy packet detect"
When the receiver received Phy packet, thePhyPkt become “1”.
When the host write ”1” on PhyPkt, it is clear to “0”. ex)Receive Remote access packet, LinkON packet….
SntRj : "Busy acknowledge sent by receiver"
When the receiver is forced to send a Ack_Busy_X to a incoming packet
because the FIFO overflowed, SntRj becomes 1.
When the host writes "1" on SntRj, it is cleared to 0.
PhRRx : "Phy register information received"
When a Phy register value is transferred to the Phy_Access register from the Phy interface,
PhyRRx becomes 1.
When the host writes "1" on PhRRx, it is cleared to 0.
IFAcc : “Invalid FIFO Access”
When IFAcc is set, invalid ATF access sequence is violated.
HdrErr : "Header error"
When the receiver detects a header CRC error on an incoming packet that may have been
addressed to this node, HdrErr becomes 1.
When the host writes "1" on HdrErr, it is cleared to 0.
note) We do not test this function yet.
TCErr : "TCode error"
When the transmitter detects an invalid TCode in the data, TCErr becomes 1.
When the host writes "1" on TCErr, it is cleared to 0.
CySec : "Cycle second"
When the cycle-second field in the cycle-timer register incremented, CySec becomes 1.
When the host writes "1" on CySec, it is cleared to 0.
: "Cycle started"
CySt
When the transmitter sends or the receiver receives a cycle-start packets, CySt becomes 1.
When the host writes "1" on CySt, it is cleared to 0.
Page 26
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
DRHUpdate : "DRF Header Update"
When Host read out DRF data and packet header is been read, this bit is set .
When the Host writes “1” on DRHUpdate, it is clear to 0. This bit is no meaning if DRHStr(0x90) is set.
FaGap : "Fair Gap"
When the serial bus has been idle for an arbitration reset gap, FaGap becomes 1.
When the host writes "1" on FaGap, it is cleared to 0.
TxRdy : "Transmitter ready"
When the transmitter is idle and ready, TxRdy becomes 1.
When the host writes "1" on TxRdy, it is cleared to 0.
CyDne : "Cycle done"
When an arbitration gap is detected on the bus after the transmission or reception of a cycle-start packet,
CyDone becomes 1.
When the host writes "1" on CyDne, it is cleared to 0.
CyPnd : “Cycle pending”
When Cypnd is set, the cycle timer offset is set to 0 (roll over or reset) and remains set until the isochronous cycle end.
: "Cycle lost"
CyLst
When the cycle timer rolls over twice without the reception of a cycle-start packet,
CyLst becomes 1.
When the host writes "1" on CyLst, it is cleared to 0.
CyArbF : "Cycle arbitration failed"
When the arbitration to send the cycle-start packet fails, CyArbF becomes 1.
When the host writes "1" on CyArbF, it is cleared to 0.
ATFEnd : "ATF Transaction End"
When the transmitter completed transmission(received Ack_comp, Response packet, Timeout), ATFEnd becomes 1.
The host can read the end status from Transaction Timer Control(0x60) and
Transaction Timer Status(0x64-0x6C) registers until the next process begins.
When the host writes "1" on ATFEnd, it is cleared to 0.
This bit will be set when receiving response in ARF which sent requesting by itself.
When receiving independent packet in ARF, It’ll be set ARFRxd.
ARFRxd : "ARF received data"
When the receiver confirms in the ARF, ARFRxd becomes 1. But this bit is not set for Response Packet.
When the host writes "1" on ARFRxd, it is cleared to 0.
MOREnd : "Management ORB fetch completed"
When the process of fetching Management ORB is completed, MOREnd becomes 1.
The host can read the end status from Transaction Timer Control(0x60) and
Transaction Timer Status(0x64-0x6C) registers until the next process begins.
When the host writes "1" on MOREnd, it is cleared to 0.
CORend : "Command block ORB fetch completed"
When the process of fetching Command block ORB is completed, CORend becomes 1.
The host can read the end status from Transaction Timer Control(0x60) and
Page 27
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Transaction Timer Status(0x64-0x6C) registers until the next process begins.
When the host writes "1" on CORend, it is cleared to 0.
DTFEnd : "DMA transaction from DTF completed"
When the transactions of all blocks from DTF are completed successfully or the transactions
of any blocks from DTF are completed with any errors, DTFEnd becomes 1.
The host can read the end status from Transaction Timer Control(0x60) and
Transaction Timer Status(0x64-0x6C) registers until the next process begins.
When the host writes "1" on DTFEnd, it is cleared to 0.
DRFEnd : "DMA transaction from DRF completed"
When the transactions of all blocks from DRF are completed successfully or the transactions
of any blocks from DRF are completed with any errors, DRFEnd becomes 1.
The host can read the end status from Transaction Timer Control(0x60) and
Transaction Timer Status(0x64-0x6C) registers until the next process begins.
When the host writes "1" on DRFEnd, it is cleared to 0.
: "Transmitter is expired"
TxExpr
When the transmitter fails to transfer the packets, TxExpr becomes 1.
When the host writes "1" on TxExpr, it is cleared to 0.
AgntWr : "Agent is written"
When any registers of any Agents (management/command) is written, AgntWr becomes 1.
The host can read State, DrBll and UnSEn from Agent_Status(0x5C)
and destinationID and ORB_offset_hi from ORB Pointer(0x54, 0x58).
When the host writes "1" on AgntWr, it is cleared to 0.
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
Default
1
31’h0000_0000
BusReset
U
U
Table 3-7. CFR map (0x10)
All R/W bit : When Each bits is set to 1, it affects Int in Interrupt(0x0c).
When Each bits is set to 0, it does not.
Page 28
N/A
R/W
R/W
N/A
N/A
R/O
Read/Write
R/W
2
9
3
0
3
1
FaGap
TxRdy
CyDne
CyPnd
CyLst
CyArbF
Reserved
ATFEnd
ARFRxd
MOREnd
CORend
DTFEnd
DRFEnd
TxExpr
AgntWr
3
DRHUpdate
2
SntRj
PhRRx
IFAcc
HdrErr
TCErr
CySec
Cyst
Reserved
1
Reserved
Interrupt
Mask
0
Int
PhInt
Breset
Cmdrst
Endslf
Phypkt
0x10
R/W
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0x14
0
Cycle
Timer
1
2
3
4
5
6
7
8
9
1
0
Seconds_Count
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
Cycle_Count
Read/
Write
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
8
2
9
3
0
3
1
Cycle_Offset
R/W
Default
7’h00
13’h0000
12’h000
BusReset
U
Table 3-8. CFR map (0x14)
Seconds_Count : "Cycle secounds count"
Seconds_Count is incremented When Cycle Count is rolled over. The host also writes the value.
: "Cycle Count" counting 125 [us]
Cycle_Count
Cycle_Count is incremented when Cycle_Offset is rolled over. The host also writes the value.
1
2
R/W
R/O
S/C
Default
BusReset
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
4h’0
Page 29
2
5
2
6
2
7
R/W
R/W
U
: "Idle insert"
IDLIns
NOTE! IDLIns is used in the test mode and should not be set at the normal operation.
BudgEn : “Budget Counter Enable”
2
4
R/O
Table 3-9. CFR map (0x18)
IsolDis : "Isolate Disable”
When set IsoDis, Phy LINK Interface disable BusHolder.
2
3
Budget_
Counter
32’h0000_0000
U
2
2
TMODE
1
1
MON
1
0
Reserved
9
N/A
8
DisAR
7
DisAgentID
6
R/W
5
Reserved
4
MAAckconf
3
N/A
2
N/A
Read/
Write
1
N/A
Diagnostics
0
IDLIns
IsolDis
BudgEn
Enlghl
regRW
AgntStWr
Reserved
AgRdy0
AgRdy1
AgRdy2
AgRdy3
RstAR
RstTrM
Reserved
0x18
R./W
: "Cycle Offset" counting 40 [ns]
Cycle_Offset
Cycle_Offset is increment every 40 [ns].The host also writes the value.
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
When this bit is set, internal budget counter is enabled.
Enlghl :
NOTE! Enlghl is used in the test mode and should not be set at the normal operation.
regRW : "Register read/write access"
NOTE! regRW is used in the test mode and should not be set at the normal operation.
AgntStWr : "Agent write access"
When set Agent Wr, Agent state is Read/Write.
AgRdy0 : "Agent0 ready"
When AgRdy0 is set to 1, command block agent0 is ready to be written or read.
When AgRdy0 is set to 0, command block agent0 is not ready.
AgRdy1 : "Agent1 ready"
When AgRdy1 is set to 1, command block agent1 is ready to be written or read.
When AgRdy1 is set to 0, command block agent1 is not ready.
AgRdy2 : "Agent2 ready"
When AgRdy2 is set to 1, command block agent2 is ready to be written or read.
When AgRdy2 is set to 0, command block agent2 is not ready.
: "Agent3 ready"
AgRdy3
When AgRdy3 is set to 1, command block agent3 is ready to be written or read.
When AgRdy3 is set to 0, command block agent3 is not ready.
: "Reset autoresponse"
RstAR
NOTE! RstAR is used in the test mode and should not be set at the normal operation.
: "Reset transaction manager"
RstTrM
NOTE! RstAR is used in the test mode and should not be set at the normal operation.
: "Management Agent Ack conflict"
MAAckconf
This bit set 1, “Ack conflict” response will be responded when management agent is busy.
: “Disable Agent ID check”
DisAgentID
NOTE! DisAgentID is used in the test mode and should not be set at the normal operation.
: “Auto responser Disable”
DisAR
NOTE! DisAR is used in the test mode and should not be set at the normal operation.
Budget_Counter : “Budget Counter Value”
This field specifies the current value of internal budget counter.
: "Monitor select"
MON
NOTE! MON is used in the test mode and should not be set at the normal operation.
: "Test mode"
TMODE
NOTE! TMODE is used in the test mode and should not be set at the normal operation.
Page 30
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0x1C
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
Monitor
State_Monitor
Read/
Write
R/O
Default
State dependent
BusReset
A
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
6
2
7
2
8
2
9
3
0
3
1
Table 3-10. CFR map (0x1C)
State_Monitor : "State monitor"
NOTE! The state machine monitor for production test. Read value is beyond of this specifications.
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
PhyRgData
S/C
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
PhyRxAd
Read/
Write
5
Reserved
Phy
Access
4
PhyRgAd
3
Reserved
2
N/A
1
Rdpy
Wrpy
0
S/C
0x20
PhyRxData
N/A
R/O
R/O
Default
32’h000_0000
BusReset
U
Table 3-11. CFR map (0x20)
: "Read Phy register"
RdPy
When RdPy is set to 1, Link sends a read register request with the address equal to PhyRdAd to the Phy.
This bit is cleared when request is sent.
: "Write Phy register"
WrPy
When WrPy is set to 1, Link sends a write register request with the address equal to PhyRdAd to the Phy.
This bit is cleared when request is sent.
: "Phy-register address"
PhyRgAd
The addresses of the Phy register to be accessed when either WrPy or RdPy is 1.
: "Phy-register data"
PhyRgData
The data to be written to the Phy register when WrPy is 1.
Page 31
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
: "Phy-register-received address"
PhyRxAd
The addresses of Phy register from which PhyRxData came.
: "Phy-register-received data"
PhyRxData
The data of Phy register addressed by PhyRxAd.
0x24
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
BusReset
BusNumber
NodeNum
BRFErr_
Code
NodeSum
CFRContID
Read/
Write
R/W
R/O
R/O
R/O
R/O
Default
10’h3FF
6’h3F
4’h00
6’h01
6’h3F
BusReset
U
A
Table 3-12. CFR map (0x24)
: "Bus number"
BusNumber
Link uses BusNumber as BusID.
When a bus reset completes, BusNumber is set to an appropriate value. The host may write BusNumber.
: "Node number"
NodeNum
Link uses NodeNum as NodeID.
When a bus reset completes, NodeNum is set to an appropriate value. The host may write NodeNum.
BRFErr_Code : "Error code in bus reset"
When a bus reset occurs, BRFErr_Code is set to the appropriate value.
If BRFErr_Code is not zero, the host should initiate a bus reset agein. The code table is below.
0000 No Error
0001 last self ID port status is not all children
0010 Phy id is sequence error. ( not have correct order )
0011 inverted-quadlet is not the reverse of preceding quadlet
0100 Phy id sequence error (two gaps in Phy IDs')
0101 Phy id sequence error (arbitration reset gap in Phy IDs')
0110 Phy id within self ID packet does not match
0111 quadlet/inverted-quadlet sequence error
1000 first 2 bits does not match either 01 or 10.
1111 At least one SelfID packet has different GAP count.
: "Number of node in this 1394 topology"
NodeSum
When a bus reset occur, NodeSum is set to the appropriate value.
Page 32
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
: "Node ID of IRM"
CFMContID
When a bus reset occurred, CFMContID is set to the appropriate value.
0x28
Time Limit
0
1
2
3
4
5
6
7
8
9
BusReset
1
1
1
2
1
3
1
4
1
5
1
6
SplitTimeOut
Read/
Write
Default
1
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
3
0
RtryLmt
ORBTime
8’h08
4’hE
4’h0
R/W
16’h0320
3
1
RetryInterval
U
Table 3-13. CFR map (0x28)
SplitTimeOut : "Split transaction time-out"
SplitTimeOut limits the time waiting for the response packet.
If the response packet has not received when the split transaction timer exceeds the SplitTimeOut period,
the transaction failed. Unit is one Iso cycle (125us)
RetryInterval : "Retry interval time"
RetryInterval defines the time from receipt of Ack_Busy_X to retransmission. Unit is one Iso cycle (125us)
RtryLmt : "Retry limit"
RtryLmt limits the number of times the transmitter retries.
If RtryLmt is 0, the transmitter shall not attempt retransmission of busied packet.
Otherwise, it shall retransmit the packet RtryLmt times or until receipt of other acknowledgements
than Ack_Busy_X.
ORBTime : "Time waited by timer to fetch command block ORB"
The timer to fetch command block ORB waits for ORBTime period before beginning to transmit
the read request packet, unit is one Iso cycle (125us)
Page 33
2
9
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
6
7
8
9
1
0
1
1
1
2
1
3
1
4
Reserved
Read/
Write
R/O
N/A
R/O
N/A
default
0 0
4’h00
0 1
11’h00
BusReset
0 0
U
0 1
U
ATF Status
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
7
2
8
4’h00
8’h0D
C
U
U
ATFAEm : "ATF almost-empty flag"
While ATF has only one quadlet in it, ATFAEm shows 1. Otherwise, ATFAEm shows 0.
Page 34
2
6
0
: "ATF almost-full flag"
ATFAFl
While ATF can accept one more write, ATFAFl shows 1. Otherwise, ATFAFl is 0.
ATF_Size : "ATF size control bits"
ATF_Size is equal to the ATF size number in quadlet.
2
5
R/W
ATFFul : "ATF full flag"
While ATF is full, ATFFul shows 1.
While ATF is not full, ATFFul shows 0.
ATFClr : "ATF clear control bit"
When ATFClr is set, ATF is cleared. This bit clears itself after the clear.
2
4
N/A
Table 3-14. CFR map (0x2C)
ATFEmp : "ATF empty flag"
While ATF is empty, ATFEmp shows 1. Otherwise, ATFEmp shows 0.
2
3
ATF_Size
5
Reserved
4
ATFClr
3
S/C
2
ATFAEm
ATFEmp
1
Reserved
0
ATFFul
ATFAFl
0x2C
2
9
3
0
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
3
2
4
2
5
2
6
Default
0 0
4’h00
0 1
8’h00
0 0 0 0
BusReset
0 0
U
0 1
8’h00
0
U
C
8’h0D
U
U
ARFFul : "ARF full flag"
While ARF is full, ARFFul shows 1.
While ARF is not full, ARFFul shows 0.
ARFAFl: "ARF almost-full flag"
While ARF can accept one more write, ARFAFl shows 1. Otherwise, ARFAFl is 0.
ARFAEm: "ARF almost-empty flag"
While ARF has only one quadlet in it, ARFAEm shows 1. Otherwise, ARFAEm shows 0.
ARFEmp: "ARF empty flag"
While ARF is empty, ARFEmp shows 1. Otherwise, ARFEmp shows 0.
ARFThere: "ARF there"
ARF has ARFThere quadlet.
ARFCD : "ARF control bit"
When the first quadlet of a packet is being read from the ARF Data(0x80) register, ARFCD shows 1.
ARF_Size: "ARF size control bits"
ARF_Size is equal to the ARF size number in quadlet.
Page 35
2
8
4’h0
Table 3-15. CFR map (0x30)
ARFClr : "ARF clear control bit"
When ARFClr is set, ARF is cleared. This bit clears itself after the clear.
2
7
R/W
N/A
ARFCD
2
2
N/A
R/O
R/O
2
1
N/A
Read/
Write
ARF Status
2
0
ARF_Size
7
Reserved
6
ARFClr
5
S/C
4
Reserved
3
ARFThere
2
ARFAEm
ARFEmp
1
Reserved
0
ARFFul
ARFAFl
0x30
2
9
3
0
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0
U
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
Reserved
6’h00
7
MTQClr
0
6
N/A
S/C
N/A
5
Reserved
4
MTQEmp
BusReset
3
R/O
Default
2
Reserved
Read/
Write
1
MTQFul
MTQ
status
0
R/O
0x34
N/A
1
11’h000
0
12’h000
1
U
C
U
2
7
2
8
2
9
3
0
3
1
2
7
2
8
2
9
3
0
3
1
Table 3-16. CFR map (0x34)
: "MTQ full flag"
MTQFul
While MTQ is full, MTQFul shows 1.
While MTQ is not full, MTQFul shows 0.
: "MTQ empty flag"
MTQEmp
While MTQ is empty, MTQEmp shows 1. Otherwise, MTQEmp shows 0.
: "MTQ clear control bit"
MTQClr
When MTQClr is set, MTQ is cleared. This bit clears itself after the clear.
3
4
5
6
7
8
9
1
0
1
1
1
2
MRFThere
2
MRFAEm
MRFEmp
1
1
3
1
4
1
5
1
6
1
7
1
8
1
9
Default
0 0
4’h0
0 1
8’h00
0 0 0 0
BusReset
0 0
U
0 1
8’h00
0
R/O
2
3
2
4
2
5
2
6
Reserved
N/A
N/A
U
C
Table 3-17. CFR map (0x38)
MRFFul: "MRF full flag"
While MRF is full, MRFFul shows 1.
While MRF is not full, MRFFul shows 0.
MRFAFl: "MRF almost-full flag"
While MRF can accept one more write, MRFAFl shows 1. Otherwise, MRFAFl is 0.
Page 36
2
2
MRFClr
N/A
2
1
S/C
R/O
2
0
Reserved
Read/
Write
MRFCD
MRF
Status
Reserved
0
MRFFul
MRFAFl
0x38
12’h00
U
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
MRFAEm: "MRF almost-empty flag"
While MRF has only one quadlet in it, MRFAEm shows 1. Otherwise, MRFAEm shows 0.
MRFEmp: "MRF empty flag"
While MRF is empty, MRFEmp shows 1. Otherwise, MRFEmp shows 0.
MRFThere: "MRF there"
MRF has MRFThere quadlet.
MRFCD: "MRF control bit"
When the first quadlet of a packet is being read from the MRF Data(0x84) register, MRFCD shows 1.
: "MRF clear control bit"
MRFClr
When MRFClr is set, MRF is cleared. This bit clears itself after the clear.
7
8
9
1
0
1
1
1
2
1
3
1
4
Read/
Write
R/O
N/A
R/O
N/A
Default
0 0
3’h0
1 0 1
11’h000
BusReset
0 0
U
1 0 1
U
CTQ status
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
4
2
5
2
6
2
7
2
8
N/A
R/W
0
4’h0
8’h0F
C
U
U
Table 3-18. CFR map (0x3C)
Note: Provide only 3quadlets only
: "CTQ full flag"
CTQFul
While CTQ is full, CTQFul shows 1.
While CTQ is not full, CTQFul shows 0.
Note: (CTQ – 1) size will be displayed.
CTQAFl: "CTQ almost-full flag"
While CTQ can accept one more write, CTQAFl shows 1. Otherwise, CTQAFl is 0.
Caution: It’ll be set 0 after writing 3 quadlets.
CTQ1Av: "CTQ 1-available flag"
CTQ can accept one more packet.
CTQAEm: "CTQ almost-empty flag"
While CTQ has only one quadlet in it, CTQAEm shows 1. Otherwise, CTQAEm shows 0.
Page 37
2
3
CTQ_Size
6
Reserved
5
CTQClr
4
S/C
3
Reserved
2
CTQ1Av
CTQAEm
CTQEmp
1
Reserved
0
CTQFul
CTQAFl
0x3C
2
9
3
0
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Caution: It’ll be set 0 after writing 2 quadlets.
CTQEmp: "CTQ empty flag"
While CTQ is empty, CTQEmp shows 1. Otherwise, CTQEmp shows 0.
: "CTQ clear control bit"
CTQClr
When CTQClr is set, CTQ is cleared. This bit clears itself after the clear.
CTQ_Size: "CTQ size control bits"
CTQ_Size is equal to the CTQ size number in quadlet.
1
0
1
1
1
2
Read/
Write
R/O
N/A
Default
0 0
4’h0
0 1
8’h00
BusReset
0 0
4’h0
0 1
8’h00
CRF status
R/O
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
N/A
R/W
0 0 0 0
4’h0
8’h40
0 0 0 C
4’h0
U
CRFFul : "CRF full flag"
While CRF is full, CRFFul shows 1.
While CRF is not full, CRFFul shows 0.
CRFAFl: "CRF almost-full flag"
While CRF can accept one more write, CRFAFl shows 1. Otherwise, CRFAFl is 0.
CRFAEm: "CRF almost-empty flag"
While CRF has only one quadlet in it, CRFAEm shows 1. Otherwise, CRFAEm shows 0.
CRFEmp: "CRF empty flag"
While CRF is empty, CRFEmp shows 1. Otherwise, CRFEmp shows 0.
CRFThere: "CRF there"
CRF has CRFThere quadlet.
CRFCD : "CRF control bit"
When the first quadlet of a packet is being read from the CRF Data(0x88) register, CRFCD shows 1.
Page 38
2
8
N/A
Table 3-19. CFR map (0x40)
CRFClr : "CRF clear control bit"
2
7
CRF_Size
9
Reserved
8
CRFClr
7
S/C
6
Reserved
5
CRFCD
4
R/O
3
CRFThere
2
CRFAEm
CRFEmp
1
Reserved
0
CRFFul
CRFAFl
0x40
2
9
3
0
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
When CRFClr is set, CRF is cleared. This bit clears itself after the clear.
CRF_Size: "CRF size control bits"
CRF_Size is equal to the CRF size number in quadlet.
Read/
Write
Default
R/W
7
0 0 0 1
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
R/W
4’h0
BusReset
S/C
8’h08
0 0 0 0 1 1 1 1 0 0 0 0
U
Table 3-20. CFR map (0x44)
MagtVld : "Management_Agent register valid"
When MagtVld is set to 1,the Management_Agent_offset in Management_Agent(0x48) is valid.
And if the management fetch agent receives the block write request addressed
to the MANAGEMENT_AGENT register.
the management ORB shall be fetched automatically and placed into MRF.
When MAgtVld is set to 0, the Management_Agent_offset is invalid.
MagtBsy : "Management_Agent register busy"
When block write request addressed to the Management_Agent register, this bit set to “1”.
The block write request addressed to the MANAGEMENT_AGENT register shall be rejected with
the conflict response or the conflict acknowledgement, when this bit is set.
When the host writes "0" on MAgtBsy, it is cleared to 0.
When MAgtBsy is set to 0, the management agent can accept the block write request.
MShtFmt : "Management ORB in short format in MRF"
When MShtFmt is set to 1, the receiver transforms the received packets containing
a fetched management ORB into short format and places into MRF.
When MShtFmt is set to 0, the receiver shall place the received packets
containing a fetched management ORB into MRF as it is.
MORB_Prior : "Management ORB transmission priority"
The read request packet to fetch a management ORB has MORB_Prior in the priority filed.
CORB_size : "Command block ORB size"
Page 39
2
7
2
8
2
9
3
0
CORB_
Prior
6
CAg2QRdy
CAg3Q Rdy
5
CAg1QRdy
4
CAg0Vld
Cag1Vld
Cag2Vld
Cag3Vld
DrBSnp
DrBFtEn
CnxFtEn
CShtFmt
3
CORB_
Size
2
MORB_
Prior
1
N/A
ORB Fetch
Control
0
MagtVld
MagtBsy
Reserved
MShtFmt
0x44
CAg0QRdy
caution) It’s not transmitted data when setting number to CRF_Size less than CORB_Size+3 quadlets.
R/W
4’h0
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Command block ORBs whose size is CORB_size shall be fetched. Unit is quadlet.
CAg0Vld : "Register of command block agent0 valid"
When CAg0Vld is set to 1, The Agent_base_offset in Command_Agent(0x4C) is valid.
If NodeID is assigned to agent0 by writing on Agent Control(0x50),
the command block agent0 can receive write/read requests.
When the block write request addressed to the ORB_POINTER register,
the command block ORB shall be fetched automatically and be placed into CRF.
Otherwise, if NodeID is not assigned to agent0, the agent0 rejects any requests.
When CAgtVld is set to 0, the Command_block_Agent_offset is invalid.
CAg1Vld : "Register of command block agent1 valid" See CAg0Vld.
CAg2Vld : "Register of command block agent2 valid" See CAg0Vld.
CAg3Vld : "Register of command block agent3 valid" See CAg0Vld.
DrBSnp : “Enable to snoop about the packet fetched by doorbell”
When DrBSnp is set to 1 and doorbell is rung, command block agent fetch the whole command block ORB and put it into
CRF. When DrBSnp is set to 0 and doorbell is rung, command block agents fetch the only next ORB field and does not
put it into FIFO, and be displayed ORB address at 0x54,58 .
DrBFtEn : "Ring the doorbell enable to fetch Command block ORB"
When DrBFtEn is set to 1 and the command block agents receive the quadlet write request addressed to the DOORBELL
register, the command block ORB shall be fetched automatically and placed into CRF. Either DrBll0 - DrBll3 in Agent
Status(0x5C) shall be also set to 1.
When DrBFtEn is set to 0 and the command block agents receive it, the command block ORB shall not be fetched
automatically.
Either DrBll0 - DrBll3 in Agent Status(0x5C) is just set to 1.
caution) do not change setting during operation.
CnxFtEn : "Next command block ORB fetch enable"
When CnxFtEn is set to 1 and the receiver receives a command block ORB whose the next_ORB field
is not null, the next command block ORB shall be fetched automatically.
When CnxFtEn is set to 0 and the receiver does so, the next command block
ORB shall not be fetched automatically.
CShtFmt : "Command block ORB in short format in CRF"
When CShtFmt is set to 1, the receiver transforms the received packets containing a fetched command
block ORB into short format and places into CRF.
When CShtFmt is set to 0, the receiver shall place the received packets containing a fetched command
block ORB into CRF as it is.
CAg0Rdy : "Command block agent 0 is ready to fetch the command block ORB"
When command block agent gets ready to fetch the command block ORB, this bit is set to 1, When the host writes ‘1’ on
CAg0Rdy, it is cleared to 0 and the agent fetches the command block ORB and put it into CRF.
Cag1Rdy : "Command block agent 0 is ready to fetch the command block ORB"
See Cag0Rdy.
Page 40
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Cag2Rdy : "Command block agent 0 is ready to fetch the command block ORB"
See Cag0Rdy.
Cag3Rdy : "Command block agent 0 is ready to fetch the command block ORB"
See Cag0Rdy.
CORB_Prior : "Command block ORB transmission priority"
The read request packet to fetch a command block ORB has CORB_Prior in the priority filed.
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
Reserved
0x48
Management_Agent_offset
Read/
Write
N/A
R/W
Default
8’h00
24’h00_4000
Management
Agent
BusReset
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
5
2
6
2
7
2
8
2
9
3
0
3
1
U
Table 3-21. CFR map (0x48)
Management_Agent_offset : "Management agent offset"
This contains the offset in quadlet from FFFF_F000_0000 [byte] to the base address of
the MANAGEMETN_AGENT register.
It shall not be less than 00_4000.
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
Command
Agent
Reserved
0x4C
Read/
Write
N/A
R/W
R/O
8’h00
21’h000_802
U
3’h0
Default
BusReset
Agent_base_offset
Table 3-22. CFR map (0x4C)
Agent_base_offset : "Agent base offset"
Page 41
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
This contains the offset in quadlet from FFFF_F000_0000 [byte] to the base address of the command
block agent0 register.
Agent_base_offset shall not be less than 00_4000 and .
The base address of registers that each command block agent has is specified as the followings:
Agent0[byte] = FFFF_F000_0000 + Agent_base_offset[quadlet] * 3'b100
Agent1[byte] = Agent0 + 6'h20
Agent2[byte] = Agent1 + 6'h20
Agent3[byte] = Agent2 + 6'h20
Management offset address shall
COMMAND_BLOCK_AGENT.
not
be
a)less
than
0xFFFFF0010000,
b)
reserved
address
for
The Unit in this CFR 0x48: Management_Agent_Offset field is in quadlet. Therefore, Managemant Agent Address
0xFFFFFFFFF0011000 should be represented as 0x04400 in this input field with the offset address.
7
Agent
Control
Read/
Write
N/A
Default
0 0
9’h000
BusReset
U
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
NodeID
R/W
S/C
6
N/A
5
USTlEn
AgntVld
Reserved
WrNdID
RdNdID
4
S/C
3
R/W
2
Reserved
1
AgtNmb
0
R/W
0x50
0 0 0 0 0
0
2
6
2
7
2
8
2
9
3
0
3
1
15’hFFFF
U
Table 3-23. FR map (0x50)
AgtNmb : "The number of command block agent"
The host can read the ORBPointer register of Agt_Nmb from ORB Pointer1(0x54) and
ORB Pointer2 (0x58) registers. Also this number is used to set NODE-ID for each AGENT.
USTlEn : "UnsolicitedStatusEn tlabel control enable"
When USTlEn is set to 1 and the host writes a packet with tlabel (tl=3’b111+2b’AgntNub+1b’X) on Write First(0x70),
either UnSEn0-UnSEn3 in 0x5C shall be cleared automatically.
When USTlEn is set to 0 and the host writes a packet with tlabel (tl=3’b111+2b’AgntNub+1b’X) on Write First(0x70),
UnSEn0 - UnSEn3 shall not be cleared automatically.
: "valid NodeID for Agent"
AgntVld
When Agntvld is set to “1” with Agent Number, then NodeID corresponding to Agent is valid,
This bit is automatically cleared at Bus reset.
WrNdID : "Write NodeID of each agent"
When WrNdID is set to 1 and AgtNmb and Agent_NodeID are set to certain values,
the command block agent of AgtNmb is assigned to Agent_NodeID.
Page 42
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
This bit is cleared after this assignment.
RdNdID : "Read NodeID of each agent"
When RdNdID is set to 1 and AgtNmb is set to a certain value,
the host can read the NodeID assigned to the command block agent of AgtNmb from Agent_NodeID.
This bit is cleared after read.
NodeID : "NodeID assigned to the each agent"
The NodeID to be assigned to the command block agent of AgtNmb when WrNdID is set to 1.
Agent_NodeID represents the NodeID assigned to the command block agent of AgtNmb after RdNdID
is set to 1.
BusReset does not effect Agent_Node_IDs.but Agent become not ready after BusReset,
So Host have to write NodeID for Agent again after BusReset to activate Agent.
0x54
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
ORB
Pointer1
Reserved
ORB_destination_offset_hi
Read/
Write
N/A
R/O
Default
32’h0000_0000
BusReset
0
2
9
3
0
3
1
2
9
3
0
3
1
Table 3-24. CFR map (0x54)
ORB_destination_offset_hi : "ORB destination offset hi in ORBPointer"
The destination offset hi part of ORB POINTER register that is contained the agent indicated
by Agent_Number in Agent Control.
(Note) The value of register returns to default value when initiator which is being log in resets agent.
0x58
ORB
Pointer2
Read/
write
Default
BusReset
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
9
2
0
ORB_destination_offset_lo
R/O
32’h0000_0000
0
Table 3-25. CFR map (0x58)
Page 43
1
8
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
ORB_destination_offset_lo : "ORB destination offset low in ORBPointer"
The destination offset low part of ORB POINTER register that is contained the agent indicated
by Agent_Number in Agent Control.
(Note) The value of register returns to default value when initiator which is being log in resets agent.
Read/
Write
7
R/O
S/C
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
R/O
Default
BusReset
S/C
1
7
1
8
1
9
2
0
2
1
2
2
2
3
R/O
S/C
2
4
2
5
2
6
2
7
2
8
R/O
32’h0000_0000
0
Table 3-26. CFR map (0x5C)
State0 : "State of the command block agent 0"
State0 shows the state of each command block agent 0.
DrBll0 : "DoorBell variable of the command block agent 0"
When the DOORBELL register receives quadlet write request, DrBll0 becomes 1.
When the host writes 1 on a DrBClr0, DrBll0 are cleared to 0.
UnStEn0: "Unsolicited Status Enable variable of the command block agent 0"
When the UNSOLICITED_STATUS_ENABLE register receives quadlet write request,
the UnStEn0 becomes 1.
If USTlEn in Agent Control(0x50) is set to 1, the transmission of packet with tlabel 6'h0F clears UnStEn0.
Or when the host writes 1 on a USEClr0, USEClr0 is cleared to 0.
Dead0 : "Dead state control bit"
When Dead0 is set to 1, State0 is set to 2'h3.
Dead0 clears itself after that.
Rst0 : "Reset state control bit"
When Rst0 is set to 1, State0 is set to 2'h0.
Rst0 clears itself after that.
DrBClr0 : "DoorBell variable clear bit"
When DrBClr0 is set to 1, DrBll0 is cleared to 0.
DrBClr0 clears itself after that.
USEClr0 : "Unsolicited Status Enable variable clear bit"
When USEClr0 is set to 1, USEClr0 is cleared to 0.
Page 44
2
9
3
0
3
1
DrBll3
UnStEn3
Dead3
Rst3
DrBClr3
USEClr3
6
State3
5
DrBll2
UnStEn2
Dead2
Rst2
DrBClr2
USEClr2
4
State2
3
DrBll1
UnStEn1
Dead1
Rst1
DrBClr1
USEClr1
2
State1
1
DrBll0
UnStEn0
Dead0
Rst0
DrBClr0
USEClr0
Agent
Status
0
State0
0x5C
S/C
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
USEClr0 clears itself after that.
There are four command block agents, which has the respective State, DrBll and UnStEn,
variables and Dead, Rst, DrBClr and USEClr bits.
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
N/A
R/O
N/A
R/O
N/A
R/O
N/A
R/O
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
N/A
6
TxAbrt
HldTr
Rlsr
Reserved
5
S/C
4
TimrNo
3
R/W
2
N/A
R/O
N/A
Read/
Write
1
R/O
Transaction
Timer Control
0
DTTxEd
DRTxEd
ATTxEd
MTTxEd
CTTxEd
Reserved
ARTxEd
Reserved
DTErr
DRErr
ATErr
MTErr
CTErr
Reserved
ARErr
Reserved
DTRtry
DRRtry
ATRtry
MTRtry
CTRtry
Reserved
ARRtry
Reserved
0x60
Default
1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4’h0
0 0 0 0
BusReset
1 1 1 1 1 0 1 0 U U 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4’h0
0 0 0 0
Table 3-27. CFR map (0x60)
DTTxEd : "DTF transaction end"
When the transaction from DTF has completed, DTTxEd becomes 1.
When the transaction from DTF begins, DTTxEd becomes 0.
DRTxEd : "DRF transaction end"
When the transaction from DRF has completed, DRTxEd becomes 1.
When the transaction from DRF begins, DRTxEd becomes 0.
ATTxEd : "ATF transaction end"
When the transaction from ATF has completed, ATTxEd becomes 1.
When the transaction from ATF begins, ATTxEd becomes 0.
MTTxEd : "MTQ transaction end"
When the transaction from MTQ has completed, MTTxEd becomes 1.
When the transaction from MTQ begins, MTTxEd becomes 0.
CTTxEd : "CTQ transaction end"
When the transaction from CTQ has completed, CTTxEd becomes 1.
When the transaction from CTQ begins, CTTxEd becomes 0.
ARTxEd : "Autoresponse transaction end"
When the autoresponse transaction has completed, ARTxEd becomes 1.
When the autoresponse transaction begins, ARTxEd becomes 0.
DTErr: "DTF transaction err"
If the transaction from DTF ends with any errors, DTErr becomes 1.
Otherwise, if it ends with no error, DTErr remains 0.
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
When the transaction from DTF begins, DTErr is cleared to 0.
DRErr: "DRF transaction err"
If the transaction from DRF ends with any errors, DRErr becomes 1.
Otherwise, if it ends with no error, DRErr remains 0.
When the transaction from DRF begins, DRErr is cleared to 0.
ATErr: "ATF transaction err"
If the transaction from ATF ends with any errors, ATErr becomes 1.
Otherwise, if it ends with no error, ATErr remains 0.
When the transaction from ATF begins, ATErr is cleared to 0.
MTErr: "MTQ transaction err"
If the transaction from MTQ ends with any errors, MTErr becomes 1.
Otherwise, if it ends with no error, MTErr remains 0.
When the transaction from MTQ begins, MTErr is cleared to 0.
CTErr : "CTQ transaction err"
If the transaction from CTQ ends with any errors, CTErr becomes 1.
Otherwise, if it ends with no error, CTErr remains 0.
When the transaction from CTQ begins, CTErr is cleared to 0.
ARErr : "Autoresponse transaction err"
If the autoresponse transaction ends with any errors, ARErr becomes 1.
Otherwise, if it ends with no error, ARErr remains 0.
When the autoresponse transaction begins, ARErr is cleared to 0.
DTRtry : "DTF retry"
When the transaction from DTF begins retrying because of receiving Ack_Busy_X, DTRtry becomes 1.
When the retransaction from DTF ends because of receiving the other acknowledgements,
a retry time-out or a bus reset, DTRtry becomes 0.
DRRtry : "DRF retry"
When the transaction from DRF begins retrying because of receiving Ack_Busy_X, DRRtry becomes 1.
When the retransaction from DRF ends because of receiving the other acknowledgements,
a retry time-out or a bus reset, DRRtry becomes 0.
ATRtry : "ATF retry"
When the transaction from ATF begins retrying because of receiving Ack_Busy_X, ATRtry becomes 1.
When the retransaction from ATF ends because of receiving the other
acknowledgements, a retry time-out or a bus reset, ATRtry becomes 0.
MTRtry : "MTQ retry"
When the transaction from MTQ begins retrying because of receiving
Ack_Busy_X, MTRtry becomes 1.
When the retransaction from MTQ ends because of receiving the other acknowledgements,
a retry time-out or a bus reset, MTRtry becomes 0.
CTRtry : "CTQ retry"
Page 46
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
When the transaction from CTQ begins retrying because of receiving Ack_Busy_X, CTRtry becomes 1.
When the retransaction from CTQ ends because of receiving the other acknowledgements,
a retry time-out or a bus reset, CTRtry becomes 0.
ARRtry : "Autoresponse retry"
When the autoresponse transaction begins retrying because of receiving Ack_Busy_X, ARRtry becomes 1.
When the autoresponse retransaction ends because of receiving the other acknowledgements,
a retry time-out or a bus reset, ARRtry becomes 0.
TimrNo : "Number of transaction timer"
When the host writes on TimerNo, the timer indicated in TimerNo is selected.
TimerNo affects TxAbort, HldRtr and reading from Transaction Timer Status1-3(0x64-0x6C).
The definition is the following.
4'h0 : The timer of transmission from DTF
4'h1 : The timer of transmission from DRF
4'h2 : The timer of transmission from ATF
4'h3 : The timer of transmission from MTQ
4'h4 : The timer of transmission from CTQ
4'h6 : The timer of autorsponse(AR) transmission
TxAbrt : "Transaction abort"
When TxAbrt is set to 1, the transmission of the timer indicated in TimrNo is aborted.
TxAbrt clears itself after it's aborted.
Note) DTErr(0x60) will be set 1 when abort DTF transaction.
HldTr : "Hold transmission"
When HldTr is set to 1, the transmission of TimerNo is held. RlsTr clears itself after it's held.
If both HldTr and RlsTr are set to 1 at the same time, HldTr is ignored.
Note) It’s necessary to set this bit to 1 when writing ATQ.ATF,MTQ,CTQ. Then transmit packet by set RlsTr.
RlsTr : "Release transmission"
When RlsTr is set to 1, the transmission of TimerNo is released.
RlsRtr clears itself after it's released.
0x64
Transaction
Timer Status1
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
Destination_ID
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
Destination_offset_hi
Read/
Write
R/O
Default
BusReset
32’h0000_0000
32’h0000_0000
Table 3-28. CFR map (0x64)
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TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Destination_ID : "TimerNo's transmitting destination ID"
The timer of TimerNo is transmitting or has transmitted the packet to Destination_ID in the last transaction.
Destination_offset_hi : "TimerNo's transmitting destination offset high"
The timer of TimerNo is transmitting or has transmitted the request packet to Destination_offset_hi
in the last transaction.
0x68
0
1
2
3
4
5
6
7
8
1
0
9
1
1
Transaction
Timer Status2
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
7
2
8
2
9
3
0
3
1
Destination_offset_lo
Read/
Write
R/O
Default
BusReset
32’h0000_0000
32’h0000_0000
Table 3-29. CFR map (0x68)
Destination_offset_lo : "TimerNo's transmitting destination offset low"
The timer of TimerNo is transmitting or has transmitted the request packet to Destination_offset_low
in the last transaction.
Transaction
Timer Status3
0
1
2
TCode
3
4
5
Spd
0x6C
6
7
8
9
Tlabel
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
Retry_
Counter
Read/
Write
R/O
Default
BusReset
32’h0000_0000
32’h0000_0000
2
0
2
1
2
2
2
3
2
4
2
5
2
6
SplitTrTimer
Table 3-30. CFR map (0x6C)
TCode : "TimerNo's transmitting TCode"
The packet that the timer of TimerNo is transmitting or has transmitted TCode in the last transaction.
Spd : "TimerNo's transmitting speed"
The timer of TimerNo is transmitting or has transmitted the packet last with Spd in the last transaction.
Page 48
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Tlabel : "TimerNo's transmitting tlabel"
The packet that the timer of TimerNo is transmitting or has transmitted has Tlabel in the last transaction.
Retry_Counter : "TimerNo's transmitting retry counter"
The timer of TimerNo is retransmitting or has retransmitted the packet Retry_Counter times
in the last transaction.
SplitTrTimer : "TimerNo's transmitting split transaction timer"
If the timer of TimerNo is waiting or has waited for the response packet for SplitTrTimer period
in the last transaction.
0x70
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
Write
First
Write_First
Read/
Write
W/O
Default
BusReset
32’h0000_0000
32’h0000_0000
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
9
3
0
3
1
Table 3-31. CFR map (0x70)
Write_First : "Write first quadlet of the packet to ATF, MTQ or CTQ"
This write only register provides the host with the capability to write the first quadlet of an transmit packet
to transmitting FIFO.
When the host writes the first quadlet of the packet here, the value of tlabel and TCode decide
which FIFO(ATF,MTQ or CTQ) the written packet is delivered to.
0x74
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
Write
Continue
Write_Continue
Read/
Write
W/O
Default
BusReset
32’h0000_0000
32’h0000_0000
Table 3-32. CFR map (0x74)
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2
0
2
1
2
2
2
3
2
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2
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8
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Write_Continue : "Write any other quadlet than first and last quadlet to ATF, MTQ or CTQ"
This write only register provides the host with the capability to write the quadlet of
an transmit packet - except the first and last quadlet - to transmitting FIFO which is decided
when the host writes on Write First(0x70).
0x78
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
Write
Update
Write_Update
Read/
Write
W/O
Default
BusReset
32’h0000_0000
32’h0000_0000
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
6
2
7
2
8
2
9
3
0
3
1
Table 3-33. CFR map (0x78)
Write_Update : "Write last quadlet of the packet"
This write only register provides the host with the capability to write the last quadlet of
an transmit packet to transmitting FIFO which is decided when the host writes on Write First(0x70).
0x80
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
ARF Data
ARFRead
Read/
Write
R/O
Default
BusReset
32’h0000_0000
32’h0000_0000
1
9
2
0
2
1
Table 3-34. CFR map (0x80)
ARFRead : "ARF data read access register"
This read only register provides the host with the capability to read the data quadlet of
an received packet from ARF. Each read outputs the next quadlet from ARF.
If ARF is empty, the last valid value is read.
Page 50
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2
3
2
4
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TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0x84
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
MRF Data
MRFRead
Read/
Write
R/O
Default
BusReset
32’h0000_0000
32’h0000_0000
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
Table 3-35. CFR map (0x84)
MRFRead : "MRF data read access register"
This read only register provides the host with the capability to read the data quadlet of
an received packet from MRF. Each read outputs the next quadlet from MRF.
If MRF is empty, the last valid value is read.
0x88
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
CRF Data
Read/
Write
CRFRead
Default
BusReset
32’h0000_0000
32’h0000_0000
1
9
2
0
2
1
R/O
Table 3-36. CFR map (0x88)
CRFRead : "CRF data read access register"
This read only register provides the host with the capability to read the data quadlet of
an received packet from CRF. Each read outputs the next quadlet from CRF.
If CRF is empty, the last valid value is read.
0x8C
Configuration
ROM
Control
Read/
Write
Default
BusReset
0
1
2
3
4
5
6
Reserved
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
AR_CSR_Size
1
8
1
9
2
0
2
1
Reserved
CSR_Size
N/A
R/W
R/O
N/A
R/W
R/O
5’h00
9’h00
0 0
5’h00
9’h00
0 0
U
0 0
Table 3-37. CFR map (0x8C)
AR_CSR_Size : "Size autoresponsed in Configuration ROM"
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TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
AR_CSR_Size is equal to the byte size number responded automatically in the ConfigROM.
AR_CSR_Size should be less than 0x20C.
1
5
QuadBndry
CheckPg
AutoPg
R/W
R/W
1
6
1
7
1
8
1
9
2
0
0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
001
001
0 0 U 0 U
U
R/W
U
U
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
DTHdIs
Dpause
DRStPS
DRHStr
DRDSel
DTDSel
DRFClr
DTFClr
1
4
Dackpnd
Drespcmp
1
3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
2
DTPage
FetchSiz
1
1
R/W
1
0
R/W
9
LongBlk
8
QuadSend
7
R/W
6
RconfSnglpkt
5
DheadSel
4
DMARW
Reserved
DRFEn
DTFEn
DRPktz
DTPktz
DRSpDis
DTSpDis
3
DRPage
FetchSiz
BusReset
2
R/W
Default
1
R/W
Read/
Write
R/W
DMA
Control
0
N/A
0x90
R/W
CSR_Size : "Size of Configuration ROM"
CSR_Size is equal to the ConifgROM size number in byte.
AR_CSR_Size should be less than 0x400.
S/C
0 0 0 0 0 0 0 0 0 0
U
Table 3-38. CFR map (0x90)
DMARW : "DMA Read/Write"
This bit controls the DMA input/output mode control for paticular bus mode.
When DMARW is set to 1, DMA is used for input. (memory à 43LV81)
When DMARW is set to 0, DMA is used for output. (43LV81 à memory)
DRFEn : "DRF enable"
When DRFEn is set to 1, DRF is enabled to receive data.
When DRFEn is set to 0, DRF is disabled to receive data.
When DRFEn is set to 0, DRF is to be DPP(direct print protocol) mode. Then direct mode field enable on 0xC0, 0XC4.
DTFEn : "DTF enable"
When DTFEn is set to 1, DTF is enabled to transmit data.
When DTFEn is set to 0, DTF is disabled to transmit data.
This bit is Active only DTPkt=0.Automatically cleared, when BusReset is occurred.
DRPktz : "DRF Packetizer enable"
When DRPktz is set to 1, the DRF Packetizer is ready to start to transmit read request packets.
When DRPktz is set to 0, it is not ready to do so.
DTPktz : "DTF Packetizer enable"
When DTFPktz is set to 1, the DTF Packetizer is ready to start to transmit write request packets.
When DTPktz is set to 0, it is not ready to do so.
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
DRSpDis: "DRF Packetizer split transaction disable"
When DRSpDis is set to 0, the DRF Packetizer waits for the response packet
if the transaction is acknowledged with Ack_pending.
When DRSpDis is set to 1, the DRF Packetizer doesn't waits for it even if the transaction is
acknowledged with Ack_pending.
DTSpDis : "DTF Packetizer split transaction disable"
When DTSpDis is set to 0, the DTF Packetizer waits for the response packet
if the transaction is acknowledged with Ack_pending.
When DTSpDis is set to 1, the DTF Packetizer doesn't waits for it even if the transaction is
acknowledged with Ack_pending.
DheadSel : "DTx header select"
00: write request header
01: DTF Packetizer status
10: read request header
11: DRF Packetizer status
RconfSnglpkt : "Receive confirm for each single packet"
When RconfSnglpkt is set to 1, each quadlet read from DRF reflect the value of DRF status. Otherwise DRF status is
updated for every “packet” received.
LongBlk : "Long block size"
When LngBlk is set to 1, the Packetizer uses long block size. Effect to Block size and Block count field in 0xB0,0xB4.
When LongBlk is set to 1, it will be swapped Block_size(0xB0) field and Block_count(0xB4) field.
Quad Boundary:
When this bit is set to one, Packetizer aligns quadlet address boundary in the first request packet.
Caution) This function is not checked yet.
CheckPg: " Check Page table "
Wen this bit is set to one, page table entry consistency is checked. If any error is observed, page fault interrupt is
initiated.
QuadSend :
When this bit is set to one, Packetizer translate 4byte block request to quadlet request packet.
(When sending 4 byte request, quad request will be used on setting 1. 4byte block request will be used on setting 0)
AutoPg: "AutoPaging"
When this bit is set to one, auto paging function is enabled. Page table read requests are automatically initiated
accordingly.
DTPageFetch size, DRF page Fetch size:
This field specifies the number of page table entry to be read requested by single read request packet.
2 ^(DxPageFetchSize+3)bytes will be fetched by single read request.
Caution) Must set value less than 4 due to destroy status buffer area.
DRRespComplete:
When DRAck complete is zero and this bit is one, complete_response is automatically set by AutoResponcer.
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
DackPnd:
When this bit is set to zero, write ack_complete acknowledges request to BDIffifo. rather than ack-pending.
DTHdIs : "DTF Header insert mode"
When DTHdLs is set to 1, DTx Head0-3(0xE8-0xF4) is inserted as the header of data transmitted from DTF.
In this mode the chip expects the data processor to load the DTF with pure data that contains no header.
When DTHdIs is set to 0, the chip expects DTF to contain completely formatted 1394 packets.
Dpause : "DRF pause"
When Dpause is set to 1, the transfer of the packet in DRF is paused after DRF RxHead0-3(0xD0-0xDC)
and DRF RxTailer(0xE0) is updated.
When Dpause is set to 0, the transfer of the packet in DRF is continued after DRF RxHead0-3(0xD0-0xDC)
and DRF RxTailer(0xE0) is updated.
DRStPS : "DRF sets Dpause automatically"
When DRStPS is set to 1, Dpause is set to 1 automatically after a packet is delivered to data processor via
BDIF. When DRStPS is set to 0, Dpause is not done so.
DRHStr : "DRF Header strip mode"
When DRHSty is set to 1, the header is stripped from the packet and only data payload is delivered to
the data processor. The stripped header is copied to DRF RxHead0-3(0xD0-0xDC) and DRF RxTailer(0xE0).
DRDSel : "DRF receiving data destination select"
When DRDSel is set to 1, the received packets are transferred to the data processor by the way of
the Bulky Data Interface(BDif).
When DRDSel is set to 0, the host has read access to DRF by reading received data from DRF Data(0xAC).
DTDSel : "DTF transmitting data source select"
When DTDSel is set to 1, the data processor has written access DTF by the way of the BDif.
When DTDSel is set to 0, the host has write access to DTF by writing transmitted data on
DTF First(0xA4) and DTF Cont&Up(0xA8).
DRFClr : "DRF clear control bit"
When DRFClr is set to 1,data in DRF is cleared.
This bit clears itself after the clear.
DTFClr : "DTF clear control bit"
When DTFClr is set to 1, data in DTF is cleared.
This bit clears itself after the clear.
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
BDIMode
1
2
Burst
1
1
R/W
1
0
BDOMode
9
R/W
8
BDIDely
7
R/W
6
BDODely
5
R/W
4
BIBsyCtl
BOAvCtl
BOEnCtl
BIEnCtl
BLECtl
AutoPad
3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
R/W
2
7
2
8
2
9
3
0
3
1
Default
7
5
5
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1
BusReset
U
U
U
U U U U U U U U U U
U
U
U
U
S/C
R/W
R/W
Read/
Write
RcvPad
BDORst
BDIRst
BDOTris
R/W
ATAckCtl
R/W
Reserved
R/W
Bulky
Interface
Control
BDAcKCtl
MTTBufSiz
1
MTRBufSiz
0
PgBufsiz
0x94
U 0 0 U
Table 3-39. CFR map (0x94)
PgBufSiz : "Specifies Pagetable fetch buffer size" (*note-1)
This is page ram size. Fetched page element will be stored here.
table is,
PgBufSiz
0
1
2
3
4
5
6
7
Size (quadlet)
0
2
4
8
10
12
14
16
Example.
If 0x90 bit19-21 is 2. Page element read size is
2^(2+3)=32 ( byte ) = 8 quadlet
in this case, Page-requester send 32 byte read request to initiator and store that data into page ram, so, PgBufSiz is 3 in
this case.
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
MTRBufSiz: "Specifies DRF status block buffer" (*note-1)
MTRBufSiz is number of quadlet for status Fifo use to DRF DMA.
table is,
MTRBufSiz Size (quadlet)
0
0
1
2
2
4
3
6
4
8
5
10
6
12
7
14
MTTBufSiz : "Specifies DTF status block buffer" (*note-1)
MTTBufSiz is number of quadlet for status Fifo use to DTF DMA.
table is,
MTTBufSiz Size (quadlet)
0
0
1
2
2
4
3
6
4
8
5
10
6
12
7
14
note-1) RAM size is followed by following caluculation.
ARConfigSize + STSiz + STSiz + MTTSiz + MTRSiz + LOGSize = 126 quadlet
ATAckCtl: "Active high control for ATAck terminal"
When AckCtl is set to 1, the ATAck is active high.
When AckCtl is set to 0, the ATAck is active low.
BDAcKCtl: "Active high control for BDAck terminal"
When BDMAcKCtl is set to 1, the BDAck is active high.
When BDMAcKCtl is set to 0, the BDAck is active low.
BIBsyCtl : "Active high control for BDIBUSY terminal"
When BIBsCtl is set to 1, the BDIBUSY is active high.
When BIBstl is set to 0, the BDIBUSY is active low.
BOAvCtl : "Active high control for BDOAVAIL terminal"
When BOAvCtl is set to 1, the BDOAVAIL is active high.
When BOAvCtl is set to 0, the BDOAVAIL is active low.
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
BOEnCtl : "Active high control for BDOEN terminal"
When BOEnCtl is set to 1, the BDOEN is active high.
When BOEnCtl is set to 0, the BDOEN is active low.
BIEnCtl : "Active high control for BDIEN terminal"
When BIEnCtl is set to 1, the BDIEN is active high.
When BIEnCtl is set to 0, the BDIEN is active low.
BLECtl : "BD Data little endian control"
Set to one set the DMA port Little Ending Mode.
AutoPad: “Automatic padding”
Set this bit to 1, set automatic padding for entire data block.
If this bit is 0, write to DMA must add padding bytes for each DMA block.
BDODely : "BDO Delay"
BDO Delay time
BDIDely : "BDI Delay"
BDI Delay inserts clock interval by each quadlet write to DMA.
BDIBUSY is negated for the duration specified by BDIDelay value.
BDOMode : "BDOMODE"
See the below table.
Burst : "Burst Mode"
When this bit is set to 1, Asynchronous DMA bus work as burst mode.
BDIMode : "BDIMODE"
See the below table.
BDI
mode
000
BDO
mode
00
001
01
010
011
100
01
10
11
101
110
111
01
10
11
description
input control
output control
8bit parallel input/
8bit parallel output
8bit parallel input/
8bit parallel output
8bit bi-directional in/out
8bit bi-directional in/out
8bit bi-directional in/out
scsi mode
16bit bi-directional in/out
16bit bi-directional in/out
16bit bi-directional in/out
scsi mode
BDIEN Sync
BDOEN Sync
in/out
select
N/A
BDIEN Async
BDOEN Async
N/A
BDIEN Async
BDIEN Sync
BDIEN Async
BDOEN Async
BDIEN Sync
BDOEN Async
N/A
CFR or BDOEN
CFR
BDIEN Async
BDIEN Sync
BDIEN Async
BDOEN Async
BDIEN Sync
BDOEN Async
N/A
CFR or BDOEN
CFR
Table 3-40. BDI/BDO mode
RcvPad : "Received data padding bits through to the BDif"
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Data must be written through to the BDif in quadlet multiples.
If a packet does not end on a quadlet boundary, zeros are padded to the last quadlet automatically.
When RcvPad is set to 1, 1394 is allowed to pad bits through to the BDif.
The BDif does not strip the zeros inserted into received packets prior to transferring them to the BDif.
When RcvPad is set to 0, 1394 is not allowed to do so.
BDORst : "BDO logic reset"
When BDORst is set to 1, BDO logic is reset.
This bit clears itself. Recommend to do reset when edit 0x94.
BDIRst : "BDI logic reset"
When BDIRst is set to 1, BDI logic is reset.
This bit clears itself. Recommend to do reset when edit 0x94.
BDOTris : "BDO tri-state"
When BDOTris is set to 1, BDO data bus is forced high-impedance state.
Effective to BDIO[15:8] only. (not effect to BDREQ)
0x98
DTF/DRF
Size
Read/
Write
Default
BusReset
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
Reserved
DTF_Size
Reserved
DRF_Size
N/A
R/W
N/A
R/W
6’h00
6’h00
10’h000
U
6’h00
6’h00
10’h040
U
Table 3-41. CFR map (0x98)
DTF_Size : "DTF size control bits"
DTF_Size is equal to the DTF size number in 4 quadlets.
DRF_Size : "DRF size control bits"
DRF_Size is equal to the DRF size number in 4 quadlets.
Page 58
2
0
2
9
3
0
3
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TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
3
4
5
6
7
8
1
0
9
1
1
1
2
1
3
Reserved
DTFAvail
N/A
R/O
1
1
5’h00
5’h00
10’h000
U
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
DRFEmpty
BDOAvail
Default
BusReset
2
Reserved
DRFThere
R/O
R/O
Read/
Write
1
DTFEmpty
DTF/DRF
Avail
0
R/O
0x9C
N/A
R/O
1 1
U U
5’h00
5’h00
10’h000
U
3
0
3
1
Table 3-42. CFR map (0x9C)
DTFEmpty :
DTFEmpty specifies the status of DTF status.
DTFAvail : "DTF available flag"
DTF has space available for DTFAvail quadlets. (Display remaining size by quadlet)
DRFEmpty :
DRFEmpty specifies the status of DRF status.
BDOAvail :
Reflect the status of BDOAvail output. (Caution: This bit is not equal to BDOAVAIL output because BDOAVAIL outpu
t is allowed to the BOAvlCtl. )
DRFThere : "DRF there flag"
DRF has DRFThere quadlets.
0
0
4’h0
4’h0
1
2
1
3
1
4
1
5
1
6
1
8
1
9
N/A
N/A
3’h0
3’h0
0
0
7’h0
7’h0
Table 3-43. CFR map (0xA0)
Page 59
1
7
2
0
2
1
2
2
2
3
2
4
2
5
2
6
R/O
0
0
4’h0
4’h0
2
7
2
8
2
9
3
0
3
1
DTAVal
R/O
1
1
N/A
R/O
1
0
9
Reserved
7’h0
7’h0
8
DtxAck
Default
BusReset
7
DTAErr
N/A
6
Reserved
Read/
Write
5
DRAVal
DTF/DRF
Ack
4
R/O
3
Reserved
2
DRxAck
1
DRAErr
0
Reserved
0xA0
3’h0
3’h0
0
0
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
: "DRF Ack error"
DRAErr
Whether the last Ack received for the read request packet for DRF has any errors.
When the Ack didn't receive nor had parity error and length error, AckErr shows 1.
When the Ack has no error or any Ack has not been received yet, AckErr shows 0.
DRxAck : "DRF transmitter acknowledge received"
The last Ack received for read request packet for DRF.
The value is updated each time the Ack is received.
DRAVal : "DRF Ack Valid"
Whether DRxAck has been already read.
When DRxAck has not read yet, DRAVld shows 1.
When DRxAck has already read, DRAVld shows 0.
: "DTF Ack error"
DTAErr
Whether the last Ack received for the packet transmitted from DTF has any errors.
When the Ack didn't receive nor had parity error and length error, AckErr shows 1.
When the Ack has no error or any Ack has not been received yet, AckErr shows 0.
DtxAck : "DTF transmitter acknowledge received"
The last Ack received for the packet transmitted from DTF.
The value is updated each time the Ack is received.
DTAVal : "DTF Ack Valid"
Whether DtxAck has been already read.
When DtxAck has not read yet, DTAVld shows 1.
When DtxAck has already read, DTAVld shows 0.
0xA4
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
DTF First
& Continue
DTF_First & Continue
Read/
Write
W/O
Default
32’h0000_0000
BusReset
32’h0000_0000
2
0
2
1
2
2
2
3
Table 3-44. CFR map (0xA4)
DTF_First & Continue : "Write any other quadlets than last quadlet of the packet to DTF"
This write only register provides the host with the capability to write the quadlets of
an transmit packet - except the last quadlet - to DTF.
Page 60
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4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0xA8
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
DTF
Update
DTF_Update
Read/
Write
W/O
Default
32’h0000_0000
BusReset
32’h0000_0000
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
8
2
9
3
0
3
1
Table 3-45. CFR map (0xA8)
DTF_Update : "Write last quadlet of the packet to DTF"
This write only register provides the host with the capability to write the last quadlet of an transmit packet
to DTF.
0xAC
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
DRF Data
DRFRead
Read/
Write
R/O
Default
32’h0000_0000
BusReset
32’h0000_0000
1
9
2
0
2
1
Table 3-46. CFR map (0xAC)
DRFRead : "DRF data read access register"
This read only register provides the host with the capability to read the data quadlet of
an received packet from DRF. Each read outputs the next quadlet from DRF.
If DRF is empty, the last valid value is read.
Page 61
2
2
2
3
2
4
2
5
2
6
2
7
TSB43LV81
Default
BusReset
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
DTF_BlockSize/
DTF_BlockCount
R/W
1
0
9
DTF Page
Size
8
R/W
DTF Spd
R/W
7
PgTblEn
Reserved
6
DTF Max
Payload
5
R/W
4
DTFNdIdval
2
DTFClr/DRFst
3
DTFNotify
Read/
Write
1
DTFCTL0
DTFCTL1
DTF
Control0
0
R/W
0xB0
R/W
R/O
R/W
N/C
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*1
U 0 U U U
U
U
U
Table 3-47. CFR map (0xB0)
Note) All bits of this register is N/A when DTpktz=0 in 0x90.
*1 depend on current condition.
DTFCtl : "DTF Packetizer transmit control"
Meaning of read value.
DTFCTL0
DTFCTL1
0
0
IDLE
1
0
BUSY
1
1
PEND
0
1
PAGEFAULT
Effect to write value.
DTFCTL0
DTFCTL1
0
0
1
0
1
1
0
1
No operation
Start/Restart
Init-start
Abort
DTFClr/DTFStx : "DTF clear control bit" (write)/”DTFStatus Transmit”(read)
When DTFClr is set to “1”, Data in DTF is cleared.
This bit clears itself after DTF cleared. Should not assert when DTFCtl = busy.
When this bit used for read it specifies whether current transaction is status transfer or not.
Caution) DTF_dest_ID(0xB8) data is required to set.
DTFSt : "DTF Packetizer Transfer Status” (read)
DTFSt represents DTF is transferring Transaction status data.
DTFNdIdval : “DTF NODE Id Valid”
represents Node ID in DTF Destination Id is valid. Writing to DTF destination Id Register sets this bit, and cleared by
bus reset.
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
note) This bit will be cleared after bus reset. And this bit should be 1 when re-setting destination ID on 0xB8 again.
DTFNotify : “DTF Notify”
When this bit is set to one, Transaction status data is transferred following DTF data transfer.
DTFSpd : "DTF transaction speed"
DTFSpd specifies the speed used by the DTF Packetizer.
2'b00 : 100Mbits/s
2'b01 : 200Mbits/s
2'b10 : 400Mbits/s
2'b11 : Not valid
DTFMaxPayload : "DTF transfer maximum payload"
DTFMaxPayload is the maximum data transfer length that the DTF Packetizer
requests in a single write transaction.
The maximum data transfer length is specified as 2^(DTFMaxPayload + 2).(byte)
PgTblEn : "Page table enable"
This bit control fetching of PgTblEn.
When PgTblEn is set to 1, enable page table enable fetch.
When PgTblEn is 0 and AutoPg is set 1, disable page table fetch.
DTF_destination_offset_hi and DTF_destination_offset_lo data point for page table address when PgTblEn is set 1.
When PgTbleEn is 0, DTF_destination_offset_hi and DTF_destination_offset_lo are data area.
DTFPageSize: "DTF transmit page size"
DTFPageSize specifies the underlying page size of data buffer memory.
Any one request packet is not permitted to cross a page boundary.
DTFPageSize value of zero indicates that the underlying page size is not
specified. Otherwise, the page size is 2^(DTFPageSize + 8).
DTF_BlockSize/DTF_BlockCount: "DTF transmit block size in byte / DTF transmit block count"
When LngSiz in DMA Control(0x90) is set to 0, this value shows DTF_BlockSize.
When LngSiz is set to 1, it showed DTF_BlockCount.
DTFBlockSize specifies the transmitted blocksize value.
DTF_BlockCount specifies the number of transmitted blocks. DTF_BlockCount is
decremented during transmission automatically.
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
DTF
Control1
DTF_BlockCount/DTF_BlockSize
Read/
Write
R/W
N/A
0xB4
Default
BusReset
30’h0000_00
30’h0000_00
00
00
Table 3-48. CFR map (0xB4)
Page 63
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
DTF_BlockCount/DTF_BlockSize: "DTF transmit block count / DTF transmit block size in byte"
When LongBlk in DMA Control(0x90) is set to 1, it showed DTF_BlockSize.
When LongBlk is set to 0, this value shows DTF_BlockCount.
0xB8
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
DTF
Control2
DTF_destination_ID
DTF_destination_offset_hi
Read/
Write
R/W
R/W
Default
BusReset
16’h0000
U
16’h0000
U
2
9
3
0
3
1
2
9
3
0
3
1
Table 3-49. CFR map (0xB8)
DTF_destination_ID : "DTF transferred destination ID"
DTF_destination_ID specifies transfer destination ID.
DTF_destination_offset_hi: "DTF transferred destination start offset high"
DTF_destination_offset_hi specifies transfer destination offset high.
0xBC
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
DTF
Control3
DTF_destination_offset_lo
00
Read/
Write
R/W
N/
A
Default
30’h0000_0000
00
BusReset
U
00
Table 3-50. CFR map (0xBC)
DTF_destination_offset_lo : "DTF transfer destination start offset low"
DTF_destination_offset_lo specifies transfer destination offset low.
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Default
BusReset
5
DRFNdIdval
DRFNotify
Reserved
DRF Spd
DRF Max
Payload
R/W
7
8
9
R/W
1
1
1
2
1
3
1
4
1
5
1
6
1
7
DRF Page
Size
4
PgTblEn
3
DRFClr/DRFst
6
1
0
2
R/W
R/O
R/W
N/C
Read/
Write
1
DRFCTL0
DRFCTL1
DRF
Control0
0
R/W
0xC0
(packetizer
mode)
R/W
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
DRF_BlockSize/
DRF_BlockCount
R/W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
U
U
U
*1 U 0 U U U
Table 3-51. CFR map (0xC0)
Note) When DRPktz is set to “1” in “0x90”,this table is used.
*1 depend on current condition.
DRFCtl : "DRF Packetizer transmit control"
Meaning of read value.
DRFCTL0
DRFCTL1
0
0
IDLE
1
0
BUSY
1
1
PEND
0
1
PAGEFAULT
Effect to write value.
DRFCTL0
DRFCTL1
0
0
1
0
1
1
0
1
No operation
Start/Restart
Init-start
Abort
DRFClr/DRFStx : "DRF clear control bit"(write)/”DRF status transmit”(read)
When DRFClr is set to “1”,all state in DRF and Data in DRF and Bulky data buffer is cleared.
This bit clears itself after DRF cleared.
Should not assert when DRFCtl = busy.
When this bit used for read it specifies whether current transaction is status transfer or not.
DRFst : "DRF Packetizer Transfer Status” (read)
DRFst represents DRF is transferring Transaction status data.
DRFNdIdval : “DRF NODE Id Valid”
represents Node ID in DRF Destination Id is valid. Writing to DRF destination Id Register sets this bit, and cleared by
Page 65
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
bus reset.
note) This bit will be cleared after bus reset. And this bit should be 1 when re-setting destination ID on 0xC8 again.
DRFNotify : “DRF Notify”
When this bit is set to one, Transaction status data is transferred following DRF data transfer.
DRFSpd : "DRF transaction speed"
DRFSpd specifies the speed used by the DRF Packetizer.
2'b00 : 100Mbits/s
2'b01 : 200Mbits/s
2'b10 : 400Mbits/s
2'b11 : Not valid
DRFMaxPayload: "DRF transfer maximum payload"
DRFMaxPayload is the maximum data transfer length that the DRF Packetizer requests
in a single read transaction.
The maximum data transfer length is specified as 2^(DRFMaxPayload + 2).
PgTblEn : "Page table enable"
This bit control fetching of PgTblEn.
When PgTblEn is set to 1, enable page table enable fetch.
When PgTblEn is 0 and AutoPg is set 1, disable page table fetch.
DRF_destination_offset_hi and DRF_destination_offset_lo data point for page table address when PgTblEn is set 1.
When PgTbleEn is 0, DRF_destination_offset_hi and DRF_destination_offset_lo are data area.
DRFPageSize: "DRF receive page size"
DRFPageSize specifies the underlying page size of data buffer memory.
Any one request packet is not permitted to cross a page boundary.
DRFPageSize value of zero indicates that the underlying page size is not specified.
Otherwise, the page size is 2^(DRFPageSize + 8).
DRF_BlockSize/DRF_BlockCount: "DRF receive block size in byte / DRF receive block count"
When LngSiz in DMA Control(0x90) is set to 0, this value shows DRF_BlockSize.
When LngSiz is set to 1, it showed DRF_BlockCount.
DRFBlockSize specifies the received blocksize value.
DRF_BlockCount specifies the number of received blocks. DRF_BlockCount is decremented
during reception automatically.
Page 66
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0xC0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
DRF
Control0
Reserved
0
DRFBIdEn
DRFSIdEn
DRFAdrEn
(direct
mode)
Read/
Write
R/W
N/A
Default
0 0 0
29’h0000_0000
BusReset
U
U
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
Table 3-52. CFR map (0xC0)
Note) When DRPktz is set to “0” in “0x90”,this table is used.
DRFBIdEn : "DRF bus id check enable"
Enables Bus Id check for write request routing control.
caution) Valid only during DRFAdrEn=1
DRFSIdEn : "DRF source id check enable"
Enables Source Id check for write request routing control.
caution) Valid only during DRFAdrEn=1
DRFAdrEn : "DRF address enable"
Enables write request routing function.
In this mode write request packet with destination address within the area specified by
DRF Control0/1/2 address is stored in DRF.
caution) It’s accepted to setting illegal qty which stick out areas. But would not work correct.
All match packet
unmatch
source_ID
unmatch address
Page 67
0xC0(DRFBIdEn,DRFSIdEn,DRFAdrEn)
000
001
010
011
ARF
DRF
ARF
DRF
100
ARF
101
DRF
110
ARF
111
DRF
ARF
DRF
ARF
ARF
ARF
DRF
ARF
ARF
ARF
ARF
ARF
ARF
ARF
ARF
ARF
ARF
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0xC4
(packetizer
mode)
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
DRF
Control1
DRF_BlockCount/DRF_BlockSize
Read/
Write
R/W
Default
32’h0000_0000
BusReset
U
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
6
2
7
2
8
2
9
3
0
3
1
Table 3-53. CFR map (0xC4)
DRF_BlockCount/DRF_BlockSize: "DRF receive block size in byte / DRF receive block count"
When LngSiz in DMA Control(0x90) is set to 1, this value shows DRF_BlockSize.
When LngSiz is set to 0, it showed DRF_BlockCount.
DRFBlockSize specifies the received blocksize value.
DRF_BlockCount specifies the number of received blocks. DRF_BlockCount is decremented
during reception automatically.
0xC4
(direct mode)
0
1
2
3
4
DRF
Control1
Read/
Write
Default
BusReset
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
DRF_destination_Width
R/W
32’h0000_0000
U
Table 3-54. CFR map (0xC4)
Note) When DRAdrEn is set to “1” in “0xC0”,this table is used.
DRF_destination_Width : "DRF destination width"
DRF_destination_Width specifies the address depth to routing write request packet to DRF.
Caution) there is a limit to the value
Page 68
FFFF FFFF > DRF_destination_Width + DRF_destination_offset_lo
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0xC8
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
DRF
Control2
DRF_destination_ID
DRF_destination_offset_hi
Read/
Write
R/W
R/W
Default
BusReset
16’h0000
U
16’h0000
U
2
9
3
0
3
1
2
9
3
0
3
1
Table 3-55. CFR map (0xC8)
DRF_destination_ID : "DRF receive destination ID"
DRF_destination_ID specifies transferred destination ID.
DRF_destination_offset_hi: "DRF receive destination offset start high"
DRF_destination_offset_hi specifies transferred destination offset high.
0xCC
DRF
Control3
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
9
DRF_destination_offset_lo
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
00
R/W
N/A
Read/
Write
Default
BusReset
1
8
30’h0000_0000
U
00
00
Table 3-56. CFR map (0xCC)
DRF_destination_offset_l
o : "DRF receive destination start offset low"
DRF_destination_offset_lo specifies transferred destination offset low.
Page 69
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0xD0
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
DRF
Header0
DRF_Header0
Read/
Write
R/O
Default
32’h0000_0000
BusReset
U
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
Table 3-57. CFR map (0xD0)
DRF_Header0 : "First quadlet of received packet header in DRF"
When DRHStr in DMA Control(0x90) is set to 1, the host can read the first header quadlet of
a received packet header after the header has been copied into DRF Header0.
0xD4
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
DRF
Header1
Read/
Write
Default
BusReset
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
DRF_Header1
R/O
32’h0000_0000
U
Table 3-58. CFR map (0xD4)
DRF_Header1 : “Second quadlet of received packet header in DRF”
When DRHStr in DMA Control(0x90) is set to 1, the host can read the first header quadlet of
a received packet header after the header has been copied into DRF Header1.
0xD8
DRF
Header2
Read/
Write
Default
BusReset
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
DRF_Header2
R/O
32’h0000_0000
U
Table 3-59. CFR map (0xD8)
Page 70
1
8
1
9
2
0
2
1
2
2
2
3
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
DRF_Header2 : “Third quadlet of received packet header in DRF”
When DRHStr in DMA Control(0x90) is set to 1, the host can read the first header quadlet of
a received packet header after the header has been copied into DRF Header2.
0xDC
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
DRF
Header3
DRF_Header3
Read/
Write
R/O
Default
32’h0000_0000
BusReset
U
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
Table 3-60. CFR map (0xDC)
DRF_Header3 : “Forth quadlet of received packet header in DRF”
When DRHStr in DMA Control(0x90) is set to 1, the host can read the first header quadlet of
a received packet header after the header has been copied into DRF Header3.
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
DRF_
TxAck
4
Reserved
3
Fll0
2
Reserved
1
Rx_Spd
0
Reserved
0xE0
Read/
Write
N/A
R/O
N/A
R/O
N/A
R/O
Default
BusReset
14’h000
14’h000
0 0
6’h00
6’h00
0 0
4’h0
4’h0
4’h0
U
DRF Tailor
U
U
Table 3-61. CFR map (0xE0)
Rx_Spd : "DRF receive speed"
Rx_Spd specifies the speed that DRF receives a response packet with.
2'b00 : 100Mbits/s
2'b01 : 200Mbits/s
2'b10 : 400Mbits/s
2'b11 : Not valid
Fll0 : "The number of fill zero byte"
The Fll0 specifies the number of zero-fill bytes in the last quadlet of the packet data payload.
Page 71
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
2'b00 : no zero fill bytes.
2'b01 : 3 zero fill byte.
2'b10 : 2 zero fill bytes.
2'b11 : 1 zero fill bytes.
DRF_TxAck : "DRF send Ack"
DRF_TxAck specifies the sent acknowledgement after receiving the packet.
4'b0000 : Reserved
4'b0001 : Ack_complete
4'b0010 : Ack_pending
4'b0011 : Reserved
4'b0100 : Ack_Busy_X
4'b0101 : Ack_Busy_A
4'b0110 : Ack_Busy_B
4'b1011 : Ack_Tardy
4'b1100 : Ack_Conflict_Error
4'b1101 : Ack_Data_Error
4'b1110 : Ack_Type_Error
4'b1111 : Ack_Address_Error
0xE4
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
DTF/DRF
Page count
DTF Page Count
DRF Page Count
Read/
Write
R/W
R/W
Default
BusReset
0
U
0
U
Table 3-62. CFR map (0xE4)
DTF /DRF Page Count :
DTF/DRF Page count specifies the number of page table entry to be fetched during data transfer. Any number other than
zero is valid value. This number is decremented following page fetch action.
note) Displaying data decrements during work.
Page 72
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
DhdSel=00
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
N/A
R/
O
R/O
R/
O
R/O
R/O
Default
14’h0000
01
6’h00
00
4’h1
4’h0
BusReset
14’h0000
U
U
U
U
U
DTxTlabel
DTxRT
Read/
Write
DTxSpd
DTx
Head0
DTxPrio
1
DtxTCode
0
Reserved
0xE8
(0xE8)
Table 3-63. CFR map DTxSpd : "DTF/DRF transaction speed code"
DTxSpd represents the speed code with which request packet is been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DTxTlabel : "DTF/DRF transaction tlabel"
DTxTlabel represents the transaction tlabel of the request packet been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DTxRT : "DTF/DRF transmit retry code"
DTxRT represents the transaction retry code of the request packet been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DtxTCode : "DTF/DRF transmit tCode"
DtxTCode represents the transaction tCode of the request packet been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
When DRPktz is enabled, DtxTCode is set to 4'h1 automatically.
DTxPrio : "DTF/DRF transmit priority"
DTxPrio represents the transaction priority of the request packet been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
Page 73
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
DhdSel=00
0xEC
0
1
2
3
DTx
Head1
Read/
Write
Default
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
DTx_destination_ID
DTx_destination_offset_hi
R/O (Note)
R/O (Note)
16’h0000
16’h0000
U
U
BusReset
2
9
3
0
3
1
3
0
3
1
CFR map (0xEC)
Table 3-64. Note)R/W when DTPktz = “0”.
DTx_destination_ID : "DTF/DRF transmit destination ID"
DTx_destination_ID represents destination ID where the request packet is been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DTx_destination_offset_hi : "DTF/DRF transmit destination offset high"
DTx_destination_offset_hi represents destination ID where the request packet is been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DhdSel=00
0xF0
0
1
2
3
DTx
Head2
Read/
Write
Default
BusReset
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
DTx_destination_offset_lo
R/O (Note)
32’h0000_0000
U
Table 3-65. CFR map (0xF0)
Note) R/W when DTPktz = “0”.
DTx_destination_offset_lo : "DTF/DRF transmit destination offset low"
DTx_destination_offset_lo represents the destination ID where the request packet is been transmitting
from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
Page 74
2
7
2
8
2
9
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
DhdSel=00
0xF4
0
1
2
3
4
DTx
Head3
Read/
Write
default
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
DTx_data_length
DTx_extended_tcode
R/O (Note)
R/O (Note)
16’h0008
16’h0000
U
U
BusReset
2
8
2
9
3
0
3
1
2
8
2
9
3
0
3
1
Table 3-66. CFR map (0xF4)
Note) R/W when DTPktz = “0”.
DTx_data_length : "DTF/DRF transmit data length"
DTx_data_length represents data length of the request packet been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DTx_extended_tcode :"DTF/DRF transmit extended tCode"
DTx_extended_tcode represents the extended tCode of the request packet been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DTx
Head0
Read/
Write
R/O
R/O
N/A
Default
4’h0
4’h0
3’h0
BusReset
*1
U
U
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
2
2
3
2
4
2
5
2
6
2
7
R/O
R/O
R/O
N/A
R/O
0
4’h0
4’h0
4’h0
3’h0
0
4’h0
U
U
*1
U
U
U
U
Table 3-67. CFR map (0xE8)
*1 Depend on previous status.
RESP :
Specified status response received.
AckErr : "Ack Error"
Whether the last Ack received for the packet transmitted from DTF has any errors.
When the Ack didn't received nor had parity error and length error, AckErr shows 1.
Page 75
2
1
PAck
9
PAckErr
8
R/O
7
Reserved
6
PRESP
5
PSTAT
4
Ack
3
AckErr
2
Reserved
1
RESP
0
STAT
0xE8
R/O
DhdSel=01
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
When the Ack has no error or any Ack has not been received yet, AckErr shows 0.
ACK :
Specified Ack code received.
STAT : "DTF transaction complete state"
DTF_State is the state that transaction from DRF complete.
4’h0 : The request block transaction from DRF completed successfully
4’h1 : The packet received Ack-pending and fall in split transaction.
4’h2 : The acknowledgement except Ack_complete, Ack_Busy_X and Ack_pending was returned to
the request packet
4’h3 : Reserved
4’h4 : The transaction was stopped because of page table fetch problem.
4’h5 : Reserved
4’h6 : Reserved
4’h7 : The request packet was transmitted Retry_Limit times
4’h8 : Reserved
4’h9 : Reserved
4’hA: The response packet was received but rCode is not complete
4’hB: The response packet was not received in Split_Time
4’hC: The request packet was stop to send because of a bus reset
4’hD: The request packet was removed because of RstTr or Clear
4’hE: Reserved
4’hF: Reserved
PSTAT :
Specified page status code received as above lists.
PRESP :
Specified page status response received.
: "Pagetable Ack Error"
PAckErr
Whether the last Ack received for the pagetable request.
When the Ack didn't received nor had parity error and length error, AckErr shows 1.
When the Ack has no error or any Ack has not been received yet, AckErr shows 0.
PACK :
Specified page Ack code received.
Page 76
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
DhdSel=01
0xEC
0
1
2
3
4
DTx
Head1
Read/
Write
Default
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
Page Number
Reserved
R/O
N/A
0
0
U
0
BusReset
2
6
2
7
2
8
2
9
3
0
3
1
Table 3-68. CFR map (0xEC)
Page Number : "Page number"
Page number specifies the current page number used during current packetization. It is incremented by one, each time
when Packetizer fetches new page table. This number is cleared to zero when Packetizer starts from initial state.
DhdSel=01
0xF0
DTx
Head2
Read/
Write
Default
BusReset
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
5
2
6
Page length
Page table hi
R/O
R/O
0
0
U
U
Table 3-69. CFR map (0xF0)
Page length : "page length"
PageLength field specifies the current page table value used during current packetization.
Page table hi : "page table hi”
Page Table hi field specifies the current page table value used during current packetization.
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2
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TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
DhdSel=01
0xF4
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
DTx
Head3
Read/
Write
default
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
page table lo
R/O
O
BusReset
U
Table 3-70. CFR map (0xF4)
Page table lo : "page table lo”
Page Table lo field specifies the current page table value used during current packetization.
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
Read/
Write
N/A
R/
O
R/O
R/
O
R/O
R/O
Default
14’h0000
01
6’h00
00
4’h1
4’h0
BusReset
14’h0000
U
U
U
U
U
DRxTlabel
DRxRT
DRx
Head0
DRxPrio
1
DRxTCode
0
Reserved
0xE8
DRxSpd
DhdSel=10
Table 3-71. CFR map (0xE8)
DRxSpd : "DTF/DRF transaction speed code"
DTxSpd represents the speed code with which request packet is been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DRxTlabel : "DTF/DRF transaction tlabel"
DTxTlabel represents the transaction tlabel of the request packet been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DRxRT : "DTF/DRF transmit retry code"
DTxRT represents the transaction retry code of the request packet been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DRxTCode : "DTF/DRF transmit tCode"
DtxTCode represents the transaction tCode of the request packet been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
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When DRPktz is enabled, DtxTCode is set to 4'h1 automatically.
DRxPrio : "DTF/DRF transmit priority"
DTxPrio represents the transaction priority of the request packet been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DhdSel=10
0xEC
0
1
2
3
DRx
Head1
Read/
Write
Default
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
DRx_destination_ID
DRx_destination_offset_hi
R/O (Note)
R/O (Note)
16’h0000
16’h0000
U
U
BusReset
2
9
3
0
3
1
3
0
3
1
Table 3-72. CFR map (0xEC)
Note)R/W when DTPktz = “0”.
DTx_destination_ID : "DTF/DRF transmit destination ID"
DTx_destination_ID represents destination ID where the request packet is been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DTx_destination_offset_hi : "DTF/DRF transmit destination offset high"
DTx_destination_offset_hi represents destination ID where the request packet is been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DhdSel=10
0xF0
0
1
2
3
DRx
Head2
Read/
Write
Default
BusReset
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
DRx_destination_offset_lo
R/O (Note)
32’h0000_0000
U
Table 3-73. CFR map (0xF0)
Note) R/W when DTPktz = “0”.
DTx_destination_offset_lo : "DTF/DRF transmit destination offset low"
DTx_destination_offset_lo represents the destination ID where the request packet is been transmitting
from FIFO.
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DHdSel in DMA Control(0x90) selects either DTF or DRF.
DhdSel=10
0xF4
0
1
2
3
4
DRx
Head3
Read/
Write
default
5
6
7
8
1
0
9
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
DRx_data_length
DRx_extended_tcode
R/O (Note)
R/O (Note)
16’h0008
16’h0000
U
U
BusReset
2
8
2
9
3
0
3
1
2
8
2
9
3
0
3
1
Table 3-74. CFR map (0xF4)
Note) R/W when DTPktz = “0”.
DTx_data_length : "DTF/DRF transmit data length"
DTx_data_length represents data length of the request packet been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DTx_extended_tcode :"DTF/DRF transmit extended tCode"
DTx_extended_tcode represents the extended tCode of the request packet been transmitting from FIFO.
DHdSel in DMA Control(0x90) selects either DTF or DRF.
DRx
Head0
Read/
Write
R/O
R/O
N/A
Default
4’h0
4’h0
3’h0
BusReset
*1
U
U
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
RESP :
Specified status response received.
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2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
R/O
R/O
R/O
N/A
R/O
0
4’h0
4’h0
4’h0
3’h0
0
4’h0
U
U
*1
U
U
U
U
Table 3-75. CFR map (0xE8)
STAT :
Specified status code received as following lists.
1
9
PAck
9
PAckErr
8
R/O
7
Reserved
6
PRESP
5
PSTAT
4
Ack
3
AckErr
2
Reserved
1
RESP
0
STAT
0xE8
R/O
DhdSel=11
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
ACK :
Specified Ack code received.
STATE : "DRF packetizer transaction complete state"
DTF_State is the state that transaction from DRF complete.
4’h0 : The request block transaction from DRF completed successfully
4’h1 : The packet received Ack-pending and fall in split transaction.
4’h2 : The acknowledgement except Ack_complete, Ack_Busy_X and Ack_pending was returned to
the request packet
4’h3 : Reserved
4’h4 : The transaction was stopped because of page table fetch problem.
4’h5 : Reserved
4’h6 : Reserved
4’h7 : The request packet was transmitted Retry_Limit times
4’h8 : Reserved
4’h9 : Reserved
4’hA: The response packet was received but rCode is not complete
4’hB: The response packet was not received in Split_Time
4’hC: The request packet was stop to send because of a bus reset
4’hD: The request packet was removed because of RstTr or Clear
4’hE: Reserved
4’hF: Reserved
PSTAT :
Specified page status code received as above lists.
PRESP :
Specified page status response received.
PACK :
Specified page Ack code received.
DhdSel=11
0xEC
0
1
2
3
4
DRx
Head1
Read/
Write
Default
BusReset
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
Page 81
1
9
2
0
2
1
2
2
2
3
2
4
2
5
Page Number
Reserved
R/W
N/A
0
0
U
0
Table 3-76. CFR map (0xEC)
Page Number : "Page number"
1
8
2
6
2
7
2
8
2
9
3
0
3
1
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Page number specifies the current page number used during current packetization. It is incremented by one, each time
when Packetizer fetches new page table. This number is cleared to zero when Packetizer starts from initial state.
DhdSel=11
0xF0
0
1
2
3
4
5
DRx
Head2
Read/
Write
Default
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
Page length
Page table hi
R/O
R/O
0
0
U
U
BusReset
2
7
2
8
2
9
3
0
3
1
2
7
2
8
2
9
3
0
3
1
Table 3-77. CFR map (0xF0)
Page length : "page length"
PageLength field specifies the current page table value used during current packetization.
Page table hi : "page table hi”
Page Table hi field specifies the current page table value used during current packetization.
DhdSel=11
0xF4
DRx
Head3
Read/
Write
default
BusReset
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
page table lo
R/O
O
U
Table 3-78. CFR map (0xF4)
Page table lo : “page table
lo”
Page Table lo field specifies the current page table value used during current packetization.
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Default
BusReset
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
7
R/O // R/W
30’h0000_0000
U
Table 3-79. CFR map (0xF8)
LogATF : "Record packets transmitted from ATF on LOG"
When LogATF is set to 1, packets transmitted from ATF shall be recorded on Log.
When LogATF is set to 0, packets transmitted from ATF shall not be done.
LogARF : "Record packets placed into ARF on LOG"
When LogARF is set to 1, packets placed into ARF shall be recorded on Log.
When LogARF is set to 0, packets placed into ARF shall not be done.
LogMAgnt : "Record packets accessed to management agent on LOG"
When LogMAgnt is set to 1, packets accessed to management agent shall be recorded on Log.
When LogMAgnt is set to 0, packets placed into MRF shall not be done.
LogMTQ : "Record packets transmitted from MTQ on LOG"
When LogMTQ is set to 1, packets transmitted from MTQ shall be recorded on Log.
When LogMTQ is set to 0, packets transmitted from MTQ shall not be done.
LogMRF : "Record packets placed into MRF on LOG"
When LogMRF is set to 1, packets placed into MRF shall be recorded on Log.
When LogMRF is set to 0, packets placed into MRF shall not be done.
LogAgnt : "Record packets accessed to command block agent on LOG"
When LogAgnt is set to 1, packets accessed to command agent shall be recorded on Log.
When LogAgnt is set to 0, packets placed into MRF shall not be done.
LogCTQ : "Record packets transmitted from CTQ on LOG"
When LogCTQ is set to 1, packets transmitted from CTQ shall be recorded on Log.
When LogCTQ is set to 0, packets transmitted from CTQ shall not be done.
LogCRF : "Record packets placed into CRF on LOG"
When LogCRF is set to 1, packets placed into CRF shall be recorded on Log.
When LogCRF is set to 0, packets placed into CRF shall not be done.
LogDTFRq : "Record write request packets transmitted from DTF on LOG"
When LogDTFRq is set to 1, write request packets transmitted from DTF shall be recorded on Log.
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6
2
8
2
9
3
0
3
1
N/A
1
2
ROMAddr
1
1
LogThere
OR
1
0
LogCD
LogFull
9
R/O
R/W
8
ROMValid
7
R/W
6
LogRetry
ShortLog
LogClr
XLOG
5
LogARROM
4
LogDTFRq
LogDTFRs
LogDRFRq
LogDRFRs
3
N/A
R/W
S/C
Read/
Write
2
LogMTQ
LogMRF
LogAgnt
LogCTQ
LogCRF
( XLOG = 0 )
1
LogMAgnt
Log/ROM
Control
0
LogATF
LogARF
0xF8
0 0
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
When LogDTFRq is set to 0, they shall not be done.
LogDTFRs : "Record write response packets received by the DTF on LOG"
When LogDTFRs is set to 1, write response packets received by DTF shall be recorded on Log.
When LogDTFRs is set to 0, they shall not be done.
LogDRFRq : "Record read request packets transmitted by DRF on LOG"
When LogDRFRq is set to 1, read request packets transmitted by DRF shall be recorded on Log.
When LogDRFRq is set to 0, they shall not be done.
LogDRFRs : "Record read response packets received into DRF on LOG"
When LogDRFRs is set to 1, read response packets received into DRF shall be recorded on Log.
When LogDRFRs is set to 0, they shall not be done.
LogARROM : "Record auto-response packet from Configuration ROM on LOG"
When LogARROM is set to 1, auto-response packets including data read from Configuration ROM shall be
recorded on Log.
When LogARROM is set to 0, they shall not be done.
LogRetry : "Record Retry Packet"
When LogRetry is set to 1, retry packet shall be recorded on Log.
When LogRetry is set to 0, they shall not be done.
ShortLog : "Short format log"
When ShortLog is set to 1, packets in general format shall be recorded on Log.
When ShortLog is set to 0, packets in short format shall be recorded on Log.
LogClr : "Log clear control bit"
When LogClr is set to 1, Log is cleared.
This bit clears itself after the clear.
XLOG : "Select Log data or ConfigROM data"
When XLOG is set to 1, the data read from Log Data( 0xFC ) is ConfigROM data.
When XLOG is set to 0, the data read from Log Data( 0xFC ) is Log data.
note) After XLOG set to 0, please clear LOG using LogClr bit.
ROMValid : "Configuration ROM valid"
When ROMValid is set to 1, the data in Configuration ROM is valid.
The receiver shall return Ack_pending for all quadlet read requests addressed to this Configuration ROM
and the respective quadlet read response packets shall be transmitted automatically.
When ROMValid is set to 0, the data in Configuration ROM is invalid.
The receiver will return Ack_Tardy for all quadlet read requests addressed to this Configuration ROM.
LogCD : "Log control bit"
When the first or the last quadlet of a packet is being read from
Log Data(0xFC), LogCD shows 1. Otherwise, LogCD shows 0.
LogFull : "Log Full"
When LogFull shows 1, Log is full.
Otherwise, Log is not full.
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5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
Reserved
Reserved
4
Adder
N/A
R/O
3
ROMValid
2
R/W
R/W
1
DTFSt
DRFst
0
R/W
R/W
0xF8
XLOG
LogThere/ROMAddr : "Log available flag / Address of Configuration ROM"
When XLOG is set to 1, LogThere/ROMAddr is ROMAddr mode.
ROMAddr is the address accessed by the host in Configuration ROM.
When XLOG is set to 0, LogThere/ROMAddr is LogThere mode.
Log has space available for LogThere quadlets.
R/W
14’h0000_0000
U
0 0
U U
Log/ROM
Control
(XLOG=1)
Read/
Write
Default
BusReset
0 0
2
7
2
8
Table 3-80. CFR map (0xF8)
DTFSt : “DTF status Block access mode”
When DTFSt is set to 1, Adder in this field and 0xFc menu access address and Data for DTF status block.
DRFst : “DRF status Block access mode”
When DRFSt is set to 1, Adder in this field and 0xFc menu access address and Data for DRF status block.
XLOG : "Select Log data or ConfigROM data"
When XLOG is set to 1, the data read from Log Data( 0xFC ) is ConfigROM data.
When XLOG is set to 0, the data read from Log Data( 0xFC ) is Log data.
ROMValid : "Configuration ROM valid"
When ROMValid is set to 1, the data in Configuration ROM is valid.
The receiver shall return Ack_pending for all quadlet read requests addressed to this Configuration ROM
and the respective quadlet read response packets shall be transmitted automatically.
When ROMValid is set to 0, the data in Configuration ROM is invalid.
The receiver will return Ack_Tardy for all quadlet read requests addressed to this Configuration ROM.
Adder:
Where address for DTF/DRF status Block and config ROM Write/Read.
Caution) Do not read within beyond the limit of writting area.
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TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
0xFC
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
Log
Data
LogRead/ROMAccess
Read/
Write
CRW
Default
32’h0000_0000
BusReset
U
2
0
2
1
2
2
2
3
2
4
2
5
2
6
Table 3-81. CFR map (0xFC)
LogRead/ROMAccess : "Log data read access register/Configuration ROM data read access register"
Meaning in this field is determined as bellow.
XLOG
DTFSt
DRFst
LogRead/ROMAccess field
0
X
X
LogRead Access
1
0
0
Config Rom access
1
1
0
DTF status Block access
1
0
1
DRF status Block access
1
1
1
NA
note)
Do not access (Read/Write) datas exceeding input packet quantities.
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TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
4. TSB43LV81 Data Formats
The data formats for transmission and reception for data are shown in the following sections. The transmit formats
describe the expected organization of data presented to the TSB43LV81 at the host-bus interface. The received formats
describe the data formats that the TSB43LV81 presents to the host-bus interface.
4.1.
Generic Asynchronous Transmit (ATF Interface to TSB43LV81)
Generic Asynchronous transmit refers to the use of the asynchronous-transmit FIFO (ATF) interface. Packet transmission
with ATF will be written with below format. As with other packet transmissions, it is accessed through CFR (0x70~0x78)
address.
4.1.1.
Generic Quadlet Transmit
The quadlet-transmit format is shown in Figure 2. The first quadlet contains packet control information. The second and
third quadlets contain the 64-bit, quadlet-aligned address. The fourth quadlet is data used only for write requests and read
responses. For read requests and write responses, the quadlet data field is omitted.
0 1 2 3 4 5 6 7 8 9
Reserved
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
spd
tlabel
destination ID
rt
tCode
Destination_Offset_high
destination_offset_Low
quadlet data
Figure 2. Generic Transmit Format of Packet with quadlet data
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Table 4-1. Quadlet-Transmit Format
FIELD NAME
DESCRIPTION
Spd
This field indicates the speed at which this packet is to be sent. 00 = 100 Mb/s, 01 = 200
Mb/s, and 10 = 400 Mb/s, and 11 is undefined for this implementation.
Tlabel
This field is the transaction label, which is a unique tag for each outstanding transaction
between two nodes. This is used to pair up a response packet with its corresponding
request packet. This tlavel must be set except 10_xxxx, 11_xxxx, 01_xxxx which is
Block Read Request handling.
Rt
The retry code for this packet is : 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
Tcode
tCode is the transaction code for this packet. (see Table 6-10 of IEEE-1394 standard)
Prior
The priority level for this packet. For cable implementation, the value of the bits must be
zero. For backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE-1394
standard.
DestinationID
This is the concatenation of the 10-bit bus number and the 6-bit node number that forms
the destination node address of this packet.
Destination OffsetHigh,
destination OffsetLow
The concatenation of these two fields addresses a quadlet in the destination nodes
address space. This address must be quadlet aligned (modulo 4).
quadlet data
For write requests and read responses, this field holds the data to be transferred. For
write responses and read requests, this field is not used and should not be written into
the FIFO.
4.1.2.
Generic Block Transmit
The block-transmit format is shown in Figure 3. The first quadlet contains packet-control information. The second and
third quadlets contain the 64-bit address. The first 16 bits of the fourth quadlet contains the dataLength field. This is the
number of bytes of data in the packet. The remaining 16 bits represent the extended_tCode field. (See Table 6-11 of the
IEEE-1394 standard for more information on extended_tCodes.) The block data, if any, follows the extended_tCode.
0 1 2 3 4 5 6 7 8 9
Reserved
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
spd
tlabel
destination ID
rt
tCode
destination_Offset_high
destination_offset_Low
data_length
extended_tCode
block data
Figure 3. Generic Transmit Format of Packet with block data
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Table 4-2. Block-Transmit Format Functions
FIELD NAME
DESCRIPTION
spd
This field indicates the speed at which this packet is to be sent. 00 = 100 Mb/s, 01 = 200 Mb/s,
and 10 = 400 Mb/s, and 11 is undefined for this implementation.
tlabel
This field is the transaction label, which is a unique tag for each outstanding transaction between
two nodes. This is used to pair up a response packet with its corresponding request packet. This
tlavel must be set except 10_xxxx, 11_xxxx, , 01_xxxx which is Block Read Request handling.
rt
The retry code for this packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode
tCode is the transaction code for this packet (see Table 6-10 of IEEE-1394 standard).
prior
The priority level for this packet. For cable implementation, the value of the bits must be zero. For
backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE-1394 standard.
destinationID
This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node
address to which this packet is being sent.
destination OffsetHigh,
destination OffsetLow
The concatenation of these two fields addresses a quadlet in the destination node’s address space.
This address must be quadlet aligned (modulo 4). The upper four bits of the destination
OffsetHigh field are used as the response code for lock-response packets and the remaining bits
are reserved.
dataLength
The number of bytes of data to be transmitted in the packet.
extended_tCode
The block extended_tCode to be performed on the data in this packet. See Table 6-11 of the
IEEE-1394 standard.
block data
The data to be sent. If dataLength is 0, no data should be written into the FIFO for this field.
Regardless of the destination or source alignment of the data, the first byte of the block must
appear in byte 0 of the first quadlet.
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4.2.
Generic Asynchronous Receive (TSB43LV81 to ARF Interface)
Transmission packets from ATF are generally received to ARF. ARF also receives request packets from other nodes,
except packets to AGENT. Received packets will be stored in ARF FIFO as below.
4.2.1.
Generic Quadlet Receive
The quadlet-receive format is shown in Figure 4. The first quadlet is a packet token and contains packet-control
information.. The first 16 bits of the second quadlet contains the destination bus and node number, and the remaining 16
bits contain packet-control information. The first 16 bits of the third quadlet contains the bus and node number of the
source, and the remaining 4 bits of the third contain packet-control information. The fifth quadlet contains data that was
used by write requests and read responses. For read requests and write responses, the quadlet data field is omitted.
0 1 2 3 4 5 6 7 8 9
status
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
Reserved
spd
Reserved
Destination ID
Source ID
tlabel
rCode
rt
Ack
tCode
Reserved
Reserved
quadlet data
Figure 4. Generic Received Format of Packet with quadlet data
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Table 4-3. Quadlet-Receive Format Functions
FIELD NAME
status
DESCRIPTION
Received packet will go into each Rx FIFO with each status. Each status are shown as below.
spd
This field indicates the speed at which this packet is to be sent. 00 = 100 Mb/s, 01 = 200 Mb/s, and
10 = 400 Mb/s, and 11 is undefined for this implementation.
Ack
This field holds the acknowledge sent by the receiver for this packet. (See Table 6-13 of the IEEE1394 standard).
destinationID
This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node
address to which this packet is being sent.
tlabel
This field is the transaction label, which is a unique tag for each outstanding transaction between two
nodes. This is used to pair up a response packet with its corresponding request packet.
rt
The retry code for this packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode
TCode is the transaction code for this packet. (See Table 6-9 of the IEEE-1394 standard).
prior
The priority level for this packet. For cable implementation, the value of the bits must be zero. For
backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE-1394 standard.
sourceID
This is the node ID of the sender of this packet.
rCode
This field is the response code for this packet. (See Table 6-11 of the IEEE-1394 standard).
quadlet data
For write requests and read responses, this field holds the transferred data. For write responses and
read requests, this field is not present.
<status>
4’h0 : Ack_comp was returned to the request packet
Transaction is terminated by SplitEn =1 in case of receiving Ack_Pnd for request packet on ATF.
4’h1 : The packet, which does not require any acknowledgement, was transmitted
4’h2 : The acknowledgement except Ack_comp, Ack_Busy_X and Ack_Pnd was returned to
the request packet. Ack_Pnd received for Response packettransmit on ATF/
4’h3 : Ack was not returned to the request packet
long acknowledge receive, short acknowledge receive, acknowledge parity error.
4’h4 : No next packet on CTQ due to fetched packet which next ORB is Invalid
4’h5 : Nex request packet is set up to CTQ because fetched packet which having next ORB pointer.
4’h6 : Reserved
4’h7 : Retry time out due to retry count exceed Retry_limit value.
4’h8 : CTQ: no request packet in CTQ due to received packet which has invalid NextORB or CnxFtEn=0.
MTQ: response packet
ATF: response packet by split transaction request
4’h9 : Request packet for getting nextORB is setup to CTQ
4’hA : The response packet was received but rCode is not complete
4’hB : Reserved
4’hC : Reserved
4’hD : Reserved
4’hE : Reserved
4’hF: Received except response packet. (expect split trnsaction response)
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4.2.2.
Generic Block Receive
The block-receive format is shown in Figure 5. The first 16 bits of the second quadlet contain the bus and node number
of the destination node, and the last 16 bits contain packet-control information. The first 16 bits of the third quadlet
contain the bus and node number of the source node, and the last 16 bits of the third quadlet and all of the fourth quadlet
contain the 48-bit, quadlet-aligned destination offset address. All remaining quadlets contain data that is used only for
write requests and read responses. For block read requests and block write responses, the data field is omitted.
0 1 2 3 4 5 6 7 8 9
status
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
Reserved
spd
Reserved
Destination ID
Source ID
Tlabel
rt
Rcode
Ack
tCode
prior
Reserved
Reserved
data_length
extended_tCode
block data
Figure 5. Generic Received Format of Packet with block data
Table 4-4. Block-Receive Format Functions
FIELD NAME
status
DESCRIPTION
Received packet will go into each Rx FIFO with each status. Each status are shown as below.
spd
This field indicates the speed at which this packet is to be sent. 00 = 100 Mb/s, 01 = 200 Mb/s, and
10 = 400 Mb/s, and 11 is undefined for this implementation.
Ack
This field holds the acknowledge sent by the receiver for this packet. (See Table 6-13 of the IEEE1394 standard).
destinationID
This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node
address to which this packet is being sent.
tlabel
This field is the transaction label, which is a unique tag for each outstanding transaction between two
nodes. This is used to pair up a response packet with its corresponding request packet.
rt
The retry code for this packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode
TCode is the transaction code for this packet. (See Table 6-9 of the IEEE-1394 standard).
prior
The priority level for this packet. For cable implementation, the value of the bits must be zero. For
backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE-1394 standard.
sourceID
This is the node ID of the sender of this packet.
rCode
This field is the response code for this packet. (See Table 6-11 of the IEEE-1394 standard).
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data-length
For write request, read responses, and locks, this field indicates the number of bytes being
transferred. For read requests, this field indicates the number of bytes of data to be read. A writeresponse packet does not use this field. Note that the number of bytes does not include the head, only
the bytes of block data.
extended_tCode
The block extended_tCode to be performed on the data in this packet. See Table 6-11 of the IEEE1394 standard.
block data
For write requests and read responses, this field holds the transferred data. For write responses and
read requests, this field is not present.
<status>
4’h0 : Ack_comp was returned to the request packet
Transaction is terminated by SplitEn =1 in case of receiving Ack_Pnd for request packet on ATF.
4’h1 : The packet, which does not require any acknowledgement, was transmitted
4’h2 : The acknowledgement except Ack_comp, Ack_Busy_X and Ack_Pnd was returned to
the request packet. Ack_Pnd received for Response packettransmit on ATF/
4’h3 : Ack was not returned to the request packet
long acknowledge receive, short acknowledge receive, acknowledge parity error.
4’h4 : No next packet on CTQ due to fetched packet which next ORB is Invalid
4’h5 : Nex request packet is set up to CTQ because fetched packet which having next ORB pointer.
4’h6 : Reserved
4’h7 : Retry time out due to retry count exceed Retry_limit value.
4’h8 : CTQ: no request packet in CTQ due to received packet which has invalid NextORB or CnxFtEn=0.
MTQ: response packet
ATF: response packet by split transaction request
4’h9 : Request packet for getting nextORB is setup to CTQ
4’hA : The response packet was received but rCode is not complete
4’hB : Reserved
4’hC : Reserved
4’hD : Reserved
4’hE : Reserved
4’hF: Received except response packet. (expect split trnsaction response)
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4.3.
DTF/DRF packet format
4.3.1.
DRF Packet format
0 1 2 3 4 5 6 7 8 9
status
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
Reserved
spd
Reserved
Destination ID
Source ID
Tlabel
rt
Rcode
Ack
tCode
prior
Reserved
Reserved
data_length
extended_tCode
block data
Figure 6. DRF Packet format with block data
Table 4-5. Block-Receive Format Functions
FIELD NAME
status
DESCRIPTION
Received packet will go into each Rx FIFO with each status. Each status are shown as below.
spd
This field indicates the speed at which this packet is to be sent. 00 = 100 Mb/s, 01 = 200 Mb/s, and
10 = 400 Mb/s, and 11 is undefined for this implementation.
Ack
This field holds the acknowledge sent by the receiver for this packet. (See Table 6-13 of the IEEE1394 standard).
destinationID
This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node
address to which this packet is being sent.
tlabel
This field is the transaction label, which is a unique tag for each outstanding transaction between two
nodes. This is used to pair up a response packet with its corresponding request packet.
rt
The retry code for this packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode
TCode is the transaction code for this packet. (See Table 6-9 of the IEEE-1394 standard).
prior
The priority level for this packet. For cable implementation, the value of the bits must be zero. For
backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE-1394 standard.
sourceID
This is the node ID of the sender of this packet.
rCode
This field is the response code for this packet. (See Table 6-11 of the IEEE-1394 standard).
data-length
For write request, read responses, and locks, this field indicates the number of bytes being
transferred. For read requests, this field indicates the number of bytes of data to be read. A write-
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response packet does not use this field. Note that the number of bytes does not include the head, only
the bytes of block data.
extended_tCode
The block extended_tCode to be performed on the data in this packet. See Table 6-11 of the IEEE1394 standard.
block data
For write requests and read responses, this field holds the transferred data. For write responses and
read requests, this field is not present.
<status>
4’h0 : The request block transaction from DRF completed successfully
4’h1 : The packet received Ack-pending and fall in split transaction.
4’h2 : The acknowledgement except Ack_complete, Ack_Busy_X and Ack_pending was returned to
the request packet
4’h3 : Reserved
4’h4 : The transaction was stopped because of page table fetch problem.
4’h5 : Reserved
4’h6 : Reserved
4’h7 : The request packet was transmitted Retry_Limit times
4’h8 : Reserved
4’h9 : Reserved
4’hA: The response packet was received but rCode is not complete
4’hB: The response packet was not received in Split_Time
4’hC: The request packet was stop to send because of a bus reset
4’hD: The request packet was removed because of RstTr or Clear
4’hE: Reserved
4’hF: Reserved
4.3.2.
DTF packet format
0 1 2 3 4 5 6 7 8 9
Reserved
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
spd
tlabel
destination ID
rt
tCode
destination_Offset_high
destination_offset_Low
data_length
extended_tCode
block data
Figure 7. DTF Packet Format with block data
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Table 4-6. Block-Transmit Format Functions
FIELD NAME
DESCRIPTION
spd
This field indicates the speed at which this packet is to be sent. 00 = 100 Mb/s, 01 = 200 Mb/s,
and 10 = 400 Mb/s, and 11 is undefined for this implementation.
tlabel
This field is the transaction label, which is a unique tag for each outstanding transaction between
two nodes. This is used to pair up a response packet with its corresponding request packet. This
tlavel must be set 01_xxxx which is Block Read Request handling.
rt
The retry code for this packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode
tCode is the transaction code for this packet (see Table 6-10 of IEEE-1394 standard).
prior
The priority level for this packet. For cable implementation, the value of the bits must be zero. For
backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE-1394 standard.
destinationID
This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node
address to which this packet is being sent.
destination OffsetHigh,
destination OffsetLow
The concatenation of these two fields addresses a quadlet in the destination node’s address space.
This address must be quadlet aligned (modulo 4). The upper four bits of the destination
OffsetHigh field are used as the response code for lock-response packets and the remaining bits
are reserved.
dataLength
The number of bytes of data to be transmitted in the packet.
extended_tCode
The block extended_tCode to be performed on the data in this packet. See Table 6-11 of the
IEEE-1394 standard.
block data
The data to be sent. If dataLength is 0, no data should be written into the FIFO for this field.
Regardless of the destination or source alignment of the data, the first byte of the block must
appear in byte 0 of the first quadlet.
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4.4.
Phy Packet common format
The format of the transmitted Phy configuration packet is shown in Figure 6. The Phy configuration packet transmit
contains two quadlets, which are loaded into the ATF. The first quadlet is written to address 70h. The second quadlet is
written to address 78h. The 00E0h in the first quadlet tells the LINK that this is the Phy configuration packet. The 'Eh' is
then replace with 0h before the packet is transmitted to the Phy interface.
There is a possibility of a false header error on receipt of a Phy configuration packet. If the first 16 bits of a Phy
configuration packet happen to match the destination identifier of a node (bus number and node number), the
TSB41LV81 issues a header error since the node misinterprets the Phy configuration packet as a data packet addressed to
the node.
0 1 2 3 4 5 6 7 8 9
0 0
root_ID
R T
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
gap_cnt
Logical inverse of first quadlet
0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 6. Phy Configuration Format
Table 4-5. Phy Configuration Format Functions
FIELD NAME
00
DESCRIPTION
This field is the Phy configuration packet identifier.
root_ID
This field is the physical_ID of the node to have its force_root bit set (only meaningful when R is
set).
R
When R is set, the force-root bit of the node identified in root_ID is set and the force_root bit of all
other nodes are cleared. When R is cleared, root_ID is ignored.
T
When T is set, the PHY_CONFIGURATION.gap_count field of all the nodes is set to the value in
the gap_cnt field.
gap_cnt
This field contains the new value for PHY_CONFIGURATION.gap_count for all nodes. This value
goes into effect immediately upon receipt and remains valid after the next bus reset. After the second
reset, gap_cnt is set to 63h unless a new Phy configuration packet is received.
A Phy configuration packet with R = 0, and T = 0 is reserved and is ignored when received .
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4.5.
PHY other packet formats
4.5.1.
Link-On packet
Reception of the following cable PHY packet shall cause a PH_EVENT.indication on LINK_ON.
0 1 2 3 4 5 6 7 8 9
0 1
phy_ID
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
Logical inverse of first quadlet
FIELD NAME
Phy_ID
4.5.2.
DESCRIPTION
Physical node identifier of the destination of this packet.
PHY configuration packet
It is possible to configure Serisal Bus performance in the following ways.
A) Optimize the gap_count used by all nodes to a smaller value (appropriate to the actual worst case round-trip
delay between any two nodes); and
B) Force a paticular node to be the root after the next bus initialization (for instance, to insure that the root is
cycle master capable).
Both of these actions shall be effect for all nodes (including the originator) by means of PHY configuration packet
show bellow. The PH_CONTROL.request service affects only the local node and is not recommended for changes
to either gap_count or force_root.
0 1 2 3 4 5 6 7 8 9
0 0
Root_ID
R T
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
gap_count
0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
Logical inverse of first quadlet
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FIELD NAME
DESCRIPTION
root_ID
This field is the physical_ID of the node to have its force_root bit set (only meaningful when R is
set).
R
When R is set, the force-root bit of the node identified in root_ID is set and the force_root bit of all
other nodes are cleared. When R is cleared, root_ID is ignored.
T
When T is set, the PHY_CONFIGURATION.gap_count field of all the nodes is set to the value in
the gap_cnt field.
gap_cnt
This field contains the new value for PHY_CONFIGURATION.gap_count for all nodes. This value
goes into effect immediately upon receipt and remains valid after the next bus reset. After the second
reset, gap_cnt is set to 63h unless a new Phy configuration packet is received.
Phy_ID
Physical node identifier of the destination of this packet.
4.5.3.
PING packet
The reception of the cable PHY packet shall cause the node identified by phy_ID to transmit self_ID packet(s) that
reflect the current configuration and status of the PHY. Because of other actions, such as the receipt of a PHY
configureation packet, the self-ID packet transmitted may differ from that of the most recent self-identify process.
0 1 2 3 4 5 6 7 8 9
0 0
phy_ID
0 0
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
Type(0)
0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
Logical inverse of first quadlet
FIELD NAME
DESCRIPTION
Phy_ID
Physical node identifier of the destination of this packet.
Type
Extended PHY packet type (zero indicates ping packet)
A PHY shall transmit a self-ID packet within RESPONSE_TIME after the receipt of a ping packet.
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4.5.4.
Remote access packet
The reception of the cable PHY packet shall cause the node identified by phy_ID to read the selected PHY register
and subsequently return a remote reply packet that contains the current value of the PHY register,
0 1 2 3 4 5 6 7 8 9
0 0
phy_ID
0 0
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
Type
page
port
reg
1 1 1 0 reserved
Logical inverse of first quadlet
FIELD NAME
DESCRIPTION
Phy_ID
Physical node identifier of the destination of this packet.
Type
Extended PHY packet type
1 Register read ( base register )
5 Register read ( paged register )
Page
This field corresponds to the Page_select field in the PHY registers. The register read behaves as if
Page_select was set to this value.
Port
This field corresponds to the Port_select field in the PHY registers. The register read behaves as if
Port_select was set to this value.
reg
This field, in combination with page and port, specifies the PHY register. If type indicates a read of
the base PHY registers reg directly addresses one of the first eight PHY registers. Otherwise the
PHYregister address is 10002 +reg.
4.5.5.
Remote command packet
The reception of the cable PHY packet shall request the node identified by phy_ID to perform the operation
specified and subsewuently return a remote confirmation packet.
0 1 2 3 4 5 6 7 8 9
0 0
phy_ID
0 0
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
Type(8)
0 0 0
port
Logical inverse of first quadlet
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FIELD NAME
DESCRIPTION
Phy_ID
Physical node identifier of the destination of this packet.
Type
Extended PHY packet type (8 indicates command packet)
Port
This field selects one of the PHY’s ports.
cmnd
Command:
0: NOP
1: Transmit TX_DISABLE_NOTIFY then disable port
2: Initiate suspend (I.e., become a suspend initiator)
4: Clear the port’s Fault bit to zero
5: Enable port
6: Resume port
4.5.6.
Resume packet
The reception of the cable PHY packet shall cause any node to commence resume operations for all PHY ports that
are both connected and suspended. This is equivalent to setting the resume variable TRUE for each of these ports.
The resume packet is broadcast; there is no reply.
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
Type
0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
0 0
(F16)
0 1 2 3 4 5 6 7 8 9
0 0
phy_ID
Logical inverse of first quadlet
FIELD NAME
DESCRIPTION
Phy_ID
Physical node identifier of the destination of this packet.
Type
Extended PHY packet type (F16 indicates resume packet)
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4.6.
MTQ/CTQ Asynchronous Transmit (ATF Interface to TSB43LV81)
MTQ/CTQ Asynchronous transmit refers to the use of the asynchronous-transmit FIFO (ATF) interface. Packet
transmission with MTQ/CTQ will be written with below format. As with other packet transmissions, it is accessed
through CFR (0x70~0x78) address. tlable and tCode attached to a packet direct each request and response packet to
appropriate FIFO. In IEEE1394, a response packet needs to have the same tlable as its request packet. With this rule,
TSB43LV81 assigns the response packet from the initiator to each Receive FIFO.
4.6.1.
MTQ/CTQ Format
Packets transmitted from MTQ/CTQ are the same as Block Read Request in write format to ATF. However, as stated in
previous section, this has to be a Block Read Request with the specified tlable. The quadlet-transmit format is shown in
Figure 6. The first quadlet contains packet control information. The second and third quadlets contain the 64-bit, quadletaligned address. The data_length of packet transmitted from MTQ should be set 32bytes alone.
0 1 2 3 4 5 6 7 8 9
Reserved
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
spd
tlabel
destination ID
rt
tCode
prior
destination_Offset_high
destination_offset_Low
data_length
extended_tCode
Figure 7. MTQ/CTQ Transmission Block Read Packet Format
Table 4-6. Block-Transmit Format Functions
FIELD NAME
DESCRIPTION
spd
This field indicates the speed at which this packet is to be sent. 00 = 100 Mb/s, 01 = 200 Mb/s,
and 10 = 400 Mb/s, and 11 is undefined for this implementation.
tlabel
This field is the transaction label, which is a unique tag for each outstanding transaction between
two nodes. This is used to pair up a response packet with its corresponding request packet. This
tlabel must be set 10_xxxx in case of using MTQ and must be set 11_xxxx in case of CTQ.
rt
The retry code for this packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode
TCode is the transaction code for this packet (see Table 6-10 of IEEE-1394 standard).
prior
The priority level for this packet. For cable implementation, the value of the bits must be zero. For
backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE-1394 standard.
destinationID
This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node
address to which this packet is being sent.
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destination Offset_high,
destination Offset_low
The concatenation of these two fields addresses a quadlet in the destination node’s address space.
This address must be quadlet aligned (modulo 4). The upper four bits of the destination
OffsetHigh field are used as the response code for lock-response packets and the remaining bits
are reserved.
data-length
The number of bytes of data to be transmitted in the packet. The data_length of packet transmitted
from MTQ should be set 32bytes alone.
extended_tCode
The block extended_tCode to be performed on the data in this packet. See Table 6-11 of the
IEEE-1394 standard.
4.6.2.
MRF/CRF Format
ORB format is stored with ORB pointer address. Setting MShtFmt and CShtFmt on CFR/ORB Fetch Control (0x44) will
record ORB in shortened format. This enables FIFO to be used effectively and speed up read access.
MRF/CRF received short format is shown in Figure 8. The first quadlet contains packet-control information. The first 16
bits of the second quadlet contain the bus and node number of source, and the last 16 bits of the third quadlet and all of
the fourth quadlet contain the 48-bit, quadlet-aligned ORB offset address. All remaining quadlets contain data that is used
only for write requests and read responses. For block read requests and block write responses, the data field is omitted.
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
next_tLabel
tlabel
Ack
status
rCode
Reserved
spd
(only to CRF)
source ID
ORB_Offset_high
ORB_Offset_low
ORB
Figure 8. MRF/CRF Received Short Format (ORB)
Page 103
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Table 4-7. Block-Receive Short Format Functions
FIELD NAME
status
DESCRIPTION
Received packet will go into each Rx FIFO with each status. Each status is shown as below.
rCode
This field is the response code for this packet. (See Table 6-11 of the IEEE-1394 standard).
spd
This field indicates the speed at which this packet is to be sent. 00 = 100 Mb/s, 01 = 200 Mb/s, and
10 = 400 Mb/s, and 11 is undefined for this implementation.
LINK command automatically generate request packet to fetch next command block ORB. This is
tlable for next packet. When not generate its automatically request packet, this is 6’b00_0000.
Note.) next_tlabel is only to CRF.
next_tlabel
tlabel
This field is the transaction label, which is a unique tag for each outstanding transaction between two
nodes. This is used to pair up a response packet with its corresponding request packet.
Ack
This field holds the acknowledge sent by the receiver for this packet. (See Table 6-13 of the IEEE1394 standard).
sourceID
This is the node ID of the sender of this packet.
ORB_Offset_high
ORB_Offset_low
These fields are ORB destination offset address that fetched from Initiator.
ORB
This is ORB pointer data that fetched from Initiator.
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
next_tlabel
Reserved
spd
Reserved
Ack
(only to CRF)
0 1 2 3 4 5 6 7 8 9
status
destination ID
tlabel
source ID
rCode
rt
tCode
Reserved
Reserved
data_length
extended_tCode
ORB
Reserved
ORB_Offset_high
ORB_Offset_low
Figure 9. MRF/CRF Received Long Format (ORB)
Page 104
prior
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Table 4-8. Block-Receive Long Format Functions
FIELD NAME
status
DESCRIPTION
Received packet will go into each Rx FIFO with each status. Each status is shown as below.
rt
This field indicates the speed at which this packet is to be sent. 00 = 100 Mb/s, 01 = 200 Mb/s, and
10 = 400 Mb/s, and 11 is undefined for this implementation.
LINK command automatically generate request packet to fetch next command block ORB. This is
for next packet. When not generate its automatically request packet, this is 6’b00_0000.
Note.) next_tlabel is only to CRF.
This field holds the acknowledge sent by the receiver for this packet. (See Table 6-13 of the IEEE1394 standard).
This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node
address to which this packet is being sent.
This field is the transaction label, which is a unique tag for each outstanding transaction between two
nodes. This is used to pair up a response packet with its corresponding request packet.
The retry code for this packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode
tCode is the transaction code for this packet (see Table 6-10 of IEEE-1394 standard).
prior
source ID
The priority level for this packet. For cable implementation, the value of the bits must be zero. For
backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE-1394 standard.
This is the node ID of the sender of this packet.
rCode
This field is the response code for this packet. (See Table 6-11 of the IEEE-1394 standard).
data_length
The number of bytes of data to be transmitted in the packet.
extended_tCode
The block extended_tCode to be performed on the data in this packet. See Table 6-11 of the IEEE1394 standard.
ORB
This is ORB pointer data that fetched from Initiator.
spd
next_tlabel
Ack
destination ID
tlabel
ORB_Offset_high / low These fields are ORB destination offset address that fetched from Initiator.
<status>
4’h0 : Ack_comp was returned to the request packet
4’h1 : The packet which does not require any acknowledgement was transmitted
4’h2 : The acknowledgement except Ack_comp, Ack_Busy_X and Ack_Pnd was returned to the request packet
4’h3 : Ack was not returned to the request packet
4’h4 : Doorbell was rung and the response packet was received.
The packet is not queued to fetch next command block ORB
4’h5 : Doorbell was rung and the response packet was received
The packet is queued to fetch next command block ORB
4’h6 : Reserved
4’h7 : The request packet was transmitted Retry_Limit times
4’h8 : ORBPointer was written and the response packet was receive. The packet is not queued to fetch next command
block because next_ORB_offset field is null or CnxFtEn(0x44) is 0
4’h9 : ORBPointer was written and the response packet was received
The packet is queued to fetch next command block ORB
4’hA : The response packet was received but rCode is not complete
4’hB : The response packet was not received in Split_Time
4’hC : The request packet was removed because of a bus reset
4’hD : The request packet was removed because of RstTr or Clear
4’hE : Reserved
4’hF : Reserved.
Page 105
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
4.7.
Status Block Set-up
TSB43LV81 can send Status block packet to initiator when DMA successfully completed to write/read entire amount of
date. The contents of status block packet should be loaded before starting DMA. This function is Active only when the
Notify bit is set. Below is basic Status Block format.
Reserved
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
AgentNum
AsAgent
0 1 2 3 4 5 6 7 8 9
destination_Offset_high
destination_Offset_low
data_length
Extened tcode
Status Block
Figure 10. Status Block Format
Table 4-8. Status Block Format Functions
FIELD NAME
DESCRIPTION
AsAgent
Associates corresponding Agent for this transaction. The only difference between associated and
non associated is when status transfer is not successful.
The agent status specified by agent number is fall into dead state.
Setting AsAgent=0 is Activate.
AgentNum
Specifies the agent number associated by this transaction.
Destination Offset_high, The concatenation of these two fields addresses a quadlet in the destination node’s address space.
destination Offset_low This address must be quadlet aligned (modulo 4) and address of status FIFO at Initiator.
Data_length
Status Block
The number of bytes of status block size is transmitted in the packet.
SBP-2 Status block. Refereed to SBP-2 standard.
To load Status Block Packet into Internal RAM
1.) Set Size of Status Block FIFO
0x94, MTXBufSiz bit is FIFO Size of status block. To set 8 quadlet of entire status block packet (for example, write
0x06 to this field). This field should be half size of status block packet in quadlet.
2.) Set internal RAM to status write mode
0xF8, DTFST/DRFST bit can enable to access Status FIFO. Set on of them, then host can access to Status FIFO.
3.) Write Status Block packet
Host can write Status Block Packet through 0xFC. Request writing in 0xFC will process its address automatically.
4.) Active Status Block
Set Notify bit enable to send Status Block Packet. Notify bit is located at both of DTF and DRF control.
Page 106
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
5. Configuration ROM setup
TSB43LV81 can have CSR ConfigROM as stated in IEEE1212 up to 528bytes. And it can auto-respond to Quadlet Read
Request.
Below is a basic ConfigROM structure for typical SBP-2 target device. Each system has a different structure and this is
for reference only.
0 1 2 3 4 5 6 7 8 9
4
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
0x11
ROM CRC
0x3133439 (ASCII “1394”)
Node Options (0x00FF_2000)
Node_vender_ID
Chip_ID_hi
Chip_ID-low
4
Root directory CRC
0x03
module_vender_ID
0x81
Test lead offset
0x0C
node_capability ( 0x00_83C0 )
0xD1
Unit directory offset
7
Unit directory CRC
0x12
unit spec ID ( 0x00_609E )
0x13
unit sw version ( 0x01_0483 )
0x38
command set spec ID
0x39
command_set
0x54
csr_offset ( 0x00_4000 )
0x3A
Logical unit characteristics ( 0x00_0A08 )
0x14
Device type and LUN ( 0 )
Figure 10. ConfigROM base structure (reference SBP-2 DRAFT)
Page 107
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
After power is on, write number of bytes written in ConfigROM into AR_ConfigROM_Size on CFR/Config ROM
Control (0x8C). Value between ConfigROM address (FFFF_F000_0400) and this will be subject for ConfigROM
Autoresponse. If content of ConfigROM does not exceed 528Bytes, write value of AR_ConfigROM_Size to
ConfigROM_Size. If it is more than 528Bytes, write total ConfigROM size into ConfigROM_Size. As stated previously,
HOST needs to transact response for ConfigROM larger than AR_ConfigROM_Size.
Next, HOST will load ConfigROM to TSB43LV81 by CFR / XLOG Control (0xF8) and CFR/Log Data (0xFC).
First, set XLOG bit to make LogData accessible to ROM. And write 0x400 into ROMAddr, which is to write data for
ConfigROM address FFFF_F000_0400 into ROMAccess. Repeat writing in LogRead will process its address
automatically and will write ConfigROM data in order. To check data, write start address to ROMAddr, then read
ROMAccess.
(Note: ConfigROM_Size does not exceed 1024 Bytes)
Then, clear XLOG bit on CFR/XLOG Control (0xF8), and at the same time, set ROMValid to indicate ConfigROM is
valid. If this ROMValid were not set, LINK would respond Ack_Tardy for Ack to ConfigROM read request.
Page 108
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
6. Internal Agent Operation for Initiator
This section describes what internal Command Block Fetch Agent act for various accesses by Initiators. Command Block
Agent registers are located in CSR address that set by Agent Base offset (0x4C) and each Command block Agent is
separated by 0x20 offset.
6.1.
Internal Agent Transaction for Write Request from Initiator
When each Active Agent Register receive Write request, Internal Agent operates various behavior. Agent state
transaction is shown in Table 6-1.
Table 6-1. Agent Transaction for Write Request from Initiator
State
RESET
ACTIVE
SUSPENDED
DEAD
Any State
§1
Register
Err/Comp§1
Action§2
Agent Transaction§3
AGENT_STATE
type_error
pending
Auto-resp
AGENT_RESET
complete
ORB_POINTER
complete
DOORBELL
complete
Write
※1
※2
and CTQ
DrBll ※3 = 1
※4
ACTIVE
-
UNSOLICITED_STATE_ENABLE
complete
AGENT_STATE
type_error
pending
Auto-resp
AGENT_RESET
complete
Reset Agent State
RESET
ORB_POINTER
conflict_error
-
-
DOORBELL
complete
UNSOLICITED_STATE_ENABLE
complete
UnStEn ※4 =1
-
AGENT_STATE
type_error
pending
Auto-resp
AGENT_RESET
complete
Reset Agent State
ORB_POINTER
complete
DOORBELL
complete
UnStEn
DrBll
Write
※1
※3
-
=1
-
=1
※2
and CTQ
DrBll ※3 = 1※5
※4
RESET
ACTIVE
-
UNSOLICITED_STATE_ENABLE
complete
AGENT_STATE
type_error
pending
Auto-resp
AGENT_RESET
complete
Reset Agent State
RESET
ORB_POINTER
complete
-
-
DOORBELL
complete
UNSOLICITED_STATE_ENABLE
complete
Reserved Agent Area
※6
pending
UnStEn
DrBll
※3
=1
=1
-
-
UnStEn ※4 =1
-
Stored in ARF
-
If it’s possible to write AGENT_STATE Register, Internal Agent returns Ack_complete. (Setting AckPnd,
Agent returns Ack_pending)
If it’s impossible to write AGENT_STATE Register, Internal Agent returns acknowledge which follows table
6-2.
§2
Agent Operation
§3
Agent State Transaction by Write Request
※1 Update ORB Pointer Register
Page 109
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
※2
※3
※4
※5
※6
Loading Read Request Packet in CTQ
This field shows DrBll of Agent Status Register (0x5C) .
This field shows UnStEn of Agent Status Register (0x5C).
If DrBFtEn(ORB Fetch Control 0x44 ) is set to ‘1’, loading Read Request Packet in CTQ again.
Returned Ack_pending
Table 6-2. Response to unexpected
StErPkt
ErrResp
Ack to Initiator
1
0
ack_complete
Received packet shall be stored in ARF
1
ack_pending
The packet which has resp_type_error or
resp_conflict_error shall be sent to Initiator
0
ack_type_error or ack_conflict_error
-
0
0
6.2.
Response Packet to Initiator and other Actions
Internal Agent Transaction for Read Request from Initiator
Table 6-3. Agent Transaction for Read Request from Initiator
Register
Ack and Response Packet
AGENT_STATE
ack_pending → Read Response (resp_complete)
AGENT_RESET
ack_type_error※7
ORB_POINTER
ack_pending → Read Response (resp_complete)
DOORBELL
ack_type_error ※7
UNSOLICITED_STATE_ENABLE
ack_type_error ※7
Reserved Agent Area
ack_pending → stored in ARF
※7 Ack and Response packet is controlled by StErPkt and ErrResp setting (Control Register 0x80)
6.3.
Controlling Command ORB Fetch Request
CAFtSt of ORB Fetch Control Register (0x44) is set to 1 when each Agent is ready for writing Read Request to CTQ.
When host writes ‘1’ to CAFtSt, Read Request is loaded to CTQ and CAFtSt is set to ‘0’.
Page 110
CORB_
Size
CAg0Qrdy
CAg1Qrdy
CAg8Qrdy
CAg3Qrdy
MORB_
Prior
CAg0Vld
Cag1Vld
Cag2Vld
Cag3Vld
DrBlSnp
DrBFtEn
CnxFtEn
CShtFmt
0x44
ORB Fetch
Control
MagtVld
MagtBsy
Reserved
MShtFmt
Table 6-4. ORB Fetch Control
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
CORB_
Prior
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
6.4.
Agent Behavior by write to DOORBELL Register
Table 6-5. DOORBELL Special Functions
DrBlSnp
DrBFtEn
ORB fetch Operation when DOORBELL is written
X
0
AgentWrInt(0x0C) occurs and DrBll(0x5C) becomes ‘1’.
0
1
Fetching only next_ORB field of previous ORB Block. No stored in CRF.
And fetching Command _ORB. This packet is stored in CRF.
1
1
Fetch previous ORB Block. Stored it in CRF and Fetch Command ORB included in it from
the address
1
0
This list effect on CShFmt(0x44) = 1 only.
Page 111
Reserved
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
7.
7.1.
Typical ORB Fetch Command Operation
Typical ORB Management ORB Fetch Command Operation
Typical Management ORB Fetch Command Operation
Initiator Operation
SPHYNX Hardware Operation
Application Software Operation
Page 112
Start
Active Management Agent by
8byte Block
write Request
Yes
packet
Send Management ORB by 32Byte
Block Read Response packet
No
No
Yes
No
32Byte Block Read Request to
Initiator’s Management ORB
(Auto Block Read Request)
Split Time Out or
other error
happened
Yes
Start Split Timer
Set Management
AgentBusy to’1’
No
Set Management
AgentBusy to ‘0’
Yes
Send each Response Packet via ATF successfully (Block Write request)
For Login
No
MRFClr is set to ‘1’
: Select Agent number
: Set Initiator’s Node_ID and CAgVld to ‘1’
For Query Login
: Select Agent number
For Reconnect : Verify EUI-64 of Initiator requesting the login
reestablishment matches the EUI-64 previously saved
For Logout
: Set AGENT_RESET to ‘1’
: Set CAgVld to’0’
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
7.2.
Typical Command ORB Fetch Command Operation
Typical Command ORB Fetch Command Operation
Start
Initiator Operation
Update ORB_POINTER by
8Byte Write Request packet
Yes
Send Command Block ORB by Read
Response Packet
No
No
Yes
Yes
SPHYNX Hardware Operation
Application Software Operation
Page 113
Block Read Request to Initiator’s
Command ORB
Next_ORB_OPINTER is
NULL OPINTER
No
Split Time Out or other error happened
No
Set CAFtSt to ‘1’ if next Block
Write Request is prepared
Yes
Start Split Timer
Set AGENT_RESET to
‘1’
AGENT_STATE
is ‘DEAD’
Start Split Timer
CRFClr is set to ‘1’
Set CagXQt to ‘1’ in piles
(Sending Block Write Request to Initiator )
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
8.
Ack and Response Packet for Request Packet
8.1.
Management Agent
ErrResp/StErPkt=0/0
ErrResp/StErPkt =1/0
ack_pending
(auto resp by type error)
ack_pending
(auto resp by confl error)
ack_pending
(auto resp by confl error)
ack_pending
(auto resp by confl error)
ErrResp/StErPkt =x/1
ack_pending
(stored in ARF)
ack_pending
(stored in ARF)
ack_pending
(stored in ARF)
ack_pending
(stored in ARF)
ack_complete/
ack_pending
(depended on cfr setting.
Responed by response
Packetl later.)
<-
<-
except 8 byte
ack_type_error
ack_pending
subsystem is in use
busy_ack
ack_pending
(auto response)
<-
ack_pending
(stored in ARF)
<-
<-
<-
Ack_pending
(auto resp by type error)
ack_pending
(stored in ARF)
ErrResp/StErPkt =1/0
ack_pending
(auto resp by type error)
ack_pending
(auto resp by type error)
<-
ErrResp/StErPkt =x/1
ack_pending(stored in
ARF)
ack_pending(stored in
ARF)
Write
Read
8byte block write
except 8 byte
MRFFULL = 1
MagtBsy = 1
MRFFULL = 1
MagtBsy = 0
MRFFULL = 0
MagtBsy = 1
MRFFULL = 0
MagtBsy = 0
ack_type_error
resp_conflict_error
busy_ack
resp_conflict_error
8 byte block read
Other
ack_type_error
Note) This table is only valid when MagtVld is set.
8.2.
Command Agent AGENT_STATE
ErrResp/StErPkt=0/0
Write
any
ack_type_error
except 4byte
ack_type_error
Subsystem is in use
busy_ack
Read
quad read
4byte block read
Other
ack_pending
(auto response)
ack_pending
(auto response)
ack_type_error
Note) This table is only valid when CagtVld is set.
Note) ErrResp is CFR 0x08 , bit14
StErPkt is CFR 0x08 , bit15
Page 114
<-
<<-
<-
<-
ack_pending
(auto resp by type error)
ack_pending(stored in
ARF)
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
8.3.
Command Agent AGENT_RESET
ErrResp/StErPkt=0/0
except 4 byte
quad write
Write
4 byte block write
Read
any
Other
ack_type_error
ack_complete/
ack_pending
(depended on cfr setting.
Responed by response
Packetl later.)
ack_complete/
ack_pending
(depended on cfr setting.
Responed by response
Packetl later.)
ack_type_error
ack_type_error
ErrResp/StErPkt =1/0
ack_pending
(auto resp by type error)
ErrResp/StErPkt =x/1
ack_pending
(stored in ARF)
<-
<-
<-
<-
ack_pending
(auto resp by type error)
ack_pending
(auto resp by type error)
ack_pending
(stored in ARF)
ack_pending
(stored in ARF)
ErrResp/StErPkt =1/0
ack_pending
(auto resp by type error)
ack_pending
(auto resp by conflict
error)
ErrResp/StErPkt =x/1
ack_pending
(stored in ARF)
Note) This table is only valid when CagtVld is set.
8.4.
Command Agent ORB pointer
ErrResp/StErPkt=0/0
except 8 byte
ack_type_error
Active
8byte block write
ack_conflict_error
8 byte block write
ack_complete/
ack_pending
(depended on cfr setting.
Responed by response
Packetl later.)
<-
<-
except 8byte
ack_type_error
ack_pending
(auto resp by type error)
ack_pending
(stored in ARF)
subsystem is in busy
8byte block read
ack_busy/
<-
<-
8byte Block read
ack_complete/
ack_pending
(depended on cfr setting.
Responed by response
Packetl later.)
<-
<-
ack_type_error
ack_pending
(auto resp by type error)
ack_pending
(stored in ARF)
Write
Read
Other
Note) This table is only valid when CagtVld is set.
Page 115
ack_pending
(stored in ARF)
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
8.5.
Command Agent DOOR_BELL
ErrResp/StErPkt=0/0
Write
except 4 byte
ack_type_error
system in busy
(Ackpnd)
ack_complete
ack_busy
ack_complete/
ack_pending
(depended on cfr setting.
Responed by response
Packetl later.)
ack_complete/
ack_pending
(depended on cfr setting.
Responed by response
Packetl later.)
quad write
4 byte block write
Other
ack_type_error
ErrResp/StErPkt =1/0
ack_pending
(auto resp by type error)
<<<-
ErrResp/StErPkt =x/1
ack_pending
(stored in ARF)
<<-
<-
<-
<-
ack_pending
(auto resp by type error)
ack_pending
(stored in ARF)
ErrResp/StErPkt =1/0
ack_pending
(auto resp by type error)
<<-
ErrResp/StErPkt =x/1
ack_pending
(stored in ARF)
<<-
<-
<-
<-
<-
ack_pending
(auto resp by type error)
ack_pending
(auto resp by type error)
ack_pending
(stored in ARF)
ack_pending
(stored in ARF)
Note) This table is only valid when CagtVld is set.
8.6.
Command Agent UNSOLISITED_STATUS_ENABLE
ErrResp/StErPkt=0/0
Write
other
Ack_type_error
system in busy
(Ackpnd)
ack_complete
ack_busy
ack_complete/
ack_pending
(depended on cfr setting.
Responed by response
Packetl later.)
ack_complete/
ack_pending
(depended on cfr setting.
Responed by response
Packetl later.)
quad write
4 byte block write
Read
ack_type_error
Other
ack_type_error
Note) This table is only valid when CagtVld is set.
Page 116
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
8.7.
Command Agent reserved area
Write
except 4 byte
ARF is full
quad write
4 byte block write
except 4 byte
ErrResp/StErPkt=0/0
ARF
busy_ack
ARF
ARF
ARF
busy_ack
ARF
ARF
Other
ARF
Note) This table is only valid when CagtVld is set.
Read
8.8.
ARF is full
quad read
4 byte block read
ErrResp/StErPkt =1/0
<<<<<-
ErrResp/StErPkt =x/1
<<<<<-
<<<<-
<<<<-
RAM ROM (Destination Address : from ( FFFF_F0000_0400 to (FFFF_F000_0400 +
AR_ConfigRom_Size))
ErrResp/StErPkt=0/0
Write
Read
any
ack_type_error
subsystem is busy
busy_ack
ack_pending
(auto response)
ack_pending
(auto response)
quad read
block read
Other
Page 117
ack_type_error
ErrResp/StErPkt =1/0
ack_pending
(auto resp by type error)
<-
ErrResp/StErPkt =x/1
ack_pending
(stored in ARF)
<-
<-
<-
<-
<-
ack_pending
(stored in ARF)
(auto resp by type error)
ack_pending
(stored in ARF)
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
8.9.
ARF ROM (Destination Address : from (FFFF_F000_0400 + AR_ConfigRom_Size) to (FFFF_F000_0400
+ ConfigRom_Size)
Write
any
Read
ready &
subsystem is busy
quad read
block read
Other
ErrResp/StErPkt=0/0
ack_type_error
ack_pending(stored
ARF )
ack_pending(stored
ARF)
ack_pending(stored
ARF)
ack_type_error
ErrResp/StErPkt =1/0
ErrResp/StErPkt =x/1
ack_pending(stored
in ack_pending(stored
in
ARF)
ARF)
in <<in
<-
<-
in
ack_pending(stored
ARF)
in
ack_pending(stored
ARF)
8.10. Out side of ROM configure (Destination Address : from FFFF_F0000_0400 + ConfigRom_Size) to
FFFF_F000_0800))
ErrResp/StErPkt=0/0
Write
Read
any
ack_type_error
ready &
subsystem is busy
ack_address_error
quad read/
block read
ack_address_error
Other
ack_type_error
ErrResp/StErPkt =1/0
ack_pending
(auto resp by type error)
ErrResp/StErPkt =x/1
ack_pending
(stored in ARF)
busy_ack
<-
ack_pending
(auto resp by address
error)
ack_pending
(auto resp by type error)
ack_pending
(stored in ARF)
ErrResp/StErPkt =1/0
ErrResp/StErPkt =x/1
<-
<-
<-
<-
<-
<-
ack_pending
(stored in ARF)
8.11. Others
Write
any
Read
any
Other
any
Page 118
ErrResp/StErPkt=0/0
ack_complete
(stored in ARF)
ack_pending
(stored in ARF)
ack_pending
(stored in ARF)
in
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
9.
DMA Interface
9.1.
mode setting
BDOMode and BDIMode register setting on CFR will determine DMA interface transaction mode.
MODE
BDI
MODE
BDO
MODE
TRANSACTION
INPUT CONTROL
OUTPUT CONTROL
A
000
00
BDIEN Synchronism
BDOEN Synchronism
B
001
01
BDIEN Asynchronism
BDOEN Asynchronism
C
010
01
8 bit parallel input/
parallel output
8 bit parallel input/
parallel output
8 bit bi-directional inout
BDIEN Asynchronism
BDOEN Asynchronism
D
011
10
8 bit bi-directional inout
BDIEN & BDOEN Synchronism
E
100
11
8 bit bi-directional inout
BDIEN & BDOEN Asynchronism
F
101
01
16 bit bi-directional inout
BDIEN Asynchronism
BDIEN & /BDOEN
Synchronism
BDIEN & /BDOEN
Asynchronism
BDOEN Asynchronism
G
110
10
16 bit bi-directional inout
BDIEN & BDOEN Synchronism
H
111
11
16 bit bi-directional inout
BDIEN & BDOEN Asynchronism
Figure 9-1. DMA mode setting
Below data is for 8 bit bus DMA interface.
MSB
LSB
7
6
5
4
3
2
1
0
B
D
I
O
7
B
D
I
O
6
B
D
I
O
5
B
D
I
O
4
B
D
I
O
3
B
D
I
O
2
B
D
I
O
1
B
D
I
O
0
Figure 9-2 BDIO (8bit)
MSB
LSB
7
6
5
4
3
2
1
0
B
D
I
O
1
5
B
D
I
O
1
4
B
D
I
O
1
3
B
D
I
O
1
2
B
D
I
O
1
1
B
D
I
O
1
0
B
D
I
O
9
B
D
I
O
8
Figure 9-3. BDO (8bit)
For 16-bit bus DMA interface, combine BDIO and BDO to make 16-bit signal as below.
Page 119
BDIEN & /BDOEN
Synchronism
BDIEN & /BDOEN
Asynchronism
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
MSB
1
5
B
D
I
O
1
5
1
4
B
D
I
O
1
4
LSB
1
3
B
D
I
O
1
3
1
2
B
D
I
O
1
2
1
1
B
D
I
O
1
1
1
0
B
D
I
O
1
0
9
8
7
6
5
4
3
2
1
0
B
D
I
O
9
B
D
I
O
8
B
D
I
O
7
B
D
I
O
6
B
D
I
O
5
B
D
I
O
4
B
D
I
O
3
B
D
I
O
2
B
D
I
O
1
B
D
I
O
0
Figure 9-4. BDIO (16bit)
Mode A
Input: BDIO
Output: BDO
Use BDIO for 8-bit request data input. Use BDO for 8-bit response data output.
Data will be input synchronously with BDICLK and will be written when BDIEN is true and BDIBUSY is
false.
Data will be output synchronously with BDICLK and will be updated when BDOEN is true and BDOAVAIL
is false.
Mode B
Input: BDIO
Output: BDO
Use BDIO for 8-bit request data input. BDO is used for 8-bit response data output.
Data will be written asynchronously by BDIEN input.
Data output will be updated asynchronously by BDOEN input. When BDOEN is false BDO will be high
impedance.
Mode C
Input: BDIO
Output: BDIO
Use BDIO for 8-bit data input/output.
Data will be output synchronously with BDICLK by BDIEN input, and will be updated when both BDOEN
and BDOAVAIL are true.
Mode D
Input: BDIO
Output: BDIO
Use BDIO for 8-bit data input/output.
Specify data input/output with BDOEN. If BDOEN is true the mode is input, if it is false the mode is output.
Data will be input synchronously with BDICLK, and will be written when BDIEN is true and BDIBUSY is
false. Data will be output synchronously with BDICLK, and will be updated when both BDIEN and
Page 120
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
BDOAVAIL are true.
Mode E
Input: BDIO
Output: BDIO
Use BDIO for 8bit data input/output.
Specify data input/output with BDOEN. If BDOEN is true, the mode is input. If it’s false, the mode is output.
Data will be written asynchronously with BDIEN input.
Data output will be updated asynchronously with BDOEN input. When BDOEN is false, BDO is high
impedance.
Mode F
Input: BDIO, BDO
Output: BDIO, BDO
Use BDIO and BDO combined for 16-bit data input/output.
Data will be written asynchronously with BDIEN input.
Data output will be updated asynchronously with BDOEN input.
Mode G
Input: BDIO, BDO
Output: BDIO, BDO
Use BDIO and BDO combined for 16-bit data input/output.
BDOEN controls data input or output. When BDOEN is true, it is input mode. When it is false, it is output
mode.
Data will be input synchronously with BDICLK, and updated when BDIEN is true and BDIBUSY is false.
Data will be output synchronously with BDICLK, and updated when both BDOEN and BDOAVAIL are true.
Mode H
Input: BDIO, BDO
Output: BDIO, BDO
Use BDIO and BDO combined for 16-bit data input/output.
BDOEN controls data input or output. When BDOEN is true, it is input mode. When it is false, it is output
mode.
Data input will be written asynchronously with BDIEN input.
Data output will be updated asynchronously with BDOEN input.
Setting active signal
Polarity of BDIBUSY, BDOAVAIL, BDOFEN and BDIFEN is determined by BIBsyCtl, BOAvCtl, BOEnCtl
and BIEnCtl register (0x90,bit12, 13,14,15) respectively. For each register 1 means active high, and 0 means
active low.
Page 121
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
9.2.
Request transmission
9.2.1.
Synchronous mode
In this mode, data will be written synchronously with BDICLK input.
BDICLK
BDIBUSY
BDIEN
DATA8/16
0
1
2
3
BDIF{2:0}F
F0
F1
F2
F3
Data will be written when BDIBUSY is false and BDIEN is true.
BDIF2~0 is an attribute flag for a packet, and each means:
8-bit Bulky
BDIF[2:0]
011
111
101
001
Comment
8-bit data except last block on packet
8-bit data of last on packet
Reset
No data
16-bit Bulky
BDIF[2:0]
011
000
010
111
100
110
101
001
Comment
8-bit data except last block on packet (Upper)
8-bit data except last block on packet (Lower)
16-bit data except last block on packet
8-bit data of last on packet (Upper)
8-bit data of last on packet (Lower)
16-bit data of last block on packet
Reset
No data
Page 122
4
F4
5
6
F5
F6
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
9.2.2.
Asynchronous SCSI mode
BDREQ
BDACK
BDWR
DATA8/16
0
1
BDIF{2:0}
F0
F1
The data needs to be guaranteed by BDWR negate edge. Also, BDACK needs to be asserted after confirming
BDREQ input is false.
16 bit bus data write can not bestride over 32-bit boundary.
Page 123
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
9.2.3.
Asynchronous handshake mode
BDIBUSY
BDIEN
DATA8/16
BDIF{2:0}
0
1
F0
F1
The data needs to be guaranteed by BDIEN negate edge. Also, BDIEN needs to be asserted after confirming
BDIBUSY input is false.
16 bit bus data write can not bestride over 32-bit boundary.
Page 124
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
9.3.
Receiving
9.3.1.
Synchronous mode
In this mode, data receipt will be recognized synchronously with BDICLK input, when both BDOEN and
BDOAVAIL are true.
BDICLK
BDOAVAIL
BDIEN
DATA8/16
0
1
2
3
4
5
6
BDOF{2:0}
F0
F1
F2
F3
F4
F5
F6
It takes maximum a little over 100 ns per 1QW.
For faster DMA port frequency, wait cycles needs to be added to every 1QW.
Frequency
wait for16 bit bus / wait for 8 bit bus
40MHz
36MHz
33MHz
25MHz
18MHz
3wait
2wait
2wait
1wait
no wait
1wait
no wait
no wait
no wait
no wait
Specify number of waits to be added (0~3) with BDODelay on CFR.
Page 125
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
9.3.2.
Asynchronous SCSI mode
BDREQ
BDACK
BDRD
DATA8/16
0
1
BDOF{2:0}
F0
F1
In this mode, data will be output as BDRD negate edge.
Specify number of waits to be added 0 with BDODelay on CFR.
Page 126
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
9.3.3.
Asynchronous handshake mode
BDOAVAIL
BDOEN
0
DATA8/16
BDIF{2:0}
F0
1
F1
The data should be output by repeating BDOEN negate and assert. Also, BDOEN needs to be asserted after
confirming BDOAVAIL input is true.
Page 127
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
9.4.
Endianness
When BLtCtl (0x94,bit11) is 1, data from DMA interface will be received in Little Endian mode. The
difference between Little Endian and Big Endian are described below.
The example is for outputting below 1394 quadlet data packets.
D0
D1
D2
D3
Data are to be output in below order. And, for 1, 2 and 3 byte data, every padded data will be deleted before
output.
8 bit mode
Big Endian Byte Ordering
4 byte data
3 byte data
2 byte data
1 byte data
D0⇒D1⇒D2⇒D3
D0⇒D1⇒D2
D0⇒D1
D0
D3 is Padding data
D2 & D3 are Padding data
D1, D2 & D3 are Padding data
Little Endian Byte Ordering
4 byte data
3 byte data
2 byte data
1 byte data
D3⇒D2⇒D1⇒D0
D2⇒D1⇒D0
D1⇒D0
D0
D3 is Padding data
D2 & D3 are Padding data
D1, D2 & D3 are Padding data
Big Endian Byte Ordering
4 byte data
3 byte data
2 byte data
1 byte data
{D0,D1}⇒{D2,D3}
{D0,D1}⇒{D2,0x00}
{D0,D1}
{D0,0x00}
D3 is Padding data
D2 & D3 are Padding data
D1, D2 & D3 are Padding data
Little Endian Byte Ordering
4 byte data
3 byte data
2 byte data
1 byte data
{D3,D2}⇒{D1,D0}
{D2,D1}⇒{0x00,D0}
{D1,D0}
{0x00,D0}
D3 is Padding data
D2 & D3 are Padding data
D1, D2 & D3 are Padding data
16 bit mode
Page 128
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
9.5.
Reference clock
DMA interface can use either internal clock or external clock as a reference clock.
When CLKSEL terminal is 0, it uses an external clock that is input through BDICLK pin.
When CLKSEL terminal is 1, it uses internal 24.976MHz clock.
Internal clock will be output through NCLK terminal by setting CLKOE signal to 0. When CLKOE signal is 1,
NCLK terminal will be kept as high impedance.
9.6.
Clearing DMA interface data
To clear DMA interface data, write 1 on DTFClr (0x90, bit31) and DRFClr (0x90, bit30).
It takes 2~3BDIClk for the data to be cleared after the micro controller writes the order.
9.7.
Resetting DMA interface
To reset DMA interface, write 1 on BDORst (0x94, bit29) and BDIRst (0x94, bit30).
It takes 2~3BDIClk for the interface to be reset after the micro controller writes the order.
9.8.
Suspending BDO output
To suspend BDO output, set 1 on BDOTris (0x94, bit31).
Under 8-bit synchronous mode, BDO is in Output State.
Page 129
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
10. Electrical Characteristics
10.1. Absolute Maximum Ratings Over Free-Air Temperature Range
Supply voltage range, VCC(5-V tolerant TTL terminals) ----------------------------------- -0.5V to 5.5V
Input voltage range, VI(5-V tolerant TTL terminals) -------------------------- -0.5V to 5V VCC +0.5V
Output voltage range, VO(TTL terminals) -------------------- -0.5V to VCC + 0.5V (4.6V maximum)
Input clamp current, IIK(VI < 0 or VI > V CC) (see Note 1) -------------------------------------- ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) ----------------------------------- ±20 mA
Operating free-air temperature range, TA ------------------------------------------------------- 0℃ to 70℃
----------------------------------------------------------- -65℃ to 150℃
Storage temperature range, TSTG
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress rating only, and functional operation of the device at these or any other conditions beyond those
indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
NOTE:
1. This parameter applies to external input and bidirectional buffers without hysteresis. VI > VCC does not
apply to fail-safe terminals. For 5-V tolerant and universal PCI use Vo > VCC 5V.
2. This parameter applies to external input and bidirectional buffers without hysteresis. Vo > VCC does not
apply to fail-safe terminals. For 5-V tolerant and universal PCI use Vo > VCC 5V.
10.2. Recommended Operating Conditions
Operating free-air temperature, TA
Virtual junction temperature range, TJ
0
0
MAX
3.6
5.5
VCC
Vcc (Vdd5V)
0.2Vcc
40
50
70
115
Differential input voltage,
VID
Cable inputs, during data reception
118
260
Cable inputs, during arbitration
168
265
Common-mode input voltage,
VIC
TPB cable inputs, Source power node
0.4706
2.515
TPB cable inputs, Non-source power node
0.4706
Power-up reset time, tpu
/RESET input
2
Receive input jitter
TPA, TPB cable inputs, S100 operation
±1.08
TPA, TPB cable inputs, S200 operation
±0.5
TPA, TPB cable inputs, S400 operation
±0.315
Supply voltage, VCC
Supply voltage, Vdd5V (5V)
Output voltage, Vo
High-level input voltage, VIH
Low-level input voltage, VIL
Clock frequency
Page 130
LVCMOS terminals
LVCMOS terminals
LVCMOS terminals
BCLK
SCLK
MIN
3
4.5
0
0.7Vcc
0
NOM
3.3
5
UNIT
V
V
V
V
V
MHz
℃
℃
mV
V
‡
2.015
msec
nsec
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Receive input skew
Between TPA and TPB cable inputs, S100
operation
±0.8
Between TPA and TPB cable inputs, S200
operation
±0.55
Between TPA and TPB cable inputs, S400
operation
±0.5
nsec
10.3. electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)
10.3.1. driver
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
172
265
mV
VOD
Differential output voltage
56 Ω, See Figure 1
IDIFF
Driver Difference current, TPA+, TPA-, TPB+,
TPB-
Drivers enabled, speed
signaling off
-1.05♣
1.05♣
mA
ISP
Common mode speed signaling current, TPB+,
TPB-
S200 speed signaling
enabled
-4.84♥
-2.53♥
mA
ISP
Common mode speed signaling current, TPB+,
TPB-
S400 speed signaling
enabled
-12.4♥
-8.10♥
mA
VOFF
Off state differential voltage
Drivers disabled, See
Figure 1
20
mV
♣
♥
Limits defined as algebraic sum of TPA+ and TPA- driver currents. Limits also apply to TPB+ and TPB- algebraic sum of driver currents.
Limits defined as absolute limit of each of TPB+ and TPB- driver currents.
10.3.2. receiver
PARAMETER
TEST CONDITION
ZID
Differential impedance
ZIC
Common mode impedance
VTH-R
Receiver input threshold voltage
Drivers disabled
VTH-CB
Cable bias detect threshold, TPB cable
inputs
VTH+
VTH-
MIN
TYP
10
14
MAX
kΩ
Drivers disabled
4
20
Page 131
UNIT
pF
kΩ
Drivers disabled
24
pF
-30
30
mV
Drivers disabled
0.6
1.0
V
Positive arbitration comparator threshold
voltage
Drivers disabled
89
168
mV
Negative arbitration comparator threshold
voltage
Drivers disabled
-168
-89
mV
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
VTH-SP200
Speed signal threshold
TPBIAS-TPA common
mode voltage, drivers
disabled
49
131
mV
VTH-SP400
Speed signal threshold
TPBIAS-TPA common
mode voltage, drivers
disabled
314
396
mV
10.3.3. device
TEST CONDITION
PARAMETER
VO
MIN
TYP
1.665
TPBIAS output voltage
MAX
UNIT
2.015
V
10.3.4. switching characteristics
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Jitter, transmit
Between TPA and TPB
±0.15
ns
Skew, transmit
Between TPA and TPB
±0.10
ns
tr
TP differential rise time,
transmit
10% to 90%,
At 1394 connector
0.5
1.2
ns
tf
TP differential fall time,
transmit
90% to 10%,
At 1394 connector
0.5
1.2
ns
tsu
Setup time, CTL0, CTL1,
D0–D7, LREQ to SYSCLK
50% to 50%,
At 1394 connector
5
ns
th
Hold time, CTL0, CTL1, D0–
D7, LREQ after SYSCLK
50% to 50%,
At 1394 connector
TBD
ns
td
Delay time, SYSCLK to
CTL0, CTL1, D0–D7
50% to 50%,
At 1394 connector
2
Page 132
11
ns
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
10.4. Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air
Temperature (Unless Otherwise Noted)
PARAMETER
VOH High-level output voltage
VOL Low-level output voltage
TEST CONDITIONS
IOH = -8mA‡
IOH = -4mA§
IOL = 8 mA‡
IOL = 4 mA§
VI = GND
VI = GND
VI = GND
VI = GND
VI = Vcc
VI = Vcc
VI = Vcc
VI = Vcc
VI = Vcc or GND
IIL Low-level input current
” ¢
” £
” ®
IIH High-level input current
” ¢
” £
” ®
IOZ High-impedance-state output
current
VIT+ positive-going threshold voltage
TTL compatible
VIT- Negative-going threshold voltage
TTL compatible
Vhys Hysteresis (Vit+ - Vit- ) ©
TTL compatible
Icc Supply current
TTL compatible
Ci Input capacitance
Input
terminals
Vcc = 3.3V,
Bidrectional
TA = 25℃
terminal
Co Output capacitance
†All typical values are at Vcc =3.3V and TA =25C
‡Terminals: output terminals of 1-15 and 37-77 pin
§Terminals: All other outputs
© Terminals: All pins except 1-15, 109-111,143.
¢ with Bus holder
£ with pull up
® with pull down
Page 133
MIN
Vcc - 0.6
Vcc - 0.6
TYP
MAX
UNIT
V
0.4
0.4
±1
±1
±20
1.8
0.8
0.30
0.70
150
5
13
8
V
μA
μA
μA
μA
μA
μA
μA
μA
μA
V
V
V
mA
pF
pF
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
10.5. AC specification for Micro interface
10.5.1. [ DA ]
Title
Item
tsu_da
Addr/Data setup
th_data
Addr/Data hold
ten1_da
Enable after XRD low
ten2_da
Disable after XRD hi
tdr_da
data read time
twr_da
data write time
Note1: access time for DRF use this value
Min
5
5
2
40
Max
15
10
210 (260-note1)
80
Unit
[ns]
[ns]
[ns]
[ns]
[ns]
[ns]
10.5.2. [XRD]
Title
tsu_xrd
tw_xrd
Item
ALE to XRD
pulse width
Min
40
160
Max
Unit
[ns]
[ns]
Min
40
160
Max
Unit
[ns]
[ns]
Min
30
100
Max
Unit
[ns]
[ns]
Min
5
5
Max
Unit
[ns]
[ns]
Min
TBD
40
Max
TBD
TBD
Unit
[ns]
[ns]
10.5.3. [ XWR ]
Title
tsu_xwr
tw_xwr
Item
ALE to XWR
pulse width
10.5.4. [ ALE ]
Title
tw_ale
t_cy
Item
pulse width
wait after last XRD or XWR
10.5.5. [ XCS ]
Title
tsu_xcs
th_xcs
Item
set up
hold
10.5.6. [ WAIT ]
Title
td_wait
tw_wait
Page 134
Item
delay from XRD
width
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
10.6. Phy-Interface Timing Requirements Over Operating Free-Air Temperature Range (See Note1)
PARAMETER
Tc2
Cycle time,SCLK (see Figure X-1)
Tw2(H) Pulse duration, SCLK high (see Figure X-1)
Tw2(L)
Pulse duration, SCLK low (see Figure X-1)
Tsu5
Setup time, D0-D7 valid before SCLK↑ (see Figure X-3)
Th5
Hold time, D0-D7 invalid after SCLK↑ (see Figure X-3)
Tsu6
Setup time, CTL0-CTL1 valid before SCLK↑ (see Figure X-3)
Th6
Hold time, CTL0-CTL1 invalid after SCLK↑ (see Figure X-3)
NOTE1: These parameters are not production tested.
MIN
20.347
9
9
6
1
6
1
MAX
20.343
UNIT
ns
ns
ns
ns
ns
ns
ns
Phy-Interface Characteristics Over Operating Free-Air Temperature Range, CL=45pF(unless otherwise noted)
(See Note1)
Td5
Td6
Td7
Td8
Td9
Td10
Td11
NOTE1:
Page 135
PARAMETER
Delay time, SCLK↑ to D0-D7 valid
Delay time, SCLK↑ to D0-D7↑↓
Delay time, SCLK↑ to D0-D7 invalid
Delay time, SCLK↑ to CTL0-CTL1 valid
Delay time, SCLK↑ to CTL0-CTL1↑↓
Delay time, SCLK↑ to CTL0-CTL1 invalid
Delay time, SCLK↑ to LREQ↑↓
These parameters are not production tested.
MIN
3
3
3
3
3
3
3
MAX
11
11
11
11
11
11
11
UNIT
ns
ns
ns
ns
ns
ns
ns
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
11. Parameter Measurement Information
11.1. Micro Interface timing diagram
tw_ale
ALE
tdr_da
DA
t_cy
ADDR
tsu_da
DATA
th_da
ten1_da
ten2_da
tsu_xrd
XRD
td_wait
tw_wait
WAIT
tsu_xcs
th_xcs
XCS
Figure 11-1. MUX Mode Read Cycle
Page 136
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
tw_ale
ALE
t_cy
DA
ADDR
tsu_da
DATA
th_da
tsu_da
tsu_xwr
th_da
tw_xwr
XWR
td_wait
tw_wait
WAIT
tsu_xcs
th_xcs
XCS
Figure 11-2. MUX Mode Write Cycle
Page 137
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
ALE
DATA
DATA
ten1_da
ten2_da
tdr_da
ADDR
tsu_da
tw_xrd
th_da
XRD
td_wait
tw_wait
WAIT
tsu_xcs
th_xcs
XCS
Figure 11-3. PARA Mode Read Cycle
Page 138
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
ALE
DATA
twr__da
ADDR
tsu_da
tw_xwr
th_da
XWR
td_wait
tw_wait
WAIT
tsu_xcs
th_xcs
XCS
Figure 11-4. PARA Mode Write Cycle
NOTE:
M8M16 mode
8 bit Mode
16 bit Mode
Page 139
DATA[7:0]
DA[15:8]
DA[15:0]
ADDR[7:0]
DA[7:0]
BDIO[15:8]
DA[7:0] ( mux mode )
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
11.2. Bulky Interface
11.2.1. Sync mode
Title
Tbdoav
Tbdibsy
Tbd
TSUbdi
THObdi
TSUbd
THObd
Item
BDOAVAIL output delay
BDIBUSY output delay
Data output delay
BDIFEN/BDOFEN input setup
BDIFEN/BDOFEN input hold
Data input setup
Data input hold
min
max
unit
2
5
5
8
2
8
2
15
17
17
ns
ns
ns
ns
ns
ns
ns
BDICLK
Tbdoav
BDOAVAIL
Tbdibsy
BDIBUSY
Tbd
BDIO/O(out)
Tbd
BDOF
TSUbdi
THObdi
TSUbd
THObd
BDIEN
BDIF{2:0}
TSUbd
THObd
BDIO(IN)
Figure 11-5. Sync Mode
Page 140
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
11.2.2. Async mode
Title
Tabdien on
Tabdien off
Tcyc
Item
BDIEN pulse width on
BDIEN pulse width off
Cycle time
min
Tcyc
Tcyc
25
max
Tabdien on
Tabdien off
Tabdoen on
Tabdoen off
BDIEN
BDOEN
Tcyc
BDICLK
Figure 11-6. Async
Page 141
unit
ns
ns
ns
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Title
TSUabd
THOabd
Tabdibsy0
Tabdibsy1
Tabdoav0
Tabdoav1
Tabdoen
Tabdodis
Item
data input setup
data input hold
BDIBUSY delay 0
BDIBUSY delay 1
BDOAVAIL delay 0
BDOAVAIL delay 1
BDData output enable
BDData output disable
min
6
2
max
11
3
11
3
3
3
11
11
unit
ns
ns
ns
ns
ns
ns
ns
ns
BDIBUSY
Tabdibsy0
Tabdibsy1
BDIEN
TSUabd
THOabd
TSUabd
THOabd
BDIF
BDIO[15(7):0]
Figure 11-7 . ASYNC Handshake Mode WRITE
BDOAVAIL
Tabdoav0
Tabdoav1
BDOEN
Tabdoen
Tabdodis
BDIO
Figure 11-8 . ASYNC Handshake mode READ
Page 142
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Title
Tbbdibsy
TSUabbd
THOabbd
Tabbdoav
Tabbdoen
Tabbdodis
Item
BDIBUSY delay
BDData input setup
BDData input hold
BDOAVAIL
BDData output enable
BDData output disable
min
max
2T+8
6
2
3
3
2T+8
11
11
BDIBUSY
Tbbdibsy
BDIEN
TSUabbd
THOabbd
TSUabbd
THOabbd
BDIF
BDIO
Figure 11-9. ASYNC Burst Mode WRITE
BDOAVAIL
Tabbdoav
BDOEN
Tabbdoen
Tabbdodis
BDIO
Figure 11-10. Async Burst Mode READ
Page 143
unit
ns
ns
ns
ns
ns
ns
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Title
Tsbdreq0
Tsbdreq1
Tsrw0
Tsrw1
TSUsbd
THOsbd
Tsbdoen
Tsbdodis
Tsbdof
Item
BDREQ delay 0
BDREQ delay 1
BDACK to BRWR/RD
BRWR/RD to BDACK
SCSI Data input setup
SCSI Data input hold
SCSI Data output enable
SCSI Data output disable
SCSI Data flag invalid
Min
3
0
0
6
2
3
3
3
max
11
11
11
11
BDREQ
Tsbdreq0
Tsbdreq1
BDACK
Tsrw0
TSrw1
BDWR/RD
TSUsbd
THOsbd
TSUsbd
THOsbd
BDIF
BDIO(in)
Tsbdof
Tsbdof
Tsbdoen
Tsbdodis
BDOF
BDIO(out)
Figure 11-11. SCSI Handshake Mode
Page 144
unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Title
Tsbbdreq
Item
BDREQ delay
min
Tsbrw0
Tsbrw1
TSUsbbd
THOsbbd
Tsbbdoen
Tsbbdodis
BDACK to BRWR/RD
BRWR/RD to BDACK
SCSI Data input setup
SCSI Data input hold
SCSI Data output enable
SCSI Data output disable
0
0
6
2
3
3
max
2T+8
unit
ns
(T: 1BDICLK cycle)
11
11
(note-1)
BDREQ
Tsbbdreq
BDACK
Tsbrw0
Tsbrw1
BDWR/RD
TSUsbbd
THOsbbd
TSUsbbd
THOsbbd
BDIF
BDIO(in)
Tsbbdoen
Tsbbdodis
Tsbbdoen
Tsbbdodis
BDOF
BDIO(out)
Figure 11-12. SCSI Burst Mode
note-1) BDREQ is active when FIFO has capacity.
note-2) Tsbbdreq means monitoring time of BDREQ transition from BDACK(BDRD/WR) edge.
Page 145
ns
ns
ns
ns
ns
ns
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Title
Tui
Tenv
Tdvs
Tdvh
Tcyc
Tmli
Tli
Tziordy
Tiordyz
Item
Unlimit interlock time
Emulate Time
Data valid setup time
Data valid hold time
Cycle time
Interlock time with minimum
Unlimited interlock time
Before driving IORDY
pull-up time
BDACK
(DMARQ)
min
max
TBD
TBD
Tcyc * (BDODelay + 1) - 6
Tcyc-13
25
TBD
TBD
TBD
TBD
Tui
ATACK
(DMACK)
Tenv
BDOAVAIL
(STOP)
Tenv
BDIBUSY
(HDMARDY)
Figure 11-13. ATAPI Initiate (READ)
Tcyc
BDIEN
(DSTROBE)
Tdvh
BDIO
(DD)
Tdvh
BDOF
Figure 11-14. ATAPI Read
Page 146
unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
BDACK
(DMARQ)
Tmli
ATACK
(DMACK)
Tli
BDOAVAIL
(STOP)
Tli
BDIBUSY
(HDMARDY)
Figure 11-15. ATAPI Terminate (READ)
BDACK
(DMARQ)
Tui
ATACK
(DMACK)
Tenv
BDOAVAIL
(STOP)
Tziordy
BDIEN
(DDMARDY)
Figure 11-16. ATAPI Initiate (Write)
Page 147
Tli
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
BDIBUSY
(HSTROBE)
Tdvs
Tdvh
Tdvs
Tdvh
BDIO
(DD)
BDIF
Figure 11-17. ATAPI Write
BDACK
(DMARQ)
Tmli
ATACK
(DMAC)
Tli
BDOAVAIL
(STOP)
Trp
Tiordyz
BDIEN
(DDMARDY)
Figure 11-18. ATAPI Terminate (Write)
Page 148
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
SCLK
50%
50%
50%
tw2(H)
tw2(L)
tc2
Figure 11-19. SCLK Waveform
SCLK
50%
50%
td5
50%
td6
td7
D0-D7
td8
td9
td10
CTL0-CTL1
Figure 11-20. TSB43LV81-to-Phy-Layer Transfer Waveforms
Page 149
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
SCLK
50%
tsu5
th5
D0-D7
tsu6
th6
CTL0-CTL1
Figure 11-21. Phy Layer-to-TSB43LV81 Transfer Waveforms
SCLK
50%
td11
LREQ
Figure 11-22. TSB43LV81 link-request-Phy-Layer Waveforms
Page 150
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
12. PHY internal register configuration
There are 16 accessible internal registers for PHY block in the TSB43LV81. The configuration of the registers at
addresses 0 through 7 (the base registers) is fixed, while the configuration of the registers at addresses 8 through Fh
(the paged registers) is dependent upon which one of eight pages, numbered 0 through 7, is currently selected. The
selected page is set in base register 7.
The configuration of the base registers is shown in Table 12-1, and corresponding field descriptions given in12-1.
The base register field definitions are unaffected by the selected page number.
A reserved register or register field (marked as “Reserved” or “Rsvd” in the register configuration tables below) is
read as 0, but is subject to future usage. All registers in pages 2 through 6 are reserved.
Table 12-1. Base Register Configuration
Bit Position
Address
0
1
2
0000
3
4
5
Physical ID
0001
RHB
IBR
6
7
R
CPS
Gap_Count
0010
Extended (‘b111)
Rsvd
Num_Ports (‘b0010)
0011
PHY_Speed (‘b010)
Rsvd
Delay (‘b0000)
0100
LCtrl
C
0101
RPIE
ISBR
0110
Jitter (‘b000)
CTOI
CPSI
Pwr_Class
STOI
PEI
EAA
EMC
Reserved
0111
Page_select
Rsvd
Port_Select
Table 12-2. Base Register Field Descriptions
FIELD
SIZE
TYPE
Physical ID
6
Rd
This field contains the physical address ID of this node determined during selfID. The physical-ID is invalid after a bus-reset until self-ID has completed as
indicated by an unsolicited register-0 status transfer.
R
1
Rd
Root. This bit indicates that this node is the root node. The R bit is reset to 0 by
bus-reset, and is set to 1 during tree-ID if this node becomes root.
CPS
1
Rd
Cable-power-status. This bit indicates the state of the CPS input pin. The CPS
pin is normally tied to serial bus cable power through a 400 kΩ resistor. A 0 in
this bit indicates that the cable power voltage has dropped below its threshold for
guaranteed reliable operation.
Page 151
DESCRIPTION
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
FIELD
SIZE
TYPE
DESCRIPTION
RHB
1
Rd/Wr
Root-holdoff bit. This bit instructs the PHY to attempt to become root after the
next bus-reset. The RHB bit is reset to 0 by hardware reset and is unaffected by
bus-reset.
IBR
1
Rd/Wr
Initiate bus-reset. This bit instructs the PHY to initiate a long (166 µs) bus-reset
at the next opportunity. Any receive or transmit operation in progress when this
bit is set will complete before the bus-reset is initiated. The IBR bit is reset to 0
by hardware reset or bus-reset.
Gap_Count
6
Rd/Wr
Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset
gap, and arb-delay times. The gap count may be set either by a write to this
register or by reception or transmission of a PHY_CONFIG packet. The gap
count is set to 3Fh by hardware reset or after two consecutive bus-resets without
an intervening write to the gap count register (either by a write to the PHY
register or by a PHY_CONFIG packet).
Extended
3
Rd
Extended register definition. For the TSB41LV01 this field is ‘b111, indicating
that the extended register set is implemented.
Num_Ports
4
Rd
Number of ports. This field indicates the number of ports implemented in the
PHY. For the TSB41LV01 this field is 1.
PHY_Speed
3
Rd
PHY speed capability. For the TSB41LV01 PHY this field is ‘b010, indicating
S400 speed capability.
Delay
4
Rd
PHY repeater data delay. This field indicates the worst case repeater data delay
of the PHY, expressed as 144+(delay*20) ns. For the TSB41LV01 this field is
0.
LCtrl
1
Rd/Wr
Link-active status control. This bit is used to control the active status of the LLC
as indicated during self-ID. The logical AND of this bit and the LPS active status
is replicated in the “L” field (bit 9) of the self-ID packet. The LLC is considered
active only if both the LPS input is active and the LCtrl bit is set.
The LCtrl bit provides a software controllable means to indicate the LLC active
status in lieu of using the LPS input.
The LCtrl bit is set to 1 by hardware reset and is unaffected by bus-reset.
NOTE: The state of the PHY-LLC interface is controlled solely by the LPS
input, regardless of the state of the LCtrl bit. If the PHY-LLC interface is
operational as determined by the LPS input being active, then received packets
and status information will continue to be presented on the interface, and any
requests indicated on the LREQ input will be processed, even if the LCtrl bit is
cleared to 0.
C
Page 152
1
Rd/Wr
Contender status. This bit indicates that this node is a contender for the bus or
isochronous resource manager. This bit is replicated in the "c" field (bit 20) of
the self-ID packet. This bit is set to the state specified by the C/LKON input pin
upon hardware reset and is unaffected by bus-reset.
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
FIELD
SIZE
TYPE
DESCRIPTION
Jitter
3
Rd
PHY repeater jitter. This field indicates the worst case difference between the
fastest and slowest repeater data delay, expressed as (JITTER+1)*20 ns. For the
TSB41LV01 this field is 0.
Pwr_Class
3
Rd/Wr
Node power class. This field indicates this node’s power consumption and
source characteristics, and is replicated in the “pwr” field (bits 21–23) of the selfID packet. This field is set to the state specified by the PC0–PC2 input pins
upon hardware reset and is unaffected by bus-reset. See table 12-5.
RPIE
1
Rd/Wr
Resuming port interrupt enable. This bit, if set to 1, enables the port event
interrupt (PEI) bit to be set whenever resume operations begin on any port. This
bit also enables the C/LKON output signal to be activated whenever the LLC is
inactive and any of the CTOI, CPSI, or STOI interrupt bits are set. This bit is
reset to 0 by hardware reset and is unaffected by bus-reset.
ISBR
1
Rd/Wr
Initiate short arbitrated bus-reset. This bit, if set to 1, instructs the PHY to
initiate a short (1.30 µs) arbitrated bus-reset at the next opportunity. This bit is
reset to 0 by bus-reset.
NOTE: Legacy IEEE Std 1394-1995 compliant PHYs may not be capable of
performing short bus-resets. Therefore, initiation of a short bus-reset in a
network that contains such a legacy device will result in a long bus-reset being
performed.
CTOI
1
Rd/Wr
Configuration time-out interrupt. This bit is set to 1 when the arbitration
controller times-out during tree-ID start, and may indicate that the bus is
configured in a loop. This bit is reset to 0 by hardware reset, or by writing a 1 to
this register bit.
If the CTOI and RPIE bits are both set and the LLC is or becomes inactive, the
PHY will activate the C/LKON output to notify the LLC to service the interrupt.
NOTE: If the network is configured in a loop, only those nodes that are part of
the loop will generate a configuration time-out interrupt. All other nodes will
instead time-out waiting for the tree-ID and/or self-ID process to complete and
then generate a state time-out interrupt and bus-reset.
CPSI
1
Rd/Wr
Cable power status interrupt. This bit is set to 1 whenever the CPS input
transitions from high to low indicating that cable power may be too low for
reliable operation. This bit is reset to 1 by hardware reset. It can be cleared by
writing a 1 to this register bit.
If the CPSI and RPIE bits are both set and the LLC is or becomes inactive, the
PHY will activate the C/LKON output to notify the LLC to service the interrupt.
STOI
1
Rd/Wr
State time-out interrupt. This bit indicates that a state time-out has occurred
(which also causes a bus-reset to occur). This bit is reset to 0 by hardware reset,
or by writing a 1 to this register bit.
If the STOI and RPIE bits are both set and the LLC is or becomes inactive, the
PHY will activate the C/LKON output to notify the LLC to service the interrupt.
Page 153
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
FIELD
PEI
SIZE
TYPE
DESCRIPTION
1
Rd/Wr
Port event interrupt. This bit is set to 1 upon a change in the bias (unless
disabled), connected, disabled, or fault bits for any port for which the port
interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt
enable (RPIE) bit is set, the PEI bit is set to 1 at the start of resume operations on
any port. This bit is reset to 0 by hardware reset, or by writing a 1 to this register
bit.
If the PEI bit is set (regardless of the state of the RPEI bit) and the LLC is or
becomes inactive, the PHY will activate the C/LKON output to notify the LLC to
service the interrupt.
EAA
1
Rd/Wr
Enable accelerated arbitration. This bit enables the PHY to perform the various
arbitration acceleration enhancements defined in P1394a (ACK-accelerated
arbitration, asynchronous fly-by concatenation, and isochronous fly-by
concatenation). This bit is reset to 0 by hardware reset and is unaffected by busreset.
NOTE: The EAA bit should be set only if the attached LLC is P1394a compliant.
If the LLC is not P1394a compliant, use of the arbitration acceleration
enhancements may interfere with isochronous traffic by excessively delaying the
transmission of cycle-start packets.
EMC
1
Rd/Wr
Enable multi-speed concatenated packets. This bit enables the PHY to transmit
concatenated packets of differing speeds in accordance with the protocols
defined in P1394a. This bit is reset to 0 by hardware reset and is unaffected by
bus-reset.
NOTE: The use of multi-speed concatenation is completely compatible with
networks containing legacy IEEE Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be P1394a compliant.
Page_Select
3
Rd/Wr
Page-select. This field selects the register page to use when accessing register
addresses 8 through 15. This field is reset to 0 by hardware reset and is
unaffected by bus-reset.
Port_Select
4
Rd/Wr
Port-select. This field selects the port when accessing per-port status or control
(e.g., when one of the port status/control registers is accessed in page 0). Ports
are numbered starting at 0. This field is reset to 0 by hardware reset and is
unaffected by bus-reset.
The Port Status page provides access to configuration and status information for each of the ports. The port is
selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7.
The configuration of the Port Status page registers is shown in Table 12-4, and corresponding field descriptions
given in Table 12-4. If the selected port is unimplemented, all registers in the Port Status page are read as 0.
Table 12-3. Page 0 (Port Status) Register Configuration
Page 154
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Bit Position
Address
0
1000
1
AStat
1001
2
3
Bstat
Peer_Speed
PIE
4
5
6
7
Ch
Con
Bias
Dis
Fault
1010
Reserved
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
Reserved
Table 12-4. Page 0 (Port Status) Register Field Descriptions
FIELD
AStat
SIZE
TYPE
2
Rd
DESCRIPTION
TPA line state. This field indicates the TPA line state of the selected port,
encoded as follows:
Code
11
01
10
00
Line State
Z
1
0
invalid
Bstat
2
Rd
TPB line state. This field indicates the TPB line state of the selected port. This
field has the same encoding as the ASTAT field.
Ch
1
Rd
Child/parent status. A 1 indicates that the selected port is a child port. A 0
indicates that the selected port is the parent port. A disconnected, disabled, or
suspended port is reported as a child port. The Ch bit is invalid after a bus-reset
until tree-ID has completed.
Con
1
Rd
Debounced port connection status. This bit indicates that the selected port is
connected. The connection must be stable for the debounce time of approximately
341ms for the Con bit to be set to 1. The Con bit is reset to 0 by hardware reset
and is unaffected by bus-reset.
NOTE: The Con bit indicates that the port is physically connected to a peer PHY,
but the port is not necessarily active.
Bias
Page 155
1
Rd
Debounced incoming cable bias status. A 1 indicates that the selected port is
detecting incoming cable bias. The incoming cable bias must be stable for the
debounce time of 52 µs for the Bias bit to be set to 1.
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
FIELD
SIZE
TYPE
DESCRIPTION
Dis
1
Rd/Wr
Port disabled control. If 1, the selected port is disabled. The Dis bit is reset to 0
by hardware reset (all ports are enabled for normal operation following hardware
reset). The Dis bit is not affected by bus-reset.
Peer_Speed
3
Rd
Port peer speed. This field indicates the highest
speed capability of the peer
PHY connected to the selected port, encoded as follows:
Code
000
001
010
011–111
Peer Speed
S100
S200
S400
invalid
The Peer_Speed field is invalid after a bus-reset until self-ID has completed.
NOTE: Peer speed codes higher than ‘b010 (S400) are defined in P1394a.
However, the TSB41LV01 is only capable of detecting peer speeds up to S400.
PIE
1
Rd/Wr
Port event interrupt enable. When set to 1, a port event on the selected port will
set the port event interrupt (PEI) bit and notify the link. This bit is reset to 0 by
hardware reset and is unaffected by bus-reset.
Fault
1
Rd/Wr
Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the
selected port and that the port is in the suspended state. A resume-fault occurs
when a resuming port fails to detect incoming cable bias from its attached peer. A
suspend-fault occurs when a suspending port continues to detect incoming cable
bias from its attached peer. Writing 1 to this bit clears the Fault bit to 0. This bit
is reset to 0 by hardware reset and is unaffected by bus-reset.
Page 156
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
The Vendor Identification page is used to identify the vendor/manufacturer and compliance level. The page is
selected by writing 1 to the Page_Select field in base register 7. The configuration of the Vendor Identification page
is shown in Table 12-5, and corresponding field descriptions given in Table 12-6.
Table 12-5. Page 1 (Vendor ID) Register Configuration
Bit Position
Address
0
1
2
3
4
1000
Compliance
1001
Reserved
1010
Vendor_ID[0]
1011
Vendor_ID[1]
1100
Vendor_ID[2]
1101
Product_ID[0]
1110
Product_ID[1]
1111
Product_ID[2]
5
6
7
Table 12-6. Page 1 (Vendor ID) Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
Compliance
8
Rd
Compliance level. For the TSB41LV01 this field is 01h, indicating
compliance with the P1394a specification.
Vendor_ID
24
Rd
Manufacturer’s organizationally unique identifier (OUI). For the TSB41LV01
this field is 08_00_28h (Texas Instruments) (the MSB is at register address
‘b1010).
Product_ID
24
Rd
Product identifier. For the TSB41LV01 this field is 41_xx_xxh (the MSB is at
register address ‘b1101).
The Vendor-Dependent page provides access to the special control features of the TSB41LV01, as well as
configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the
Page_Select field in base register 7. The configuration of the Vendor-Dependent page is shown in Table 12-7, and
corresponding field descriptions given in Table 12-8.
Table 12-7. Page 7 (Vendor-Dependent) Register Configuration
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Bit Position
Address
0
1
1000
NPA
2
3
4
5
Reserved
6
7
Link_Speed
1001
Reserved for test
1010
Reserved for test
1011
Reserved for test
1100
Reserved for test
1101
Reserved for test
1110
Reserved for test
1111
Reserved for test
Table 12-8. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
NPA
1
Rd/Wr
Null-packet actions flag. This bit instructs the PHY to not clear fair and priority
requests when a null packet is received with arbitration acceleration enabled. If
1, then fair and priority requests are cleared only when a packet of more than 8
bits is received; ACK packets (exactly 8 data bits), null packets (no data bits),
and mal-formed packets (less than 8 data bits) will not clear fair and priority
requests. If 0, then fair and priority requests are cleared when any non-ACK
packet is received, including null-packets or mal-formed packets of less than 8
bits. This bit is cleared to 0 by hardware reset and is unaffected by bus-reset.
Link_Speed
2
Rd/Wr
Link speed. This field indicates the top speed capability of the attached LLC.
Encoding is as follows:
Code
00
01
10
11
Speed
S100
S200
S400
illegal
This field is replicated in the "sp" field of the self-ID packet to indicate the speed
capability of the node (PHY and LLC in combination). However, this field does
not affect the PHY speed capability indicated to peer PHYs during self-ID; the
TSB41LV01 PHY identifies itself as S400 capable to its peers regardless of the
value in this field. This field is set to ‘b10 (S400) by hardware reset and is
unaffected by bus-reset.
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
13. APPENDIX A - PIN ASSIGNMENTS for TSB43LV81
NOTE: PIN ASSIGNMENT IS PRELIMINARY AND IS SUBJECT TO CHANGE
Pin
No
Signal Name
I/O
Pin
No
Signal Name
I/O
Pin
No
Signal Name
I/O
Pin
No
Signal Name
I/O
1
AUX[0]
I/O
37
NCLKOUT
O
73
BDIO12
I/O
109
ALE
I
2
AUX[1]
I/O
38
ATACK
O
I/O
3
DVSS
39
DVSS
4
AUX[2]
40
BDIF0
5
DVSS
41
BDIF1
6
AUX[3]
I/O*
42
BDIF2
I/O*
74
BDIO13
75
DVDD5
I/O
76
BDIO14
I/O
77
BDIO15
I/O
78
DVSS
79
XINT
O
80
DVSS
7
DVDD
43
DVSS
8
AUX[4]
I/O*
44
BDOF0
I/O*
45
BDOF1
O
81
DA[0]
46
BDOF2
O
82
DA[1]
110
XCS
I
111
XRESETL
I
I/O
112
DVDD5
I/O
113
DVSS
114
AGND
I/O
115
AGND
116
AVDD
I/O
117
AVDD
I/O
118
TPB-
I/O
I/O
9
AUX[5]
10
DVDD5
11
AUX[6]
I/O*
47
DVDD
83
DA[2]
I/O
119
TPB+
12
AUX[7]
I/O*
48
DVSS
84
DA[3]
I/O
120
AGND
13
AUX[8]
I/O*
49
BDIBSY
85
DVDD
121
TPA-
50
BDIEN
I
86
DVSS
122
TPA+
I/O
I/O*
51
BDOAVAIL
O
87
DA[4]
I/O
123
TPBIAS
I/O
I
14
DVSS
15
AUX[9]
O
I/O
16
DVSS
52
BDOEN
88
DA[5]
I/O
124
AGND
17
AUX[10]
I
53
DVDD5
89
DA[6]
I/O
125
AGND
18
AUX[11]
O
54
DVSS
90
DA[7]
I/O
126
R0
I/O*
19
DVDD
55
BDIO0
I/O
91
DVSS
127
R1
I/O*
20
CAN
O
56
BDIO1
I/O
92
DA[8]
128
AVDD
I/O
21
PD
I
57
BDIO2
I/O
93
DA[9]
I/O
129
AVDD
22
LPS
I
58
BDIO3
I/O
94
DA[10]
I/O
130
DVDD
23
DVSS
59
DVSS
95
DVSS
24
TM
I
60
BDIO4
I/O
96
DA[11]
25
CPS
I
61
BDIO5
I/O
97
DVDD
I/O
131
DVSS
132
DVSS
133
FLT0
I/O*
I/O*
26
DVSS
62
BDIO6
I/O
98
DA[12]
I/O
134
FLT1
27
DVDD5
63
BDIO7
I/O
99
DA[13]
I/O
135
PLLV
28
MODE[0]
I
64
DVSS
100
DA[14]
I/O
136
PLLG
29
MODE[1]
I
65
BDACK
101
DA[15]
I/O
137
PLLG
30
M8M16
I
66
DVDD
102
DVSS
138
DVSS
31
DVDD
67
DVSS
103
DVDD5
139
XO
I/O*
32
DVSS
68
BDIO8
I/O
104
DVSS
140
XI
I/O*
33
MUXMODE
I
69
BDIO9
I/O
105
WAIT
O
141
DVSS
34
CLKSEL
I/O
70
BDIO10
I/O
106
XRD
I
142
DVDD5
I/O
107
XWR
I
143
XRESETP
108
DVDD
144
DVDD
35
BDICLK
I/O
71
BDIO11
36
NCLKOEN
I/O
72
DVSS
Note)Pins marked “*” are not 5[V] tolelante,other pins are 5[V] tolelante.
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