ETC LMF40

LMF40 High Performance 4th-Order
Switched-Capacitor Butterworth Low-Pass Filter
General Description
Features
The LMF40 is a versatile, easy to use, precision 4th-order
Butterworth low-pass filter fabricated using National’s high
performance LMCMOS process. Switched-capacitor techniques eliminate external component requirements and allow a clock-tunable cutoff frequency. The ratio of the clock
frequency to the low-pass cutoff frequency is internally set
to 50-to-1 (LMF40-50) or 100-to-1 (LMF40-100). A Schmitt
trigger clock input stage allows two clocking options, either
self-clocking (via an external resistor and capacitor) for
stand-alone applications, or for tighter cutoff frequency control, an external TTL or CMOS logic compatible clock can
be applied. The maximally flat passband frequency response together with a DC gain of 1 V/V allows cascading
LMF40 sections together for higher-order filtering.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Cutoff frequency range of 0.1 Hz to 40 kHz
Cutoff frequency accuracy of g 1.0%, maximum
Low offset voltage, g 100 mV, maximum, g 5V supply
Low clock feedthrough of 5 mVP-P, typical
Dynamic range of 88 dB, typical
No external components required
8-pin mini-DIP or 14-pin wide-body small-outline packages
4V to 14V single/dual supply operation
Cutoff frequency set by external or internal clock
Pin-compatible with MF4
Applications
Y
Y
Y
Communication systems
Instrumentation
Automated control systems
Block and Connection Diagrams
Dual-In-Line Package
TL/H/10557 – 2
Top View
Small-Outline-Wide-Body Package
TL/H/10557 – 1
*Pin numbers in parentheses are for the 14-pin package
Ordering Information
Industrial (b40§ C s TA s a 85§ C)
Package
LMF40CIN-50, LMF40CIN-100
N08E
LMF40CIWM-50
M14B
LMF40CIWM-100
M14B
TL/H/10557 – 3
Top View
Military (b55§ C s TA s a 125§ C)
LMF40CMJ-50, LMF40CMJ-100
J08A
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/H/10557
RRD-B30M115/Printed in U. S. A.
LMF40 High Performance 4th-Order Switched-Capacitor
Butterworth Low-Pass Filter
December 1994
Absolute Maximum Ratings
(Notes 1 & 2)
Lead Temperature
N Package, Soldering (10 sec.)
J Package, Soldering (10 sec.)
WM Package, Vapor Phase (60 sec.) (Note 16)
WM Package, Infrared (15 sec.)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V a – Vb)
15V
Voltage at Any Pin
Vb b 0.2V to V a a 0.2V
Input Current at Any Pin (Note 13)
5 mA
Package Input Current (Note 13)
20 mA
Power Dissipation (Note 14)
500 mW
b 65§ C to a 150§ C
Storage Temperature
ESD Susceptibility (Note 12)
Pin 1 CLK IN
a 260§ C
a 300§ C
a 215§ C
a 220§ C
2000V
1700V
Operating Ratings (Notes 1 & 2)
Temperature Range
TMIN s TA s TMAX
LMF40CIN-50, LMF40CIN-100
LMF40CIWM-50,
b 40§ C s TA s a 85§ C
LMF40CIWM-100
LMF40CMJ-50, LMF40CMJ-100 b55§ C s TA s a 125§ C
4V to 14V
Supply Voltage Range (V a b Vb)
Filter Electrical Characteristics
The following specifications apply for fCLK e 500 kHz. Boldface limits apply for TA e TJ e TMIN to TMAX: All other limits TA
e TJ e 25§ C.
Symbol
Parameter
Typical
(Note 10)
Conditions
Limits
(Note 11)
Units
(Limit)
2
Hz (min)
MHz (max)
V a e a 5V, Vb e b5V
fCLK
Clock Frequency Range
(Note 17)
5
IS
Supply Current
CMJ
CIN, CIJ, CIWM
3.5 / 7.0
3.5 / 5.0
mA (max)
mA (max)
HO
DC Gain
RSource s 2 kX
a 0.05 / a 0.05
b 0.15 / b 0.20
dB (max)
dB (min)
fCLK/fc
Clock to Cutoff
Frequency Ratio
(Note 3)
LMF40-50
LMF40-100
49.80 g 0.8% / 49.80 g 1.0%
99.00 g 0.8% / 99.00 g 1.0%
(max)
(max)
DfCLK/fc/DT
AMIN
Clock to Cutoff Frequency
Ratio Temperature
Coefficient
LMF40-50
LMF40-100
Stopband Attenuation
5
5
At 2 fc
ppm/§ C
ppm/§ C
24.0
2
dB (min)
Filter Electrical Characteristics (Continued)
The following specifications apply for fCLK e 500 kHz. Boldface limits apply for TA e TJ e TMIN to TMAX: All other limits TA
e TJ e 25§ C.
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limit)
g 80 / g 100
g 80 / g 100
mV (max)
mV (max)
a 3.9 / a 3.7
b 4.2 / b 4.0
V (min)
V (max)
V a e a 5V, Vb e b5V (Continued)
VOS
Unadjusted DC
Offset Voltage
LMF40-50
LMF40-100
VO
Output Swing
RL e 5 kX
ISC
Output Short Circuit
Current (Note 8)
Source
Sink
Dynamic Range
(Note 4)
Additional Magnitude
Response Test Points
(Note 6)
LMF40-50
LMF40-100
Clock Feedthrough
90
2.2
mA
mA
88
dB
fIN e 12 kHz
fIN e 9 kHz
b 7.50 g 0.26 / b 7.50 g 0.30
b 1.46 g 0.12 / b 1.46 g 0.16
dB (max)
dB (max)
fIN e 6 kHz
fIN e 4.5 kHz
b 7.15 g 0.26 / b 7.15 g 0.30
b 1.42 g 0.12 / b 1.42 g 0.16
dB (max)
dB (max)
Filter Output
VIN e 0V
5
mVP – P
Filter Electrical Characteristics The following specifications apply for fCLK e 250 kHz. Boldface limits
apply for TA e TJ e TMIN to TMAX: All other limits TA e TJ e 25§ C.
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limit)
1.0
Hz (min)
MHz (max)
V a e a 2.5V, Vb e b2.5V
fCLK
Clock Frequency Range
(Note 17)
5
IS
Supply Current
CMJ
CIN, CIJ, CIWM
2.1 / 4.0
2.1 / 3.0
mA (max)
mA (max)
HO
DC Gain
RS s 2 kX
fCLK e 250 kHz
a 0.05 / a 0.05
b 0.15 / b 0.20
dB (max)
dB (min)
fCLK/fc
Clock to Cutoff
Frequency Ratio
LMF40-50
fCLK e 500 kHz
b 0.1
fCLK e 250 kHz
fCLK e 500 kHz
LMF40-100
(Note 3)
dB
49.80 g 0.8%
(max)
99.00 g 1.0% / 99.00 g 1.2%
(max)
49.80
g 0.6%
fCLK e 250 kHz
fCLK e 500 kHz
99.00
g 1.2%
3
Filter Electrical Characteristics (Continued)
The following specifications apply for fCLK e 250 kHz. Boldface limits apply for TA e TJ e TMIN to TMAX: All other limits TA
e TJ e 25§ C.
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limit)
V a e a 2.5V, Vb e b2.5V (Continued)
DfCLK/fc/DT
Clock to Cutoff
Frequency Ratio
Temperature Coefficient
LMF40-50
LMF40-100
AMIN
Stopband Attenuation
VOS
Unadjusted DC
Offset Voltage
5
5
ppm/§ C
ppm/§ C
At 2 fc
LMF40-50
LMF40-100
VO
Output Swing
RL e 5 kX
ISC
Output Short Circuit
Current (Note 8)
Source
Sink
Dynamic Range
(Note 4)
Additional Magnitude Response
Test Points (Note 6)
LMF40-50
LMF40-100
Clock Feedthrough
b 24.0
dB (min)
g 80 / g 100
g 80 / g 100
mV (max)
mV (max)
a 1.4 / a 1.2
b 2.0 / b 1.8
V (min)
V (max)
42
0.9
mA
mA
81
dB
fIN e 6 kHz
fIN e 4.5 kHz
b 7.50 g 0.26 / b 7.50 g 0.30
b 1.46 g 0.12 / b 1.46 g 0.16
dB (max)
dB (max)
fIN e 3 kHz
fIN e 2.25 kHz
b 7.15 g 0.26 / b 7.15 g 0.30
b 1.42 g 0.12 / b 1.42 g 0.16
dB (max)
dB (max)
Filter Output
VIN e 0V
5
mVP – P
Logic Input-Output Characteristics The following specifications apply for Vb e 0V unless otherwise
specified. Boldface limits apply for TA e TJ e TMIN to TMAX: all other limits TA e TJ e 25§ C.
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limit)
2.0 / 2.1
0.8 / 0.8
V (min)
V (max)
2.0 / 2.0
0.6 / 0.4
V (min)
V (max)
TTL CLOCK INPUT, CLK R PIN (Note 9)
TTL CLK R Pin Input Voltage
V a e a 5V
Vb e b5V
Logic ‘‘1’’
Logic ‘‘0’’
CLK R Input Voltage
V a e a 2.5V
Vb e b2.5V
Logic ‘‘1’’
Logic ‘‘0’’
Maximum Leakage Current
at CLK R Pin
2.0
mA
SCHMITT TRIGGER
VT a
Positive Going Input
Threshold Voltage
CLK IN Pin
V a e a 10V
6.1 / 6.0
8.8 / 8.9
V (min)
V (max)
V a e a 5V
3.0 / 2.9
4.3 / 4.4
V (min)
V (max)
4
Logic Input-Output Characteristics (Continued) The following specifications apply for Vb e 0V unless
otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX: all other limits TA e TJ e 25§ C.
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limit)
SCHMITT TRIGGER (Continued)
VTb
VT a b VTb
Negative Going Input
Threshold Voltage
CLK IN Pin
V a e a 10V
1.4 / 1.3
3.8 / 3.9
V (min)
V (max)
V a e a 5V
0.7 / 0.6
1.9 / 2.0
V (min)
V (max)
Hysteresis CLK IN Pin
V a e a 10V
2.3 / 2.1
7.4 / 7.6
V (min)
V (max)
V a e a 5V
1.1 / 0.9
3.6 / 3.8
V (min)
V (max)
Logical ‘‘1’’ Output
Voltage CLK R
Pin
IO e b10 mA
V a e a 10V
V a e a 5V
9.1 / 9.0
4.6 / 4.5
V (min)
V (min)
Logical ‘‘0’’ Output
Voltage CLK R
Pin
IO e b10 mA
V a e a 10V
V a e a 5V
0.9 / 1.0
0.4 / 0.5
V (max)
V (max)
Output Source Current
CLK R Pin
CLK R to Vb
V a e a 10V
V a e a 5V
4.9 / 3.7
1.6 / 1.2
mA (min)
mA (min)
Output Sink Current
CLK R Pin
CLK R to V a
V a e a 10V
V a e a 5V
4.9 / 3.7
1.6 / 1.2
mA (min)
mA (min)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating range.
Note 2: All voltages are specified with respect to ground.
Note 3: The filter’s cutoff frequency is defined as the frequency where the magnitude response is 3.01 dB less than the DC gain of the filter.
Note 4: For g 5V supplies the dynamic range is referenced to 2.62 Vrms (3.7V peak) where the wideband noise over a 20 kHz bandwidth is typically 100 mVrms for
the LMF40. For g 2.5V supplies the dynamic range is referenced to 0.849 Vrms (1.2V peak) where the wideband noise over a 20 kHz bandwidth is typically
75 mVrms for the LMF40.
Note 5: The specifications for the LMF40 have been given for a clock frequency (fCLK) of 500 kHz at g 5V and 250 kHz at g 2.5V. Above this clock frequency the
cutoff frequency begins to deviate from the specified error band of g 0.8% over the temperature range, but the filter still maintains its magnitude characteristics.
See Application Information, Section 1.4.
Note 6: The filter’s magnitude response is tested at the cutoff frequency, fc, fS e 2 fc, and at these other two additional frequencies.
Note 7: For simplicity all logic levels have been referenced to Vb e 0V (except for the TTL input logic levels). The logic levels will scale accordingly for g 5V and
g 2.5V supplies.
Note 8: The short circuit source current is measured by forcing the output that is being tested to its maximum positive swing and then shorting that output to the
negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage and then shorting that output
to the positive supply. These are worst case conditions.
Note 9: The LMF40 is operated with symmetrical supplies and L. Sh. is tied to ground.
Note 10: Typicals are at TJ e 25§ C and represent the most likely parametric norm.
Note 11: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Human body model; 100 pF discharged through a 1.5 kX resistor.
Note 13: When the input voltage (VIN) at any pin exceeds the power supply voltages (VIN k Vb or VIN l V a ) the absolute value of the current at that pin should
be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply voltages with 5 mA current limit to four.
Note 14: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, iJA, and the ambient temperature TA. The
maximum allowable power dissipation is PD e (TJMAX b TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LMF40,
TJMAX e 125§ C, and the typical junction-to-ambient thermal resistance, when board mounted, is 67§ C/W for the LMF40CIN, 62§ C/W for the LMF40CIJ and
LMF40CMJ, and 78§ C/W for the LMC40CIWM.
Note 15: In popular usage the term cutoff frequency defines that frequency at which a filter’s gain drops 3.01 dB below its DC value. Equations (2) and (3) and
design example 2.1, however, use the term cutoff frequency (fb) to define that frequency at which a filter’s gain drops by a variable amount as determined from the
given design specifications.
Note 16: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering surface mount devices or see the section
titled ‘‘Surface Mount’’ in the Linear Data Book .
Note 17: The nominal ratio of the clock frequency to the low-pass cutoff frequency is internally set to 50-to-1 (LMF40-50) or 100-to-1 (LMF40-100).
5
Typical Performance Characteristics
fCLK/fc Deviation
vs Power Supply Voltage
fCLK/fc Deviation
vs Temperature
fCLK/fc Deviation
vs Clock Frequency
DC Gain Deviation
vs Power Supply Voltage
DC Gain Deviation
vs Temperature
DC Gain Deviation
vs Clock Frequency
fCLK/fc Deviation
vs Power Supply Voltage
fCLK/fc Deviation
vs Temperature
fCLK/fc Deviation
vs Clock Frequency
DC Gain Deviation
vs Power Supply Voltage
DC Gain Deviation
vs Temperature
DC Gain Deviation
vs Clock Frequency
TL/H/10557 – 5
6
Typical Performance Characteristics
(Continued)
Power Supply Current
vs Power Supply Voltage
Power Supply Current
vs Temperature
Positive Voltage Swing
vs Power Supply Voltage
Negative Voltage Swing
vs Power Supply Voltage
Positive Voltage Swing
vs Temperature
Negative Voltage Swing
vs Temperature
DC Offset Voltage Deviation
vs Power Supply Voltage
DC Offset Voltage Deviation
vs Temperature
CLK R Trigger Threshold
vs Power Supply Voltage
Schmitt Trigger Threshold
vs Power Supply Voltage
TL/H/10557 – 6
7
Pin Descriptions
(Numbers in ( ) are for 14-pin package).
Pin
Ý
1
(1)
2
(3)
3
(5)
5
(8)
6
(10)
Pin
Name
CLK IN
CLK R
L. Sh
FILTER
OUT
AGND
Pin
Function
Ý
7, 4
(7, 12)
A CMOS Schmitt-trigger input
to be used with an external
CMOS logic level clock. Also
used for self clocking Schmitttrigger oscillator (see Section
1.1).
A TTL logic level clock input
when in split supply operation
( g 2.0V to g 7V) with L. Sh
tied to system ground. This pin
becomes a low impedance
output when L. Sh is tied to
Vb. Also used in conjunction
with the CLK IN pin for a self
clocking Schmitt-trigger
oscillator (see Section 1.1).
The TTL input signal must not
exceed the supply voltages by
more than 0.2V.
Level shift pin; selects the
logic threshold levels for the
clock. When tied to Vb it
enables an internal TRISTATEÉ buffer stage between
the Schmitt trigger and the
internal clock level shift stage
thus enabling the CLK IN
Schmitt-trigger input and
making the CLK R pin a low
impedance output. When the
voltage level at this input
exceeds 25% (V a b Vb) a
Vb the internal TRI-STATE
buffer is disabled allowing the
CLK R pin to become the
clock input for the internal
clock level-shift stage. The
CLK R threshold level is now
2V above the voltage on the L.
Sh pin. The CLK R pin will be
compatible with TTL logic
levels when the LMF40 is
operated on split supplies with
the L. Sh pin connected to
system ground.
The output of the low-pass
filter.
The analog ground pin. This
pin sets the DC bias level for
the filter section and must be
tied to the system ground for
split supply operation or to
mid-supply for single supply
operation (see Section 1.2).
When tied to mid-supply this
pin should be well bypassed.
8
(14)
Pin
Name
V a , Vb
Function
The positive and negative
supply pins. The total power
supply range is 4V, to 14V.
Decoupling these pins with
0.1 mF capacitors is highly
recommended.
The input to the low-pass filter.
To minimize gain errors the
source impedance that drives
this input should be less than
2k (see Section 3). For single
supply operation the input
signal must be biased to midsupply or AC coupled through
a capacitor.
FILTER
IN
1.0 LMF40 Application Information
The LMF40 is a non-inverting unity gain low-pass fourth-order Butterworth switched-capacitor filter. The switched-capacitor topology makes the cutoff frequency (where the gain
drops 3.01 dB below the DC gain) a direct ratio (100:1 or
50:1) of the clock frequency supplied to the filter. Internal
integrator time constants set the filter’s cutoff frequency.
The resistive element of these integrators is actually a capacitor which is ‘‘switched’’ at the clock frequency (for a
detailed discussion see Input Impedance section). Varying
the clock frequency changes the value of this resistive element and thus the time constant of the integrators. The
clock-to-cutoff-frequency ratio (fCLK/fc) is set by the ratio of
the input and feedback capacitors in the integrators. The
higher the clock-to-cutoff-frequency ratio the closer this approximation is to the theoretical Butterworth response.
1.1 CLOCK INPUTS
The LMF40 has a Schmitt-trigger inverting buffer which can
be used to construct a simple R/C oscillator. Pin 3 is connected to Vb, making Pin 2 a low impedance output. The
oscillator’s frequency is nominally
fCLK e
RC In
which is typically
Ð#
1
VCC b Vtb
VCC b Vt a
fCLK j
1
1.37 RC
J #V J(
Vt a
tb
(1)
(1a)
for VCC e 10V.
Note that fCLK is dependent on the buffer’s threshold levels
as well as the resistor/capacitor tolerance (see Figure 1 ).
Schmitt-trigger threshold voltage levels can change significantly causing the R/C oscillator’s frequency to vary greatly
from part to part.
Where accurate cutoff frequency is required, an external
clock can be used to drive the CLK R input of the LMF40.
This input is TTL logic level compatible and also presents a
very light load to the external clock source ( E 2 mA). With
split supplies and the level shift (L. Sh) tied to system
ground, the logic level is about 2V. (See the Pin Description
for L. Sh).
8
1.0 LMF40 Application Information (Continued)
As an example, with a source impedance of 10 kX the overall gain would be:
1.2 POWER SUPPLY
The LMF40 can be powered from a single supply or split
supplies. The split supply mode shown in Figure 2 is the
most flexible and easiest to implement. Supply voltages of
g 5V to g 7V enable the use of TTL or CMOS clock logic
levels. Figure 3 shows AGND resistor-biased to V a /2 for
single supply operation. In this mode only CMOS clock logic
levels can be used, and input signals should be capacitorcoupled or biased near mid-supply.
AV e
Since the maximum overall gain error for the LMF40 is
a 0.05, b 0.15 dB @ 25§ C with RS s 2 kX the actual gain
error for this case would be b0.04 dB to b0.24 dB.
1.4 CUTOFF FREQUENCY RANGE
The filter’s cutoff frequency (fc) has a lower limit due to
leakage currents through the internal switches draining the
charge stored on the capacitors. At lower clock frequencies
these leakage currents can cause millivolts of error. For example:
fCLK e 100 Hz, ILeakage e 1 pA, C e 1 pF
1.3 INPUT IMPEDANCE
The LMF40 low-pass filter input (FILTER IN) is not a high
impedance buffer input. This input is a switched-capacitor
resistor equivalent, and its effective impedance is inversely
proportional to the clock frequency. The equivalent circuit of
the filter’s input can be seen in Figure 4 . The input capacitor
charges to VIN during the first half of the clock period; during the second half the charge is transferred to the feedback capacitor. The total transfer of charge in one clock
cycle is therefore Q e CIN VIN, and since current is defined
as the flow of charge per unit time, the average input current
becomes
IIN e Q/T
Ve
CIN VIN
e CIN VIN fCLK
IIN AVE e
T
The equivalent input resistor (RIN) then can be expressed
as
VIN
1
e
RIN e
IIN
CIN fCLK
The input capacitor is 2 pF for the LMF40-50 and 1 pF for
the LMF40-100, so for the LMF40-100
2.0 Designing with the LMF40
Given any low-pass filter specification, two equations will
come in handy in trying to determine whether the LMF40 will
do the job. The first equation determines the order of the
low-pass filter required to meet a given response specification:
log [(100.1Amin b 1)/(100.1Amax b 1)]
ne
(2)
2 log (fs/fb)
1 c 1012
1 c 1012
1 c 1010
e
e
fCLK
fc c 100
fc
and
5 c 1011
5 c 1011
1 c 1010
e
e
fCLK
fc c 50
fc
for the LMF40-50. The above equation shows that for a
given cutoff frequency (fc), the input resistance of the
LMF40-50 is the same as that of the LMF40-100. The higher the clock-to-cutoff-frequency ratio, the greater equivalent
input resistance for a given clock frequency.
This input resistance will form a voltage divider with the
source impedance (RSource). Since RIN is inversely proportional to the cutoff frequency, operation at higher cutoff frequencies will be more likely to attenuate the input signal
which would appear as an overall decrease in gain to the
output of the filter. Since the filter’s ideal gain is unity, the
overall gain is given by:
RIN e
where n is the order of the filter, Amin is the minimum stopband attenuation (in dB) desired at frequency fs, and Amax is
the passband ripple or attenuation (in dB) at cutoff frequency fb (Note 15). If the result of this equation is greater than
4, more than one LMF40 will be required.
The attenuation at any frequency can be found by the following equation:
Attn (f) e 10 log [1 a (100.1Amax b 1)(f/fb)2n]dB
(3)
where n e 4 for the LMF40.
2.1 A LOW-PASS DESIGN EXAMPLE
Suppose the amplitude response specification in Figure 6 is
given. Can the LMF40 be used? The order of the Butterworth approximation will have to be determined using (1):
RIN
RIN a RSource
If the LMF40-50 or the LMF40-100 were set up for a cutoff
frequency of 10 kHz the input impedance would be:
AV e
RIN e
1 pA
e 10 mV
1 pF (100 Hz)
The propagation delay in the logic and the settling time required to acquire a new voltage level on the capacitors limit
the filter’s accuracy at high clock frequencies. The amplitude characteristic on g 5V supplies will typically stay flat
until fCLK exceeds 1.5 MHz and then peak at about 0.1 dB
at the corner frequency with a 2 MHz clock. As supply voltage drops to g 2.5V, a shift in the fCLK/fc ratio occurs which
will become noticeable when the clock frequency exceeds
500 kHz. The response of the LMF40 is still a good approximation of the ideal Butterworth low-pass characteristic
shown in Figure 5 .
(where T equals one clock period) or
RIN e
1 MX
e 0.99009 or b 0.086 dB
10 kX a 1 MX
Amin e 18 dB, Amax e 1.0 dB, fs e 2 kHz, and fb e 1 kHz
log[(101.8 b 1)/(100.1 b 1)]
e 3.95
2 log(2)
Since n can only take on integer values, n e 4. Therefore
the LMF40 can be used. In general, if n is 4 or less a single
LMF40 can be utilized.
ne
1 c 1010
e 1 MX
10 kHz
9
2.0 Designing with the LMF40 (Continued)
Likewise, the attenuation at fs can be found using (3) with
the above values and n e 4:
Attn (2 kHz) e 10 log[1 a 100.1 b 1) (2 kHz/1 kHz)8]
Equation (4) will determine whether the order of the filter is
adequate (n s 4) while equation (5) can determine the actual stopband attenuation and cutoff frequency (fc) necessary
to obtain the desired frequency response. The design procedure would be identical to the one shown in Section 2.0.
e 18.28 dB
This result also meets the design specification given in Figure 6 again verifying that a single LMF40 section will be
adequate.
Since the LMF40’s cutoff frequency (fc), which corresponds
to a gain attenuation of b3.01 dB, was not specified in this
example, it needs to be calculated. Solving equation (3)
where f e fc as follows:
e
100.1(3.01 dB) b 1 1/(2n)
0.1Amax b 1)
Ð (10
10
1 kHz
Ð 10
fc e fb
2.3 CHANGING CLOCK FREQUENCY
INSTANTANEOUSLY
The LMF40 responds well to an instantaneous change in
clock frequency. If the control signal in Figure 9 is low the
LMF40-50 has a 100 kHz clock making fc e 2 kHz; when
this signal goes high the clock frequency changes to 50 kHz
yielding fc e 1 kHz. As Figure 9 illustrates, the output signal
changes quickly and smoothly in response to a sudden
change in clock frequency.
The step response of the LMF40 in Figure 10 is dependent
on fc. The LMF40 responds as a classical fourth-order Butterworth low-pass filter.
e 1.184 kHz
(
0.301 b 1
1/8
0.1 b 1
(
2.4 ALIASING CONSIDERATIONS
Aliasing effects have to be considered when input signal
frequencies exceed half the sampling rate. For the LMF40
this equals half the clock frequency (fCLK). When the input
signal contains a component at a frequency higher than half
the clock frequency fCLK/2, as in Figure 11a , that component will be ‘‘reflected’’ about fCLK/2 into the frequency
range below fCLK/2, as in Figure 11b . If this component is
within the passband of the filter and of large enough amplitude it can cause problems. Therefore, if frequency components in the input signal exceed fCLK/2 they must be attenuated before being applied to the LMF40 input. The necessary amount of attenuation will vary depending on system
requirements. In critical applications the signal components
above fCLK/2 will have to be attenuated at least to the filter’s residual noise level.
where fc e fCLK /50 or fCLK/100. To implement this example for the LMF40-50 the clock frequency will have to be set
to fCLK e 50(1.184 kHz) e 59.2 kHz, or for the LMF40-100,
fCLK e 100 (1.184 kHz) e 118.4 kHz.
2.2 CASCADING LMF40s
When a steeper stopband attenuation rate is required, two
LMF40s can be cascaded (Figure 7) yielding an 8th order
slope of 48 dB per octave. Because the LMF40 is a Butterworth filter and therefore has no ripple in its passband,
when LMF40s are cascaded the resulting filter also has no
ripple in its passband. Likewise the DC and passband gains
will remain at 1V/V. The resulting response is shown in Figure 8a .
In determining whether the cascaded LMF40s will yield a
filter that will meet a particular amplitude response specification, as above, equations (4) and (5) can be used, shown
below.
ne
log[(10,0.05Amin b 1)/(100.05Amax b 1)]
2 log(fs/fb)
Attn (f) e 10 log [1 a (100.05Amax b 1) (f/fb)2]dB
where n e 4 (the order of each filter).
(4)
(5)
fe
RC In
Ð#
1
VCC b Vt b
VCC b Vt a
1
fj
1.37 RC
(VCC e 10V)
TL/H/10557 – 7
FIGURE 1. Schmitt Trigger R/C Oscillator
10
J#V J(
Vt a
tb
2.0 Designing with the LMF40 (Continued)
VIH t 0.8 VCC
VIL s 0.2 VCC
VCC e V a b Vb
TL/H/10557 – 8
TL/H/10557 – 9
(a)
(b)
FIGURE 2. Split Supply Operation with CMOS Level Clock (a), and TTL Level Clock (b)
TL/H/10557 – 10
FIGURE 3. Single Supply Operation. AGND Resistor Biased to V a /2
TL/H/10557 – 11
TL/H/10557 – 12
a) Equivalent Circuit for LMF40 Filter Input
b) Actual Circuit for LMF40 Filter Input
FIGURE 4. LMF40 Filter Input
11
2.0 Designing with the LMF40 (Continued)
TL/H/10557–13
FIGURE 5a. LMF40-100 Amplitude
Response with g 5V Supplies
TL/H/10557 – 14
FIGURE 5b. LMF40-50 Amplitude
Response with g 5V Supplies
TL/H/10557 – 15
FIGURE 5c. LMF40-100 Amplitude
Response with g 2.5V Supplies
TL/H/10557 – 16
FIGURE 5d. LMF40-50 Amplitude
Response with g 2.5V Supplies
TL/H/10557 – 17
FIGURE 6. Design Example Magnitude Response
Specification. The response of the filter design
must fall within the shaded area of the specification.
12
2.0 Designing with the LMF40 (Continued)
TL/H/10557 – 18
FIGURE 7. Cascading Two LMF40s
TL/H/10557 – 19
FIGURE 8a. One LMF40-50
vs Two LMF40-50s Cascaded
FIGURE 8b. Phase Response
of Two Cascaded LMF40-50s
TL/H/10557 – 21
TL/H/10557 – 20
FIGURE 10. LMF40-50 Input Step Response
FIGURE 9. LMF40-50 Abrupt Clock Frequency Change
13
2.0 Designing with the LMF40 (Continued)
TL/H/10557–22
TL/H/10557 – 23
(a) Input Signal Spectrum
(b)Output Signal Spectrum. Note that the input signal at
fs/2 a f causes an output signal to appear at fs/2 b f.
FIGURE 11. The phenomenon of aliasing in sampled-data systems. An input signal whose
frequency is greater than one-half the sampling frequency will cause an output to appear
at a frequency lower than one-half the sampling frequency. In the LMF40, fs e fCLK.
14
Physical Dimensions inches (millimeters)
Order Number LMF40CMJ-50 or LMF40CMJ-100
NS Package Number J08A
Order Number LMF40CIWM-50 or LMF40CIWM-100
NS Package Number M14B
15
LMF40 High Performance 4th-Order Switched-Capacitor
Butterworth Low-Pass Filter
Physical Dimensions inches (millimeters) (Continued)
Order Number LMF40CIN-50, or LMF40CIN-100
NS Package Number N08E
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