ETC DS1806-10

DS1806
DS1806
Digital Sextet Potentiometer
FEATURES
PIN ASSIGNMENT
• Six digitally controlled 64–position potentiometers
• 3–Wire Serial Port provides for reading and setting
each potentiometer
• Devices can be cascaded for single processor multi–
device control
• Standard Resistance Values
– DS1806–010 – 10K ohm
– DS1806–050 – 50K ohm
– DS1806–100 – 100K ohm
• Temperature:
W1
1
20
VCC
W2
2
19
H1
L1-3
3
18
H2
W3
4
17
H3
W4
5
16
H4
L4-6
6
15
H5
W6
7
14
W5
RST
8
13
H6
CLK
9
12
DIN
GND
10
11
COUT
DS1806 20–PIN DIP (300 MIL)
DS1806S 20–PIN SOIC (300 MIL)
DS1806E 20–PIN TSSOP (173 MIL)
See Mech. Drawings
Section
– Industrial: –40°C to +85° C
PIN DESCRIPTION
VCC
RST
DIN
CLK
COUT
H1 – H6
W1 – W6
GND
L1–3
L4–6
–
–
–
–
–
–
–
–
–
–
3V or 5V Supply
Serial Port Reset Input
Serial Port Data Input
Serial Port Clock Input
Cascade Data Output
High End Terminal of Pot
Wiper Terminal of Pot
Ground
Low Terminal Pots 1 thru 3
Low Terminal Pots 4 thru 6
DESCRIPTION
The DS1806 is a six–channel digitally controlled solid–
state linear potentiometer. Each potentiometer is comprised of 63 equiresistive sections as illustrated in the
block diagram of Figure 1. Each potentiometer has
three terminals accessible to the user. These include
the high side terminals, HX, the wiper terminals, WX, and
the low–end terminals, L1–3 and L4–6. Potentiometers
1 through 3 share the same low–end terminal L1–3. And
likewise, potentiometers 4 through 6 share the low–end
terminal L4–6.
Each wiper’s position is selected via an 8–bit register
value. Communication and control of the device is ac-
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
complished via a 3–wire serial port interface. This interface in conjunction with a cascade output allows the value of the device wiper settings to be read.
For multiple device and single processor environments,
the DS1806 can be cascaded or daisy chained. This
feature allows a single processor to control multiple devices.
The DS1806 is available in 10K, 50K and 100K ohm versions and is specified over the industrial temperature
range. Packages for the device include 20–lead DIPs,
SOICs, and TSSOPs.
062097 1/8
DS1806
OPERATION
A block diagram of the device is provided in Figure 1. As
shown, the DS1806 contains six 64–position potentiometers whose wiper positions are set by an 8–bit value.
The DS1806 contains a 48–bit I/O shift register which is
used to store the respective wiper position data for each
of the six potentiometers.
Each potentiometer has three terminals accessible to
the user. These include the high side terminals, HX, the
wiper terminals, WX, and the low–end terminals, L1–3
and L4–6. Potentiometers 1 through 3 share the same
low–end terminal L1–3. And likewise, potentiometers 4
through 6 share the low–end terminal L4–6.
Control of the DS1806 is accomplished via a 3–wire serial communication interface which allows the user to
set the wiper position value for each potentiometer. The
3–wire serial interface consists of the control signals
RST, DIN, and CLK. On power–up, the wiper positions of
each potentiometer are set to the low–end terminal LX
(00000000).
The RST control signal is used to enable 3–wire serial
port operation. The RST signal (3–wire serial port) is active when in a high state. Any communication intended
to change wiper settings must begin with the transition
of the RST from the low–state to the high–state.
The CLK signal input is used to provide timing synchronization for data input and output. Wiper position data is
loaded into the DS1806 through the DIN input terminal.
This data is shifted one bit at a time into the 48–bit I/O
shift register of the part, LSB first. Figure 3 provides an
illustration of the 48–bit shift register.
Figure 4 provides 3–wire serial port protocol and timing
diagrams. As shown, the 3–wire port is inactive when
the RST signal input is low. Once RST has transitioned
from the low to the high state, the serial port becomes
062097 2/8
active. When active, data is loaded into the I/O shift register on the low–to–high transition of the CLK.
Data is transmitted in order of LSB first. Potentiometers
are designated from 1 through 6 and the value for potentiometer–1 will be the first data entered into the shift register, followed by that of potentiometer–2 and so forth.
Each wiper has an 8–bit register which is used for setting the position of the wiper on the resistor array. Because the DS1806 is a 64–position potentiometer, only
six bits of information are needed to set wiper position.
The remaining two bits of information are used to provide a “don’t change” feature. Wiper position is controlled by bit positions 0 through 5 of each register. The
“don’t change” feature is controlled by bits 6 and 7 of
each register. When bits 6 and 7 have value “11 xxxxxx”,
wiper position will not change regardless of the states of
bits 0 through 5. If bits 6 and 7 are set to any other value,
bits 0 through 5 will be used as the new wiper position.
The “don’t change” feature allows the user to change
the value of any potentiometer of the DS1806 without affecting or having to remember the remaining positions
of the potentiometer wipers. Figure 2 provides the format for a wiper’s register.
Wiper placement for each potentiometer is such that
position–63 corresponds to the HX terminal of the device while position–0 corresponds to the ground terminal. For example, to set a potentiometer’s wiper position
to 15 (decimal), the binary value shifted into the wiper
register should be 00001111. This will place the wiper
tap at the 15th step above the low end terminal, LX.
All communication transactions should provide the total
48 bits of information when writing or reading from the
part. This is especially true for applications using all six
potentiometers. If a complete set of 48 bits is not transmitted to the part, undesired wiper position settings may
occur.
DS1806
DS1806 BLOCK DIAGRAM Figure 1
POTENTIOMETER–6
H6
W6
POTENTIOMETER–5
....
H5
W5
POTENTIOMETER–1
....
64–TO–1 MULTIPLEXER
H1
W1
....
64–TO–1 MULTIPLEXER
64–TO–1 MULTIPLEXER
L46
L13
WIPER–6 (8 BITS)
WIPER–5 (8–BITS)
WIPER–1 (8–BITS)
48–BIT SHIFT REGISTER
COUT
DIN
RST
CONTROL LOGIC
CLK
3–WIRE SERIAL
INTERFACE
WIPER REGISTER CONFIGURATION Figure 2
LOAD/NO LOAD
BIT 7
BIT 6
WIPER POSITION VALUE
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MSB
LSB
Bits 6 and 7 Functionality
11 –
10 –
01 –
00 –
Do not load wiper value
Load wiper value
Load wiper value
Load wiper value
48–BIT I/O SHIFT REGISTER Figure 3
B0
LSB
POT 1
B7
B0
MSB
LSB
POT 2
B7
B0
MSB LSB
POT 3
B7
B0
MSB
LSB
POT 4
B7
B0
MSB LSB
POT 5
B7
B0
MSB
LSB
POT 6
B7
MSB
Data entered LSB first, starting with potentiometer–1.
062097 3/8
DS1806
3–WIRE SERIAL PORT TIMING Figure 4
tRLT
RST
tCC
tCH
tHLT
• ••
CLK
tDC
tCDH
• ••
DIN
LSB
POT 1
COUT
CASCADE OPERATION
A feature of the DS1806 is the ability to control multiple
devices from a single processor. Multiple DS1806s can
be linked or daisy chained as shown in Figure 5. As a
data bit is entered into the I/O shift register of the
DS1806, a bit will appear at the COUT terminal before a
maximum delay of 50 nanoseconds. The LSB of potentiometer–1 will always be the first out of the part at the
beginning of a transaction. Additionally, the COUT terminal is always active regardless of the state RST. However, DIN and CLK inputs are ignored when RST is in the
low state.
The COUT output of the DS1806 can be used to drive the
DIN input of another DS1806. When cascading multiple
devices, the total number of bits transmitted is always
48 multiplied by the total number of DS1806s being cascaded.
An optional feedback resistor can be placed between
the COUT terminal of the last device and the first DS1806
DIN input, which allows the controlling processor to
read, as well as, write data, or circularly clock data
through the daisy chain. The value of the feedback or
isolation resistor should be in the range from 1KΩ to
10KΩ.
To read data, the reading device configures itself as an
input and monitors the state of the DIN line, which is driven by COUT through the isolation resistor. When RST is
driven high, bit 48 is present on the COUT pin, which is
fed back to the input DIN pin through the isolation resistor. When the CLK input transitions low to high, bit 48 is
062097 4/8
• ••
loaded into the first position of the I/O shift register and
bit 47 becomes present on COUT and DIN of the next device. After 48 bits (or 48 times the number of the
DS1806s in the daisy chain), the data has shifted completely around and back to its original position. When
RST transitions to the low state to end data transfer, the
value (the same as before the read occurred) is loaded
in the shift register.
ABSOLUTE AND RELATIVE LINEARITY
Absolute linearity is defined as the difference between
the actual measured output voltage and the expected
output voltage. Absolute linearity is given in terms of a
minimum increment or expected output when the wiper
is moved one position. The DS1806 is specified to have
an absolute linearity of ±0.50 LSB.
Relative linearity is a measure of error between two adjacent wiper position points. The DS1806 is specified to
have a relative linearity of ±0.25 LSB.
TYPICAL APPLICATION CONFIGURATIONS
Figure 6 shows the typical application configuration of
the DS1806 as a fixed gain attenuator. In this configuration, the DS1806 adjusts the attenuation level of the incoming signal. Variations in wiper resistance are minimized by connecting the wiper terminal of the part to a
high impedance load. Depending on voltage across the
wiper, its resistance may vary from 400 ohms to
1000 ohms. Note that the resistance R1 in Figure 6
should be chosen to be much greater than the wiper resistance RW.
DS1806
CASCADING MULTIPLE DEVICES Figure 5
DIN
DIN
DS1806
DIN
DS1806
#1
#2
COUT
DS1806
COUT
#n
COUT
ISOLATION RESISTOR
FOR READING REGISTER DATA
1KΩ–10KΩ
FIXED GAIN ATTENUATOR Figure 6
Hx
DS1806
Wx
+
–
RF
Lx
R1
062097 5/8
DS1806
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
–0.5V to +7.0V
–40°C to +85°C; industrial
–55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
Supply Voltage
VCC
+2.7
(-40°C to +85°C)
TYP
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
MAX
UNITS
NOTES
5.5
V
1
(–40°C to +85°C; VCC = 2.7 to 5.5V)
MIN
TYP
MAX
UNITS
1.3
2
mA
+1
µA
1000
Ω
1
mA
NOTES
Supply Current Active
ICC
Input Leakage
IIL
Wiper Resistance
RW
Wiper Current
IW
Input Logic 1
VIH
2.0
VCC+0.5
V
1
Input Logic 0
VIL
–0.5
+0.8
V
1, 6
–1
400
+0.6
Logic 1 Output @ 2.4 Volts
IOH
Logic 0 Output @ 0.4 Volt
IOL
Standby Current:
3 Volts
5 Volts
Resistor Inputs
–1
12
20
ISTBY
HX, LX,
WX
mA
GND –0.5
ANALOG RESISTOR CHARACTERISTICS
PARAMETER
SYMBOL
4
mA
6
40
µA
µA
9
VCC +0.5
µA
2
(–40°C to +85°C; VCC = 2.7 to 5.5V)
MIN
TYP
MAX
UNITS
NOTES
End–to–End Resistor Tolerance
–20
+20
%
Absolute Linearity
–0.5
+0.5
LSB
7
Relative Linearity
–0.25
+0.25
LSB
8
Hz
4
–3 dB Cutoff Frequency
Temperature Coefficient
062097 6/8
Icutoff
650
PPM/°C
DS1806
CAPACITANCE
PARAMETER
(tA = 25°C)
SYMBOL
Input Capacitance
Output Capacitance
MIN
TYP
MAX
UNITS
NOTES
CIN
5
pF
3
COUT
7
pF
3
AC ELECTRICAL CHARACTERISTICS
PARAMETER
(-40°C to +85°C; VCC = 2.7 to 5.5V)
SYMBOL
MIN
Clock Frequency
fCLK
DC
Width of CLK Pulse
tCH
Data Setup Time
TYP
MAX
UNITS
NOTES
10
MHZ
5
50
ns
5
tDC
30
ns
5
Data Hold Time
tCDH
0
ns
5
Propagation Delay Time Low to
High Level Clock to Output
tPLH
ns
5
RST High to Clock Input High
tCC
50
ns
5
RST Low from lock Input High
tHLT
50
ns
5
RST Inactive
tRLT
125
ns
5
CLK Rise Time, CLK Fall Time
tCR
ns
5
50
50
NOTES:
1. All voltages are referenced to ground.
2. Resistor inputs cannot go below GND by more than 0.5 volts or above VCC by 0.5 volts in the positive direction.
3. Capacitance values apply at 25°C.
4. –3 dB cutoff frequency characteristics for the DS1806 depend on potentiometer total resistance: DS1806–010;
1 MHz; DS1806–050; 200 KHz, DS1806–100; 100 KHz.
5. See Figure 4.
6. For VCC = 5V ± 10% maximum VIL = +0.8V. For VCC = 3.0 ± 10% VIL = +0.6V.
7. Absolute Linearity is to used measure expected wiper voltage versus measured wiper voltage as determined by
wiper position. The DS1806 is specified to provide an Absolute Linearity of +0.5 LSB.
8. Relative Linearity is used to determine the change in wiper voltage between two adjacent wiper positions. The
DS1806 is specified to provide a relative linearity of +0.25 LSB.
9. Standby current levels apply when all inputs are driven to appropriate supply levels.
062097 7/8
DS1806
DS1806 ORDERING INFORMATION
ORDERING NUMBER
PACKAGE
OPERATING
TEMPERATURE
VERSION
DS1806–010
20L DIP
–40°C TO +85°C
10KΩ
DS1806–050
20L DIP
–40°C TO +85°C
50KΩ
DS1806–100
20L DIP
–40°C TO +85°C
100KΩ
DS1806E–010
20L TSSOP (173 MIL)
–40°C TO +85°C
10KΩ
DS1806E–050
20L TSSOP (173 MIL)
–40°C TO +85°C
50KΩ
DS1806E–100
20L TSSOP (173 MIL)
–40°C TO +85°C
100KΩ
DS1806S–010
20L SOIC (300 MIL)
–40°C TO +85°C
10KΩ
DS1806S–050
20L SOIC (300 MIL)
–40°C TO +85°C
50KΩ
DS1806S–100
20L SOIC (300 MIL)
–40°C TO +85°C
100KΩ
062097 8/8