EM78447S
MASK ROM
1. GENERAL DESCRIPTION
EM78447S is an 8-bit microprocessor with low-power and high-speed CMOS technology. Integrated into
a single chip are on-chip watchdog timer (WDT), RAM, ROM, real time clock/counter, external and
interrupt, power down mode, and tri-state I/O.
This specification is subject to change without prior notice.
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2002/03/01
EM78447S
MASK ROM
2. FEATURES
• Operating voltage range: 2.3V~5.5V.
• Operating in temperature range: 0°C~70°C.
• Operating frequency range ( base on 2 clocks)
* Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V.
* RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V.
• Low power consumption:
* Less then 2.2 mA at 5V/4MHz
* Typically 30 µA at 3V/32KHz
* Typically 1 µA during sleep mode
• 4K × 13 bits on chip ROM
• One configuration register to accommodate user’s requirements
• 148× 8 bits on chip registers (SRAM, general purpose register)
• 3 bi-directional I/O ports
• 5 level stacks for subroutine nesting
• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt
• Two clocks per instruction cycle
• Power down (SLEEP) mode
• Two available interruptions
* TCC overflow interrupt
* External interrupt
• Programmable free running watchdog timer
• 10 programmable pull-high pins
• 2 programmable open-drain pins
• 2 programmable R-option pins
• Package types:
* 28 pin DIP 600mil
:EM78447SAP
* 28 pin SOP(SOIC) 300mil :EM78447SAM
* 28 pin SSOP 209mil
:EM78447SAS
* 32 pin DIP 300mil
:EM78447SBP
* 32 pin SOP(SOIC) 450mil :EM78447SBWM
This specification is subject to change without prior notice.
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2002/03/01
EM78447S
MASK ROM
• 99.9% single instruction cycle commands
• The transient point of system frequency between HXT and LXT is around 400KHz
This specification is subject to change without prior notice.
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2002/03/01
EM78447S
MASK ROM
3. PIN ASSIGNMENT
EM78447SAP
EM78447SAM
EM78447SAS
TCC
1
28
/RESET
VDD
2
27
NC
3
26
VSS
4
/INT
P50
EM78447SBP
EM78447SBWM
VSS
1
28
/RESET
P55
1
32
P56
OSCI
TCC
2
27
OSCO
VDD
3
26
OSCI
P54
2
31
P57
OSCO
TCC
3
30
25
P77
/INT
4
/RESET
25
P77
VDD
4
29
OSCI
5
24
P76
P50
6
23
P75
P51
5
24
P76
NC
5
28
OSCO
6
23
P75
VSS
6
27
P77
P51
7
22
P74
P52
8
21
P73
P52
7
22
P74
/INT
7
26
P76
P53
8
21
P73
P50
8
25
P53
9
20
P75
P72
P60
9
20
P72
P51
9
24
P60
10
P74
19
P71
P61
10
19
P71
P52
10
23
P73
P61
P62
11
18
P70
P62
11
18
P70
P53
11
22
P72
12
17
P67
P63
12
17
P67
P60
12
21
P71
P63
13
16
P66
P64
13
16
P66
P61
13
20
P70
P64
14
15
P65
VSS
14
15
P65
P62
14
19
P67
P63
15
18
P66
P64
16
17
P65
DIP
SOP
SOIC
SSOP
DIP
SOP
SOIC
Fig. 1 Pin assignment
Table 1 EM78447SAP and EM78447SAM Pin Description
Symbol
VDD
Pin No.
2
Type
-
OSCI
27
I
OSCO
26
I/O
TCC
1
I
/RESET
28
I
P50~P53
6~9
I/O
P60~P67 10~17
I/O
P70~P77 18~25
I/O
Function
* Power supply.
* XTAL type: Crystal input terminal or external clock input pin.
* RC type: RC oscillator input pin.
* XTAL type: Output terminal for crystal oscillator or external clock input
pin.
* RC type: Instruction clock output.
* External clock signal input.
* The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
* P50~P53 are bi-directional I/O pins.
* P60~P67 are bi-directional I/O pins. These can be pulled-high internally
by software control.
* P70~P77 are bi-directional I/O pins.
* P74~P75 can be pulled-high internally by software control.
* P76~P77 can have open-drain output by software control.
* P70 and P71 can also be defined as the R-option pins.
This specification is subject to change without prior notice.
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2002/03/01
EM78447S
MASK ROM
/INT
VSS
NC
5
4
3
I
-
* External interrupt pin triggered by falling edge.
* Ground.
* No connection.
Table 2 EM78447SAS Pin Description
Symbol
VDD
Pin No.
3
Type
-
OSCI
27
I
OSCO
26
I/O
TCC
2
I
/RESET
28
I
P50~P53
5~8
9~13,
P60~P67
15~17
P70~P77 18~25
/INT
VSS
4
1,14
I/O
I/O
I/O
I
-
Function
* Power supply.
* XTAL type: Crystal input terminal or external clock input pin.
* RC type: RC oscillator input pin.
* XTAL type: Output terminal for crystal oscillator or external clock input
pin.
* RC type: Instruction clock output.
* External clock signal input.
* The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
* P50~P53 are bi-directional I/O pins.
* P60~P67 are bi-directional I/O pins. These can be pulled-high internally
by software control.
* P70~P77 are bi-directional I/O pins.
* P74~P75 can be pulled-high internally by software control.
* P76~P77 can have open-drain output by software control.
* P70 and P71 can also be defined as the R-option pins.
* External interrupt pin triggered by falling edge.
* Ground.
Table 3 EM78447SBP and EM78447SBWM Pin Description
Symbol
VDD
Pin No.
4
Type
-
OSCI
29
I
OSCO
28
I/O
TCC
3
I
/RESET
30
I
P50~P57
8~11,2~1,
32~31
I/O
P60~P67
12~19
I/O
P70~P77
20~27
I/O
7
6
5
I
-
/INT
VSS
NC
Function
* Power supply.
* XTAL type: Crystal input terminal or external clock input pin.
* RC type: RC oscillator input pin.
* XTAL type: Output terminal for crystal oscillator or external clock input
pin.
* RC type: Instruction clock output.
* External clock signal input.
* The real time clock/counter (with Schmitt trigger input pin), must be tied
to VDD or VSS if not in use.
* Input pin with Schmitt trigger. If this pin remains at logic low, the
controller will also remain in reset condition.
* P50~P57 are bi-directional I/O pins.
* P60~P67 are bi-directional I/O pins. These can be pulled-high internally
by software control.
* P70~P77 are bi-directional I/O pins.
* P74~P75 can be pulled -high internally by software control.
* P76~P77 can have open-drain output by software control.
* P70 and P71 can also be defined as the R-option pins.
* External interrupt pin triggered by falling edge.
* Ground.
* No connection.
This specification is subject to change without prior notice.
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2002/03/01
EM78447S
MASK ROM
4. FUNCTION DESCRIPTION
OSCI
OSCO
/RESET
TCC
/INT
WDT Timer
STACK 1
P C
Oscillator/Timing
STACK 2
Control
STACK 3
Prescale
STACK 4
ROM
r
STACK 5
WDT
T i m-e o u t
Interrupt
Control
R1(TCC)
Sleep
&
Wake-up
Control
Instruction
Register
ALU
Instruction
Decoder
RAM
R3
ACC
R4
DATA & CONTROL BUS
IOC5
R5
IOC6
R6
P PPPP PPP
5 5555 555
0 123 4567
P PPPP PPP
6 6666 666
0 123 4567
IOC7
R7
PPP PPPP P
777 7777 7
0 1 2 3 45 6 7
Fig. 2 Functional block diagram
4.1 Operational Registers
1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is as indirect addressing pointer. Any
instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4).
2. R1 (Time Clock /Counter)
• Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or
by the instruction cycle clock.
• Writable and readable as any other registers.
• Defined by resetting PAB (CONT-3).
• The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
This specification is subject to change without prior notice.
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EM78447S
MASK ROM
• The contents of the prescaler counter will be cleared only when TCC register is written with a value.
3. R2 (Program Counter) & Stack
• Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in
Fig.3.
• Generating 1024×13 bits on-chip ROM addresses to the relative programming instruction codes.
One program page is 1024 words long.
• R2 is set as all "0"s when under RESET condition.
• "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC
to go to any location within a page.
• "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus,
the subroutine entry address can be located anywhere within a page.
• "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level
stack.
• "ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits of
the PC are cleared.
• "MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the
ninth and tenth bits of the PC are cleared.
• Any instruction that writes to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will cause the ninth
and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256
locations of a page.
• All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would
change the contents of R2. Such instruction will need one more instruction cycle.
CALL
PC
A11A10
A9A8
A7
~
A0
RET
RETL
RETI
00
000
3FF
Stack
Stack
Stack
Stack
Stack
1
2
3
4
5
Page 0
001:Hareware in terrupt location
01
400
7FF
10
location
800
BFF
11
002:Software interrupt (INT instruction)
Page 1
C00
FFF
Page 2
FFF:Reset location
Page 3
Fig. 3 Program Counter Organization
This specification is subject to change without prior notice.
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2002/03/01
EM78447S
MASK ROM
4. R3 (Status Register)
7
GP
6
PS1
5
PS0
4
T
3
P
2
Z
1
DC
0
C
• Bit 0 (C) Carry flag
• Bit 1 (DC) Auxiliary carry flag
• Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
• Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a
"SLEP" command.
• Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" commands, or during power up and
reset to 0 by WDT timeout.
• Bits 5 (PS0) ~ 6 (PS1) Page select bits. PS0~PS1 are used to pre-select a program memory page.
When executing a "JMP", "CALL", or other instructions which causes the program counter to
change (e.g. MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter
where it selects one of the available program memory pages. Note that RET (RETL, RETI)
instruction does not change the PS0~PS1 bits. That is, the return will always be to the page from
where the subroutine was called, regardless of the current setting of PS0~PS1 bits.
PS1
0
0
1
1
PS0
0
1
0
1
Program memory page [Address]
Page 0 [000-3FF]
Page 1 [400-7FF]
Page 2 [800-BFF]
Page 3 [C00-FFF]
• Bit 7 (GP) General read/write bit.
5. R4 (RAM Select Register)
• Bits 0~5 are used to select the registers (address: 00~3F) in the indirect addressing mode.
• Bits 6~7 determine which bank is activated among the 4 banks.
• If no indirect addressing is used, the RSR is used as an 8-bit general-purposed read/writer register.
• See the configuration of the data memory in Fig. 4.
6. R5~R7 (Port 5 ~ Port7)
• R5, R6 and R7 are I/O registers
7. R8~R1F and R20~R3E (General-Purpose Register)
• R8~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
8. R3F (Interrupt Status Register)
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
EXIF
Bit 2
-
Bit 1
-
Bit 0
TCIF
• Bit 0 (TCIF) TCC overflow interrupt flag. Set as TCC overflows; flag cleared by software.
This specification is subject to change without prior notice.
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2002/03/01
EM78447S
MASK ROM
• Bit 3(EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by software
• Bits 1,2,4~7 are not used and read as “0”.
• "1" means interrupt request, "0" means non-interrupt.
• R3F can be cleared by instruction, but cannot be set by instruction.
• IOCF is the interrupt mask register.
• Note that to read R3F will obtain the result of "logic AND" of R3F and IOCF.
00
01
R0
R1(TCC)
02
03
04
R2(PC)
05
06
07
08
09
R5(Port5)
R6(Port6)
R7(Port7)
R8
R9
0A
0B
0C
0D
0E
0F
RA
RB
RC
RD
RE
RF
10
:
:
Stack
(5 level)
R3(Status)
R4(RSR)
IOC5
IOC6
IOC7
IOCB
IOCE
IOCF
16x8
Common
Register
1F
00
20
:
:
31x8
Bank
Register
(Bank 0)
01
10
31x8
Bank
Register
(Bank 1)
31x8
Bank
Register
(Bank 2)
11
31x8
Bank
Register
(Bank 3)
3E
3F
R3F
Fig. 4 Data Memory Configuration
This specification is subject to change without prior notice.
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EM78447S
MASK ROM
9. R20~R3E (General-Purpose Register)
• RA~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
10. R3F (Interrupt Status Register)
7
-
6
-
5
-
4
-
3
EXIF
2
-
1
0
TCIF
“1” means interrupt request, and “0” means no interrupt occur.
• Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software.
• Bit 3 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.
• Bits 1, 2 and 3 ~ 7 Not used.
• R3F can be cleared by instruction but cannot be set.
• IOCF is the interrupt mask register.
• Note that the result of reading R3F is the "logic AND" of R3F and IOCF.
4.2 Special Purpose Registers
1. A (Accumulator)
• Internal data transfer, or instruction operand holding.
• It can not be addressed.
2. CONT (Control Register)
7
/PHEN
6
/INT
5
TS
4
TE
3
PAB
2
PSR2
1
PSR1
0
PSR0
• Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2
0
0
0
0
1
1
1
1
PSR1
0
0
1
1
0
0
1
1
PSR0
0
1
0
1
0
1
0
1
TCC Rate
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
WDT Rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
• Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
• Bit 4 (TE) TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
This specification is subject to change without prior notice.
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EM78447S
MASK ROM
• Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
• Bit 6 (/INT) Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
• Bit 7 (/PHEN) Control bit used to enable the pull-high of P60~P67, P74 and P75 pins
0: Enable internal pull-high.
1: Disable internal pull-high.
• CONT register is both readable and writable.
3. IOC5 ~ IOC7 (I/O Port Control Register)
• "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.
• IOC5 and IOC7 registers are both readable and writable.
4. IOCB (Wake-up Control Register for Port 6)
7
/WUE7
6
/WUE6
5
/WUE5
4
/WUE4
3
/WUE3
2
/WUE2
1
/WUE1
0
/WUE0
• Bit 0 (/WUE0) Control bit used to enable the wake-up function of P60 pin.
0: Enable internal wake-up.
1: Disable internal wake-up.
• Bit 1 (/WUE1) Control bit is used to enable the wake-up function of P61 pin.
• Bit 2 (/WUE2) Control bit is used to enable the wake-up function of P62 pin.
• Bit 3 (/WUE3) Control bit is used to enable the wake-up function of P63 pin.
• Bit 4 (/WUE4) Control bit is used to enable the wake-up function of P64 pin.
• Bit 5 (/WUE5) Control bit is used to enable the wake-up function of P65 pin.
• Bit 6 (/WUE6) Control bit is used to enable the wake-up function of P66 pin.
• Bit 7 (/WUE7) Control bit is used to enable the wake-up function of P67 pin.
• IOCB Register is both readable and writable.
6. IOCE (WDT Control Register)
7
-
6
ODE
5
WDTE
4
SLPC
3
ROC
2
-
1
-
0
/WUE
• Bit 0 (/WUE) Control bit used to enable the wake-up function of P74 and P75.
0: Enable the wake-up function.
1: Disable the wake-up function.
The /WUE bit can be read and written.
This specification is subject to change without prior notice.
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EM78447S
MASK ROM
• Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of R-option pins
(P70, P71) to be read by the controller. Clearing ROC will disable the R-option function. Otherwise,
the R-option function is introduced. Users must connect the P71 pin or/and P70 pin to VSS by a
560KΩ external resistor (Rex). If Rex is connected/disconnected with VDD, the status of P70 (P71)
will be read as "0"/"1" (refer to Fig. 7(b)). The ROC bit can be read and written.
• Bit 4 (SLPC) This bit is set by hardware at the falling edge of wake-up signal and is cleared in
software. SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator is
stopped, and the controller enters the SLEEP2 mode) on the high-to-low transition and is enabled
(the controller is awakened from SLEEP2 mode) on low-to-high transition. In order to ensure the
stable output of the oscillator, once the oscillator is enabled again, there is a delay for approximately
18 1 ms (oscillator start-up timer (OST)) before the next program instruction is executed. The OST is
always activated by wake-up from sleep mode whether the Code Option bit ENWDT is "0" or not.
After waking up, the WDT is enabled if Code Option ENWDT is "1". The block diagram of SLEEP2
mode and wake-up caused by input triggered is depicted in Fig. 5. The SLPC bit can be read and
written.
• Bit 5 (WDTE) Control bit used to enable Watchdog timer.
The WDTE bit can be used only if ENWDT, the CODE Option bit, is "0". If the ENWDT bit is "0", then
WDT can be disabled/enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is "1". That is, if the ENWDT bit
is "1", WDT is always disabled no matter what the WDTE bit status is.
The WDTE bit can be read and written.
• Bit 6 (ODE) Control bit used to enable the open-drain of P76 and P77 pins
0: Disable open-drain output.
1: Enable open-drain output.
The ODE bit can be read and written.
• Bits 1~2, and 7 Not used.
7. IOCF (Interrupt Mask Register)
7
-
1
6
-
5
-
4
-
3
EXIE
2
-
1
-
0
TCIE
NOTE: Vdd = 5V, set up time period = 16.2ms ± 5%
Vdd = 3V, set up time period = 19.6ms ± 5%
This specification is subject to change without prior notice.
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EM78447S
MASK ROM
• Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
• Bit 3 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
• Bits 1, 2 and 4~7 Not used.
• Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".
• Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig.
9.
• IOCF register is both readable and writable.
/WUE0
Oscillator
Enable
Disable
/WUE1
Reset
Q
Q
Clear
P D
R
CLK
C
L
VCC
Set
/WUE7
8
from S/W
P60~P67
VCC
/WUE
/PHEN
2
P74~P75
Fig. 5 Block Diagram of Sleep Mode and Wake-up Circuits on I/O Ports
This specification is subject to change without prior notice.
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2002/03/01
EM78447S
MASK ROM
4.3 TCC/WDT & Prescaler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available for either the
TCC or WDT only at any given time, and the PAB bit of CONT register is used to determine the
prescaler assignment. The PSR0~PSR2 bits determine the prescale ratio. The prescaler is cleared
each time the instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to
WDT mode, are cleared by the WDTC or SLEP instructions. Fig. 6 depicts the circuit diagram of
TCC/WDT.
• R1 (TCC) is an 8-bit timer/counter. The TCC clock source can be internal clock or external clock input
(edge selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at
every instruction cycle (without prescaler). Referring to Fig. 6 below, clock category (CLK=Fosc/2 or
CLK=Fosc/4) is dependent on the CODE Option bit CLKS status. CLK=Fosc/2 if CLKS bit is "0", and
CLK=Fosc/4 if CLKS bit is "1". If TCC signal source is from external clock input, TCC will increase by
1 at every falling edge or rising edge of TCC pin.
• The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after
the oscillator driver has been turned off (i.e., in sleep mode). During normal operation or sleep mode,
a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any
time during the normal mode by software programming. Refer to WDTE bit of IOCE register. Without
presacler, the WDT time-out period is approximately 18ms 1(default).
Data Bus
CLK(=Fosc/2)
0
TCC
Pin
1
1
M
U
X
0
TE
TS
0
WDT
1
M
U
X
SYNC
2 cycles
TCC overflow interrupt
PAB
M
U
X
8-bit Counter
8-to-1 MUX
WDTE
(in IOCE)
TCC(R1)
PSR0~PSR2
PAB
0
1
MUX
PAB
WDT timeuot
Fig. 6 Block Diagram of TCC and WDT
1
NOTE: Vdd = 5V, set up time period = 16.2ms ± 5%
Vdd = 3V, set up time period = 19.6ms ± 5%
This specification is subject to change without prior notice.
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EM78447S
MASK ROM
4.4 I/O Ports
The I/O registers, Port 5, Port 6, and Port 7, are bi-directional tri-state I/O ports. The functions; Pull-high,
R-option, and Open-drain can be internally done by CONT and IOCE respectively. Input status change
wake-up function is provided by Port 6, P74, and P75. Each I/O pin can be defined as "input" or "output"
pin by the I/O control registers (IOC5 ~ IOC7). The I/O registers and I/O control registers are both
readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are shown in the following
Figures. 7(a), (b) respectively.
PCRD
Q
PORT
0
1
P
R
D
PCWR
CLK
Q
C
L
Q
P
R
Q
C CLK
L
IOD
D
PDWR
M
U
X
PDRD
Fig. 7 (a) The I/O Port and I/O Control Register Circuit
PCRD
VCC
ROC
Q
Weakly
Pull- up
PORT
0
Rex*
1
P
R
D
CLK
Q
C
L
Q
P
R
Q
C CLK
L
PCWR
IOD
D
M
U
X
PDWR
PDRD
*The Rex is 560K ohm external resistor
Fig.7(b) The I/O Port with R-Option (P70, P71) Circuit
This specification is subject to change without prior notice.
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EM78447S
MASK ROM
4.5 RESET and Wake-up
1. RESET
A RESET can be invoked by
(1) Power on reset, or
(2) /RESET pin input “low”, or
(3) WDT timeout. (if enabled)
The device is kept in a RESET condition for a period of approx. 18ms 1 (one oscillator start-up timer
period) after the reset signal is detected. Once the RESET occurs, the following functions are
performed (refer to Fig.8).
• The oscillator is running, or initiated.
• The Program Counter (R2) is set to all "1".
• When power is switched on, Bits 5~6 of R3 and the upper 2 bits of R4 are cleared.
• All I/O port pins are configured as input mode (high-impedance state).
• The Watchdog timer and prescaler are cleared.
• On power on, Bits 5~6 of R3 are cleared.
• On power on, the upper 2 bits of R4 are cleared.
• The bits of CONT register are set to all "1," except for Bit 6 (INT flag).
• IOCB register is set to ”1” (disable P60 ~ P67 wake-up function).
• Bits 3 and 6 of IOCE register are cleared, and Bits 0, 4, and 5 are set to "1".
• Bits 0 and 3 of R3F register and Bits 0 and 3 of IOCF registers are cleared.
Executing the “SLEP” instruction (designated as SLEEP1 mode) achieves sleep mode. While
entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller can be
awakened by(1) External reset input on /RESET pin;
(2) WDT time-out (if enabled)
The above two cases will cause the EM78447S controller to reset. The T and P flags of R3 can be
used to determine the source of the reset (wake-up).
In addition to the basic SLEEP1 MODE, EM78447S has another sleep mode (set off by clearing
“SLPC” bit of IOCE register, designated as SLEEP2 MODE). In the SLEEP2 MODE, the controller
1
NOTE: Vdd = 5V, set up time period = 16.2ms ± 5%
Vdd = 3V, set up time period = 19.6ms ± 5%
This specification is subject to change without prior notice.
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EM78447S
MASK ROM
can be awakened by (A) Any one of the wake-up pins is set to “0.” (refer to Figure 5). Upon waking, the controller will
continue to execute the succeeding address. In this case, before entering SLEEP2 MODE, the
wake-up function of the trigger sources (P60~P67, and P74~P75) should be selected (e.g.,
input pin) and enabled (e.g., pull-high, wake-up control). One caution should be noted, after
waking up, the WDT is enabled if Code Option bit ENWDT is “0”. The WDT operation (to be
enabled or disabled) should be appropriately controlled by software after waking up.
(B) WDT time-out (if enabled) or external reset input on /RESET pin will cause a controller reset.
Table 4 The Summary of the Initialized Values for Registers
Address
Name
N/A
IOC5
N/A
IOC6
N/A
IOC7
N/A
CONT
0x00
R0(IAR)
0x01
R1(TCC)
0x02
R2(PC)
0x03
R3(SR)
0x04
R4(RSR)
0x05
R5(P5)
0x06
R6(P6)
0x07
R7(P7)
Reset Type
Bit Name
Type
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit 7
C57
A
B
0
1
0
1
0
P
C67
1
1
P
C77
1
1
P
/PHEN
1
1
P
U
P
P
0
0
P
Bit 6
C56
A
B
0
1
0
1
0
P
C66
1
1
P
C76
1
1
P
/INT
0
P
P
U
P
P
0
0
P
Bit 5
C55
A
B
0
1
0
1
0
P
C65
1
1
P
C75
1
1
P
TS
1
1
P
U
P
P
0
0
P
Bit 4
C54
A
B
0
1
0
1
0
P
C64
1
1
P
C74
1
1
P
TE
1
1
P
U
P
P
0
0
P
Bit 3
C53
1
1
P
C63
1
1
P
C73
1
1
P
PAB
1
1
P
U
P
P
0
0
P
Bit 2
C52
1
1
P
C62
1
1
P
C72
1
1
P
PSR2
1
1
P
U
P
P
0
0
P
Bit 1
C51
1
1
P
C61
1
1
P
C71
1
1
P
PSR1
1
1
P
U
P
P
0
0
P
Bit 0
C50
1
1
P
C60
1
1
P
C70
1
1
P
PSR0
1
1
P
U
P
P
0
0
P
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
1
1
**0/P
GP
0
0
P
RSR.1
0
0
P
P57
U
P
P
1
1
**0/P
PS1
0
0
P
RSR.0
0
0
P
P56
U
P
P
1
1
**0/P
PS0
0
0
P
U
P
P
P55
U
P
P
1
1
**0/P
T
1
t
t
U
P
P
P54
U
P
P
1
1
**0/P
P
1
t
t
U
P
P
P53
U
P
P
1
1
**0/P
Z
U
P
P
U
P
P
P52
U
P
P
1
1
**0/P
DC
U
P
P
U
P
P
P51
U
P
P
1
1
**0/P
C
U
P
P
U
P
P
P50
U
P
P
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
P67
U
P
P
P66
U
P
P
P65
U
P
P
P64
U
P
P
P63
U
P
P
P62
U
P
P
P61
U
P
P
P60
U
P
P
Bit Name
Power-On
/RESET and WDT
P77
U
P
P76
U
P
P75
U
P
P74
U
P
P73
U
P
P72
U
P
P71
U
P
P70
U
P
This specification is subject to change without prior notice.
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EM78447S
MASK ROM
0x3F
R3F(ISR)
0x0B
IOCB
0x0E
IOCE
0x0F
IOCF
0x08
R8
0x09~0x3E
R9~R3E
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
P
U
U
U
/WUE7
1
1
P
P
U
U
U
/WUE6
1
1
P
P
U
U
U
/WUE5
1
1
P
P
U
U
U
/WUE4
1
1
P
P
EXIF
0
0
P
/WUE3
1
1
P
Bit Name
-
ODE
WTE
SLPC
ROC
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
U
U
U
U
U
U
0
0
P
U
P
P
0
0
P
U
U
U
0
0
P
U
P
P
1
1
1
U
U
U
0
0
P
U
P
P
1
1
1
U
U
U
0
0
P
U
P
P
0
0
P
EXIE
0
0
P
0
0
P
U
P
P
P
U
U
U
/WUE2
1
1
P
P
U
U
U
/WUE1
1
1
P
P
TCIF
0
0
P
/WUE0
1
1
P
-
-
/WUE
U
U
U
U
U
U
0
0
P
U
P
P
U
U
U
U
U
U
0
0
P
U
P
P
1
1
P
TCIE
0
0
P
0
0
P
U
P
P
** To execute the next instruction after the ”SLPC” bit status of IOCE register is on high-to-low
transition.
X: Not used. U: Unknown or don’t care.
P: Previous value before reset.
t: Check Table 5
2. The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by one of the following events:
1. A power-on condition,
2. A high-low-high pulse on /RESET pin, and
3. Watchdog timer time-out.
The values of T and P, listed in Table 5 can be used to check how the processor wakes up.
Table 6 shows the events that may affect the status of T and P.
Table 5 The Values of RST, T, and P after RESET
Reset Type
Power on
/RESET during Operating mode
/RESET wake-up during SLEEP1 mode
/RESET wake-up during SLEEP2 mode
WDT during Operating mode
WDT wake-up during SLEEP1 mode
WDT wake-up during SLEEP2 mode
Wake-Up on pin change during SLEEP2 mode
T
1
*P
1
*P
0
0
0
*P
P
1
*P
0
*P
*P
0
*P
*P
*P: Previous status before reset
This specification is subject to change without prior notice.
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MASK ROM
Table 6 The Status of RST, T, and P that are Affected by Events
Event
T
1
1
0
1
*P
Power on
WDTC instruction
WDT time-out
SLEP instruction
Wake-Up on pin change during SLEEP2 mode
P
1
1
*P
0
*P
*P: Previous value before reset
VDD
D
CLK
Oscillator
Q
CLK
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT
WDT Timeout
Setup Time
RESET
/RESET
Fig. 8 Reset Block Diagram
4.6 Interrupt
The EM78447S has two interrupts as listed below:
(1) TCC overflow interrupt
(2) External interrupt (/INT pin).
R3F is the interrupt status register, which records the interrupt requests in the relative flags/bits. IOCF is
an interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the
DISI instruction. When one of the interrupts (if enabled) occurs, the next instruction will be fetched from
address 001H. Once in the interrupt service routine, the source of an interrupt can be determined by
polling the flag bits in the R3F. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and enabling interrupts to avoid recursive interrupts.
This specification is subject to change without prior notice.
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MASK ROM
The flag (except ICIF bit) in the Interrupt Status Register (R3F) is set regardless of the status of its mask
bit or the execution of ENI. Note that the result of R3F will be the logic AND of R3F and IOCF (refer to
Fig. 9). The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of
ENI).
When an interrupt is generated by the INT instruction (if enabled), the next instruction will be fetched
from address 002H.
IRQn
P Q
R
CLK C
L Q
D
/IRQn
R3F
ENI/DISI
Q
Q
RESET
interrupt
IRQm
RFRD
P
D
R
C CLK
L
IOD
IOCFWR
IOCF
IOCF R D
RFWR
Fig. 9 Interrupt input circuit
4.7 Oscillator
1. Oscillator Modes
The EM78447S can operate in three different oscillator modes, i.e., high XTAL (HXT) oscillator mode,
low XTAL (LXT) oscillator mode, and External RC oscillator mode (ERC) oscillator mode. User can
select one of modes by programming MS, HLF, and HLP in the Code Option Register. Table 7 depicts
how the three modes are defined.
The maximum operating frequencies of crystal/resonator on different VDDs are listed in Table 8.
Table 7 Oscillator Modes Defined by MS and HLP
Mode
ERC(External RC oscillator mode)
HXT(High XTAL oscillator mode)
This specification is subject to change without prior notice.
MS
0
1
20
HLF
*X
1
HLP
*X
*X
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EM78447S
MASK ROM
LXT(Low XTAL oscillator mode)
<Note>
1
0
0
1. X, Don’t care
2. The transient point of system frequency between HXT and LXY is around 400 KHz.
Table 8 The Summary of Maximum Operating Speeds
Conditions
VDD
2.3
3.0
5.0
Two cycles with two clocks
Fxt max.(MHz)
4.0
8.0
20.0
2. Crystal Oscillator/Ceramic Resonators(XTAL)
EM78447S can be driven by an external clock signal through the OSCI pin as shown in Fig. 10.
In most applications, Pin OSCI and Pin OSCO is connected with a crystal or ceramic resonator to
generate oscillation. Fig. 11 depicts of such circuit. This is applicable in either HXT mode or in the LXT
mode. Table 9 provides the recommended values of C1 and C2. Since each resonator has its own
attribute, user should refer to its specification for appropriate values of C1 and C2. RS, a serial
resistor, may be required for AT strip cut crystal or low frequency mode.
OSCI
Ext. Clock
OSCO
EM78447S
Fig. 10 External Clock Input Circuit
C1
OSCI
EM78P447S
XTAL
OSCO
RS
C2
Fig. 11 Crystal/Resonator Circuit
This specification is subject to change without prior notice.
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MASK ROM
Table 9 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Frequency Mode
Ceramic Resonators
HXT
LXT
Crystal Oscillator
HXT
Frequency
455 kHz
2.0 MHz
4.0 MHz
32.768kHz
100KHz
200KHz
455KHz
1.0MHz
2.0MHz
4.0MHz
C1(pF)
100~150
20~40
10~30
25
25
25
20~40
15~30
15
15
330
C2(pF)
100~150
20~40
10~30
15
25
25
20~150
15~30
15
15
330
C
OSCI
7404
7404
7404
EM78447S
XTAL
Fig. 12 Crystal/Resonator-Series Mode Circuit
4. 7K
10K
Vdd
OSCI
7404
7404
EM78447S
10K
XTAL
C1
C2
Fig. 13 Crystal/Resonator-Parallel Mode Circuit
This specification is subject to change without prior notice.
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MASK ROM
3. External RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC oscillator (Fig. 15)
offers a lot of cost savings. Nevertheless, user should be aware that the frequency of the RC oscillator
is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by
the operation temperature. Moreover, the frequency also changes slightly from one chip to another
due to the manufacturing process variations.
In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF,
and that the value of Rext should not be greater than 1 M ohm. If they can not be kept in this range,
the frequency is easily affected by noise, humidity, and leakage.
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the contrary, for very low
Rext values, for instance, 1 KΩ, the oscillator could become unstable, because the NMOS cannot
properly discharge the current from the capacitor.
Based on the above reasons, it must be kept in mind that all of the supply voltage, the operation
temperature, the components of the RC oscillator, the package types, and the way the PCB is layout,
will affect the system frequency in one way or another.
VCC
Rext
OSCI
Cext
EM78447S
Fig. 14 External RC Oscillator Mode Circuit
This specification is subject to change without prior notice.
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EM78447S
MASK ROM
Table 10 RC Oscillator Frequencies
Cext
Rext
20 pF
100 pF
300 pF
<Note>
Average Fosc 5V,25°C Average Fosc 3V,25°C
4.32 MHz
3.56 MHz
2.83 MHz
2.8 MHz
1.62MHz
1.57 MHz
184 KHz
187 KHz
1.39 MHz
1.35 MHz
950 KHz
930 KHz
500 KHz
490 KHz
54KHz
55 KHz
580 KHz
550 KHz
390 KHz
380 KHz
200 KHz
200 KHz
21 KHz
21 KHz
3.3k
5.1k
10k
100k
3.3k
5.1k
10k
100k
3.3k
5.1k
10k
100k
1. Measured on DIP packages.
2. Design reference only.
4.8 CODE Option Register
The EM78447S has one CODE option word that is not a part of the normal program memory. The option
bits cannot be accessed during normal program execution.
Bit0
CLK
Bit1
MS
Bit2
HLF
Bit3
LVDD
Bit4
/ENWDT
Bit5
TYPE
Bit6
-
• Bit 0 (CLK): Instruction period option bit.
0: two oscillator periods.
1: four oscillator periods.
Refer to the section on Instruction Set.
• Bit 1 (MS):Oscillator type selection.
0: RC type
1: XTAL type(XTAL1 and XTAL2)
• Bit 2 (HLF): XTAL frequency selection
0: XTAL2 type (low frequency, 32.768KHz)
1: XTAL1 type (high frequency)
This bit will affect system oscillation only when Bit1 (MS) is “1”. When MS is”0”, HLF must be “0”.
<Note>: The transient point of system frequency between HXT and LXY is around 400 KHz.
• Bit 3 (LVDD):Levels of the Operating Voltage.
0: Operating Voltage 2.3V ~ 5.5V, not power saving.
This specification is subject to change without prior notice.
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MASK ROM
1: Operating Voltage 4V ~ 5.5V, power saving.
• Bit 4 (/ENWDT): Watchdog timer enable bit.
0: Enable
1: Disable
• Bit 5(TYPE): Type selection for EM78447SA or B.
0: EM78447SB
1: EM78447SA
• Bit 6 : Reserved.
The bit6 set to “1” all the time.
4.9 Power On Considerations
Any microcontroller is not guaranteed to start operating properly before the power supply stabilizes.
EM78447S is equipped with Power On Voltage Detector (POVD) with a detection level of 2.0V. Its
performance improves if Vdd rise fast enough (10 ms or less). Under critical applications, however,
extra devices may still be required to assist in solving power-up problems.
4.10 External Power On Reset Circuit
The circuit shown in Fig.15 implements an external RC to produce a reset pulse. The pulse width (time
constant) should be kept long enough to allow Vdd to reach minimum operation voltage. This circuit is
used when the power supply has a slow rise speed. Because the current leakage from the /RESET pin
is about ±5µA, it is recommended that R should not be great than 40 K. In this way, the voltage at Pin
/RESET is held below 0.2V. The diode (D) acts as a short circuit at power-down. The capacitor, C, is
discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD
(electrostatic discharge) from flowing into Pin /RESET.
Vdd
R
/RESET
D
EM78447S
Rin
C
Fig. 15 External Power-Up Reset Circuit
This specification is subject to change without prior notice.
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MASK ROM
4.11 Residue-Voltage Protection
When battery is replaced, device power (Vdd) is removed but residue-voltage remains. The
residue-voltage may trips below Vdd minimum, but not to zero. This condition may cause a poor power
on reset. Fig.16 and Fig.17 show how to build a residue-voltage protection circuit.
Vdd
Vdd
33K
EM78447S
Q1
10K
/RESET
40K
1N4684
Fig. 16 Circuit 1 for the Residue Voltage Protection
Vdd
Vdd
R1
EM78447S
Q1
/RESET
R2
40K
Fig. 17 Circuit 2 for the Residue Voltage Protection
This specification is subject to change without prior notice.
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MASK ROM
4.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more
operands. Normally, all instructions are executed within one single instruction cycle (one instruction
consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A",
"ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6",
"CLR R2", ⋅⋅⋅⋅). In this case, the execution takes two instruction cycles.
Under certain conditions, if the instruction cycle specification is not suitable for some applications,
they can be modified as follows:
(A) Change one instruction cycle to consist of 4 oscillator periods.
(B) Executed within two instruction cycles, "JMP", "CALL", "RET", "RETL", "RETI", or the
conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") instructions which were tested to be
true. Also execute within two instruction cycles, the instructions that are written to the program
counter.
Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle consists of two
oscillator clocks if CLK is low, and four oscillator clocks if CLK is high.
Note that once the 4 oscillator periods within one instruction cycle is selected as in Case (A), the
internal clock source to TCC should be CLK=Fosc/4, not Fosc/ 2 as indicated in Fig. 5.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction can operate
on I/O register.
The symbol "R" represents a register designator that specifies which one of the registers (including
operational registers and general purpose registers) is to be utilized by the instruction. "b" represents
a bit field designator that selects the value for the bit which is located in the register "R", and affects
operation. "k" represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0000 rrrr
0 0000 0001 0000
0 0000 0001 0001
HEX
0000
0001
0002
0003
0004
000r
0010
0011
MNEMONIC
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
This specification is subject to change without prior notice.
OPERATION
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
27
STATUS AFFECTED
None
C
None
T,P
T,P
None <Note1>
None
None
2002/03/01
EM78447S
MASK ROM
INSTRUCTION BINARY
0 0000 0001 0010
HEX
0012
MNEMONIC
RET
0 0000 0001 0011
0013
RETI
0 0000 0001 0100
0 0000 0001 rrrr
0014
001r
CONTR
IOR R
0 0000 0010 0000
0020
TBL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
0 0110 00rr rrrr
06rr
RRCA R
0 0110 01rr rrrr
06rr
RRC R
0 0110 10rr rrrr
06rr
RLCA R
0 0110 11rr rrrr
06rr
RLC R
0 0111 00rr rrrr
07rr
SWAPA R
0
0
0
0
0
0
0
1
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
1kkk
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
CALL k
0000
0000
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
0111
0111
0111
100b
101b
110b
111b
00kk
01rr
1000
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
01rr
10rr
11rr
bbrr
bbrr
bbrr
bbrr
kkkk
rrrr
0000
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
kkkk
This specification is subject to change without prior notice.
OPERATION
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
CONT → A
IOCR → A
R2+A → R2,
Bits 8~9 of R2 unchanged
A→R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A∨R→A
A∨R→R
A&R → A
A&R → R
A⊕R→ A
A⊕R→ R
A+R → A
A+R → R
R→ A
R→ R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP],
28
STATUS AFFECTED
None
None
None
None <Note1>
Z,C,DC
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
None
C
C
C
C
None
None
None
None
None <Note2>
None <Note3>
None
None
None
2002/03/01
EM78447S
MASK ROM
INSTRUCTION BINARY
1
1
1
1
1
1
1
1
1
01kk
1000
1001
1010
1011
1100
1101
1110
1111
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
0000 0010
kkkk kkkk
HEX
MNEMONIC
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1E02
1Fkk
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
INT
ADD A,k
OPERATION
(Page, k) → PC
(Page, k) → PC
k→A
A∨k→A
A&k→A
A⊕k→A
k → A, [Top of Stack] → PC
k-A → A
PC+1 → [SP], 002H → PC
k+A → A
STATUS AFFECTED
None
None
Z
Z
Z
None
Z,C,DC
None
Z,C,DC
<Note1> This instruction is applicable to IOC5 ~ IOC7, IOCB, IOCE, IOCF only.
<Note2> This instruction is not recommended for R3F operation.
<Note3> This instruction cannot operate under R3F.
This specification is subject to change without prior notice.
29
2002/03/01
EM78447S
MASK ROM
4.13 Timing Diagram
AC Test Input/Output Waveform
2.4
2.0
2.0
TEST POINTS
0.8
0.8
0.4
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are
made at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
This specification is subject to change without prior notice.
30
2002/03/01
EM78447S
MASK ROM
5. ABSOLUTE MAXIMUM RATINGS
Items
Temperature under bias
Storage temperature
Input voltage
Output voltage
Operating Frequency (2clk)
This specification is subject to change without prior notice.
Rating
0°C
to
to
to
to
to
-65°C
-0.3V
-0.3V
DC
31
70°C
150°C
+6.0V
+6.0V
20MHz
2002/03/01
EM78447S
MASK ROM
6. ELECTRICAL CHARACTERISTICS
6.1 DC Electrical Characteristic
( Ta= 0°C ~ 70 °C, VDD= 5.0V±5%, VSS= 0V )
Symbol
IPH
Parameter
XTAL: VDD to 3V
XTAL: VDD to 5V
ERC: VDD to 5V
Input Leakage Current for input pins
Input High Voltage (VDD=5V)
Input Low Voltage (VDD=5V)
Input High Threshold Voltage (VDD=5V)
Input Low Threshold Voltage (VDD=5V)
Clock Input High Voltage (VDD=5V)
Clock Input Low Voltage (VDD=5V)
Input High Voltage (VDD=3V)
Input Low Voltage (VDD=3V)
Input High Threshold Voltage (VDD=3V)
Input Low Threshold Voltage (VDD=3V)
Clock Input High Voltage (VDD=3V)
Clock Input Low Voltage (VDD=3V)
Output High Voltage
(Ports 5, 6, 7)
Output Low Voltage
(Ports 5, 6)
Output Low Voltage
(Port7)
Pull-high current
ISB1
Power down current
FXT
ERC
IIL
VIH1
VIL1
VIHT1
VILT1
VIHX1
VILX1
VIH2
VIL2
VIHT2
VILT2
VIHX2
VILX2
VOH1
VOL1
VOL2
ISB2
ICC1
ICC2
ICC3
ICC4
Power down current
Operating supply current
(VDD=3V)
at two cycles/four clocks
Operating supply current
(VDD=3V)
at two cycles/four clocks
Operating supply current
(VDD=5V)
at two cycles/two clocks
Operating supply current
(VDD=5V)
at two cycles/four clocks
Condition
Two cycle with two clocks
Two cycle with two clocks
R: 5.1KΩ, C: 100 pF
VIN = VDD, VSS
Ports 5, 6
Ports 5, 6
/RESET, TCC
/RESET, TCC
OSCI
OSCI
Ports 5, 6
Ports 5, 6
/RESET, TCC
/RESET, TCC
OSCI
OSCI
Min
DC
DC
F±30%
IOH = -10.0 mA
2.4
Typ.
950
2.0
0.8
2.0
0.8
3.5
1.5
1.5
0.4
1.5
0.4
2.1
0.9
0.4
IOL = 14.0 mA
This specification is subject to change without prior notice.
32
-50
15
Unit
MHz
MHz
KHz
µA
V
V
V
V
V
V
V
V
V
V
V
V
V
IOL = 9.0 mA
Pull-high active, input pin at VSS
All input and I/O pins at VDD, output
pin floating, WDT disabled
All input and I/O pins at VDD, output
pin floating, WDT enabled
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"), output pin
floating, WDT disabled
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"), output pin
floating, WDT enabled
/RESET= 'High', Fosc=4MHz
(Crystal type, CLKS="0"), output pin
floating, WDT enabled
/RESET= 'High', Fosc=10MHz
(Crystal type, CLKS="0"), output pin
floating, WDT enabled
Max
8.0
20.0
F±30%
±1
V
0.4
V
-240
µA
1
µA
8
µA
25
30
µA
30
35
µA
2.2
mA
5.0
mA
-100
2002/03/01
EM78447S
MASK ROM
6.2 AC Electrical Characteristic
(Ta=0°C ~ 70 °C, VDD=5V±5%, VSS=0V)
Symbol
Dclk
Tins
Ttcc
Tdrh
Trst
Twdt
Tset
Thold
Tdelay
Parameter
Input CLK duty cycle
Instruction cycle time
(CLKS="0")
TCC input period
Device reset hold time
/RESET pulse width
Watchdog timer period
Input pin setup time
Input pin hold time
Output pin delay time
Conditions
Crystal type
RC type
Ta = 25°C
Ta = 25°C
Ta = 25°C
Cload=20pF
Min
45
100
500
(Tins+20)/N*
17.0
2000
17.0
Typ
50
Max
55
DC
DC
16.2
15.4
16.2
0
20
50
15.4
Unit
%
ns
ns
ns
ms
ns
ms
ns
ns
ns
* N= selected prescaler ratio.
This specification is subject to change without prior notice.
33
2002/03/01
EM78447S
MASK ROM
APPENDIX
Package Types:
MASK MCU
EM78447SAP
EM78447SAM
EM78447SAS
EM78447SBP
EM78447SBWM
Package Type
DIP
SOP
SSOP
DIP
SOP
This specification is subject to change without prior notice.
Pin Count
28
28
28
32
32
34
Package Size
600 mil
300 mil
209 mil
600 mil
450 mil
2002/03/01