0 CY2280 100-MHz Pentium® II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop PCs Features Functional Description • Mixed 2.5V and 3.3V operation • Clock solution for Pentium® II, and other similar processor-based motherboards — Four 2.5V CPU clocks up to 100 MHz — Eight 3.3V sync. PCI clocks, one free-running — Two 3.3V 48-MHz USB clocks — Three 3.3V Ref. clocks at 14.318 MHz — Two 2.5V APIC clocks at 14.318 MHz or PCI/2 • EMI control — Spread spectrum clocking The CY2280 is a Spread Spectrum clock synthesizer/driver for a Pentium II, or other similar processor-based PC requiring 100-MHz support. All of the required system clocks are provided in a space-saving 48-pin SSOP package. The CY2280 can be used with the CY231x for a total solution for systems with SDRAM. The CY2280 provides the option of spread spectrum clocking on the CPU and PCI clocks for reduced EMI. A downspread percentage is introduced when the SEL_SS input is asserted. The device can be run without spread spectrum when the SEL_SS input is deasserted. The percentage of spreading is EPROM-programmable to optimize EMI-reduction. — Factory-EPROM programmable spread spectrum margin The CY2280 has power-down, CPU stop, and PCI stop pins for power management control. The signals are synchronized on-chip, and ensure glitch-free transitions on the outputs. When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PCI_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. When the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. — Factory-EPROM programmable output drive and slew rate • Factory-EPROM programmable CPU clock frequencies for custom configurations • Available in space-saving 48-pin SSOP package CY2280 Selector Guide CY2280 Configuration Options Clock Outputs CPU (66.6, 100 MHz) –1 –11S –21S 4 4 4 PCI (CPU/2, CPU/3) 8 8 8 USB (48 MHz) 2 2 2 APIC (14.318 MHz) 2 2 — APIC (PCI/2) — — 2 Reference (14.318 MHz) CPU-PCI delay 3 3 3 1.5−4.0 ns 1.5−4.0 ns 1.5−4.0 ns — — 2.0–4.5 ns N/A −0.6% −0.6% CPU-APIC delay Spread Spectrum (Downspread) Logic Block Diagram -1 -2 APIC [0:1] VDDAPIC CPU_STOP XTALIN REF [0-2] 14.318 MHz OSC. XTALOUT VDDREF STOP LOGIC CPU PLL CPUCLK [0-3] Divider VDDCPU PWR_DWN PCICLK_F SEL0 SEL1 SEL100 SEL_SS EPROM VDDPCI Delay STOP LOGIC PCI [1-7] VDDPCI PCI_STOP USBCLK [0:1] SYS PLL VDDUSB Pentium is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-07207 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 08, 2002 CY2280 Pin Configurations VSS XTALIN 1 2 3 48 47 46 4 VDDREF REF0 REF2 REF1 VSS XTALIN VDDAPIC APIC0 APIC1 5 6 43 PCICLK_F 7 42 VSS RESERVED 8 9 10 11 12 41 VDDCPU 40 39 38 CPUCLK0 37 36 35 34 VDDCPU CPUCLK2 CPUCLK3 PCICLK1 VDDPCI PCICLK2 PCICLK3 VSS 48-pin SSOP (Top View) XTALOUT VSS 45 44 PCICLK4 PCICLK5 VDDPCI 13 PCICLK6 16 33 PCICLK7 VSS AVDD VSS VDDUSB 17 32 VSS 18 31 19 20 30 29 21 28 PCI_STOP CPU_STOP PWR_DWN N/C USBCLK0 USBCLK1 VSS 22 27 23 24 26 25 14 15 VSS AVDD SEL0 SEL1 SEL100 CY2280-1 4 VDDREF REF2 VDDAPIC APIC0 APIC1 XTALOUT VSS 5 6 43 PCICLK_F 7 42 VSS RESERVED 8 9 10 11 12 41 VDDCPU 40 39 38 CPUCLK0 37 36 35 34 VDDCPU CPUCLK2 CPUCLK3 PCICLK2 PCICLK3 VSS VSS 48 47 46 45 44 PCICLK1 VDDPCI CPUCLK1 1 2 3 48-pin SSOP (Top View) REF0 REF1 CPUCLK1 VSS PCICLK4 PCICLK5 VDDPCI 13 PCICLK6 16 33 PCICLK7 VSS AVDD VSS VDDUSB 17 32 VSS 18 31 19 20 30 29 21 28 PCI_STOP CPU_STOP PWR_DWN SEL_SS USBCLK0 USBCLK1 VSS 22 27 23 24 26 25 14 15 VSS AVDD SEL0 SEL1 SEL100 CY2280-11S CY2280-21S Pin Summary Name Pins Description VDDPCI 15, 9 3.3V Digital voltage supply for PCI clocks VDDUSB 21 3.3V Digital voltage supply for USB clocks VDDREF 48 3.3V Digital voltage supply for REF clocks VDDAPIC 46 2.5V Digital voltage supply for APIC clocks VDDCPU 41, 37 2.5V Digital voltage supply for CPU clocks AVDD 33, 19 Analog voltage supply, 3.3V VSS 3, 6, 12, 18, 20, 24, 32, 34, 38, 43 Ground XTALIN[1] 4 Reference crystal input 5 Reference crystal feedback PCI_STOP 31 Active LOW control input to stop PCI clocks CPU_STOP 30 Active LOW control input to stop CPU clocks PWR_DWN 29 Active LOW control input to power down device SEL_SS 28 Spread spectrum select input (-11S and -21S options) N/C 28 Spread spectrum select input (-1 option) SEL0 27 CPU frequency select input, bit 0 (see Function Table) SEL1 26 CPU frequency select input, bit 1 (see Function Table) SEL100 25 CPU frequency select input, selects between 100 MHz and 66.6 MHz (see Function Table) CPUCLK[0:3] 40, 39, 36, 35 CPU clock outputs PCICLK[1:7] 8, 10, 11, 13, 14, 16, 17 PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz or 100 MHz respectively PCICLK_F 7 Free-running PCI clock output APIC[0:1] 45, 44 APIC clock outputs REF[0:2] 1, 2, 47 3.3V Reference clock outputs USBCLK[0:1] 22, 23 USB clock outputs RESERVED 42 Reserved XTALOUT [1] Note: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. Document #: 38-07207 Rev. *A Page 2 of 12 CY2280 Function Table (-11S Option) CPU/PCI Ratio CPUCLK N/A 2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 N/A 2 Reserved Reserved 14.318 MHz 14.318 MHz 48 MHz 0 N/A 2 Reserved Reserved 14.318 MHz 14.318 MHz 48 MHz 1 1 0 (downspread) 2 66.66 MHz 33.33 MHz 14.318 MHz 14.318 MHz 48 MHz 1 1 1 (no spread) 2 66.66 MHz 33.33 MHz 14.318 MHz 14.318 MHz 48 MHz 1 0 0 N/A 3 TCLK/2 TCLK/6 TCLK[3] TCLK[3] TCLK/2 1 0 1 N/A 3 Reserved Reserved 14.318 MHz 14.318 MHz 48 MHz 1 1 0 N/A 3 Reserved Reserved 14.318 MHz 14.318 MHz 48 MHz 1 1 1 0 (downspread) 3 100 MHz 33.33 MHz 14.318 MHz 14.318 MHz 48 MHz 1 1 1 1 (no spread) 3 100 MHz 33.33 MHz 14.318 MHz 14.318 MHz 48 MHz CPU/PCI Ratio CPUCLK SEL100 SEL1 SEL0 0 0 0 0 0 0 1 0 0 SEL_SS[2] PCICLK_F PCICLK REF APIC USBCLK Function Table (-21S Option) SEL_SS[2] PCICLK_F PCICLK SEL100 SEL1 SEL0 REF APIC USBCLK 0 0 0 N/A 2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 1 N/A 2 Reserved Reserved 14.318 MHz Reserved 48 MHz 0 1 0 N/A 2 Reserved Reserved 14.318 MHz Reserved 48 MHz 0 1 1 0 (downspread) 2 66.66 MHz 33.33 MHz 14.318 MHz 16.67 MHz 48 MHz 0 1 1 1 (no spread) 2 66.66 MHz 33.33 MHz 14.318 MHz 16.67 MHz 48 MHz 1 0 0 N/A 3 TCLK/2 TCLK/6 TCLK[3] TCLK/12[3] TCLK/2 1 0 1 N/A 3 Reserved Reserved 14.318 MHz Reserved 48 MHz 1 1 0 N/A 3 Reserved Reserved 14.318 MHz Reserved 48 MHz 1 1 1 0 (downspread) 3 100 MHz 33.33 MHz 14.318 MHz 16.67 MHz 48 MHz 1 1 1 1 (no spread) 3 100 MHz 33.33 MHz 14.318 MHz 16.67 MHz 48 MHz Actual Clock Frequency Values Clock Output Target Frequency Actual Frequency (MHz) (MHz) PPM CPUCLK 66.67 66.654 –195 CPUCLK 100 99.77 –2346 USBCLK 48.0 48.008 167 Power Management Logic CPU_STOP PCI_STOP PWR_DWN CPUCLK PCICLK PCICLK_F Other Clocks Osc. PLLs X X 0 Low Low Low Low Off 0 0 1 Low Low Running Running Running Running Off 0 1 1 Low Running Running Running Running Running 1 0 1 Running Low Running Running Running Running 1 1 1 Running Running Running Running Running Running Notes: 2. Target frequency is modulated by percentage shown (max.) when SEL_SS = 0. 3. TCLK supplied on the XTALIN pin in Test Mode. Document #: 38-07207 Rev. *A Page 3 of 12 CY2280 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature (Non-Condensing) ... –65°C to +150°C Junction Temperature............................................... +150°C Supply Voltage .................................................–0.5 to + 7.0V Package Power Dissipation.............................................. 1W Input Voltage ............................................ –0.5V to VDD + 0.5 Static Discharge Voltage........................................... > 2000V (per MIL-STD-883, Method 3015, like VDD pins tied together) Operating Conditions[4] Parameter Description Min. Max. Unit AVDD, VDDPCI, VDDUSB, VDDREF Analog and Digital Supply Voltage 3.135 3.465 V VDDCPU CPU Supply Voltage 2.375 2.625 V VDDAPIC APIC Supply Voltage 2.375 2.625 V TA Operating Temperature, Ambient 0 70 CL Max. Capacitive Load on CPUCLK PCICLK APIC, REF USB f(REF) Reference Frequency, Oscillator Nominal Value tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) °C pF 20 30 20 20 14.318 14.318 MHz 0.05 50 ms Electrical Characteristics Over the Operating Range Parameter VIH VIL VOH Description Test Conditions High-level Input Voltage Except Crystal Inputs[5] Low-level Input Voltage Inputs[5] Voltage[6] High-level Output Except Crystal VDDCPU = VDDAPIC = 2.375V Min. Max. Unit 2.0 V 0.8 IOH = 12 mA CPUCLK 2.0 V V IOH = 18 mA APIC VOL Low-level Output Voltage[6] VDDCPU = VDDAPIC = 2.375V VOH High-level Output Voltage[6] VDDPCI, AVDD, VDDREF, VDDUSB = 3.135V IOH = 14.5 mA PCICLK IOH = 16 mA USBCLK IOL = 12 mA CPUCLK IOL = 18 mA APIC 0.4 2.4 V V IOH = 16 mA REF VOL Low-level Output Voltage[6] VDDPCI, AVDD, VDDREF, VDDUSB= 3.135V IOL = 9.4 mA PCICLK IOL = 9 mA USBCLK IOL = 9 mA IIH Input High Current VIH = VDD 0.4V V –10 +10 µA 10 µA –10 +10 µA REF IIL Input Low Current VIL = 0V IOZ Output Leakage Current Three-state IDD25 Power Supply Current for 2.5V Clocks[6] VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.6 MHz 70 mA IDD25 Power Supply Current for 2.5V Clocks[6] VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 100 MHz 100 mA IDD33 Power Supply Current for 3.3V Clocks[6] VDD = 3.465V, VIN = 0 or VDD, Loaded Outputs 170 mA IDDS Power-down Current[6] Current draw in power-down state 500 µA Document #: 38-07207 Rev. *A Page 4 of 12 CY2280 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit Notes: 4. Electrical parameters are guaranteed with these operating conditions. 5. Crystal Inputs have CMOS thresholds. 6. Parameter is guaranteed by design and characterization. Not 100% tested in production. Switching Characteristics[6, 7] Parameter Output Description Test Conditions Min. Typ. Max. Unit 45 50 55 % 1.0 4.0 V/ns 1.0 4.0 V/ns 0.5 2.0 V/ns -1,-11S, -21S 0.4 1.6 ns -1,-11S, -21S 0.4 1.6 ns 175 ps 4.0 ns 250 ps 4.5 ns 100 175 ps 200 250 ps 250 500 ps 3 ms t1 All Output Duty Cycle[8] t1 = t1A ÷ t1B t2 CPUCLK, APIC CPU and APIC Clock Rising and Falling Edge Rate Between 0.4V and 2.0V -1,-11S, -21S t2 PCICLK PCI Clock Rising and Falling Edge Rate Between 0.4V and 2.4V -1,-11S, -21S t2 USBCLK, REF USB, REF Rising and Falling Edge Rate Between 0.4V and 2.4V t3 CPUCLK CPU Clock Rise Time Between 0.4V and 2.0V t4 CPUCLK CPU Clock Fall Time Between 2.0V and 0.4V t5 CPUCLK CPU-CPU Clock Skew Measured at 1.25V Skew[9] t6 CPUCLK, PCICLK CPU-PCI Clock Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks t7 PCICLK, PCICLK PCI-PCI Clock Skew Measured at 1.5V t8 CPUCLK, APIC CPU-APIC Clock Skew[10] Measured at 1.25V for 2.5V clocks t9 APIC APIC-APIC Clock Skew Measured at 1.25V t10 CPUCLK Cycle-Cycle Clock Jitter Measured at 1.25V t11 PCICLK Cycle-Cycle Clock Jitter Measured at 1.5V t12 CPUCLK, PCICLK Power-up Time CPU, PCI clock stabilization from power-up 100 -1,-11S, -21S -21S -1,-11S, -21S 1.5 2.0 Notes: 7. All parameters specified with loaded outputs. 8. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 9. PCI lags CPU for -11S and -21S options. 10. APIC lags CPU for -21S option. Document #: 38-07207 Rev. *A Page 5 of 12 CY2280 Switching Waveforms Duty Cycle Timing t1A t1B OUTPUT All Outputs Rise/Fall Time VDD OUTPUT 0V t2 t4 t2 t3 CPU-CPU Clock Skew CPUCLK CPUCLK t5 CPU-PCI Clock Skew CPUCLK PCICLK t6 PCI-PCI Clock Skew PCICLK PCICLK t7 CPU-APIC Clock Skew (-21S only) CPUCLK APIC t8 Document #: 38-07207 Rev. *A Page 6 of 12 CY2280 Switching Waveforms (continued) APIC-APIC Clock Skew APIC APIC t9 CPU_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) PCI_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. Document #: 38-07207 Rev. *A Page 7 of 12 CY2280 Spread Spectrum Clocking Spread Spectrum Disabled Amplitude (dB) Spread Spectrum Enabled Frequency (MHz) Description Modulation Frequency Configuration Outputs Max. Unit 30.0 33.0 kHz Down Spread Margin at the Fundamental Frequency -11S CPU, PCI 0.0 –0.6 % Down Spread Margin at the Fundamental Frequency -21S CPU, PCI, APIC 0.0 –0.6 % Document #: 38-07207 Rev. *A All (except -1) Min. Page 8 of 12 CY2280 Application Information Clock traces must be terminated with either series or parallel termination, as is normally done. Application Circuit Summary • A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF. In some cases, smaller value capacitors may be required. • The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. • A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout and Termination Techniques for Cypress Clock Generators” for more details. • If a Ferrite Bead is used, a 10 µF–22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. Document #: 38-07207 Rev. *A Page 9 of 12 CY2280 Test Circuit VDDPCI, VDDCORE, VDDUSB, VDDREF 3, 6, 12, 18, 20, 24, 32, 34, 38, 43 9, 15, 19, 21, 33, 48 0.1 µF CY2280 VDDCPU, VDDAPIC OUTPUTS CLOAD 37, 41, 46 0.1 µF Notes: Each supply pin must have an individual decoupling capacitor. All capacitors must be placed as close to the pins as is possible. Ordering Information Ordering Code Package Name Package Type Operating Range CY2280PVC-1 O48 48-Pin SSOP Commercial CY2280PVC-11S O48 48-Pin SSOP Commercial CY2280PVC-21S O48 48-Pin SSOP Commercial Document #: 38-07207 Rev. *A Page 10 of 12 CY2280 Package Diagram 48-Lead Shrunk Small Outline Package O48 51-85061-B Document #: 38-07207 Rev. *A Page 11 of 12 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2280 Revision History Document Title: CY2280 100-MHz Pentium® II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop PCs Document Number: 38-07207 REV. ECN NO. Issue Date Orig. of Change ** 111721 12/16/01 DSG *A 121842 12/14/02 RBI Document #: 38-07207 Rev. *A Description of Change Change from Spec number: 38-00694 to 38-07207 Power up requirements added to Operating Conditions Information Page 12 of 12