User's Manual (Preliminary) IE-78K0K1-ET In-Circuit Emulator Target Devices μPD780103 Subseries (78K0/KB1) μPD780114 Subseries (78K0/KC1) μPD780124 Subseries (78K0/KD1) μPD780138 Subseries (78K0/KE1) μPD780148 Subseries (78K0/KF1) Document No. U16604EJ1V0UM00 Date Published February 2003 CP(K) © NEC Electronics Corporation 2003 Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Corporation. NEC Electronics Corporation assumes no responsibility for any errors which may appear in this document. • NEC Electronics Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics Corporation or of others. Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product, operation and application examples. The incorporation of these circuits, software, and information in the design of the customer’s equipment shall be done under the full responsibility of the customer. NEC Electronics Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. User’s Manual (Preliminary) U16604EJ1V0UM00 2 INTRODUCTION Product Overview The IE-78K0K1-ET is designed to be used to debug the following target devices that belong to the 78K0 Series of 8-bit single-chip microcontrollers. • 78K0/KB1 (µPD780103 Subseries): µPD780101, 780102, 780103, 78F0103 • 78K0/KC1 (µPD780114 Subseries): µPD780111, 780112, 780113, 780114, 78F0114 • 78K0/KD1 (µPD780124 Subseries): µPD780121, 780122, 780123, 780124, 78F0124 • 78K0/KE1 (µPD780138 Subseries): µPD780131, 780132, 780133, 780134, 780136, 780138, 78F0134, 78F0138 • 78K0/KF1 (µPD780148 Subseries): µPD780143, 780144, 780146, 780148, 78F0148 Target Readers This manual is intended for engineers who will use the IE-78K0K1-ET to perform system debugging. Engineers who use this manual are expected to be thoroughly familiar with the target device’s functions and use methods and to be knowledgeable about debugging. Purpose This manual’s purpose is to explain various debugging functions that can be performed when using the IE-78K0K1-ET. Organization When using the IE-78K0K1-ET, refer to the manual supplied with the IE-78K0K1-ET (this manual). This manual is organized as follows. IE-78K0K1-ET User’s Manual • Basic specifications • General • System configuration • Part names • External interface functions • Installation • Differences between target devices and target interface circuits How to Use This Manual To understand the functions in general: → Read this manual in the order of the contents. To understand the basic specifications: → Read CHAPTER 1 GENERAL and CHAPTER 2 PART NAMES. To learn the settings when debugging the target device of the IE-78K0K1-ET: → Read CHAPTER 3 INSTALLATION. User’s Manual (Preliminary) U16604EJ1V0UM00 3 Terminology The meanings of certain terms used in this manual are listed below. Term Emulation device Meaning This is a general term that refers to the device in the emulator that is used to emulate the target device. It includes the emulation CPU. Emulation CPU This is the CPU block in the emulator that is used to execute user-generated programs. Target device This is the device (the real chip) that is the target of emulation. Target system This includes the target program and the hardware provided by the user. When defined narrowly, it includes only the hardware. IE system Conventions Caution This refers to the IE-78K0K1-ET. Data significance: Higher digits on the left and lower digits on the right Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information When referring the ID78K0-NS User’s Manual, read IE-78K0-NS as IE-78K0K1-ET. User’s Manual (Preliminary) U16604EJ1V0UM00 4 CONTENTS CHAPTER 1 GENERAL ..........................................................................................................................6 1.1 System Configuration .....................................................................................................................7 1.2 Hardware Configuration..................................................................................................................9 1.3 Basic Specifications........................................................................................................................10 1.4 Package Contents...........................................................................................................................12 CHAPTER 2 PART NAMES ....................................................................................................................13 2.1 Names of Main Unit ........................................................................................................................13 2.2 Names of Parts on Board ...............................................................................................................14 CHAPTER 3 INSTALLATION ..................................................................................................................15 3.1 Connection......................................................................................................................................16 3.2 Clock Settings .................................................................................................................................19 3.3 External Trigger Settings ................................................................................................................31 3.4 Multiplication Circuit Selection Switches (SW2, SW3) Settings.....................................................32 3.5 Switch for Clock Monitor (SW7)......................................................................................................32 3.6 Settings of Mask Options................................................................................................................33 3.7 Emulation of POC and LVI Functions .............................................................................................33 3.8 Low-Voltage Emulation Settings.....................................................................................................33 3.9 LED Specifications..........................................................................................................................34 3.10 User Power Supply Selection Switch (SW8) Settings..................................................................34 CHAPTER 4 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS ......................................................................................35 CHAPTER 5 CAUTIONS ON USE..........................................................................................................55 APPENDIX A EMULATION PROBE PIN CORRESPONDENCE TABLE ..............................................56 APPENDIX B INTERFACE BOARD .......................................................................................................65 User’s Manual (Preliminary) U16604EJ1V0UM00 5 CHAPTER 1 GENERAL The IE-78K0K1-ET is a development tool for efficient debugging of hardware or software when using one of the following target devices that belong to the 78K0 Series 8-bit of single-chip microcontrollers. This chapter describes the IE-78K0K1-ET system configuration and basic specifications. • Target devices • 78K0/KB1 (µPD780103 Subseries): µPD780101, 780102, 780103, 78F0103 • 78K0/KC1 (µPD780114 Subseries): µPD780111, 780112, 780113, 780114, 78F0114 • 78K0/KD1 (µPD780124 Subseries): µPD780121, 780122, 780123, 780124, 78F0124 • 78K0/KE1 (µPD780138 Subseries): µPD780131, 780132, 780133, 780134, 780136, 780138, 78F0134, 78F0138 • 78K0/KF1 (µPD780148 Subseries): µPD780143, 780144, 780146, 780148, 78F0148 User’s Manual (Preliminary) U16604EJ1V0UM00 6 1.1 System Configuration Figure 1-1 illustrates the IE-78K0K1-ET system configuration. Figure 1-1. System Configuration Host machine CD-ROM (included with IE-78K0K1-ET) • Device file Note 1 • Integrated debugger ID-78K0-NS, etc. Interface board (Included with IE-78K0K1-ET) Interface cable (Included with IE-78K0K1-ET) IE-78K0K1-ET (this product) AC adapter (Included with IE-78K0K1-ET) Probe conversion board (included with IE-78K0K1-ET) Note 2 Emulation probe (sold separately) Note 2 Conversion socket/conversion adapter (sold separately) Note 2 User’s Manual (Preliminary) U16604EJ1V0UM00 7 Notes 1. The device file is as follows. The device file can be downloaded from the website of NEC Electronics at http://www.necel.com/micro/. µSxxxxDF780103: 78K0/KB1 µSxxxxDF780114: 78K0/KC1 µSxxxxDF780124: 78K0/KD1 µSxxxxDF780138: 78K0/KE1 µSxxxxDF780148: 78K0/KF1 2. Refer to Table 1-1 for details of the probe conversion board, emulation probe and conversion socket/conversion adapter. Table 1-1. List of Emulation Probes, Conversion Sockets, and Conversion Adapters Package Probe Conversion Emulation Probe Conversion Socket/ Board Conversion Adapter 80-pin QFP 78014X PROBE NP-80GC *1 *4 EV-9200GC-80 *3 (14 x 14 mm) Board NP-80GC-TQ *1 TGC-080SBP *2 *5 NP-H80GC-TQ *1 80-pin TQFP NP-80GK *1 (12 x 12 mm) NP-H80GK-TQ *1 64-pin TQFP 78013X PROBE NP-64GK *1 (12 x 12 mm) Board NP-H64GK-TQ *1 TGK-080SDP *2 *6 TGK-064SBP *2 *5 64-pin LQFP NP-64GC *1 EV-9200GC-64 *3 (14 x 14 mm) NP-64GC-TQ *1 TGC-064SAP *2 *5 NP-H64GC-TQ *1 64-pin LQFP NP-H64GB-TQ *1 TGB-064SDP *2 *5 NP-H52GB-TQ *1 TGB-052SBP *2 *5 (10 x 10 mm) 52-pin LQFP 78012X PROBE (10 x 10 mm) Board 44-pin LQFP 78011X PROBE NP-44GB *1 *4 EV-9200G-44 *3 (10 x 10 mm) Board NP-44GB-TQ *1 TGB-44SAP *2 *5 NP-H44GB-TQ *1 30-pin SSOP 78010X PROBE (300 mil) Board NP-30MC *1 YSPACK30BK + NSPACK30BK + YQ-Guide *2 *1 Made by Naito Densei Machida Mfg. Co., Ltd. *2 Made by Tokyo Eletech Corp. *3 Made by NEC Electronics *4 OEM product *5 Tokyo Eletech’s NQPACK series socket can also be used. *6 Tokyo Eletech’s NQPACK series socket cannot be used. User’s Manual (Preliminary) U16604EJ1V0UM00 8 1.2 Hardware Configuration The IE-78K0K1-ET’s position is shown below. Figure 1-2. Basic Hardware Configuration IE system Host machine Interface board (Sold separately) Dedicated bus interface IE-78K0K1-ET Emulation board (This product) Probe conversion board (Included with IE78K0K1-ET) Emulation probe (Sold separately) User’s Manual (Preliminary) U16604EJ1V0UM00 9 1.3 Basic Specifications Table 1-2. Basic Specifications (1/2) Parameter Supervisor CPU Description V40 TM (operating frequency: 16.0 MHz) • 78K0/KB1 (µPD780103 Subseries): µPD780101, 780102, 780103, 78F0103 Target device • 78K0/KC1 (µPD780114 Subseries): µPD780111, 780112, 780113, 780114, 78F0114 • 78K0/KD1 (µPD780124 Subseries): µPD780121, 780122, 780123, 780124, 78F0124 • 78K0/KE1 (µPD780138 Subseries): µPD780131, 780132, 780133, 780134, 780136, 780138, 78F0134, 78F0138 • 78K0/KF1 (µPD780148 Subseries): µPD780143, 780144, 780146, 780148, 78F0148 • Main system clock: 10 MHz System clock • Ring-OSC: 240 kHz • Subsystem clock: 32.768 kHz (not provided for the µPD78010x and 78F0103) Clock supply External Internal Pulse input Mounted on the emulation board Emulation memory capacity 64 KB Mapping unit Internal ROM 4 KB Internal high- 64 bytes speed RAM Internal low- 128 bytes speed RAM External 8 KB expansion memory Emulation functions • Real-time execution • Break execution • Step execution Real-time internal RAM monitor 2 KB among all data memory spaces • Program execution detection Event detection • Bus event detection • External trigger detection • Trigger output (open-drain output) Event integration • Bus condition • Trace qualify condition • Delay condition • Trigger condition • Event break Break trigger • Manual break • Command break • Fail-safe break Real-time Trace source • All trace • Qualify trace trace Trace capacity Trace target 32 bits × 8 KB Address, data, status Execution time measurement 4 min. 28 sec. Max., resolution: 62.5 ns Target interface Emulation board (sold separately) available for each device shape User’s Manual (Preliminary) U16604EJ1V0UM00 10 Table 1-2. Basic Specifications (2/2) Parameter Description Host interface Dedicated bus interface Low voltage support 2.7 to 5.5 V (same as target device) Host machine IBM PC/AT compatible machines Power supply DC 9V Operating ambient 10 to 40°C temperature External dimensions Height: 193 mm, width: 265 mm, length: 72 mm (not including projection) User’s Manual (Preliminary) U16604EJ1V0UM00 11 1.4 Package Contents The packing box contains the IE-78K0K1-ET, probe conversion board, attachment bag, guarantee card, AC adapter, interface board, and packing list. The documentation bag contains the user’s manual (this document), CD-ROM, and interface cable. If there are any missing or damaged items, please contact an NEC Electronics sales representative. Fill out and return the guarantee card that comes with the main unit. Figure 1-3. Package Contents <2> Probe conversion board • 78010X PROBE board • 78011X PROBE board • 78012X PROBE board • 78013X PROBE board • 78014X PROBE board <3> Interface board <4> AC adapter <5> Guarantee card <6> Packing list <7> Software product license agreement <8> Installation manual <9> Operating precautions <1> IE-78K0K1-ET <10> Attachment bag <12> Interface cable <11> CD-ROM (Software tools and documents) User’s Manual (Preliminary) U16604EJ1V0UM00 12 CHAPTER 2 PART NAMES This chapter introduces the part names of the IE-78K0K1-ET main unit. 2.1 Names of Main Unit Figure 2-1. Names of Parts on Main Unit (1) Probe side LED1: POWER (red) LED2: RETRY (yellow) LED3: POC RESET (orange) LED4: USER VDD (green) SW7: CLOCK MONITOR SW CN2: Probe connector (2) Top SW8: User power supply selection switch CN1: Dedicated bus interface connector CN2: Probe connector JK1: DC IN (3) Interface side JK1: DC IN SW5: Reset switch SW4: Power switch CN1: Dedicated bus interface connector User’s Manual (Preliminary) U16604EJ1V0UM00 13 2.2 Names of Parts on Board (1) Emulation board (S-780148 Board) × 1 Figure 2-2. Package Drawing of Emulation board (S-780148 Board) EXTIN CN1: Dedicated bus interface connector LED1: POWER (red) LED2: RETRY (yellow) LED3: POC RESET (orange) LED4: USER VDD (green) EXTOUT SW8 CN1 SW1 SW7: CLOCK MONITOR SW SW2 CN2 SW2, SW3: Multiplication circuit selection switch SW4: Power switch SW3 CN2: Probe connector SW4 SW1: Subsystem source clock selection switch JK1 JK1: DC IN SW5 SW8: User power supply selection switch SW5: Reset switch (2) Probe conversion boards (five boards) 78010X PROBE Board × 1 78011X PROBE Board × 1 78012X PROBE Board × 1 78013X PROBE Board × 1 78014X PROBE Board × 1 Figure 2-3. Package Drawings of Probe Conversion Boards (Four Boards) 78010X PROBE Board CN1 78012X PROBE Board CN1 78011X PROBE Board CN1 78013X PROBE Board CN1 78014X PROBE Board CN1 User’s Manual (Preliminary) U16604EJ1V0UM00 14 CHAPTER 3 INSTALLATION This chapter describes methods for connecting the IE-78K0K1-ET to the cables, etc. Mode setting methods are also described. The following components are connected. Refer to 1.1 System Configuration for details of the IE-78K0K1-ET system configuration. • Emulation probe: NP-XXXXX (Sold separately) • Probe conversion board (Included) • AC adapter (Included) • Interface cable (Included) • Interface board (Included) Caution Connecting or removing parts to or from the target system, or making switch or other setting changes must be carried out after the power supply to both the IE system and the target system has been switched off. User’s Manual (Preliminary) U16604EJ1V0UM00 15 3.1 Connection (1) Connection with emulation probe With the IE-78K0K1-ET, the connection method differs according to the emulation probe used. Use the probe conversion board corresponding to the target device shown in Table 3-1. Caution Incorrect connection may damage the IE system. For more details on connection, see the user’s manual for each emulation probe. • When using the probe conversion board <1> Connect CN2 of the probe conversion board to CN2 of the IE-78K0K1-ET (Figure 3-1). <2> Connect CN1 of the probe conversion board to the emulation probe (Figure 3-2). Figure 3-1. When Using Probe Conversion Board C N 1 Probe conversion board · 78010X PRO BE Board or · 78011X PRO BE Board or · 78012X PRO BE Board or C N 2 · 78013X PRO BE Board or · 78014X PR O BE B oard User’s Manual (Preliminary) U16604EJ1V0UM00 16 Figure 3-2. When Not Using Probe Conversion Board Em ulation probe (Sold separately) C C N N 1 2 Table 3-1. Target Device and Corresponding Probe Conversion Board Target Device Probe Conversion Board to Be Used µPD780101, 780102, 780103, 78F0103 78010X PROBE Board µPD780111, 780112, 780113, 780114, 78F0114 78011X PROBE Board µPD780121, 780122, 780123, 780124, 78F0124 78012X PROBE Board µPD780131, 780132, 780133, 780134, 780136, 78013X PROBE Board 780138, 78F0134, 78F0138 µPD780143, 780144, 780146, 780148, 78F0148 78014X PROBE Board User’s Manual (Preliminary) U16604EJ1V0UM00 17 (2) Connection with AC adapter Use the AC adapter supplied with the IE-78K0K1-ET. <1> Insert the AC adapter in “JK1” on the interface panel of the IE-78K0K1-ET. Figure 3-3. Connection with AC Adapter JK1: DC IN (3) Connection with interface cable Use the interface cable supplied with the IE-78K0K1-ET. <1> Insert the interface cable in the dedicated bus interface connector on the interface panel of the IE78K0K1-ET. Figure 3-4. Connection with Interface Cable CN1: Dedicated bus interface connector User’s Manual (Preliminary) U16604EJ1V0UM00 18 3.2 Clock Settings 3.2.1 Outline of clock settings The main system clock and subsystem clock to be used can be selected from (1) to (4) below. (1) Clock already mounted on emulation board (2) Clock mounted by user (3) Clock input from the target system (4) Clock generated using Ring-OSC Note Note (4) can be selected only for the main system clock. When the target system includes a clock oscillator, refer to 3.2.2 (1) Clock already mounted on emulation board or 3.2.2 (2) Clock mounted by user. Caution An abnormal main system clock supply will cause the IE system to hang up. Figure 3-5. Target System Clock Oscillator (a) Clock oscillator (b) External clock Target device Target device X1 or XT1 External clock X2 or XT2 VSS X1 or XT1 X2 or XT2 Crystal resonator or ceramic resonator • When the target system includes a clock oscillator: Select clock (1), (2), or (4) for Figure 3-5 (a). (3) cannot be selected. • When the target system includes an external clock: Clock (1), (2), (3), or (4) can be selected for Figure 3-5 (b). User’s Manual (Preliminary) U16604EJ1V0UM00 19 Figure 3-6. Outline of System Clock • Main system clock IE-78K0K1-ET Target system Emulation probe Switched by debugger Clock oscillator or external clock UMCLK RingMCM0 OSC PD780009A • Subsystem clock IE-78K0K1-ET Target system Emulation probe Switched by SW1 Oscillator Clock oscillator or external clock UMCLK RingMCM0 OSC PD780009A User’s Manual (Preliminary) U16604EJ1V0UM00 20 3.2.2 Main system/subsystem clock settings The settings of the main system clock are shown in Table 3-2. Table 3-2. Settings of Main System Clock Frequency of Main System Clock Used SFR IE-78K0K1-ET (MCM0) Integrated Debugger (ID78K0-NS) Parts Board (UMCLK) CPU Clock Source Selection (1) Clock already mounted 10.0 MHz 1 Oscillator Note 2 Internal on emulation board (2) Clock mounted by user Other than Oscillator assembled or 10.0 MHz prepared by user (3) Clock input from the Oscillator (not used) External target system (4) Ring-OSC Note 1 240 kHz 0 Oscillator (not used) Internal or external Notes 1. The IE-78K0K1-ET operates with the Ring-OSC clock when the debugger is activated and immediately after reset. 2. Select the source clock for the main system clock when the debugger is started. After that, do not change the setting. The settings of the subsystem clock are shown in Table 3-3. Table 3-3. Settings of Subsystem Clock Frequency of Subsystem Clock Used (1) Clock that is already mounted on IE-78K0K1-ET IE-78K0K1-ET Parts Board (USCLK) SW1 32.768 kHz 6-8 shorted Other than Oscillator assembled or 32.768 kHz prepared by user I side (Internal) emulation board (2) Clock that is mounted by user (3) Clock input from the target system Oscillator (not used) E side (External) A 32.768 kHz clock is supplied from the oscillator on the IE-78K0K1-ET according to the factory settings. The main system/subsystem clock settings of (1) to (4) are individually described in the following pages. User’s Manual (Preliminary) U16604EJ1V0UM00 21 (1) When using clock already mounted on emulation board When the IE-78K0K1-ET is shipped, a 10.0 MHz crystal oscillator and a parts board with 6-8 shorted are already mounted on the UMCLK socket and USCLK socket, respectively, and a clock is supplied from the 32.768 kHz oscillator on the board. When using the factory-set mode settings, there is no need to make any other hardware settings. A setting outline is shown in Figure 3-7. Set the main system clock in the following steps. <1> When starting the integrated debugger (ID78K0-NS), open the configuration dialog box and select “Internal” in the area (Clock) for selecting the CPU clock source. <2> After the debugger is activated, set the special-function register MCM0 to 1 to switch the CPU operating clock from Ring-OSC (default) to the clock already mounted on the emulation board. Set SW1 to the I side for the subsystem clock to set the clock already mounted on the emulation board. Figure 3-7. When Using Clock Already Mounted on Emulation Board Target system IE-78K0K1-ET Oscillator already mounted (used) Emulation probe Clock oscillator or external clock (not used) Remark The clock that is supplied by the IE-78K0K1-ET’s oscillator (encircled in the figure) is used. User’s Manual (Preliminary) U16604EJ1V0UM00 22 Figure 3-8. Flow of Clock (Main System Clock) IE-78K0K1-ET Target system Emulation probe Switched by debugger Clock oscillator or external clock UMCLK RingMCM0 OSC Remark The flow of the clock is indicated by the bold line. Figure 3-9. Flow of Clock (Subsystem Clock) IE-78K0K1-ET Target system Emulation probe Switched by SW1 Clock oscillator or external clock USCLK PD780009A PD78F0148 Remark The flow of the clock is indicated by the bold line. User’s Manual (Preliminary) U16604EJ1V0UM00 23 (2) When using clock mounted by user Remove the crystal oscillator already mounted on the emulation board (UMCLK: 10.0 MHz) or parts board (USCLK: 6-8 shorted) and mount the parts board (oscillator) that includes the oscillator or resonator to be used. This is effective when debugging with a clock with a different frequency from the clock already mounted (main system clock: 2.0 MHz to 10.0 MHz, subsystem clock: 32 kHz to 38.5 kHz). A setting outline is shown in Figure 3-10. The settings of either (a) or (b) described in the following pages are required, depending on the type of clock to be used. Set the main system clock in the following steps. <1> When starting the integrated debugger (ID78K0-NS), open the configuration dialog box and select “Internal” in the area (Clock) for selecting the CPU clock source. <2> After the debugger is activated, set the special-function register MCM0 to 1 to switch the CPU operating clock from Ring-OSC (default) to the clock mounted by user. Set SW1 to the I side for the subsystem clock to set the clock mounted by user. Figure 3-10. When Using Clock Mounted by User Target system IE-78K0K1-ET Parts board Oscillator or clock oscillator (used) Emulation probe Clock oscillator or external clock (not used) Remark The clock that is supplied by the IE-78K0K1-ET’s oscillator (encircled in the figure) is used. User’s Manual (Preliminary) U16604EJ1V0UM00 24 Figure 3-11. Flow of Clock (Main System Clock) IE-78K0K1-ET Target system Emulation probe Switched by debugger Clock oscillator or external clock UMCLK RingMCM0 OSC Remark The flow of the clock is indicated by the bold line. Figure 3-12. Flow of Clock (Subsystem Clock) IE-78K0K1-ET Target system Emulation probe Switched by SW1 Clock oscillator or external clock USCLK Remark The flow of the clock is indicated by the bold line. User’s Manual (Preliminary) U16604EJ1V0UM00 25 (a) When using a crystal oscillator ♦ Necessary items • Crystal oscillator (with pin configuration as shown in Figure 3-13) Figure 3-13. Crystal Oscillator (Main System Clock) NC +5 V GND CLOCK OUT <Procedure> <1> Prepare the IE-78K0K1-ET. <2> Remove the crystal oscillator or parts board from the socket (marked UMCLK or USCLK) on the IE78K0K1-ET. <3> Mount the new crystal oscillator in the socket from which the oscillator was removed in <2> above (UMCLK or USCLK). At this time, insert the oscillator into the socket aligning the pins as indicated below. Figure 3-14. Crystal Oscillator and Socket Pins Crystal oscillator NC Socket (UMCLK/USCLK) +5 V GND CLOCK OUT 1 14 7 8 (Top view) Table 3-4. Crystal Oscillator Pins and Socket Pin Numbers Crystal Oscillator Pin Socket Pin No. NC 1 GND 7 CLOCK OUT 8 +5 V 14 User’s Manual (Preliminary) U16604EJ1V0UM00 26 (b) When using a ceramic or crystal resonator ♦ Necessary items • Parts board • Capacitor CA • Ceramic or crystal resonator • Capacitor CB • Resistor Rx • Solder kit <Procedure> <1> Solder the target ceramic or crystal resonator, resistor Rx, capacitor CA, and capacitor CB (all with suitable oscillation frequencies) onto the supplied parts board (as shown below). Figure 3-15. Connections on Parts Board Parts board (UMCLK/USCLK) 5V NC 1 MΩ 1 14 2 CA 13 3 CB 12 4 11 5 HCU04 NC 10 Rx 6 9 Jumper 7 8 HCU04 Remark NC: No Connection Table 3-5. Connection Pins and Parts Board Pin No. Connection 2-13 Capacitor CA 3-12 Capacitor CB 4-11 Resonators 5-10 Resistor Rx 8-9 Shorted <2> Prepare the IE-78K0K1-ET. <3> Remove the crystal oscillator that is mounted in the IE-78K0K1-ET’s UMCLK socket. <4> Connect the parts board (<1> above) to the socket (UMCLK or USCLK) from which the crystal oscillator was removed. Check the pin 1 mark to make sure the board is mounted in the correct direction. <5> Make sure that the parts board mounted in the UMCLK or USCLK socket is wired as shown in Figure 3-15 above. User’s Manual (Preliminary) U16604EJ1V0UM00 27 (3) Input a clock from the target system The external clock pulse signal on the target system is used via an emulation probe. Therefore this clock can be used only when an external clock is connected on the target system A setting outline is shown in Figure 3-16. Set the main system clock in the following steps. <1> When starting the integrated debugger (ID78K0-NS), open the configuration dialog box and select “External” in the area (Clock) for selecting the CPU clock source. <2> After the debugger is activated, set the special-function register MCM0 to 1 to switch the CPU operating clock from Ring-OSC (default) to the clock input from the target system. Set SW1 to the E side for the subsystem clock to set the clock from the target system. Caution The clock input from the target should be a rectangular wave. Figure 3-16. When Using Clock Input from Target System (Main System Clock) Target system IE-78K0K1-ET Emulation probe Oscillator already mounted (not used) External clock (used) Remark The external clock that is supplied by the target system (encircled in the figure) is used. User’s Manual (Preliminary) U16604EJ1V0UM00 28 Figure 3-17. Flow of Clock (Main System Clock) IE-78K0K1-ET Target system Emulation probe Switched by debugger Clock oscillator or external clock UMCLK RingMCM0 OSC Remark The flow of the clock is indicated by the bold line. Figure 3-18. Flow of Clock (Subsystem Clock) IE-78K0K1-ET Target system Emulation probe Switched by SW1 Clock oscillator or external clock USCLK PD780009A PD78F0148 Remark The flow of the clock is indicated by the bold line. User’s Manual (Preliminary) U16604EJ1V0UM00 29 (4) When using Ring-OSC This clock can be selected only for the main system clock. When the IE system is activated, Ring-OSC (240 kHz) is selected as the CPU operating clock. A setting outline is shown in Figure 3-19. Caution Use of the peripheral functions, except for the following cases, is prohibited when Ring-OSC is selected as the CPU operating clock (MCM0 = 0). • When watchdog timer is used • When clock monitor is used • When fosc/2 is selected for the TMH1 count clock (CKS12 = 1, CKS11 = 0, CKS10 = 1) 7 • When peripheral function that uses an external clock as the operating clock is used Figure 3-19. When Using Ring-OSC (Main System Clock) Target system IE-78K0K1-ET Ring-OSC of emulation device (µPD78F0148) is used Emulation probe Clock oscillator or external clock (not used) Figure 3-20. Flow of Clock (Main System Clock) IE-78K0K1-ET Target system Emulation probe Switched by debugger Clock oscillator or external clock UMCLK RingMCM0 OSC Remark The flow of the clock is indicated by the bold line. User’s Manual (Preliminary) U16604EJ1V0UM00 30 3.3 External Trigger Settings (1) EXTOUT A low-level pulse is output from the EXTOUT pin on the emulation board for 1.3 µs upon the occurrence of a break event. Caution Because this is an open-drain output, a pull-up resistor should be connected on the target system. (2) EXTIN An event signal can be input from the EXTIN pin on the emulation board. Input a high-level pulse signal for 2 CPU operating clocks or longer. Caution Satisfy the following electrical specifications. Table 3-6. Electrical Specifications Parameter MIN. [V] MAX. [V] Input voltage, high Target voltage × 0.7 Target voltage Input voltage, low 0 Target voltage × 0.3 See the ID78K Series Integrated Debugger Ver.2.30 or Later Operation User’s Manual (U15181E) for descriptions of usage. Figure 3-21. Package Drawing of Emulation board (S-780148 Board) EXTIN EXTOUT LED1: POWER (red) LED2: RETRY (yellow) LED3: POC RESET (orange) LED4: USER VDD (green) SW8 CN1: Dedicated bus interface connector CN1 SW1 SW7: CLOCK MONITOR SW SW2 CN2 SW2, SW3: Multiplication circuit selection switch SW4: Power switch SW3 CN2: Probe connector SW4 SW1: Subsystem source clock selection switch JK1 JK1: DC IN SW5 SW8: User power supply selection switch User’s Manual (Preliminary) U16604EJ1V0UM00 SW5: Reset switch 31 3.4 Multiplication Circuit Selection Switches (SW2, SW3) Settings Change the settings of the multiplication circuit as shown in Table 3-7 according to the operating frequency of the main system clock. Table 3-7. Settings of Multiplication Circuit Main System Clock Frequency SW2 SW3 2.0 MHz to less than 2.5 MHz 1 ON (Other: OFF) 1 ON (Other: OFF) 2.5 MHz to less than 3.5 MHz 2 ON (Other: OFF) 2 ON (Other: OFF) 3.5 MHz to less than 5.0 MHz 3 ON (Other: OFF) 3 ON (Other: OFF) 5.0 MHz to less than 6.5 MHz 4 ON (Other: OFF) 4 ON (Other: OFF) 6.5 MHz to less than 9 MHz 5 ON (Other: OFF) 5 ON (Other: OFF) 9 MHz to 10 MHz (factory setting) 6 ON (Other: OFF) 6 ON (Other: OFF) 3.5 Switch for Clock Monitor (SW7) A switch for clock monitor emulation (SW7) is mounted on the IE-78K0K1-ET board. Emulation for when the clock is stopped can be performed by pressing SW7. Figure 3-22. Switch for Clock Monitor SW7: CLOCK MONITOR SW User’s Manual (Preliminary) U16604EJ1V0UM00 32 3.6 Settings of Mask Options The following mask options are provided in the IE-78K0K1-ET. • Ring-OSC • POC ON/OFF and detection voltage 2.85 V, 3.5 V • P60 to P63 (these ports are not provided in the µPD780101, 780102, 780103 and 78F0103) Set the mask options in the integrated debugger. Open the mask option window from [Option] → [Mask Option] and set the mask options. Refer to the ID78K Series Integrated Debugger Ver.2.30 or Later Operation User’s Manual (U15185E) for details of the settings. • RINGMSK NONMSK: Ring-OSC stop by software enabled Watchdog timer stop enabled MSK: Ring-OSC by software disabled Watchdog timer stop disabled • POC • POCV • P60 to P63 ON: POC function ON OFF: POC function OFF 2.85 V: POC detection voltage 2.85 V 3.5 V: POC detection voltage 3.5 V ON: Pulled up by mask option resistor OFF: No mask option resistor 3.7 Emulation of POC and LVI Functions Emulation of the POC (power-on clear) and LVI (low-voltage detection) functions is implemented by detecting a voltage input from the VDD pin of the target device. Apply VDD (target voltage) from the target system via the emulation probe (apply in the same manner when operated at 5 V). 3.8 Low-Voltage Emulation Settings Low-voltage emulation is implemented by detecting the voltage input from the VDD pin of the target device. Apply VDD (target voltage) from the target system via the emulation probe (apply in the same manner when operated at 5 V). User’s Manual (Preliminary) U16604EJ1V0UM00 33 3.9 LED Specifications The LED lighting specifications are as follows. • LED1: POWER (red): Power is being applied to the IE-78K0K1-ET • LED2: RETRY (yellow): A retry is being performed • LED3: POC RESET (orange): POC is being reset • LED4: USER VDD (green): Power for the target system is being detected Figure 3-23. LED Specifications LED1: POWER (red) LED2: RETRY (yellow) LED3: POC RESET (orange) LED4: USER VDD (green) 3.10 User Power Supply Selection Switch (SW8) Settings Set SW8 according to the power supply voltage of the target system. Table 3-8. Settings of User Power Supply Selection Switch (SW8) Target System Voltage SW8 2.7 V to less than 4 V 1 side 4 V to 5.5 V 3 side (factory setting) User’s Manual (Preliminary) U16604EJ1V0UM00 34 CHAPTER 4 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS This chapter describes the differences between the signal lines of the target device and those of the IE-78K0K1ET's target interface circuit. The target device consists of CMOS circuits, whereas the IE-78K0K1-ET's target interface circuit consists of emulation circuits such as the emulation CPU, TTL, and CMOS-IC. At the time of debugging by connecting the IE system and the target system, the IE system performs emulation as if the actual target device is operating on the target system, however, in reality, it is the IE system that performs the emulation, thus producing slight differences. (a) Signals that are input/output from emulation CPU µPD78F0148 (b) Signals that are input/output from emulation CPU µPD780009A (c) Other signals Regarding the signals in (a) to (c) above, the circuits of the IE system are shown below. (1) When µPD780101, 780102, 780103, and 78F0103 are emulated (a) Signals that are input/output from emulation CPU µPD78F0148 • P03 to P00 • P17 to P10 • P23 to P20 • P33 to P30 • P120 • P130 • AVREF (b) Signals that are input/output from emulation CPU µPD780009A None (c) Other signals • X1, X2, RESET, VDD, IC/VPP, VSS, AVSS User’s Manual (Preliminary) U16604EJ1V0UM00 35 Figure 4-1. Equivalent Circuit of Emulation Circuit (a) • Probe • IE system 100 Ω P03 to P00 P17 to P10 P33 to P30 P120 P130 1 MΩ µPD78F0148 Emulation CPU P23 to P20 AVREF User’s Manual (Preliminary) U16604EJ1V0UM00 36 Figure 4-2. Equivalent Circuit of Emulation Circuit (c) • IE system • Probe µPD78F0148 Emulation CPU 10 MHz UMCLK HC157 Level shifter µPD780009A LVDD 100 Ω X1 PVDD (5 V) 2.2 kΩ 1.5 kΩ PVDD (5 V) 680 Ω 390 Ω 270 Ω 1 kΩ 3.0 kΩ ON 2.2 kΩ 1.5 kΩ 1.2 kΩ 820 Ω 680 Ω ON SW3 OFF SW2 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 OFF HC08 LS07 HC04 33 pF HC32 HC04 LS07 HC04 HC02 33 pF µPD780009A Emulation CPU (CLK block) LVDD 100 Ω RESET (RESET block) 4.7 kΩ (Level shifter) User’s Manual (Preliminary) U16604EJ1V0UM00 37 Figure 4-3. Equivalent Circuit of Emulation Circuit (c) • Probe • IE system LVDD 100 Ω E Level shifter µPD780009A XT1 µPD780009A Emulation CPU SW1 I 32.768 kHz USCLK VCC 3.3 kΩ VCC 1.5 kΩ 100 Ω VDD 1 MΩ HVDD 10 kΩ − + Power detection µPC393G 2SC2720 2 1 3 VDD 620 Ω + − Relay LVDD UPC457G2 X2 IC/VPP OPEN VSS AVSS User’s Manual (Preliminary) U16604EJ1V0UM00 38 (2) When µPD780111, 780112, 780113, and 78F0114 are emulated (a) Signals that are input/output from emulation CPU µPD78F0148 • P01 to P00 • P17 to P10 • P27 to P20 • P33 to P30 • P73 to P70 • P120 • P130 • AVREF (b) Signals that are input/output from emulation CPU µPD780009A • P63 to P60 (c) Other signals • X1, X2, XT1, XT2, RESET, IC/VPP, VDD, VSS, EVDD, EVSS, AVSS User’s Manual (Preliminary) U16604EJ1V0UM00 39 Figure 4-4. Equivalent Circuit of Emulation Circuit (a) • Probe • IE system 100 Ω P01 to P00 P17 to P10 P33 to P30 P73 to P70 P120 1 MΩ 100 Ω P130 µPD78F0148 Emulation CPU P27 to P20 AVREF Figure 4-5. Equivalent Circuit of Emulation Circuit (b) • Probe • IE system LVDD 39 kΩ Photo coupler 100 Ω P63 to P60 µPD780009A Emulation CPU User’s Manual (Preliminary) U16604EJ1V0UM00 40 Figure 4-6. Equivalent Circuit of Emulation Circuit (c) • IE system • Probe µPD78F0148 Emulation CPU 10 MHz UMCLK HC157 Level shifter µPD780009A LVDD 100 Ω X1 PVDD (5 V) 2.2 kΩ 1.5 kΩ PVDD (5 V) 680 Ω 390 Ω 270 Ω 1 kΩ 3.0 kΩ ON 2.2 kΩ 1.5 kΩ 820 Ω 680 Ω 1.2 kΩ ON SW3 OFF SW2 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 OFF HC08 LS07 HC04 33 pF HC32 HC04 LS07 HC04 HC02 33 pF µPD780009A Emulation CPU (CLK block) LVDD 100 Ω (RESET block) 4.7 kΩ RESET (Level shifter) User’s Manual (Preliminary) U16604EJ1V0UM00 41 Figure 4-7. Equivalent Circuit of Emulation Circuit (c) • Probe • IE system LVDD 100 Ω E Level shifter µPD780009A XT1 µPD780009A Emulation CPU SW1 I 32.768 kHz USCLK VCC 3.3 kΩ VCC 1.5 kΩ 100 Ω VDD EVDD HVDD 10 kΩ − + 1 MΩ Power detection µPC393G 2SC2720 2 1 3 VDD 620 Ω + − Relay LVDD UPC457G2 X2 IC/VPP XT2 OPEN VSS AVSS EVSS User’s Manual (Preliminary) U16604EJ1V0UM00 42 (3) When µPD780120, 780121, 780123, 780124, and 78F0124 are emulated (a) Signals that are input/output from emulation CPU µPD78F0148 • P03 to P00 • P17 to P10 • P27 to P20 • P33 to P30 • P77 to P70 • P120 • P130 • P140 • AVREF (b) Signals that are input/output from emulation CPU µPD780009A • P63 to P60 (c) Other signals • X1, X2, XT1, XT2, RESET, IC/VPP, VDD, VSS, EVDD, EVSS, REGC, AVSS User’s Manual (Preliminary) U16604EJ1V0UM00 43 Figure 4-8. Equivalent Circuit of Emulation Circuit (a) • Probe • IE system 100 Ω P03 to P00 P17 to P10 P33 to P30 P77 to P70 P120 P140 1 MΩ µPD78F0148 Emulation CPU 100 Ω P130 P27 to P20 AVREF Figure 4-9. Equivalent Circuit of Emulation Circuit (b) • Probe • IE system LVDD 39 kΩ Photo coupler 100 Ω P63 to P60 µPD780009A Emulation CPU User’s Manual (Preliminary) U16604EJ1V0UM00 44 Figure 4-10. Equivalent Circuit of Emulation Circuit (c) • IE system • Probe µPD78F0148 Emulation CPU 10 MHz UMCLK HC157 Level shifter µPD780009A LVDD 100 Ω X1 PVDD (5 V) 2.2 kΩ 1.5 kΩ PVDD (5 V) 680 Ω 390 Ω 270 Ω 1 kΩ 3.0 kΩ ON 2.2 kΩ 1.5 kΩ 1.2 kΩ 820 Ω 680 Ω ON SW3 OFF SW2 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 OFF HC08 LS07 HC04 33 pF HC32 HC04 LS07 HC04 HC02 33 pF µPD780009A Emulation CPU (CLK block) LVDD 100 Ω RESET (RESET block) 4.7 kΩ (Level shifter) User’s Manual (Preliminary) U16604EJ1V0UM00 45 Figure 4-11. Equivalent Circuit of Emulation Circuit (c) • Probe • IE system LVDD 100 Ω E Level shifter µPD780009A XT1 µPD780009A Emulation CPU SW1 I 32.768 kHz USCLK VCC 3.3 kΩ VCC 1.5 kΩ 100 Ω VDD EVDD HVDD 10 kΩ − + 1 MΩ Power detection µPC393G 2SC2720 2 1 3 VDD 620 Ω + − Relay LVDD UPC457G2 X2 IC/VPP XT2 REGC OPEN VSS AVSS EVSS User’s Manual (Preliminary) U16604EJ1V0UM00 46 (4) When µPD780131, 780132, 780133, 780134, 780136, 780138, 78F0134, and 78F0138 are emulated (a) Signals that are input/output from emulation CPU µPD78F0148 • P06 to P00 • P17 to P10 • P27 to P20 • P33 to P30 • P77 to P70 • P120 • P130 • P141 and P140 • AVREF (b) Signals that are input/output from emulation CPU µPD780009A • P43 to P40 • P53 to P50 • P63 to P60 (c) Other signals • X1, X2, XT1, XT2, RESET, IC/VPP, VDD, VSS, EVDD, EVSS, REGC, AVSS User’s Manual (Preliminary) U16604EJ1V0UM00 47 Figure 4-12. Equivalent Circuit of Emulation Circuit (a) • Probe • IE system 100 Ω P06 to P00 P17 to P10 P33 to P30 P77 to P70 P120 P141 and P140 1 MΩ µPD78F0148 Emulation CPU 100 Ω P130 P27 to P20 AVREF Figure 4-13. Equivalent Circuit of Emulation Circuit (b) • Probe • IE system LVDD 39 kΩ Photo coupler 100 Ω P63 to P60 P43 to P40 P53 to P50 µPD780009A Emulation CPU 100 Ω 1 MΩ User’s Manual (Preliminary) U16604EJ1V0UM00 48 Figure 4-14. Equivalent Circuit of Emulation Circuit (c) • IE system • Probe µPD78F0148 Emulation CPU 10 MHz UMCLK HC157 Level shifter µPD780009A LVDD 100 Ω X1 PVDD (5 V) 2.2 kΩ 1.5 kΩ PVDD (5 V) 680 Ω 390 Ω 270 Ω 1 kΩ 3.0 kΩ ON 2.2 kΩ 1.5 kΩ 820 Ω 680 Ω 1.2 kΩ ON SW3 OFF SW2 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 OFF HC08 LS07 HC04 33 pF HC32 HC04 LS07 HC04 HC02 33 pF µPD780009A Emulation CPU (CLK block) LVDD 100 Ω RESET (RESET block) 4.7 kΩ (Level shifter) User’s Manual (Preliminary) U16604EJ1V0UM00 49 Figure 4-15. Equivalent Circuit of Emulation Circuit (c) • Probe • IE system LVDD 100 Ω E Level shifter µPD780009A XT1 µPD780009A Emulation CPU SW1 I 32.768 kHz USCLK VCC 3.3 kΩ VCC 1.5 kΩ 100 Ω VDD EVDD HVDD 10 kΩ − + 1 MΩ Power detection µPC393G 2SC2720 2 1 3 VDD 620 Ω + − Relay LVDD UPC457G2 X2 IC/VPP XT2 REGC OPEN VSS AVSS EVSS User’s Manual (Preliminary) U16604EJ1V0UM00 50 (5) When µPD780143, 780144, 780146, 780148, and 78F0148 are emulated (a) Signals that are input/output from emulation CPU µPD78F0148 • P06 to P00 • P17 to P10 • P27 to P20 • P33 to P30 • P77 to P70 • P120 • P130 • P145 to P140 • AVREF (b) Signals that are input/output from emulation CPU µPD780009A • P47 to P40 • P57 to P50 • P67 to P60 (c) Other signals • X1, X2, XT1, XT2, RESET, IC/VPP, VDD, VSS, EVDD, EVSS, REGC, AVSS User’s Manual (Preliminary) U16604EJ1V0UM00 51 Figure 4-16. Equivalent Circuit of Emulation Circuit (a) • Probe side • IE system P06 to P00 P17 to P10 P33 to P30 P77 to P70 P120 P145 to P140 100 Ω 1 MΩ 100 Ω µPD78F0148 Emulation CPU P130 P27 to P20 AVREF Figure 4-17. Equivalent Circuit of Emulation Circuit (b) • Probe • IE system LVDD 39 kΩ Photo coupler 100 Ω P63 to P60 P47 to P40 P53 to P50 P67 to P64 µPD780009A Emulation CPU 100 Ω 1 MΩ User’s Manual (Preliminary) U16604EJ1V0UM00 52 Figure 4-18. Equivalent Circuit of Emulation Circuit (c) • IE system • Probe µPD78F0148 Emulation CPU 10 MHz UMCLK HC157 Level shifter µPD780009A LVDD 100 Ω X1 PVDD (5 V) 2.2 kΩ 1.5 kΩ PVDD (5 V) 680 Ω 390 Ω 270 Ω 1 kΩ 3.0 kΩ ON 2.2 kΩ 1.5 kΩ 1.2 kΩ 820 Ω 680 Ω ON SW3 OFF SW2 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 OFF HC08 LS07 HC04 33 pF HC32 HC04 LS07 HC04 HC02 33 pF µPD780009A Emulation CPU (CLK block) LVDD 100 Ω (RESET block) 4.7 kΩ RESET (Level shifter) User’s Manual (Preliminary) U16604EJ1V0UM00 53 Figure 4-19. Equivalent Circuit of Emulation Circuit (c) • Probe • IE system LVDD 100 Ω E Level shifter µPD780009A XT1 µPD780009A Emulation CPU SW1 I 32.768 kHz USCLK VCC 3.3 kΩ VCC 1.5 kΩ 100 Ω VDD EVDD HVDD 10 kΩ − + 1 MΩ Power detection µPC393G 2SC2720 2 1 3 VDD 620 Ω + − Relay LVDD UPC457G2 X2 IC/VPP XT2 REGC OPEN VSS AVSS EVSS User’s Manual (Preliminary) U16604EJ1V0UM00 54 CHAPTER 5 CAUTIONS ON USE Observe the following cautions on use to avoid damaging the emulator. • Do not place heavy objects on the emulator, or apply pressure to it. • Do not drop the emulator, or subject it to physical shock or vibration. • Do not use the emulator in a hot, humid or dusty environment. Avoid using or storing the emulator in a location where it is exposed to direct sunlight. • Avoid subjecting the emulator to sudden environmental changes (in temperature or humidity) • Do not spill liquids on the emulator. • Do not use the connectors or cables of a different product. User’s Manual (Preliminary) U16604EJ1V0UM00 55 APPENDIX A EMULATION PROBE PIN CORRESPONDENCE TABLE Table A-1. Pin Correspondence of 78010X PROBE Board + Emulation Probe Emulation Probe 78010x PROBE Board IE-78K0K1-ET Device Side CN1 CN2 1 58 107 2 56 104 3 49 103 4 55 100 5 19 99 6 18 30 7 22 94 8 62 29 9 65 24 10 66 23 11 92 8 12 91 7 13 98 14 14 97 13 15 21 15 16 99 10 17 63 9 18 64 37 19 70 43 20 69 44 21 72 47 22 102 48 23 71 16 24 94 76 25 93 79 26 30 80 27 29 85 28 24 114 29 23 113 30 20 108 Remarks 1. The emulation probe is the NP-30MC. The NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd. 2. The numbers in the Emulation Probe Device Side column refer to the pin number of the target system. 3. The numbers in the 78010X PROBE Board CN1 column refer to the 78010X PROBE Board pin to be connected to the emulation probe. 4. The numbers in the IE-78K0K1-ET CN2 column refer to the IE-78K0K1-ET pin to be connected to the 78010X PROBE Board. User’s Manual (Preliminary) U16604EJ1V0UM00 56 Table A-2. Pin Correspondence of 78011X PROBE Board + Emulation Probe Emulation Probe 78011X PROBE Board IE-78K0K1-ET Device Side CN1 CN2 1 104 114 2 103 113 3 100 99 4 99 94 5 94 30 6 93 29 7 30 24 8 29 23 9 24 20 10 23 19 11 20 16 12 47 108 13 48 107 14 51 104 15 52 103 16 57 100 17 58 48 18 59 56 19 60 55 20 55 58 21 56 57 22 49 59 23 18 60 24 17 47 25 22 44 26 21 43 27 28 37 28 27 9 29 92 10 30 91 15 31 98 14 32 97 13 33 102 64 34 73 61 35 72 62 36 69 65 37 70 66 38 63 71 39 64 72 40 61 75 41 62 76 42 65 79 43 66 80 44 71 85 User’s Manual (Preliminary) U16604EJ1V0UM00 57 Remarks 1. The emulation probe is the NP-44GB, NP-44GB-TQ, or H44GB-TQ. The NP-44GB, NP-44GB-TQ, and H44GB-TQ are products of Naito Densei Machida Mfg. Co., Ltd. 2. The numbers in the Emulation Probe Device Side column refer to the pin number of the target system. 3. The numbers in the 78011X PROBE Board CN1 column refer to the 78011X PROBE Board pin to be connected to the emulation probe. 4. The numbers in the IE-78K0K1-ET CN2 column refer to the IE-78K0K1-ET pin to be connected to the 78011X PROBE Board. User’s Manual (Preliminary) U16604EJ1V0UM00 58 Table A-3. Pin Correspondence of 78012X PROBE Board + Emulation Probe Emulation Probe 78012X PROBE Board IE-78K0K1-ET Device Side CN1 CN2 1 118 114 2 114 113 3 108 99 4 104 94 5 100 93 6 94 30 7 30 29 8 29 24 9 24 23 10 20 20 11 16 19 12 10 16 13 6 108 14 33 107 15 37 104 16 43 103 17 47 100 18 51 51 19 57 48 20 59 47 21 55 44 22 49 56 23 45 55 24 41 58 25 35 57 26 31 59 27 4 60 28 8 43 29 14 37 30 18 9 31 22 10 32 28 15 33 92 8 34 91 7 35 98 14 36 102 13 37 106 74 38 112 69 39 116 70 40 87 63 41 83 64 42 77 61 43 73 62 44 69 65 45 63 66 46 61 71 User’s Manual (Preliminary) U16604EJ1V0UM00 59 47 65 72 48 71 75 49 75 76 50 79 79 51 85 80 52 89 85 Remarks 1. The emulation probe is the NP-H52GB-TQ. The NP-H52GB-TQ is a product of Naito Densei Machida Mfg. Co., Ltd. 2. The numbers in the Emulation Probe Device Side column refer to the pin number of the target system. 3. The numbers in the 78012X PROBE Board CN1 column refer to the 78012X PROBE Board pin to be connected to the emulation probe. 4. The numbers in the IE-78K0K1-ET CN2 column refer to the IE-78K0K1-ET pin to be connected to the 78012X PROBE Board. User’s Manual (Preliminary) U16604EJ1V0UM00 60 Table A-4. Pin Correspondence of 78013X PROBE Board + Emulation Probe (1/2) Emulation Probe 78013X PROBE Board IE-78K0K1-ET Device Side 1 CN1 108 CN2 114 2 107 113 3 104 99 4 103 94 5 100 93 6 99 30 7 94 29 8 93 24 9 30 23 10 29 20 11 24 19 12 23 16 13 20 108 14 19 107 15 16 104 16 15 103 17 43 100 18 44 51 19 47 52 20 48 48 21 51 47 22 52 44 23 57 43 24 58 37 25 59 9 26 60 10 27 55 15 28 56 56 29 49 55 30 50 58 31 45 57 32 46 59 Remarks 1. The emulation probe is the NP-64GB-TQ, H64GB-TQ, H64GK, H64GK-TQ, H64GC, H64GC-TQ, or H64GC-TQ. The NP-64GB-TQ, H64GB-TQ, H64GK, H64GK-TQ, H64GC, H64GC-TQ, and H64GC-TQ are products of Naito Densei Machida Mfg. Co., Ltd. 2. The numbers in the Emulation Probe Device Side column refer to the pin number of the target system. 3. The numbers in the 78013X PROBE Board CN1 column refer to the 78013X PROBE Board pin to be connected to the emulation probe. 4. The numbers in the IE-78K0K1-ET CN2 column refer to the IE-78K0K1-ET pin to be connected to the 78013X PROBE Board. User’s Manual (Preliminary) U16604EJ1V0UM00 61 Table A-4. Pin Correspondence of 78013X PROBE Board + Emulation Probe (2/2) Emulation Probe 78013X PROBE Board IE-78K0K1-ET Device Side CN1 CN2 33 14 60 34 13 41 35 18 42 36 17 35 37 22 8 38 21 7 39 28 14 40 27 13 41 92 98 42 91 97 43 98 102 44 97 101 45 102 83 46 101 77 47 106 78 48 105 73 49 77 74 50 78 69 51 73 70 52 74 63 53 69 64 54 70 61 55 63 62 56 64 65 57 61 66 58 62 71 59 65 72 60 66 75 61 71 76 62 72 79 63 75 80 64 76 85 Remarks 1. The emulation probe is the NP-64GB-TQ, H64GB-TQ, H64GK, H64GK-TQ, H64GC, H64GC-TQ, or H64GC-TQ. The NP-64GB-TQ, H64GB-TQ, H64GK, H64GK-TQ, H64GC, H64GC-TQ, and H64GC-TQ are products of Naito Densei Machida Mfg. Co., Ltd. 2. The numbers in the Emulation Probe Device Side column refer to the pin number of the target system. 3. The numbers in the 78013X PROBE Board CN1 column refer to the 78013X PROBE Board pin to be connected to the emulation probe. 4. The numbers in the IE-78K0K1-ET CN2 column refer to the IE-78K0K1-ET pin to be connected to the 78013X PROBE Board. User’s Manual (Preliminary) U16604EJ1V0UM00 62 Table A-5. Pin Correspondence of Emulation Probe Emulation Probe 78014X PROBE IE-78K0K1-ET Emulation Probe 78014X PROBE IE-78K0K1-ET Device Side Board CN1 CN2 Device Side Board CN1 CN2 1 114 114 41 8 8 2 113 113 42 7 7 3 108 108 43 14 14 4 107 107 44 13 13 5 104 104 45 18 18 6 103 103 46 17 17 7 100 100 47 22 22 8 99 99 48 21 21 9 94 94 49 28 28 10 93 93 50 27 27 11 30 30 51 92 92 12 29 29 52 91 91 13 24 24 53 98 98 14 23 23 54 97 97 15 20 20 55 102 102 16 19 19 56 101 101 17 16 16 57 106 106 18 15 15 58 105 105 19 10 10 59 112 112 20 9 9 60 111 111 21 37 37 61 83 83 22 43 43 62 77 77 23 44 44 63 78 78 24 47 47 64 73 73 25 48 48 65 74 74 26 51 51 66 69 69 27 52 52 67 70 70 28 57 57 68 63 63 29 58 58 69 64 64 30 59 59 70 61 61 31 60 60 71 62 62 32 55 55 72 65 65 33 56 56 73 66 66 34 49 49 74 71 71 35 50 50 75 72 72 36 45 45 76 75 75 37 46 46 77 76 76 38 41 41 78 79 79 39 42 42 79 80 80 40 35 35 80 85 85 User’s Manual (Preliminary) U16604EJ1V0UM00 63 Remarks 1. The emulation probe is the NP-80GC, NP-80GC-TQ, H80GC-TQ, H80GK, or H80GK-TQ. The NP-80GC, NP-80GC-TQ, H80GC-TQ, H80GK, and H80GK-TQ are products of Naito Densei Machida Mfg. Co., Ltd. 2. The numbers in the Emulation Probe Device Side column refer to the pin number of the target system. 3. The numbers in the 78014X PROBE Board CN1 column refer to the 78014X PROBE Board pin to be connected to the emulation probe. 4. The numbers in the IE-78K0K1-ET CN2 column refer to the IE-78K0K1-ET pin to be connected to the emulation probe. User’s Manual (Preliminary) U16604EJ1V0UM00 64 APPENDIX B INTERFACE BOARD This chapter explains the settings when connecting the interface board to the IE-78K0K1-ET. B.1 General The interface board included with the IE-78K0K1-ET is used mounted in the PCI slot the host machine. Although this interface board supports PCI Rev.2.2, operation with PCI Rev.2.1 causes no problem. Hardware resources used: I/O address 0000H to FFFFH Interrupt Not used Memory 80H bytes used Power consumption +5V, 300 mA max. User’s Manual (Preliminary) U16604EJ1V0UM00 65 B.2 Installation This section explains the overall flow of installation. Be sure to refer to the document in the CD-ROM for details of other OSs and descriptions. (1) Board setting This interface board does not have jumpers and DIP switches. (2) Mounting on the host machine Confirm that the power supply to the host machine is disconnected, then mount the interface board in the PCI bus slot, in accordance with the directions in the user’s manual of the host machine. When mounting, fix the host machine and interface board tightly with screws. (3) Installation of driver Install the driver by Plug&Play. Figure B-1. Package Drawing of Interface Board P ackage d rawing of the b oard P C I board User’s Manual (Preliminary) U16604EJ1V0UM00 66 B.2.1 Installing in Windows 98 This section explains the installation procedure when using Windows 98 with a PC/AT compatible machine or PC9800 series computer as the host machine. The procedure explained is applicable to any host machine model. <Installation procedure> Remark The CD-ROM drive is assumed as E: in the explanation below. If the NEC PC-9800 series is used, read E as C. Step 1 Shutdown Windows 98 and turn off the power of the computer. Shutdown Windows 98 and turn off the power of the host machine. Furthermore, disconnect the power supply cable of the host machine to assure safety. Step 2 Connect the interface board to an open PCI card slot. Remove the cover of the host machine in accordance with the user’s manual of the host machine, and connect the interface board to an open PCI card slot. At this time, be sure to fix them with screws tightly. In addition, check the connection again before mounting the cover. Step 3 Turn on the power to the host machine and activate Windows 98. Apply the power to the host machine and activate Windows 98. Step 4 Install the driver by Plug&Play of Windows 98. User’s Manual (Preliminary) U16604EJ1V0UM00 67 (1) While Windows 98 is being activated, the [Add New Hardware Wizard] window appears. Click [Next]. Figure B-2 (2) Select “Search for the best driver for your device. (Recommended)” and click [Next]. Figure B-3 (3) Insert the attached CD-ROM in the CD-ROM drive. User’s Manual (Preliminary) U16604EJ1V0UM00 68 (4) Select “Specify a location:” and input “E:\ID78K0NS\driver\WIN9X\PCI-IF”. Alternately, click [Browse], select “E:\ID78K0NS\ driver \WIN9X\PCI-IF” from the drop-down list, and click [Next]. Figure B-4 Figure B-5 (5) Click [OK]. User’s Manual (Preliminary) U16604EJ1V0UM00 69 (6) “NEC IE-PC Interface Card [PCI IF Card]” is displayed. Click [Next]. The necessary files are then automatically copied. Figure B-6 Figure B-7 User’s Manual (Preliminary) U16604EJ1V0UM00 70 (7) Installation is complete. Click [Finish]. Activation of Windows 98 then continues. Figure B-8 Step 5 Completion of installing the IE-PC Driver. Installation of the driver is complete. User’s Manual (Preliminary) U16604EJ1V0UM00 71 B.2.2 Installing in Windows 2000 This section explains the installation procedure when using Windows 2000 with a PC/AT compatible machine or PC-9800 series computer as the host machine. The procedure explained is applicable to any host machine model. <Installation procedure> Remark The CD-ROM drive is assumed as E: in the explanation below. If the NEC PC-9800 series is used, read E as C. Step 1 Shutdown Windows 2000 and turn off the power of the computer. Shutdown Windows 2000 and turn off the power of the host machine. Furthermore, disconnect the power supply cable of the host machine to assure safety. Step 2 Connect the interface board to an open PCI card slot. Remove the cover of the host machine in accordance with the user’s manual of the host machine, and connect the interface board to an open PCI card slot. At this time, be sure to fix them with screws tightly. In addition, check the connection again before mounting the cover. Step 3 Turn on the power to the host machine and activate Windows 2000. Apply the power to the host machine and activate Windows 2000. Step 4 Install the driver by Plug&Play of Windows 2000. (1) While Windows 2000 is being activated, the [Found New Hardware Wizard] window appears. Click [Next]. Figure B-9 User’s Manual (Preliminary) U16604EJ1V0UM00 72 (2) Select “Search for a suitable driver for my device (recommended)” and click [Next]. Figure B-10 (3) Select “Specify a location” and click [Next]. Figure B-11 User’s Manual (Preliminary) U16604EJ1V0UM00 73 (4) Insert the attached CD-ROM in the CD-ROM drive and input “E:\ID78K0NS\driver\WIN2000” in the “Copy manufacturer’s files from:” field and click [OK]. Figure B-12 (5) Click [Next]. Figure B-13 User’s Manual (Preliminary) U16604EJ1V0UM00 74 (6) The [Insert Disk] window is displayed. Click [OK]. Figure B-14 (7) The [Files Needed] window is displayed. Click [Browse] to open the [Locate File] window. Specify NECPCIF.SYS and click [Open]. Figure B-15 Figure B-16 User’s Manual (Preliminary) U16604EJ1V0UM00 75 (8) The necessary files are automatically copied. Figure B-17 (9) The message “Completing the Found New Hardware Wizard” is displayed. Click [Finish]. Activation of Windows 2000 then continues. Figure B-18 Step 5 Completion of installing the IE-PC Driver. Installation of the driver is complete. User’s Manual (Preliminary) U16604EJ1V0UM00 76 Revision History Version Page − 1st 2nd 8, 9, 12, 14, 16, Description Newly created (SUD-TT-0228-1-E) Addition of probe conversion board 78014X PROBE Board 17, 63 13, 14, 31, 34 Addition of SW8 2, 15, 32, 33, 37, Correction of description 41, 45, 49, 52, 65 User’s Manual (Preliminary) U16604EJ1V0UM00 77 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics America, Inc. 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