CY28349B FTG for Intel® Pentium® 4 CPU and Chipsets Features • Compatible to Intel® CK-Titan and CK-408 Clock Synthesizer/driver specifications • Support SMBus byte read/write and block read/ write operations to simplify system BIOS development • System frequency synthesizer for Intel Brookdale 845 and Brookdale – G Pentium® 4 chipsets • Vendor ID and Revision ID support • Programmable clock output frequency with less than 1-MHz increment • Programmable output skew support • Integrated fail-safe Watchdog timer for system recovery • Automatically switch to hardware-selected or softwareprogrammed clock frequency when w timer time-out • Fixed 3V66 and PCI output frequency mode. • Programmable drive strength support • Power management control inputs • Available in 48-pin SSOP CPU 3V66 PCI REF 48M 24_48M x3 x4 x 10 x2 x1 x1 • Capable of generating system RESET after a Watchdog timer time-out occurs or a change in output frequency via SMBus interface Pin Configuration [1] Block Diagram X1 X2 XTAL OSC *FS0:4 VTT_PWRGD# VDD_CPU CPU0:1, CPU0:1#, CPU_ITP, CPU_ITP# *MULTSEL0:1 PWR_DWN# PLL2 2 SDATA SCLK SMBus Logic RST# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CY28349B *MULTSEL1/REF1 VDD_REF X1 X2 GND_PCI *FS2/PCI_F0 *FS3/PCI_F1 PCI_F2 VDD_PCI VDD_3V66 *FS4/PCI0 3V66_0:2 PCI1 PCI2 GND_PCI VDD_PCI PCI3 PCI_F0:2 PCI4 PCI0:6 PCI5 VDD_48MHz PCI6 3V66_3/48MHz_1 VDD_PCI VTT_PWRGD# VDD_48MHz 48MHz_0 RST# GND_48MHz *FS0/48MHz_0 24_48MHz *FS1/24_48MHz VDD_48MHz Divider Network ~ PLL 1 VDD_REF REF0:1 PLL Ref Freq 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0/MULTSEL0* GND_REF VDD_CPU CPU_ITP CPU_ITP# GND_CPU PWR_DWN# CPU0 CPU0# VDD_CPU CPU1 CPU1# GND_CPU IREF VDD_CORE GND_CORE VDD_3V66 3V66_0 3V66_1 GND_3V66 3V66_2 3V66_3/48MHz_1 SCLK SDATA SSOP-48 Note: 1. Signals marked with ‘*’ and “^” have internal pull-up and pull-down resistors, respectively. Cypress Semiconductor Corporation Document #: 38-07454 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 14, 2005 CY28349B Pin Definitions Pin No. Pin Type X1 3 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 4 O Crystal Connection: Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. REF0/MULTSEL0 48 I/O Reference Clock 0/Current Multiplier Selection 0: 3.3V 14.318-MHz clock output. This pin also serves as a power-on strap option to determine the current multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows: MULTSEL1:0 00 = Ioh is 4 x IREF 01 = Ioh is 5 x IREF 10 = Ioh is 6 x IREF 11 = Ioh is 7 x IREF REF1/MULTSEL1 1 I/O Reference Clock 1/Current Multiplier Selection 1: 3.3V 14.318-MHz clock output. This pin also serves as a power-on strap option to determine the current multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows: MULTSEL1:0 00 = Ioh is 4 x IREF 01 = Ioh is 5 x IREF 10 = Ioh is 6 x IREF 11 = Ioh is 7 x IREF CPU0:1, CPU0:1# 41, 38, 40, 37 O CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through serial input interface. CPU_ITP, CPU_ITP# 44, 45 I/O CPU Clock Output for ITP: Frequency is set by the FS0:4 inputs or through serial input interface. 3V66_0:2 31, 30, 28 O 66-MHz Clock Outputs: 3.3V fixed 66-MHz clock. PCI_F0/FS2 6 I/O Free-running PCI Output 0/Frequency Select 2: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. PCI_F1/FS3 7 I/O Free-running PCI Output 1/Frequency Select 3: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 4. Pin Name Pin Description PCI_F2 8 I/O Free-running PCI Output 2: 3.3V free-running PCI output. PCI0/FS4 10 I/O PCI Output 0/Frequency Select 4: 3.3V PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 4. 11, 12, 14, 15, 16, 17 O PCI Clock Output 1 to 6: 3.3V PCI clock outputs. 48MHz_0/FS0 22 I/O 48-MHz Output/Frequency Select 0: 3.3V fixed 48-MHz, non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 4. This output will be used as the reference clock for USB host controller in Intel 845 (Brookdale) platforms. For Intel Brookdale – G platforms, this output will be used as the VCH reference clock. 24_48MHz/FS1 23 I/O 24- or 48-MHz Output/Frequency Select 1: 3.3V fixed 24-MHz or 48-MHz non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 4. This output will be used as the reference clock for SIO devices in Intel 845 (Brookdale) platforms. For Intel Brookdale – G platforms, this output will be used as the reference clock for both USB host controller and SIO devices. We recommend system designer to configure this output as 48 MHz and “HIGH Drive” by setting Byte [5], Bit [0] and Byte [9], Bit [7], respectively. 3V66_3/48MHz_1 27 O 48-MHz or 66-MHz Output: 3.3V output. PCI1:6 Document #: 38-07454 Rev. *B Page 2 of 21 CY28349B Pin Definitions (continued) Pin No. Pin Type PWR_DWN# 42 I Power-down Control: 3.3V LVTTL compatible input that places the device in power down mode when held low. SCLK 26 I SMBus Clock Input: Clock pin for serial interface. SDATA 25 I/O RST# 20 IREF 35 I Current Reference for CPU Output: A precision resistor is attached to this pin which is connected to the internal current reference. VTT_PWRGD# 19 I Powergood from Voltage Regulator Module (VRM): 3.3V LVTTL input. VTT_PWRGD# is a level-sensitive strobe used to determine when FS0:4 and MULTSEL0:1 inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored. VDD_REF, VDD _PCI, VDD_48MHz, VDD_3V66, VDD_CPU 2, 9, 18, 24, 32, 39, 46 P 3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. GND_PCI, GND_48MHz, GND_3V66, GND_CPU, GND_REF, 5, 13, 21, 29, 36, 43, 47 G Ground Connection: Connect all ground pins to the common system ground plane. VDD_CORE 34 P 3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. GND_CORE 33 G Analog Ground Connection: Ground for core logic, PLL circuitry. Pin Name Document #: 38-07454 Rev. *B Pin Description SMBus Data Input: Data pin for serial interface. O System Reset Output: Open-drain system reset output. (open-d rain) Page 3 of 21 CY28349B Swing Select Functions MULTSEL1 MULTSEL0 Board Target Trace/Term Z Reference R, IREF = VDD/(3*Rr) Output Current VOH @ Z 0 0 50Ω Rr = 221 1%, IREF = 5.00 mA IOH = 4*Iref 1.0V @ 50 0 0 60Ω Rr = 221 1%, IREF = 5.00 mA IOH = 4*Iref 1.2V @ 60 0 1 50Ω Rr = 221 1%, IREF = 5.00 mA IOH = 5*Iref 1.25V @ 50 0 1 60Ω Rr = 221 1%, IREF = 5.00 mA IOH = 5*Iref 1.5V @ 60 1 0 50Ω Rr = 221 1%, IREF = 5.00 mA IOH = 6*Iref 1.5V @ 50 1 0 60Ω Rr = 221 1%, IREF = 5.00 mA IOH = 6*Iref 1.8V @ 60 1 1 50Ω Rr = 221 1%, IREF = 5.00 mA IOH = 7*Iref 1.75V @ 50 1 1 60Ω Rr = 221 1%, IREF = 5.00 mA IOH = 7*Iref 2.1V @ 60 0 0 50Ω Rr = 475 1%, IREF = 2.32 mA IOH = 4*Iref 0.47V @ 50 0 0 60Ω Rr = 475 1%, IREF = 2.32 mA IOH = 4*Iref 0.56V @ 60 0 1 50Ω Rr = 475 1%, IREF = 2.32 mA IOH = 5*Iref 0.58V @ 50 0 1 60Ω Rr = 475 1%, IREF = 2.32 mA IOH = 5*Iref 0.7V @ 60 1 0 50Ω Rr = 475 1%, IREF = 2.32 mA IOH = 6*Iref 0.7V @ 50 1 0 60Ω Rr = 475 1%, IREF = 2.32 mA IOH = 6*Iref 0.84V @ 60 1 1 50Ω Rr = 475 1%, IREF = 2.32 mA IOH = 7*Iref 0.81V @ 50 1 1 60Ω Rr = 475 1%, IREF = 2.32 mA IOH = 7*Iref 0.97V @ 60 Document #: 38-07454 Rev. *B Page 4 of 21 CY28349B Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc. can be individually enabled or disabled. The register associated with the Serial Data Interface initializes to its default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. The clock driver serial protocol accepts Byte Write, byte read, Block Write and Block Read operation from the controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The Block Write and Block Read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit Descriptions 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation 7 Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be ‘0000000’. 6:0 Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 Description Start Block Read Protocol Bit 1 Slave address – 7 bits 2:8 Description Start Slave address – 7 bits Write 9 Write Acknowledge from slave 10 Acknowledge from slave Command Code – 8 bits ‘00000000’ stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave 11:18 Command Code – 8 bits ‘00000000’ stands for block operation 19 Acknowledge from slave 20 Repeat start 21:27 Slave address – 7 bits Data byte 0 – 8 bits 28 Read Acknowledge from slave 29 Acknowledge from slave Data byte 1 – 8 bits 46 Acknowledge from slave ... Data Byte N/Slave Acknowledge... ... Data Byte N – 8 bits ... Acknowledge from slave ... Stop 30:37 38 39:46 47 48:55 56 Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge ... Data bytes from slave/Acknowledge ... Data byte N from slave – 8 bits ... Not Acknowledge ... Stop Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 Description Start Slave address – 7 bits Document #: 38-07454 Rev. *B Byte Read Protocol Bit 1 2:8 Description Start Slave address – 7 bits Page 5 of 21 CY28349B Table 3. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Byte Read Protocol Description Bit Description 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave 19 Acknowledge from slave Data byte – 8 bits 20 Repeat start 28 Acknowledge from slave 29 Stop 21:27 28 29 30:37 Slave address – 7 bits Read Acknowledge from slave Data byte from slave – 8 bits 38 Not Acknowledge 39 Stop Data Byte Configuration Map Data Byte 0 Bit Pin# Name Description Power On Default Bit 7 – Spread Select2 ‘000’ = OFF 0 Bit 6 – Spread Select1 ‘001’ = Reserved 0 Bit 5 – Spread Select0 ‘010’ = Reserved 0 ‘011’ = Reserved ‘100’ = ± 0.25% ‘101’ = – 0.5% ‘110’ = ±0.5% ‘111’ = ±0.38% Bit 4 – SEL4 SW Frequency selection bits. See Table 4. 0 Bit 3 – SEL3 0 Bit 2 – SEL2 0 Bit 1 – SEL1 0 Bit 0 – SEL0 0 Data Byte 1 Bit Pin# Name Description Power On Default Bit 7 38, 37 CPU1, CPU1# (Active/Inactive) 1 Bit 6 41, 40 CPU0, CPU0# (Active/Inactive) 1 Bit 5 22 48MHz (Active/Inactive) 1 Bit 4 23 24_48MHz (Active/Inactive) 1 Bit 3 27 3V66_3 (Active/Inactive) 1 Bit 2 28 3V66_2 (Active/Inactive) 1 Bit 1 30 3V66_1 (Active/Inactive) 1 Bit 0 31 3V66_0 (Active/Inactive) 1 Document #: 38-07454 Rev. *B Page 6 of 21 CY28349B Data Byte 2 Bit Pin# Name Pin Description Power On Default Bit 7 – Reserved Reserved 0 Bit 6 17 PCI6 (Active/Inactive) 1 Bit 5 16 PCI5 (Active/Inactive) 1 Bit 4 15 PCI4 (Active/Inactive) 1 Bit 3 14 PCI3 (Active/Inactive) 1 Bit 2 12 PCI2 (Active/Inactive) 1 Bit 1 11 PCI1 (Active/Inactive) 1 Bit 0 10 PCI0 (Active/Inactive) 1 Data Byte 3 Bit Pin# Name Pin Description Power On Default Bit 7 8 PCI_F2 (Active/Inactive) 1 Bit 6 7 PCI_F1 (Active/Inactive) 1 Bit 5 6 PCI_F0 (Active/Inactive) 1 Reserved Reserved 0 CPU_ITP, CPU_ITP# (Active/Inactive) 1 Bit 4 – Bit 3 44, 45 Bit 2 – Reserved Reserved 0 Bit 1 1 REF1 (Active/Inactive) 1 Bit 0 48 REF0 (Active/Inactive) 1 Data Byte 4 Bit Pin# Name Pin Description Power On Default Bit 7 – MULTSEL_Override This bit control the selection of IREF multiple. 0 = HW control; IREF multiplier is determined by MULTSEL[0:1] input pins 1 = SW control; IREF multiplier is determined by Byte[4], Bit[5:6]. 0 IREF multiplier 00 = Ioh is 4 x IREF 01 = Ioh is 5 x IREF 10 = Ioh is 6 x IREF 11 = Ioh is 7 x IREF 0 Bit 6 – SW_MULTSEL1 Bit 5 – SW_MULTSEL0 Bit 4 – Reserved Reserved Reserved Bit 3 – Reserved Reserved Reserved Bit 2 – Reserved Reserved Reserved Bit 1 – Reserved Reserved Reserved Bit 0 – Reserved Reserved Reserved 0 Data Byte 5 Bit Pin# Name Pin Description Bit 7 10 Latched FS4 input Bit 6 7 Latched FS3 input X Bit 5 6 Latched FS2 input X Bit 4 23 Latched FS1 input X Bit 3 22 Latched FS0 input X Document #: 38-07454 Rev. *B Latched FS[4:0] inputs. These bits are read-only. Power On Default X Page 7 of 21 CY28349B Data Byte 5 (continued) Bit Pin# Name Pin Description Power On Default Bit 2 – FS_Override 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings 0 Bit 1 27 SEL 3V66 0 = 48-MHz output on pin 27 1 = 66-MHz output on pin 27 0 Bit 0 23 SEL 48MHZ 0 = 24-MHz 1 = 48-MHz 0 Data Byte 6 Bit Pin# Name Pin Description Power On Default Bit 7 – Revision_ID3 Revision ID bit[3] 0 Bit 6 – Revision_ID2 Revision ID bit[2] 0 Bit 5 – Revision_ID1 Revision ID bit[1] 0 Bit 4 – Revision_ID0 Revision ID bit[0] 0 Bit 3 – Vendor_ID3 Bit[3] of Cypress’s Vendor ID. This bit is read-only. 1 Bit 2 – Vendor_ID2 Bit[2] of Cypress’s Vendor ID. This bit is read-only. 0 Bit 1 – Vendor _ID1 Bit[1] of Cypress’s Vendor ID. This bit is read-only. 0 Bit 0 – Vendor _ID0 Bit[0] of Cypress’s Vendor ID. This bit is read-only. 0 Data Byte 7 Bit Pin# Name Pin Description Power On Default Bit 7 – Reserved Reserved 0 Bit 6 – Reserved Reserved 0 Bit 5 – Reserved Reserved 0 Bit 4 – Reserved Reserved 0 Bit 3 – Reserved Reserved 0 Bit 2 – Reserved Reserved 0 Bit 1 – Reserved Reserved 0 Bit 0 – Reserved Reserved 0 Data Byte 8 Bit Pin# Name Pin Description Power On Default Bit 7 – Reserved Reserved 0 Bit 6 – Reserved Reserved 0 Bit 5 – WD_TIMER4 1 Bit 4 – WD_TIMER3 Bit 3 – WD_TIMER2 Bit 2 – WD_TIMER1 Bit 1 – WD_TIMER0 These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the pre-scaler. The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit and generate Reset if RST_EN_WD is enabled. Bit 0 – WD_PRE_SCALER 0 = 150 ms 1 = 2.5 sec 0 Document #: 38-07454 Rev. *B 1 1 1 1 Page 8 of 21 CY28349B Data Byte 9 Bit Pin# Name Pin Description Power On Default Bit 7 – 48MHz_DRV 48MHz and 24_48MHz clock output drive strength 0 = Normal 1 = High Drive (Recommend to set to high drive if this output is being used to drive both USB and SIO devices in Intel Brookdale - G platforms) 0 Bit 6 – PCI_DRV PCI clock output drive strength 0 = Normal 1 = High Drive 0 Bit 5 – 3V66_DRV 3V66 clock output drive strength 0 = Normal 1 = High Drive 0 Bit 4 – RST_EN_WD This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled 0 Bit 3 – RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled 0 Bit 2 – WD_TO_STATUS Watchdog Timer Time-out Status bit 0 = No time-out occurs (Read); Ignore (Write) 1 = time-out occurred (Read); Clear WD_TO_STATUS (Write) 0 Bit 1 – WD_EN 0 = Stop and reload Watchdog Timer 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs. Note: CY28349B will generate system reset, reload a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog Timer time-out occurs. Under recovery frequency mode, CY28349B will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock CY28349B from its recovery frequency mode by clearing the WD_EN bit. 0 Bit 0 – Reserved Reserved 0 Data Byte 10 Bit Pin# Name Bit 7 – CPU_Skew2 Bit 6 – CPU_Skew1 Bit 5 – CPU_Skew0 Bit 4 – Fixed 3V66/PCI Document #: 38-07454 Rev. *B Pin Description Power On Default CPU skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps 0 Fixed 3V66 and PCI output mode 0 = Disabled 1 = Enabled When enabled, 3V66 and PCI output frequency will be fixed at 64 MHz and 32 MHz respectively. 0 0 0 Page 9 of 21 CY28349B Data Byte 10 (continued) Bit Pin# Name Bit 3 – PCI_Skew1 Bit 2 – PCI_Skew0 Bit 1 – 3V66_Skew1 Bit 0 – 3V66_Skew0 Power On Default Pin Description PCI skew control 00 = Normal 01 = –500 ps 10 = Reserved 11 = +500 ps 0 3V66 skew control 00 = Normal 01 = –150 ps 10 = +150 ps 11 = +300 ps 0 0 0 Data Byte 11 Bit Pin# Name Bit 7 – ROCV_FREQ_N7 Bit 6 – ROCV_FREQ_N6 Bit 5 – ROCV_FREQ_N5 Bit 4 – ROCV_FREQ_N4 Bit 3 – ROCV_FREQ_N3 Bit 2 – ROCV_FREQ_N2 Bit 1 – ROCV_FREQ_N1 Bit 0 – ROCV_FREQ_N0 Power On Default Pin Description If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. 0 0 0 0 0 0 0 0 Data Byte 12 Bit Pin# Name Power On Default Pin Description Bit 7 – ROCV_FREQ_SEL ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] 0 Bit 6 – ROCV_FREQ_M6 0 Bit 5 – ROCV_FREQ_M5 Bit 4 – ROCV_FREQ_M4 Bit 3 – ROCV_FREQ_M3 Bit 2 – ROCV_FREQ_M2 Bit 1 – ROCV_FREQ_M1 Bit 0 – ROCV_FREQ_M0 If ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency.when a Watchdog Timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When FS_Override bit is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Document #: 38-07454 Rev. *B 0 0 0 0 0 0 Page 10 of 21 CY28349B Data Byte 13 Bit Pin# Name Bit 7 – CPU_FSEL_N7 Bit 6 – CPU_FSEL_N6 Bit 5 – CPU_FSEL_N5 Bit 4 – CPU_FSEL_N4 Bit 3 – CPU_FSEL_N3 Bit 2 – CPU_FSEL_N2 Bit 1 – CPU_FSEL_N1 Bit 0 – CPU_FSEL_N0 Pin Description If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Power On Default 0 0 0 0 0 0 0 0 Data Byte 14 Bit Pin# Name Pin Description Power On Default Bit 7 – Pro_Freq_EN Programmable output frequencies enabled 0 = Disabled 1 = Enabled 0 If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. 0 Bit 6 – CPU_FSEL_M6 Bit 5 – CPU_FSEL_M5 Bit 4 – CPU_FSEL_M4 Bit 3 – CPU_FSEL_M3 Bit 2 – CPU_FSEL_M2 Bit 1 – CPU_FSEL_M1 Bit 0 – CPU_FSEL_M0 0 0 0 0 0 0 Data Byte 15 Bit Pin# Name Pin Description Power On Default Bit 7 – Reserved Reserved 0 Bit 6 – Reserved Reserved 0 Bit 5 – Reserved Reserved 0 Bit 4 – Reserved Reserved 0 Bit 3 – Reserved Reserved 0 Bit 2 – Reserved Reserved 0 Bit 1 – Vendor Test Mode Reserved. Write with “1” 1 Bit 0 – Vendor Test Mode Reserved. Write with “1” 1 Data Byte 16 Bit Pin# Name Pin Description Power On Default Bit 7 – Reserved Reserved 0 Bit 6 – Reserved Reserved 0 Bit 5 – Reserved Reserved 0 Bit 4 – Reserved Reserved 0 Bit 3 – Reserved Reserved 0 Bit 2 – Reserved Reserved 0 Bit 1 – Reserved Reserved 0 Bit 0 – Reserved Reserved 0 Document #: 38-07454 Rev. *B Page 11 of 21 CY28349B Data Byte 17 Bit Pin# Name Power On Default Pin Description Bit 7 – Reserved Reserved 0 Bit 6 – Reserved Reserved 0 Bit 5 – Reserved Reserved 0 Bit 4 – Reserved Reserved 0 Bit 3 – Reserved Reserved 0 Bit 2 – Reserved Reserved 0 Bit 1 – Reserved Reserved 0 Bit 0 – Reserved Reserved 0 Table 4. Frequency Selection Table Input Conditions Output Frequency FS4 FS3 FS2 FS1 FS0 SEL4 SEL3 SEL2 SEL1 SEL0 CPU 3V66 PCI PLL Gear Constants (G) 0 0 0 0 0 100.7 67.1 33.6 48.00741 0 0 0 0 1 100.9 67.3 33.6 48.00741 0 0 0 1 0 108.0 72.0 36.0 48.00741 0 0 0 1 1 101.2 67.5 33.7 48.00741 0 0 1 0 0 114.0 76.0 38.0 48.00741 0 0 1 0 1 117.0 78.0 39.0 48.00741 0 0 1 1 0 120.0 80.0 40.0 48.00741 0 0 1 1 1 123.0 82.0 41.0 48.00741 0 1 0 0 0 126.0 63.0 31.5 48.00741 0 1 0 0 1 130.0 65.0 32.5 48.00741 0 1 0 1 0 133.9 67.0 33.5 48.00741 0 1 0 1 1 134.2 67.1 33.6 48.00741 0 1 1 0 0 134.5 67.3 33.6 48.00741 0 1 1 0 1 148.0 74.0 37.0 48.00741 0 1 1 1 0 152.0 76.0 38.0 48.00741 0 1 1 1 1 156.0 78.0 39.0 48.00741 1 0 0 0 0 160.0 80.0 40.0 48.00741 1 0 0 0 1 164.0 82.0 41.0 48.00741 1 0 0 1 0 167.4 66.9 33.5 48.00741 1 0 0 1 1 170.0 68.0 34.0 48.00741 1 0 1 0 0 175.0 70.0 35.0 48.00741 1 0 1 0 1 180.0 72.0 36.0 48.00741 1 0 1 1 0 185.0 74.0 37.0 48.00741 1 0 1 1 1 190.0 76.0 38.0 48.00741 1 1 0 0 0 166.8 66.7 33.4 48.00741 1 1 0 0 1 100.2 66.8 33.4 48.00741 1 1 0 1 0 133.6 66.8 33.4 48.00741 1 1 0 1 1 200.4 66.8 33.4 48.00741 1 1 1 0 0 166.6 66.6 33.3 48.00741 1 1 1 0 1 100.0 66.6 33.3 48.00741 1 1 1 1 0 200.0 66.6 33.3 48.00741 Document #: 38-07454 Rev. *B Page 12 of 21 CY28349B Table 4. Frequency Selection Table (continued) Input Conditions Output Frequency FS4 FS3 FS2 FS1 FS0 SEL4 SEL3 SEL2 SEL1 SEL0 CPU 3V66 PCI PLL Gear Constants (G) 1 1 1 1 1 133.3 66.6 33.3 48.00741 Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency from the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. The Watchdog Timer and Recovery Output Frequency features allow users to implement a recovery mechanism when the system hangs or gets unstable. System BIOS or other control software can enable the Watchdog Timer before they attempt to make a frequency change. If the system hangs and a Watchdog Timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All of the related registers are summarized in Table 5. Table 5. Register Summary Name Description Pro_Freq_EN Programmable output frequencies enabled 0 = Disabled (default) 1 = Enabled. When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs. FS_Override When Pro_Freq_EN is cleared or disabled, 0 = Select operating frequency by FS input pins (default) 1 = Select operating frequency by SEL bits in SMBus control bytes. When Pro_Freq_EN is set or enabled, 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default) 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes. CPU_FSEL_N, CPU_FSEL_M When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]. ROCV_FREQ_N[7:0], ROCV_FREQ_M[6:0] When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block Write to update both registers within the same SMBus bus operation. WD_EN 0 = Stop and reload Watchdog Timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Document #: 38-07454 Rev. *B Page 13 of 21 CY28349B Table 5. Register Summary (continued) Name Description WD_TO_STATUS Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = Time-out occurred (READ); Clear WD_TO_STATUS (WRITE). WD_TIMER[4:0] These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the pre-scaler. The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit. WD_PRE_SCALER 0 = 150 ms 1 = 2.5 sec RST_EN_WD This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Program the CPU Output Frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * (N+3)/(M+3). “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 4. The ratio of (N+3) and (M+3) need to be greater than “1” [(N+3)/(M+3) > 1]. The following table lists set of N and M values for different frequency output ranges.This example use a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Table 6. Examples of N and M Value for Different CPU Frequency Range Frequency Ranges Gear Constants Fixed Value for M-Value Register Range of N-Value Register for Different CPU Frequency 50 MHz–129 MHz 48.00741 93 97–255 130 MHz–248 MHz 48.00741 45 127–245 Document #: 38-07454 Rev. *B Page 14 of 21 CY28349B Maximum Ratings Storage Temperature (Non-condensing) .... –65°C to +150°C (Above which the useful life may be impaired. For user guidelines, not tested.) Max. Soldering Temperature (10 sec) ...................... +260°C Junction Temperature ............................................... +150°C Supply Voltage ..................................................–0.5 to +7.0V Package Power Dissipation.............................................. 1W Input Voltage .............................................. –0.5V to VDD+0.5 Static Discharge Voltage......................................................... (per MIL-STD-883, Method 3015) ............................ > 2000V Operating Conditions Over which Electrical Parameters are Guaranteed[2] Parameter Description Min. Max. Unit 3.135 3.465 V 0 VDD_REF, VDD_PCI,VDD_CORE, VDD_3V66, VDD_48 MHz, VDD_CPU, 3.3V Supply Voltages TA Operating Temperature, Ambient 70 °C Cin Input Pin Capacitance 5 pF CXTAL XTAL Pin Capacitance 22.5 pF CL Max. Capacitive Load on 48MHz, REF PCICLK, 3V66 f(REF) Reference Frequency, Oscillator Nominal Value pF 20 30 14.318 14.318 MHz Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VIH High-level Input Voltage Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 VIL Low-level Input Voltage Except Crystal Pads VOH High-level Output Voltage 2.0 V 0.8 V 48MHz, REF, 3V66 IOH = –1 mA 2.4 V PCI IOH = –1 mA 2.4 V VOL Low-level Output Voltage 48MHz, REF, 3V66 IOL = 1 mA PCI IOL = 1 mA 0.55 V IIH Input High Current 0 < VIN < VDD –5 5 mA IIL Input Low Current 0 < VIN < VDD –5 5 mA IOH High-level Output Current CPU For IOH =6*IRef Configuration REF, 48 MHz Type X1, VOH = 0.65V 0.4 12.9 Type X1, VOH = 0.74V Type 3, VOH = 1.00V Type 5, VOH = 1.00V –29 –23 –33 Type 5, VOH = 3.135V IOL Low-level Output Current REF, 48MHz Type 3, VOL = 1.95V –33 29 Type 3, VOL = 0.4V 3V66, PCI, Type 5, VOL =1.95 V IOZ Output Leakage Current 3.3V Power Supply Current VDD_CORE/VDD33 = 3.465V, FCPU = 133 MHz IDDPD3 3.3V Shutdown Current 30 38 Three-state VDD_CORE/VDDQ3 = 3.465V mA 27 Type 5, VOL = 0.4V IDD3 mA 14.9 Type 3, VOH = 3.135V 3V66, PCI V 10 10 mA 250 mA 40 mA Note: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07454 Rev. *B Page 15 of 21 CY28349B - Switching Characteristics Over the Operating Range[3] Min. Max. Unit t1 Parameter All Output Duty Cycle[4] t1A/(t1B) 45 55 % t2 CPU Rise Time Measured at 20% to 80% of Voh 175 700 ps t2 48MHz, REF Rising Edge Rate Between 0.4V and 2.4V 0.5 2.0 V/ns t2 PCI, 3V66, Rising Edge Rate Between 0.4V and 2.4V 1.0 4.0 V/ns t3 CPU Fall Time Measured at 80% to 20% of Voh 175 700 ps t3 48MHz, REF Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 V/ns t3 PCI, 3V66 Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t5 3V66 [0:1] 3V66-3V66 Skew Measured at 1.5V 500 ps t6 PCI PCI-PCI Skew Measured at 1.5V 500 ps t7 3V66,PCI 3V66-PCI Clock Skew 3V66 leads. Measured at 1.5V 3.5 ns t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B With all outputs running 200 ps t9 3V66 Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 250 ps t9 48MHz Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 350 ps t9 PCI Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 500 ps t9 REF Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 1000 ps CPU, PCI Settle Time CPU and PCI clock stabilization from power-up 3 ms CPU Rise/Fall Matching Measured with test loads[5, 6] Voh Output Description Test Conditions 1.5 20% loads[6] CPU Overshoot Measured with test CPU Undershoot Measured with test loads[6] –0.2 Measured with test loads[6] 0.65 0.74 V loads[6] 0.0 0.05 V CPU High-level Output Voltage Vol CPU Low-level Output Voltage Measured with test Vcrossover CPU Crossover Voltage Measured with test loads[6] Voh + 0.2 V V 45% of 55% of 0.65 0.74 V Notes: 3. All parameters specified with loaded outputs. 4. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 5. Determined as a fraction of 2*(Trp – Trn)/(Trp + Trn) Where Trp is a rising edge and Trn is an intersecting falling edge. 6. The test load is Rs = 33.2Ω, Rp = 49.9Ω in test circuit. Document #: 38-07454 Rev. *B Page 16 of 21 CY28349B Switching Waveforms Duty Cycle Timing (Single-ended Output) t1B t1A Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VDD OUTPUT t3 t2 0V CPU-CPU Clock Skew Host_b Host Host_b Host t4 3V66-3V66 Clock Skew 3V66 3V66 t5 PCI-PCI Clock Skew PCI PCI t6 Document #: 38-07454 Rev. *B Page 17 of 21 CY28349B Switching Waveforms (continued) 3V66-PCI Clock Skew 3V66 PCI t7 CPU Clock Cycle-Cycle Jitter t8A t8B Host_b Host Cycle-Cycle Clock Jitter t9A t9B CLK Ordering Information Ordering Code Package Type Operating Range CY28349BOC 48-pin SSOP Commercial, 0°C to 70°C CY28349BOCT 48-pin SSOP – Tape and Reel Commercial, 0°C to 70°C CY28349BOXC 48-pin SSOP Commercial, 0°C to 70°C CY28349BOXCT 48-pin SSOP – Tape and Reel Commercial, 0°C to 70°C Lead-free Document #: 38-07454 Rev. *B Page 18 of 21 CY28349B Layout Example +3.3V Supply FB VDDQ3 0.005µF G G G G VDDQ3 5Ω 48 47 V 46 G 45 44 G 43 42 41 G 40 V 39 G 38 37 G 36 G 35 V 34 G 3 V 32 G 31 30 G 29 28 27 26 G 25 G CY28349B 1 2 VG 3 4 5 G 6 7 8 G 9 V G 10 11 12 13 G 14 15 16 17 G 18 V 19 G 20 21 G 22 23 24 * G C5 G C3 G G G G G G G C6 FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) C4 = 0.005 µF Ceramic Caps C3 = 10–22 µF G = VIA to GND plane layer C5 = 10 µF C6 = 0.1 µF V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 µF ceramic * For use with onboard video using 48 MHz for Dot Clock or connect to VDDQ3 Document #: 38-07454 Rev. *B Page 19 of 21 CY28349B Package Diagram 48-lead Shrunk Small Outline Package O48 51-85061-*C Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07454 Rev. *B Page 20 of 21 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28349B Document History Page Document Title: CY28349B FTG for Intel® Pentium® 4 CPU and Chipsets Document Number: 38-07454 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 117127 08/13/02 RGL New Data Sheet *A 122932 12/17/02 RBI Add power up requirements to operating condition information. *B 334154 See ECN Document #: 38-07454 Rev. *B RGL Added Lead-free Page 21 of 21