CATALYST CAT5251WI-00

CAT5251
Quad Digitally Programmable Potentiometer (DPP™) with
256 Taps and SPI Interface
FEATURES
DESCRIPTION
„ Four linear-taper digitally programmable
potentiometers
„ 254 resistor taps per potentiometer
„ End to end resistance 50kΩ or 100kΩ
„ Potentiometer control and memory access via
SPI interface
„ Low wiper resistance, typically 100Ω
„ Nonvolatile memory storage for up to four
wiper settings for each potentiometer
„ Automatic recall of saved wiper settings at
power up
„ 2.5 to 6.0 volt operation
„ Standby current less than 1µA
„ 1,000,000 nonvolatile WRITE cycles
„ 100 year nonvolatile memory data retention
„ SOIC 24-lead and TSSOP 24-lead
„ Industrial temperature range
The CAT5251 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of resistive elements connected between
two externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the
wiper tap switches for each DPP. Associated with
each wiper control register are four 8-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register.
The CAT5251 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40°C to 85°C
industrial operating temperature range and offered in
a 24-lead SOIC and TSSOP package.
For Ordering Information details, see page 14.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
SOIC 24-Lead (W)
TSSOP 24-Lead (Y)
SO
1
24
¯¯¯¯¯
HOLD
A0
2
23
SCK
RW3
3
22
RL2
RH3
4
21
RH2
RL3
5
20
RW2
NC
NC
VCC
6 CAT 19
7 5251 18
RLO
8
17
RW1
RHO
9
16
RH1
RWO
10
15
RL1
¯¯¯
CS
11
14
A1
¯¯¯
WP
12
13
SI
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
GND
RH0
CS
SCK
SI
SO
SPI BUS
INTERFACE
RH1
RH2
RH3
WIPER
CONTROL
REGISTERS
RW0
RW1
RW2
WP
A0
A1
HOLD
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
RW3
RL0
1
RL1
RL2
RL3
Doc. No. MD-2017 Rev. F
CAT5251
PIN DESCRIPTION
the registers. If the internal write cycle has already
been initiated, ¯¯¯
WP going low will have no effect on
any write operation.
SI: Serial Input
SI is the serial data input pin. This pin is used to
input all opcodes, byte addresses and data to be
written to the CAT5251. Input data is latched on the
rising edge of the serial clock.
¯¯¯¯¯ : Hold
HOLD
The ¯¯¯¯¯
HOLD pin is used to pause transmission to the
CAT5251 while in the middle of a serial sequence
without having to re-transmit entire sequence at a
¯¯¯¯¯ must be brought low
later time. To pause, HOLD
while SCK is low. The SO pin is in a high impedance
state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
¯¯¯¯¯ is brought high, while SCK is
communication, HOLD
¯¯¯¯¯
low. (HOLD should be held high any time this
¯¯¯¯¯ may be tied high
function is not being used.) HOLD
directly to VCC or tied to VCC through a resistor.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5251. During a read
cycle, data is shifted out on the falling edge of the
serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5251. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
PIN DESCRIPTION
Pin #
1
2
3
Name
SO
A0
RW3
4
RH3
5
RL3
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to the
terminal
connections
on
a
mechanical
potentiometer.
6
7
NC
VCC
8
RL0
RW: Wiper
The four RW pins are equivalent to the wiper terminal
of a mechanical potentiometer.
9
RH0
10
11
12
13
14
RW0
¯¯¯
CS
¯¯¯
WP
SI
A1
15
RL1
16
RH1
17
18
19
20
RW1
GND
NC
RW2
21
RH2
22
RL2
23
24
SCK
¯¯¯¯¯
HOLD
A0, A1: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of four devices
can be addressed on a single bus. A match in the
slave address must be made with the address input
in order to initiate communication with the CAT5251.
¯¯¯
CS : Chip Select
¯¯¯
CS is the Chip select pin. ¯¯¯
CS low enables the
CAT5251 and ¯¯¯
CS high disables the CAT5251. ¯¯¯
CS
high takes the SO output pin to high impedance and
forces the devices into a Standby mode (unless an
internal write operation is underway). The CAT5251
draws ZERO current in the Standby mode. A high to
low transition on ¯¯¯
CS is required prior to any
sequence being initiated. A low to high transition on
¯¯¯
CS after a valid write sequence is what initiates an
internal write cycle.
¯¯¯
WP: Write Protect
¯¯¯
WP is the Write Protect pin. The Write Protect pin
will allow normal read/write operations when held
high. When ¯¯¯
WP is tied low, all non-volatile write
operations to the Data registers are inhibited
(change of wiper control register is allowed). ¯¯¯
WP
going low while ¯¯¯
CS is still low will interrupt a write to
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
2
Function
Serial Data Output
Device Address, LSB
Wiper Terminal for Potentiometer 3
High Reference Terminal for
Potentiometer 3
Low Reference Terminal for
Potentiometer 3
No Connect
Supply Voltage
Low Reference Terminal for
Potentiometer 0
High Reference Terminal for
Potentiometer 0
Wiper Terminal for Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal for
Potentiometer 1
High Reference Terminal for
Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
Wiper Terminal for Potentiometer 2
High Reference Terminal for
Potentiometer 2
Low Reference Terminal for
Potentiometer 2
Bus Serial Clock
Hold
Doc. No. MD-2017 Rev. F
CAT5251
SERIAL BUS PROTOCOL
DEVICE OPERATION
The CAT5251 supports the SPI bus data
transmission protocol. The synchronous Serial
Peripheral Interface (SPI) helps the CAT5251 to
interface directly with many of today's popular
microcontrollers. The CAT5251 contains an 8-bit
instruction register. The instruction set and the
operation codes are detailed in Table 3, Instruction
Set on page 8.
The CAT5251 is four resistor arrays integrated with an
SPI serial interface logic, four 8-bit wiper control
registers and sixteen 8-bit, non-volatile memory data
registers. Each resistor array contains 255 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (RH and RL). RH and RL
are symmetrical and may be interchanged. The tap
positions between and at the ends of the series
resistors are connected to the output wiper terminals
(RW) by a CMOS transistor switch. Only one tap point
for each potentiometer is connected to its wiper terminal
at a time and is determined by the value of the wiper
control register. Data can be read or written to the wiper
control registers or the non-volatile memory data
registers via the SPI bus. Additional instructions allow
data to be transferred between the wiper control
registers and each respective potentiometer's nonvolatile data registers. Also, the device can be
instructed to operate in an "increment/decrement"
mode.
After the device is selected with ¯¯¯
CS going low the
first byte will be received. The part is accessed via
the SI pin, with data being clocked in on the rising
edge of SCK. The first byte contains one of the six
op-codes that define the operation to be performed.
ABSOLUTE MAXIMUM RATINGS
(1)
Parameter
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to VSS(2)(3)
Ratings
-55 to +125
-65 to +150
Units
°C
°C
-2.0 to +VCC +2.0
V
-2.0 to +7.0
1.0
300
±6
V
W
°C
mA
Ratings
-40 to +85
Units
°C
VCC with Respect to Ground
Package Power Dissipation Capability (TA = 25°C)
Lead Soldering Temperature (10 secs)
Wiper Current
Recommended Operating Conditions
VCC = +2.5V to +6V
Parameter
Operating Ambient Temperature (Industrial)
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2)
The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(3)
Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-2017 Rev. F
CAT5251
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
RPOT
RPOT
Test Conditions
IW
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance Tolerance
RPOT Matching
Power Rating
Wiper Current
RW
Wiper Resistance
VTERM
VN
Voltage on any RH or RL Pin
Noise
Resolution
Absolute Linearity (2)
Relative Linearity (3)
TCRPOT Temperature Coefficient of RPOT
TCRATIO Ratiometric Temp. Coefficient
CH/CL/CW Potentiometer Capacitances
fc
Frequency Response
Min
Typ
Max
100
50
25°C, each pot
IW = ±3mA @ VCC = 3V
IW = ±3mA @ VCC = 5V
VSS = 0V
(1)
200
100
GND
±20
1
50
±3
300
150
VCC
0.4
RW(n)(actual) - R(n)(expected)
RW(n+1) - [RW(n)+LSB](5)
(1)
(1)
(1)
RPOT = 50kΩ (1)
(5)
±1
±0.5
±300
20
10/10/25
0.4
Units
kΩ
kΩ
%
%
mW
mA
Ω
Ω
V
nV/√Hz
%
LSB(4)
LSB(4)
ppm/°C
ppm/°C
pF
MHz
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Test Conditions
ICC1
Power Supply Current
ICC2
Min
Max
Units
fSCK = 2.5MHz, SO Open
VCC = 6V Inputs = GND
1
mA
Power Supply Current
Non-volatile Write
fSCK = 2.5MHz, SO = Open
VCC = 6V Inputs = GND
5
mA
ISB
Standby Current (VCC = 5.0V)
VIN = GND or VCC; SO Open
1
µA
ILI
Input Leakage Current
VIN = GND to VCC
10
µA
ILO
Output Leakage Current
VOUT = GND to VCC
10
µA
VIL
Input Low Voltage
-1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
VOL1
Output Low Voltage (VCC = 3V)
IOL = 3mA
0.4
V
VOH1
Output High Voltage (VCC = 6V)
IOH = -1.6mA
VCC - 0.8
Typ
V
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2)
Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(3)
Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
(4)
LSB = RTOT / 255 or (RH - RL) / 255, single pot
(5)
n = 0, 1, 2, ..., 255.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
4
Doc. No. MD-2017 Rev. F
CAT5251
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA = 25ºC, f = 1.0MHz, VCC = +5.0V (unless otherwise noted).
Symbol
COUT
CIN
Parameter
Test Conditions
Output Capacitance (SO)
Max
Units
VOUT = 0V
8
pF
VIN = 0V
6
pF
¯¯¯, SCK, SI, ¯¯¯
¯¯¯¯¯, A0, A1)
Input Capacitance (CS
WP, HOLD
Min
Typ
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
tSU
Data Setup Time
50
ns
tH
Data Hold Time
50
ns
tWH
SCK High Time
125
ns
tWL
SCK Low Time
125
ns
fSCK
Clock Frequency
DC
tLZ
3
MHz
¯¯¯¯¯ to Output Low Z
HOLD
50
ns
tRI(1)
tFI(1)
Input Rise Time
2
µs
Input Fall Time
2
µs
tHD
tCD
¯¯¯¯¯ Setup Time
HOLD
¯¯¯¯¯ Hold Time
HOLD
tV
Output Valid from Clock Low
tHO
Output Hold Time
tDIS
Output Disable Time
250
ns
tHZ
¯¯¯¯¯ to Output High Z
HOLD
¯¯¯
CS High Time
100
ns
250
¯¯¯
CS Setup Time
¯¯¯
CS Hold Time
250
ns
250
ns
tCS
tCSS
tCSH
CL = 50pF
100
ns
100
ns
200
0
ns
ns
ns
POWER UP TIMING (1)(2)
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
tPUR
tPUW
Min
Max
Units
Power-up to Read Operation
1
ms
Power-up to Write Operation
1
ms
XDCP TIMING
Symbol Parameter
Min
Max
Units
tWRPO
Wiper Response Time After Power Supply Stable
5
10
µs
tWRL
Wiper Response Time After Instruction Issued
5
10
µs
Typ
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2)
tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-2017 Rev. F
CAT5251
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol
tWR
Parameter
Min
Typ
Max
Units
5
ms
Write Cycle Time
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
NEND
(1)
TDR(1)
VZAP(1)
ILTH(1)
Parameter
Reference Test Method
Min
Typ
Max
Units
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
Data Retention
MIL-STD-883, Test Method 1008
100
Years
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
V
Latch-Up
JEDEC Standard 17
100
mA
Figure 1. Sychronous Data Timing
tCS
VIH
CS
VIL
SCK
tCSH
tCSS
VIH
tWL
tWH
VIL
tH
tSU
VIH
VALID IN
SI
VIL
tRI
tFI
tV
SO
VOH
tHO
tDIS
HI-Z
HI-Z
VOL
Note: Dashed Line = mode (1, 1)
¯¯¯¯¯ Timing
Figure 2. HOLD
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
HIGH IMPEDANCE
SO
tLZ
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2017 Rev. F
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5251
INSTRUCTION BYTE
INSTRUCTION AND REGISTER
DESCRIPTION
The next byte sent to the CAT5251 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I3-I0. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of four Wiper
Control Registers. The format is shown in Table 2.
DEVICE TYPE / ADDRESS BYTE
The first byte sent to the CAT5251 from the
master/processor is called the Device Address Byte.
The most significant four bits of the Device Type
address are a device type identifier. These bits for the
CAT5251 are fixed at 0101[B] (refer to Table 1).
Data Register Selection
The two least significant bits in the slave address
byte, A1 - A0, are the internal slave address and
must match the physical device address which is
defined by the state of the A1 - A0 input pins for the
CAT5251 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A1 - A0 inputs
can be actively driven by CMOS input signals or tied
to VCC or VSS. The remaining two bits in the device
address byte must be set to 0.
Data Register Selected
R1
R0
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
Table 1. Identification Byte Format
Device Type
Identifier
ID3
0
ID2
1
ID1
0
Slave Address
ID0
1
0
0
A1
(MSB)
A0
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
I3
(MSB)
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
I2
Data Register
Selection
I1
I0
R1
7
R0
WCR/Pot Selection
P1
P0
(LSB)
Doc. No. MD-2017 Rev. F
CAT5251
WIPER CONTROL AND DATA REGISTERS
If the application does not require storage of multiple
settings for the potentiometer; the Data Registers can
be used as standard memory locations for system
parameters or user preference data.
Wiper Control Register (WCR)
The CAT5251 contains four 8-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of
256 switches along its resistor array. The contents of
the WCR can be altered in four ways: it may be
written by the host via Write Wiper Control Register
instruction; it may be written by transferring the
contents of one of four associated Data Registers via
the XFR Data Register instruction; it can be modified
one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register
zero (DR0) upon power-up.
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the ¯¯¯
CS input goes HIGH
after a write sequence is received. The status of the
internal write cycle can be monitored by issuing a
Read Status command to read the Write in Process
(WIP) bit.
INSTRUCTIONS
Four of the ten instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register – read the current
wiper position of the selected potentiometer in
the WCR
The Wiper Control Register is a volatile register that
loses its contents when the CAT5251 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
— Write Wiper Control Register – change current
wiper position in the WCR of the selected
potentiometer
Data Registers (DR)
Each potentiometer has four 8-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data
Registers is a non-volatile operation and will take a
maximum of 5ms.
— Read Data Register – read the contents of the
selected Data Register
— Write Data Register – write a new value to the
selected Data Register
— Read Status – Read the status of the WIP bit which
when set to "1" signifies a write cycle is in progress.
Table 3. Instruction Set
Note: 1/0 = data is one or zero
Instruction Set
Operations
I3
I2
I1
I0
R1
R0
WCR1/
P1
1
0
0
1
0
0
1/0
1/0
Read the contents of the Wiper Control Register
pointed to by P1-P0
1
0
1
0
0
0
1/0
1/0
Write new value to the Wiper Control Register pointed
to by P1-P0
Read Data Register
1
0
1
1 1/0 1/0
1/0
1/0
Write Data Register
1
1
0
0 1/0 1/0
1/0
1/0
XFR Data Register to
Wiper Control Register
1
1
0
1 1/0 1/0
1/0
1/0
XFR Wiper Control
Register to Data Register
1
1
1
0 1/0 1/0
1/0
1/0
Global XFR Data Registers
to Wiper Control Registers
0
0
0
1 1/0 1/0
0
0
Global XFR Wiper Control
Registers to Data Register
1
0
0
0 1/0 1/0
0
0
Read the contents of the Data Register pointed to by
P1-P0 and R1-R0
Write new value to the Data Register pointed to by
P1-P0 and R1-R0
Transfer the contents of the Data Register pointed to
by P1-P0 and R1-R0 to its associated Wiper Control
Register
Transfer the contents of the Wiper Control Register
pointed to by P1-P0 to the Data Register pointed to by
R1-R0
Transfer the contents of the Data Registers pointed to by
R1-R0 of all four pots to their respective Wiper Control
Registers
Transfer the contents of both Wiper Control Registers
to their respective data Registers pointed to by R1-R0
of all four pots
0
0
1
0
0
0
1/0
1/0
Enable Increment/decrement of the Control Latch
pointed to by P1-P0
0
1
0
1
0
0
0
1
Read WIP bit to check internal write cycle status
Instruction
Read Wiper Control
Register
Write Wiper Control
Register
Increment/Decrement
Wiper Control Register
Read Status (WIP bit)
Doc. No. MD-2017 Rev. F
8
WCR0/
P0
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5251
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be
delayed by tWRL. A transfer from the WCR (current
wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the
four potentiometers and one of its associated
registers; or the transfer can occur between all
potentiometers and one associated register.
— Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Global XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 9
and 10). The Increment/Decrement command is
different from the other commands. Once the
command is issued the master can clock the selected
wiper up and/or down in one segment steps; thereby
providing a fine tuning capability to the host. For each
SCK clock pulse (tHIGH) while SI is HIGH, the selected
wiper will move one resistor segment towards the RH
terminal. Similarly, for each SCK clock pulse while SI
is LOW, the selected wiper will move one resistor
segment towards the RL terminal.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5251; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
See Instructions format for more detail.
Figure 7. Two-Byte Instruction Sequence
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0 A3
A2 A1 A0 I3
Internal
Address
Device ID
I2
I1
R1 R0 P1 P0
I0
Instruction
Opcode
Register
Address
Pot/WCR
Address
Figure 8. Three-Byte Instruction Sequence
SI
0
1
0
1
0
0
A2
ID3 ID2 ID1 ID0 A3
A1
A0 I3
Internal
Address
Device ID
I2
I1 I0
R1 R0 P1 P0
Instruction
Opcode
D7 D6 D5 D4 D3 D2 D1 D0
Data
Pot/WCR
Register Address
Address
WCR[7:0]
or
Data Register D[7:0]
Figure 9. Increment/Decrement Instruction Sequence
SI
1
0
ID3 ID2 ID1 ID0
0
1
0
A3
Device ID
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
0
A2 A1 A0
Internal
Address
I3
I2
I1
I0
Instruction
Opcode
9
R1 R0 P1 P0
I
N
Pot/WCR C
Data
Register Address 1
Address
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
Doc. No. MD-2017 Rev. F
CAT5251
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
tWRL
SCK
SI
Voltage Out
RW
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
DEVICE ADDRESSES
0 1 0 1
¯¯¯
CS
0
0
A
1
INSTRUCTION
A 1 0
0
0
1
0
0
DATA
P
1
P
0
7
6
5
4
3
2
1
0 ¯¯¯
CS
Write Wiper Control Register (WCR)
DEVICE ADDRESSES
0 1 0 1
¯¯¯
CS
0
0
A
1
INSTRUCTION
A
0
1
0
1
0
A
0
1 0 1 1 R
1
0
DATA
0
P
1
7
P
0
6
5
4
3
2
1
0 ¯¯¯
CS
Read Data Register (DR)
DEVICE ADDRESSES
0 1 0 1
¯¯¯
CS
0
0
A
1
INSTRUCTION
R
0
DATA
P
1
P 7 6 5 4 3 2 1 0 ¯¯¯
CS
0
Write Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
DATA
0 1 0 1 0 0 A A 1 1 0 0 R R P P 7 6 5 4 3 2 1 0 ¯¯¯ High Voltage
¯¯¯
CS
CS
Write Cycle
1 0
1 0 1 0
Read Status (WIP)
DEVICE ADDRESSES
0 1 0 1
¯¯¯
CS
Doc. No. MD-2017 Rev. F
0
0
A
1
A
0
INSTRUCTION
0
1
0
1
0
0
10
DATA
0
1
7
0
6
0
5
0
4
0
3
0
2
0
1 W ¯¯¯
CS
0 I
P
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5251
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
0 1 0 1
¯¯¯
CS
0
0
A
1
(1)
INSTRUCTION
A
0
0 0 0 1 R R
1 0
0
0 ¯¯¯
CS
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
0 1 0 1 0
¯¯¯
CS
INSTRUCTION
A A 1 0 0 0 R R 0
1 0
1 0
0
0 ¯¯¯ High Voltage
CS
Write Cycle
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
0 1 0 1 0
¯¯¯
CS
INSTRUCTION
A A 1 1 1 0 R R P P ¯¯¯ High Voltage
CS
Write Cycle
1 0
1 0 1 0
0
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
0 1 0 1
¯¯¯
CS
0
0
A
1
INSTRUCTION
A
0
1 1 0 1 R R P
1 0 1
P ¯¯¯
CS
0
Increment (I)/Decrement (D) Wiper Control Register (WCR)
DEVICE ADDRESSES
0 1 0 1
¯¯¯
CS
0
0
A
1
A
0
INSTRUCTION
0 0 1 0 0
0
DATA
P P I/D I/D
1 0
...
I/D I/D ¯¯¯
CS
Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. MD-2017 Rev. F
CAT5251
PACKAGING OUTLINE DRAWINGS
SOIC 24-Lead 300mils (W)
(1)(2)
SYMBOL
E1
E
MIN
e
PIN#1 IDENTIFICATION
MAX
A
2.35
2.65
A1
0.10
0.30
A2
2.05
2.55
b
0.31
0.51
c
0.20
0.33
D
15.20
15.40
E
10.11
10.51
E1
7.34
e
b
NOM
7.60
1.27 BSC
h
0.25
0.75
L
0.40
1.27
θ
0°
8°
θ1
5°
15°
TOP VIEW
h
D
A2
A
A1
SIDE VIEW
h
θ1
θ
θ1
L
c
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2)
Complies with JEDEC standard MS-013.
Doc. No. MD-2017 Rev. F
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5251
TSSOP 24-Lead 4.4mm (Y)
(1)(2)
b
SYMBOL
MIN
NOM
MAX
A
A1
E1
E
1.20
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.80
7.90
E
6.25
6.40
6.55
E1
4.30
4.40
4.50
e
0.65 BSC
L
1.00 REF
L1
0.50
θ1
0°
0.60
0.70
8°
e
TOP VIEW
D
c
A2
A
θ1
L1
A1
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MO-153.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. MD-2017 Rev. F
CAT5251
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
CAT
5251
W
Optional
Company ID
Product
Number
5251
(1)
I
-50
Temperature Range
I = Industrial (-40ºC to 85ºC)
Resistance
-50: 50kΩ
-00: 100kΩ
Package
W: SOIC
Y: TSSOP
– T1
Tape & Reel
T: Tape & Reel
1: 1000/Reel - SOIC
2: 2000/Reel - TSSOP
ORDERING PART NUMBER
CAT5251WI-50
CAT5251WI-00
CAT5251YI-50
CAT5251YI-00
Notes:
(1) All packages are RoHS compliant (Lead-free, Halogen-free).
(2) This device used in the above example is a CAT5251WI-50-T1 (SOIC, Industrial Temperature, 50kΩ, Tape & Reel).
Doc. No. MD-2017 Rev. F
14
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
REVISION HISTORY
Date
Rev.
11/11/2003
C
05/06/2004
D
12/13/2007
E
02/07/2008
F
Reason
Eliminated BGA package in all areas
Eliminated Commercial temperature range
Updated Functional Diagram
Updated wiper resistance from 50Ω to 100Ω
Updated notes in Absolute Max Ratings
Eliminated Commercial temperature range in all areas
Updated Potentiometer Characteristics table
Updated DC Characteristics table
Updated AC Characteristics table
Added XDCP Timing Table on page 6
Corrected Synchronous Data Timing (Figure 1) drawing
Updated Package Outline Drawings
Updated Example of Ordering Information
Added MD- to document number
Reformatted data sheet layout
Update Instruction Format – Read Data Register (DR) and Write Data Register (DR)
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
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OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal
injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
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Corporate Headquarters
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Santa Clara, CA 95054
Phone: 408.542.1000
Fax:
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1Hwww.catsemi.com
Document No: MD-2017
Revision:
F
Issue date:
02/07/08