Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier Non-volatile Program and Data Memories – In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase Cycles 32K bytes (ATmega329/ATmega3290) 64K bytes (ATmega649/ATmega6490) – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – EEPROM, Endurance: 100,000 Write/Erase Cycles 1K bytes (ATmega329/ATmega3290) 2K bytes (ATmega649/ATmega6490) – Internal SRAM 2K bytes (ATmega329/ATmega3290) 4K bytes (ATmega649/ATmega6490) – Programming Lock for Software Security JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features – 4 x 25 Segment LCD Driver (ATmega329/ATmega649) – 4 x 40 Segment LCD Driver (ATmega3290/ATmega6490) – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages – 53/68 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP Speed Grade: – ATmega329V/ATmega3290V/ATmega649V/ATmega6490V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V – ATmega329/3290/649/6490: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V Temperature range: – -40°C to 85°C Industrial 8-bit Microcontroller with In-System Programmable Flash ATmega329/V ATmega3290/V ATmega649/V ATmega6490/V Preliminary Summary 2552HS–AVR–11/06 Features (Continued) • Ultra-Low Power Consumption – Active Mode: 1 MHz, 1.8V: 350 µA 32 kHz, 1.8V: 20 µA (including Oscillator) 32 kHz, 1.8V: 40 µA (including Oscillator and LCD) – Power-down Mode: 100 nA at 1.8V Pin Configurations Figure 1. Pinout ATmega3290/6490 2 AVCC AGND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) DNC DNC PH7 (PCINT23/SEG36) PH6 (PCINT22/SEG37) PH5 (PCINT21/SEG38) PH4 (PCINT20/SEG39) DNC DNC GND VCC DNC PA0 (COM0) PA1 (COM1) PA2 (COM2) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 TQFP LCDCAP 1 75 PA3 (COM3) (RXD/PCINT0) PE0 2 74 PA4 (SEG0) (TXD/PCINT1) PE1 3 73 PA5 (SEG1) (XCK/AIN0/PCINT2) PE2 4 72 PA6 (SEG2) (AIN1/PCINT3) PE3 5 71 PA7 (SEG3) (USCK/SCL/PCINT4) PE4 6 70 PG2 (SEG4) (DI/SDA/PCINT5) PE5 7 69 PC7 (SEG5) (DO/PCINT6) PE6 8 68 PC6 (SEG6) (CLKO/PCINT7) PE7 9 67 DNC VCC 10 66 PH3 (PCINT19/SEG7) GND 11 65 PH2 (PCINT18/SEG8) DNC 12 64 PH1 (PCINT17/SEG9) (PCINT24/SEG35) PJ0 13 63 PH0 (PCINT16/SEG10) (PCINT25/SEG34) PJ1 14 62 DNC DNC 15 61 DNC DNC 16 60 DNC DNC 17 59 DNC DNC 18 58 PC5 (SEG11) (SS/PCINT8) PB0 19 57 PC4 (SEG12) (SCK/PCINT9) PB1 20 56 PC3 (SEG13) (MOSI/PCINT10) PB2 21 55 PC2 (SEG14) (MISO/PCINT11) PB3 22 54 PC1 (SEG15) (OC0A/PCINT12) PB4 23 53 PC0 (SEG16) (OC1A/PCINT13) PB5 24 52 PG1 (SEG17) (OC1B/PCINT14) PB6 25 51 PG0 (SEG18) INDEX CORNER 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (OC2A/PCINT15) PB7 DNC (T1/SEG33) PG3 (T0/SEG32) PG4 RESET/PG5 VCC GND (TOSC2) XTAL2 (TOSC1) XTAL1 DNC DNC (PCINT26/SEG31) PJ2 (PCINT27/SEG30) PJ3 (PCINT28/SEG29) PJ4 (PCINT29/SEG28) PJ5 (PCINT30/SEG27) PJ6 DNC (ICP1/SEG26) PD0 (INT0/SEG25) PD1 (SEG24) PD2 (SEG23) PD3 (SEG22) PD4 (SEG21) PD5 (SEG20) PD6 (SEG19) PD7 ATmega3290/6490 ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 LCDCAP 1 (RXD/PCINT0) PE0 2 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (COM0) PA1 (COM1) PA2 (COM2) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 2. Pinout ATmega329/649 48 PA3 (COM3) 47 PA4 (SEG0) INDEX CORNER (TXD/PCINT1) PE1 3 46 PA5 (SEG1) (XCK/AIN0/PCINT2) PE2 4 45 PA6 (SEG2) (AIN1/PCINT3) PE3 5 44 PA7 (SEG3) (USCK/SCL/PCINT4) PE4 6 43 PG2 (SEG4) (DI/SDA/PCINT5) PE5 7 42 PC7 (SEG5) (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 40 PC5 (SEG7) (SS/PCINT8) PB0 10 39 PC4 (SEG8) Disclaimer (SEG15) PD7 32 29 (SEG18) PD4 (SEG16) PD6 31 28 (SEG17) PD5 30 27 (SEG19) PD3 33 PG0 (SEG14) (SEG20) PD2 16 26 (OC1B/PCINT14) PB6 25 34 PG1 (SEG13) (INT0/SEG21) PD1 15 (ICP1/SEG22) PD0 (OC1A/PCINT13) PB5 (TOSC1) XTAL1 35 PC0 (SEG12) 24 14 23 (OC0A/PCINT12) PB4 22 36 PC1 (SEG11) GND 13 (TOSC2) XTAL2 (MISO/PCINT11) PB3 VCC 21 37 PC2 (SEG10) RESET/PG5 20 38 PC3 (SEG9) 12 (T0/SEG23) PG4 19 11 (T1/SEG24) PG3 18 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (OC2A/PCINT15) PB7 17 Note: 41 PC6 (SEG6) ATmega329/649 The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 3 2552HS–AVR–11/06 Overview The ATmega329/3290/649/6490 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega329/3290/649/6490 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram PF0 - PF7 VCC DATA DIR. REG. PORTF DATA REGISTER PORTF PC0 - PC7 PA0 - PA7 PORTA DRIVERS PORTF DRIVERS PORTC DRIVERS DATA DIR. REG. PORTA DATA REGISTER PORTA XTAL1 GND XTAL2 Figure 3. Block Diagram DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC AGND CALIB. OSC ADC INTERNAL OSCILLATOR AREF STACK POINTER WATCHDOG TIMER ON-CHIP DEBUG PROGRAM FLASH SRAM MCU CONTROL REGISTER BOUNDARYSCAN INSTRUCTION REGISTER LCD CONTROLLER/ DRIVER TIMER/ COUNTERS GENERAL PURPOSE REGISTERS X PROGRAMMING LOGIC INSTRUCTION DECODER CONTROL LINES + - ANALOG COMPARATOR Z INTERRUPT UNIT ALU EEPROM Y STATUS REGISTER AVR CPU USART UNIVERSAL SERIAL INTERFACE DATA REGISTER PORTE DATA DIR. REG. PORTE PORTE DRIVERS PE0 - PE7 4 TIMING AND CONTROL RESET DATA DIR. REG. PORTH DATA REGISTER PORTH PROGRAM COUNTER DATA DIR. REG. PORTJ DATA REGISTER PORTJ PORTH DRIVERS PORTJ DRIVERS PJ0 - PJ6 PH0 - PH7 OSCILLATOR JTAG TAP SPI DATA REGISTER PORTB DATA DIR. REG. PORTB PORTB DRIVERS PB0 - PB7 DATA REGISTER PORTD DATA DIR. REG. PORTD PORTD DRIVERS PD0 - PD7 DATA REG. PORTG DATA DIR. REG. PORTG PORTG DRIVERS PG0 - PG4 ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega329/3290/649/6490 provides the following features: 32/64K bytes of InSystem Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, a complete On-chip LCD controller with internal contrast control, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer and the LCD controller continues to run, allowing the user to maintain a timer base and operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with lowpower consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega329/3290/649/6490 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega329/3290/649/6490 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 5 2552HS–AVR–11/06 Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490 The ATmega329, ATmega3290, ATmega649, and ATmega6490 differs only in memory sizes, pin count and pinout. Table 1 on page 6 summarizes the different configurations for the four devices. Table 1. Configuration Summary Device Flash EEPROM RAM LCD Segments General Purpose I/O Pins ATmega329 32K bytes 1K bytes 2K bytes 4 x 25 54 ATmega3290 32K bytes 1K bytes 2K bytes 4 x 40 69 ATmega649 64K bytes 2K bytes 4K bytes 4 x 25 54 ATmega6490 64K bytes 2K bytes 4K bytes 4 x 40 69 Pin Descriptions The following section describes the I/O-pin special functions. VCC Digital supply voltage. GND Ground. Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 67. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 68. Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega329/3290/649/6490 as listed on page 71. Port D (PD7..PD0) 6 Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 Port D also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 73. Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 75. Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. Port G (PG5..PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 75. Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega3290/6490 as listed on page 75. Port J (PJ6..PJ0) Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3290/6490 as listed on page 75. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 16 on page 41. Shorter pulses are not guaranteed to generate a reset. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 7 2552HS–AVR–11/06 XTAL2 Output from the inverting Oscillator amplifier. AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. AREF This is the analog reference pin for the A/D Converter. LCDCAP An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Figure 99. This capacitor acts as a reservoir for LCD power (VLCD). A large capacitance reduces ripple on VLCD but increases the time until VLCD reaches its target value. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 8 ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 Register Summary Note: Registers with bold type only available in ATmega3290/6490. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xFF) LCDDR19 SEG339 SEG338 SEG337 SEG336 SEG335 SEG334 SEG333 SEG332 234 (0xFE) LCDDR18 SEG331 SEG330 SEG329 SEG328 SEG327 SEG326 SEG325 SEG324 234 (0xFD) LCDDR17 SEG323 SEG322 SEG321 SEG320 SEG319 SEG318 SEG317 SEG316 234 (0xFC) LCDDR16 SEG315 SEG314 SEG313 SEG312 SEG311 SEG310 SEG309 SEG308 234 (0xFB) LCDDR15 SEG307 SEG306 SEG305 SEG304 SEG303 SEG302 SEG301 SEG300 234 (0xFA) LCDDR14 SEG239 SEG238 SEG237 SEG236 SEG235 SEG234 SEG233 SEG232 234 (0xF9) LCDDR13 SEG231 SEG230 SEG229 SEG228 SEG227 SEG226 SEG225 SEG224 234 (0xF8) LCDDR12 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 234 (0xF7) LCDDR11 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 234 (0xF6) LCDDR10 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 234 (0xF5) LCDDR09 SEG139 SEG138 SEG137 SEG136 SEG135 SEG134 SEG133 SEG132 234 (0xF4) LCDDR08 SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 234 (0xF3) LCDDR07 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 234 (0xF2) LCDDR06 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 234 (0xF1) LCDDR05 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 234 (0xF0) LCDDR04 SEG039 SEG038 SEG037 SEG036 SEG035 SEG034 SEG033 SEG032 234 (0xEF) LCDDR03 SEG031 SEG030 SEG029 SEG028 SEG027 SEG026 SEG025 SEG024 234 (0xEE) LCDDR02 SEG023 SEG022 SEG021 SEG020 SEG019 SEG018 SEG017 SEG016 234 (0xED) LCDDR01 SEG015 SEG014 SEG013 SEG012 SEG011 SEG010 SEG009 SEG008 234 (0xEC) LCDDR00 SEG007 SEG006 SEG005 SEG004 SEG003 SEG002 SEG001 SEG000 234 (0xEB) Reserved - - - - - - - - (0xEA) Reserved - - - - - - - - (0xE9) Reserved - - - - - - - - (0xE8) Reserved - - - - - - - - (0xE7) LCDCCR LCDDC2 LCDDC1 LCDDC0 - LCDCC3 LCDCC2 LCDCC1 LCDCC0 (0xE6) LCDFRR - LCDPS2 LCDPS1 LCDPS0 - LCDCD2 LCDCD1 LCDCD0 231 (0xE5) LCDCRB LCDCS LCD2B LCDMUX1 LCDMUX0 LCDPM3 LCDPM2 LCDPM1 LCDPM0 229 229 233 (0xE4) LCDCRA LCDEN LCDAB - LCDIF LCDIE - - LCDBL (0xE3) Reserved - - - - - - - - (0xE2) Reserved - - - - - - - - (0xE1) Reserved - - - - - - - - (0xE0) Reserved - - - - - - - - (0xDF) Reserved - - - - - - - - (0xDE) Reserved - - - - - - - - (0xDD) PORTJ - PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 88 (0xDC) DDRJ - DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 88 (0xDB) PINJ - PINJ6 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 88 (0xDA) PORTH PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 88 (0xD9) DDRH DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 88 (0xD8) PINH PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 88 (0xD7) Reserved - - - - - - - - (0xD6) Reserved - - - - - - - - (0xD5) Reserved - - - - - - - - (0xD4) Reserved - - - - - - - - (0xD3) Reserved - - - - - - - - (0xD2) Reserved - - - - - - - - (0xD1) Reserved - - - - - - - - (0xD0) Reserved - - - - - - - - (0xCF) Reserved - - - - - - - - (0xCE) Reserved - - - - - - - - (0xCD) Reserved - - - - - - - - (0xCC) Reserved - - - - - - - - (0xCB) Reserved - - - - - - - - (0xCA) Reserved - - - - - - - - (0xC9) Reserved - - - - - - - - (0xC8) Reserved - - - - - - - - (0xC7) Reserved - - - - - - - - (0xC6) UDR0 (0xC5) UBRR0H (0xC4) UBRR0L (0xC3) Reserved USART0 Data Register 179 USART0 Baud Rate Register High 182 USART0 Baud Rate Register Low - - - - - 182 - - - 9 2552HS–AVR–11/06 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xC2) UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 181 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 180 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 179 10 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) Reserved - - - - - - - - (0xBC) Reserved - - - - - - - - (0xBB) Reserved - - - - - - - - (0xBA) USIDR (0xB9) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 195 (0xB8) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 196 USI Data Register 194 (0xB7) Reserved - - - - - - - - (0xB6) ASSR - - - EXCLK AS2 TCN2UB OCR2UB TCR2UB (0xB5) Reserved - - - - - - - - (0xB4) Reserved - - - - - - - - (0xB3) OCR2A Timer/Counter 2 Output Compare Register A 146 (0xB2) TCNT2 Timer/Counter2 146 (0xB1) Reserved - - - - - - - - (0xB0) TCCR2A FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 (0xAF) Reserved - - - - - - - - 147 144 (0xAE) Reserved - - - - - - - - (0xAD) Reserved - - - - - - - - (0xAC) Reserved - - - - - - - - (0xAB) Reserved - - - - - - - - (0xAA) Reserved - - - - - - - - (0xA9) Reserved - - - - - - - - (0xA8) Reserved - - - - - - - - (0xA7) Reserved - - - - - - - - (0xA6) Reserved - - - - - - - - (0xA5) Reserved - - - - - - - - (0xA4) Reserved - - - - - - - - (0xA3) Reserved - - - - - - - - (0xA2) Reserved - - - - - - - - (0xA1) Reserved - - - - - - - - (0xA0) Reserved - - - - - - - - (0x9F) Reserved - - - - - - - - (0x9E) Reserved - - - - - - - - (0x9D) Reserved - - - - - - - - (0x9C) Reserved - - - - - - - - (0x9B) Reserved - - - - - - - - (0x9A) Reserved - - - - - - - - (0x99) Reserved - - - - - - - - (0x98) Reserved - - - - - - - - (0x97) Reserved - - - - - - - - (0x96) Reserved - - - - - - - - (0x95) Reserved - - - - - - - - (0x94) Reserved - - - - - - - - (0x93) Reserved - - - - - - - - (0x92) Reserved - - - - - - - - (0x91) Reserved - - - - - - - - (0x90) Reserved - - - - - - - - (0x8F) Reserved - - - - - - - - (0x8E) Reserved - - - - - - - - (0x8D) Reserved - - - - - - - - (0x8C) Reserved - - - - - - - - (0x8B) OCR1BH Timer/Counter1 Output Compare Register B High (0x8A) OCR1BL Timer/Counter1 Output Compare Register B Low 130 (0x89) OCR1AH Timer/Counter1 Output Compare Register A High 130 (0x88) OCR1AL Timer/Counter1 Output Compare Register A Low 130 (0x87) ICR1H Timer/Counter1 Input Capture Register High 130 (0x86) ICR1L Timer/Counter1 Input Capture Register Low 130 (0x85) TCNT1H Timer/Counter1 High 130 (0x84) TCNT1L Timer/Counter1 Low 130 130 ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x83) Reserved - - - - - - - - Page (0x82) TCCR1C FOC1A FOC1B - - - - - - 129 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 128 126 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 201 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 218 (0x7D) Reserved - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 214 (0x7B) ADCSRB - ACME - - - ADTS2 ADTS1 ADTS0 199/217 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH ADC Data Register High 216 217 (0x78) ADCL (0x77) Reserved - - - ADC Data Register Low - - - - - 217 (0x76) Reserved - - - - - - - - (0x75) Reserved - - - - - - - - (0x74) Reserved - - - - - - - - (0x73) PCMSK3 - PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 (0x72) Reserved - - - - - - - - (0x71) Reserved - - - - - - - - (0x70) TIMSK2 - - - - - - OCIE2A TOIE2 (0x6F) TIMSK1 - - ICIE1 - - OCIE1B OCIE1A TOIE1 131 (0x6E) TIMSK0 - - - - - - OCIE0A TOIE0 102 (0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 58 (0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 58 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 58 (0x6A) Reserved - - - - - - - - (0x69) EICRA - - - - - - ISC01 ISC00 (0x68) Reserved - - - - - - - - (0x67) Reserved - - - - - - - - (0x66) OSCCAL (0x65) Reserved - - - - - - - - (0x64) PRR - - - PRLCD PRTIM1 PRSPI PSUSART0 PRADC (0x63) Reserved - - - - - - - - (0x62) Reserved - - - - - - - - (0x61) CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 31 (0x60) WDTCR - - - WDCE WDE WDP2 WDP1 WDP0 46 I T H S V N Z C 11 Oscillator Calibration Register [CAL7..0] 57 149 55 29 38 0x3F (0x5F) SREG 0x3E (0x5E) SPH Stack Pointer High 0x3D (0x5D) SPL Stack Pointer Low 0x3C (0x5C) Reserved - - - - - - - - 0x3B (0x5B) Reserved - - - - - - - - 0x3A (0x5A) Reserved - - - - - - - - 0x39 (0x59) Reserved - - - - - - - - 0x38 (0x58) Reserved - - - - - - - - 0x37 (0x57) SPMCSR SPMIE RWWSB - RWWSRE BLBSET PGWRT PGERS SPMEN 271 0x36 (0x56) Reserved 52/67/244 13 13 0x35 (0x55) MCUCR JTD - - PUD - - IVSEL IVCE 0x34 (0x54) MCUSR - - - JTRF WDRF BORF EXTRF PORF 44 0x33 (0x53) SMCR - - - - SM2 SM1 SM0 SE 38 0x32 (0x52) Reserved - - - - - - - - 0x31 (0x51) OCDR IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 240 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 199 0x2F (0x4F) Reserved - - - - - - - - 0x2E (0x4E) SPDR 0x2D (0x4D) SPSR SPIF WCOL - - - - - SPI2X 159 0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 157 0x2B (0x4B) GPIOR2 General Purpose I/O Register 0x2A (0x4A) GPIOR1 General Purpose I/O Register 0x29 (0x49) Reserved - - - 0x28 (0x48) Reserved - - - 0x27 (0x47) OCR0A Timer/Counter0 Output Compare A 102 0x26 (0x46) TCNT0 Timer/Counter0 101 0x25 (0x45) Reserved SPI Data Register - - - 159 24 24 - - - - - - - - - - - - - - - 11 2552HS–AVR–11/06 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 99 0x23 (0x43) GTCCR TSM - - - - - PSR2 PSR10 104/151 0x22 (0x42) EEARH - - - - - 0x21 (0x41) EEARL EEPROM Address Register Low 0x20 (0x40) EEDR EEPROM Data Register 0x1F (0x3F) EECR - - - - EERIE Page EEPROM Address Register High 20 20 20 EEMWE EEWE EERE 20 0x1E (0x3E) GPIOR0 0x1D (0x3D) EIMSK PCIE3 PCIE2 PCIE1 General Purpose I/O Register PCIE0 - - - INT0 24 56 0x1C (0x3C) EIFR PCIF3 PCIF2 PCIF1 PCIF0 - - - INTF0 57 0x1B (0x3B) Reserved - - - - - - - - 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 0x18 (0x38) Reserved - - - - - - - - 0x17 (0x37) TIFR2 - - - - - - OCF2A TOV2 149 0x16 (0x36) TIFR1 - - ICF1 - - OCF1B OCF1A TOV1 131 0x15 (0x35) TIFR0 - - - - - - OCF0A TOV0 102 0x14 (0x34) PORTG - - - PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 88 0x13 (0x33) DDRG - - - DDG4 DDG3 DDG2 DDG1 DDG0 88 0x12 (0x32) PING - - PING5 PING4 PING3 PING2 PING1 PING0 88 0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 87 0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 87 0x0F (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 87 0x0E (0x2E) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 87 0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 87 0x0C (0x2C) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 87 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 87 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 87 87 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 86 0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 86 0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 86 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 86 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 86 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 86 0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 86 0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 86 0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 86 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega329/3290/649/6490 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 12 ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 Z,C 2 Z,C 2 Z,C 2 2 FMULS Rd, Rr Fractional Multiply Signed FMULSU Rd, Rr Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS RJMP k IJMP Relative Jump PC ← PC + k + 1 None Indirect Jump to (Z) PC ← Z None 2 JMP k Direct Jump PC ← k None 3 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 Indirect Call to (Z) PC ← Z None 3 Direct Subroutine Call PC ← k None 4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 ICALL CALL k CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 1/2/3 1 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 13 2552HS–AVR–11/06 Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C←1 C 1 CLC Clear Carry C←0 C 1 SEN Set Negative Flag N←1 N 1 CLN Clear Negative Flag N←0 N 1 SEZ Set Zero Flag Z←1 Z 1 CLZ Clear Zero Flag Z←0 Z 1 SEI Global Interrupt Enable I←1 I 1 CLI Global Interrupt Disable I←0 I 1 SES Set Signed Test Flag S←1 S 1 CLS Clear Signed Test Flag S←0 S 1 SEV Set Twos Complement Overflow. V←1 V 1 CLV Clear Twos Complement Overflow V←0 V 1 SET Set T in SREG T←1 T 1 CLT Clear T in SREG T←0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H←1 H←0 H H 1 1 Rd ← Rr Rd+1:Rd ← Rr+1:Rr None 1 None 1 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd ← K None LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 Load Program Memory R0 ← (Z) None 3 LPM LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 Store Program Memory (Z) ← R1:R0 None - IN Rd, P In Port Rd ← P None 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 SPM 14 ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 Mnemonics POP Operands Rd Description Pop Register from Stack Operation Rd ← STACK Flags #Clocks None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/timer) For On-chip Debug Only None None 1 N/A 15 2552HS–AVR–11/06 Ordering Information ATmega329 Speed (MHz)(3) 8 16 Notes: Ordering Code Package Type(1) 1.8 - 5.5V ATmega329V-8AI ATmega329V-8AU(2) ATmega329V-8MI ATmega329V-8MU(2) 64A 64A 64M1 64M1 Industrial (-40°C to 85°C) 2.7 - 5.5V ATmega329-16AI ATmega329-16AU(2) ATmega329-16MI ATmega329-16MU(2) 64A 64A 64M1 64M1 Industrial (-40°C to 85°C) Power Supply Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see Figure 138 on page 314 and Figure 139 on page 315. Package Type 64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 16 ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 ATmega3290 Speed (MHz)(3) Power Supply 8 16 Notes: Ordering Code Package Type(1) 1.8 - 5.5V ATmega3290V-8AI ATmega3290V-8AU(2) 100A 100A Industrial (-40°C to 85°C) 2.7 - 5.5V ATmega3290-16AI ATmega3290-16AU(2) 100A 100A Industrial (-40°C to 85°C) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see Figure 138 on page 314 and Figure 139 on page 315. Package Type 64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 17 2552HS–AVR–11/06 ATmega649 Speed (MHz)(3) 8 16 Notes: Ordering Code Package Type(1) 1.8 - 5.5V ATmega649V-8AI ATmega649V-8AU(2) ATmega649V-8MI ATmega649V-8MU(2) 64A 64A 64M1 64M1 Industrial (-40°C to 85°C) 2.7 - 5.5V ATmega649-16AI ATmega649-16AU(2) ATmega649-16MI ATmega649-16MU(2) 64A 64A 64M1 64M1 Industrial (-40°C to 85°C) Power Supply Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see Figure 138 on page 314 and Figure 139 on page 315. Package Type 64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 18 ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 ATmega6490 Speed (MHz)(3) Power Supply 8 16 Notes: Ordering Code Package Type(1) 1.8 - 5.5V ATmega6490V-8AI ATmega6490V-8AU(2) 100A 100A Industrial (-40°C to 85°C) 2.7 - 5.5V ATmega6490-16AI ATmega6490-16AU(2) 100A 100A Industrial (-40°C to 85°C) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see Figure 138 on page 314 and Figure 139 on page 315. Package Type 64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 19 2552HS–AVR–11/06 Packaging Information 64A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e NOTE Note 2 Note 2 0.80 TYP 10/5/2001 R 20 2325 Orchard Parkway San Jose, CA 95131 TITLE 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 64A B ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 64M1 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A K 0.08 C L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 – 0.02 0.05 0.18 0.25 0.30 A1 b K Option C b e Pin #1 Notch (0.20 R) BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. D 8.90 9.00 9.10 D2 5.20 5.40 5.60 E 8.90 9.00 9.10 E2 5.20 5.40 5.60 e NOTE 0.50 BSC L 0.35 0.40 0.45 K 1.25 1.40 1.55 5/25/06 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 64M1 REV. G 21 2552HS–AVR–11/06 100A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 B 0.17 – 0.27 C 0.09 – 0.20 L 0.45 – 0.75 e NOTE Note 2 Note 2 0.50 TYP 10/5/2001 R 22 2325 Orchard Parkway San Jose, CA 95131 TITLE 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 100A REV. C ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 Errata ATmega329 rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Wortkaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2. ATmega329 rev. B Not sampled. ATmega329 rev. A • LCD contrast voltage too high • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. LCD contrast voltage too high When the LCD is active and using low power waveform, the LCD contrast voltage can be too high. This occurs when VCC is higher than VLCD, and when using low LCD drivetime. Problem Fix/Workaround There are several possible workarounds: - Use normal waveform instead of low power waveform - Use drivetime of 375 µs or longer 2. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Wortkaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2. 23 2552HS–AVR–11/06 ATmega3290 rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Wortkaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2. ATmega3290 rev. B Not sampled. ATmega3290 rev. A • LCD contrast voltage too high • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. LCD contrast voltage too high When the LCD is active and using low power waveform, the LCD contrast voltage can be too high. This occurs when VCC is higher than VLCD, and when using low LCD drivetime. Problem Fix/Workaround There are several possible workarounds: - Use normal waveform instead of low power waveform - Use drivetime of 375 µs or longer 2. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Wortkaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2. 24 ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 ATmega649 rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Wortkaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2. ATmega6490 rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Wortkaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2. 25 2552HS–AVR–11/06 Datasheet Revision History Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision. Rev. 2552H – 11/06 1. 2. Updated Table 141 on page 318. Updated note in Table 141 on page 318 and Table 143 on page 319. 1. 2. 3. 4. 5. Updated Table 55 on page 100, Table 57 on page 100, Table 62 on page 127, Table 64 on page 128, Table 64 on page 128, Table 67 on page 144 and Table 69 on page 145. Updated “Fast PWM Mode” on page 118. Updated Features in “USI – Universal Serial Interface” on page 187. Added “Clock speed considerations.” on page 194. “Errata” on page 364. 1. 2. 3. Updated “Calibrated Internal RC Oscillator” on page 28. Updated “OSCCAL – Oscillator Calibration Register” on page 29 Added Table 143 on page 319. 1. Updated “Calibrated Internal RC Oscillator” on page 28. 1. Updated “Errata” on page 364. 1. 2. 3. 4. Added “Resources” on page 8. Added Addresses in Registers. Updated number of General Purpose I/O pins. Updated code example in “Bit 0 – IVCE: Interrupt Vector Change Enable” on page 52. Updated Introduction in “I/O-Ports” on page 59. Updated “SPI – Serial Peripheral Interface” on page 152. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 201. Updated Features in “Analog to Digital Converter” on page 203. Updated “Prescaling and Conversion Timing” on page 206. Updated features in “LCD Controller” on page 220. Updated “ATmega329/3290/649/6490 Boot Loader Parameters” on page 280. Updated “DC Characteristics” on page 310. Updated “LCD Controller Characteristics – Preliminary Data – TBD” on page 319. Rev. 2552G – 07/06 Rev. 2552F – 06/06 Rev. 2552E – 04/06 Rev. 2552D – 03/06 Rev. 2552C – 03/06 5. 6. 7. 8. 9. 10. 11. 12. 13. 26 ATmega329/3290/649/6490 2552HS–AVR–11/06 ATmega329/3290/649/6490 Rev. 2552B – 05/05 1. 4. 5. 6. 7. 8. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF”. Added “Pin Change Interrupt Timing” on page 54. Updated Table 104 on page 233, Table 105 on page 234 and Table 137 on page 299. Added Figure 131 on page 300. Updated Figure 92 on page 211 and Figure 124 on page 292. Updated algorithm “Enter Programming Mode” on page 287. Added “Supply Current of I/O modules” on page 325. Updated “Ordering Information” on page 357. 1. Initial version. 2. 3. Rev. 2552A –11/04 27 2552HS–AVR–11/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2006 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof, Everywhere You Are®, AVR ®, and AVR Studio ® are registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 2552HS–AVR–11/06