XILINX XCR5128

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XCR5128: 128 Macrocell CPLD
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Product Specification
Features
Description
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The XCR5128 CPLD (Complex Programmable Logic
Device) is the third in a family of CoolRunner® CPLDs from
Xilinx. These devices combine high speed and zero power
in a 128 macrocell CPLD. With the FZP design technique,
the XCR5128 offers true pin-to-pin speeds of 7.5 ns, while
simultaneously delivering power that is less than 100 µA at
standby without the need for ‘turbo bits' or other power
down schemes. By replacing conventional sense amplifier
methods for implementing product terms (a technique that
has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is
also substantially lower than any competing CPLD. These
devices are the first TotalCMOS PLDs, as they use both a
CMOS process technology and the patented full CMOS
FZP design technique. For 3V applications, Xilinx also
offers the high-speed XCR3128 CPLD that offers these features in a full 3V implementation.
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Industry's first TotalCMOS™ PLD - both CMOS design
and process technologies
Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
IEEE 1149.1-compliant, JTAG Testing Capability
- Four pin JTAG interface (TCK, TMS, TDI, TDO)
- IEEE 1149.1 TAP Controller
- JTAG commands include: Bypass, Sample/Preload,
Extest, Usercode, Idcode, HighZ
5V, In-System Programmable (ISP) using the JTAG
interface
- On-chip supervoltage generation
- ISP commands include: Enable, Erase, Program,
Verify
- Supported by multiple ISP programming platforms
High speed pin-to-pin delays of 7.5 ns
Ultra-low static power of less than 100 µA
100% routable with 100% utilization while all pins and
all macrocells are fixed
Deterministic timing model that is extremely simple to
use
Four clocks available
Programmable clock polarity at every macrocell
Support for asynchronous clocking
Innovative XPLA™ architecture combines high speed
with extreme flexibility
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Logic expandable to 37 product terms
PCI compliant
Advanced 0.5µ E2CMOS process
Security bit prevents unauthorized access
Design entry and verification using industry standard
and Xilinx CAE tools
Reprogrammable using industry standard device
programmers
Innovative Control Term structure provides either sum
terms or product terms in each logic block for:
- Programmable 3-state buffer
- Asynchronous macrocell register preset/reset
Programmable global 3-state pin facilitates "bed of
nails" testing without using logic resources
Available in PLCC, VQFP, and PQFP packages
Available in both Commercial and Industrial grades
DS041 (v1.4) January 19, 2001
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combines the best features of both PLA
and PAL type structures to deliver high speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 7.5 ns PAL path with five
dedicated product terms per output. This PAL path is joined
by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product terms to any output in the logic
block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as
37 product terms on an output. The speed with which logic
is allocated from the PLA array to an output is only 2 ns,
regardless of the number of PLA product terms used, which
results in worst case tPD's of only 9.5 ns from any pin to any
other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and
shared across multiple outputs via the OR array, effectively
increasing design density.
The XCR5128 CPLDs are supported by industry standard
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional
and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting
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XCR5128: 128 Macrocell CPLD
uses a Xilinx developed tool, XPLA Professional (available
on the Xilinx web site).
architecture consists of logic blocks that are interconnected
by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths
from the macrocells and I/O pins.
The XCR5128 CPLD is electrically reprogrammable using
industry standard device programmers from vendors such
as Data I/O, BP Microsystems, SMS, and others. The
XCR5128 also includes an industry-standard, IEEE
1149.1, JTAG interface through which in-system programming (ISP) and reprogramming of the device is supported.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
XPLA Architecture
Figure 1 shows a high level block diagram of a 128 macrocell device implementing the XPLA architecture. The XPLA
MC1
MC2
I/O
MC1
LOGIC
BLOCK
36
36
16
16
16
16
36
36
16
16
16
16
LOGIC
BLOCK
MC16
I/O
MC1
LOGIC
BLOCK
LOGIC
BLOCK
MC16
I/O
ZIA
LOGIC
BLOCK
36
16
16
16
16
36
36
16
16
16
16
LOGIC
BLOCK
MC2
I/O
MC16
MC1
I/O
I/O
MC1
36
MC16
MC2
MC2
MC16
MC1
MC2
I/O
MC16
MC1
MC2
MC2
MC1
LOGIC
BLOCK
MC16
LOGIC
BLOCK
MC2
I/O
MC16
SP00464
Figure 1: Xilinx XPLA CPLD Architecture
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XCR5128: 128 Macrocell CPLD
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
16 macrocells. the six control terms can individually be configured as either SUM or PRODUCT terms, and are used to
control the preset/reset and output enables of the 16 macrocells’ flip-flops. The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array
consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased
product term density.
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Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin tPD of the XCR5128 device
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using one or all 32 PLA product terms is just 2 ns. So
the total pin-to-pin tPD for the XCR5128 using six to 37
product terms is 9.5 ns (7.5 ns for the PAL + 2 ns for the
PLA)
.
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XCR5128: 128 Macrocell CPLD
36 ZIA INPUTS
6
CONTROL
TO 16 MACROCELLS
5
PAL
ARRAY
PLA
ARRAY
(32)
SP00435A
Figure 2: Xilinx XPLA Logic Block Architecture
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XCR5128: 128 Macrocell CPLD
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in
the CoolRunner family. The macrocell consists of a flip-flop
that can be configured as either a D- or T- type. A D-type
flip-flop is generally more useful for implementing state
machines and data buffering. A T-type flip-flop is generally
more useful in implementing counters. All CoolRunner family members provide both synchronous and asynchronous
clocking and provide the ability to clock off either the falling
or rising edges of these clocks. These devices are
designed such that the skew between the rising and falling
edges of a clock are minimized for clocking integrity. There
are four clocks available on the XCR5128 device. Clock 0
(CLK0) is designated as the "synchronous" clock and must
be driven by an external source. Clock 1 (CLK1), Clock 2
(CLK2), and Clock 3 (CLK3) can either be used as a synchronous clock (driven by an external source) or as an
asynchronous clock (driven by a macrocell equation). The
timing for asynchronous clocks is different in that the tCO
time is extended by the amount of time that it takes for the
signal to propagate through the array and reach the clock
network, and the tSU time is reduced.
Two of the control terms (CT0 and CT1) are used to control
the Preset/Reset of the macrocell’s flip-flop. The Preset/Reset feature for each macrocell can also be disabled.
Note that the Power-on Reset leaves all macrocells in the
"zero" state when power is properly applied. The other four
control terms (CT2-CT5) can be used to control the Output
Enable of the macrocell’s output buffers. The reason there
are as many control terms dedicated for the Output Enable
of the macrocell is to insure that all CoolRunner devices are
PCI compliant. The macrocell’s output buffers can also be
always enabled or disabled. All CoolRunner devices also
provide a Global 3-State (GTS) pin, which, when enabled
and pulled Low, will 3-state all the outputs of the device.
This pin is provided to support "In-Circuit Testing" or
"Bed-of-Nails Testing".
There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path
before the output buffer is the macrocell feedback path,
while the ZIA feedback path after the output buffer is the I/O
pin ZIA path. When the macrocell is used as an output, the
output buffer is enabled, and the macrocell feedback path
can be used to feedback the logic implemented in the macrocell. When the I/O pin is used as an input, the output
buffer will be 3-stated and the input signal will be fed into
the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA
via the macrocell feedback path. It should be noted that
unused inputs or I/Os should be properly terminated (see
the section on Terminations in this data sheet and the application note: Terminating Unused I/O Pins in xilinx XPLA1
and XPLA2 CPLDs).
TO ZIA
PAL
PLA
D/T
Q
INIT
(P or R)
GTS
CLK0
CLK0
GND
CT0
CLK1
CLK1
CT1
CLK2
CLK2
GND
CLK3
CLK3
CT2
CT3
CT4
CT5
VCC
GND
SP00457
Figure 3: XCR5128 Macrocell Architecture
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XCR5128: 128 Macrocell CPLD
Simple Timing Model
TotalCMOS Design Technique for Fast Zero
Power
Figure 4 shows the CoolRunner Timing Model. The CoolRunner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including tPD, tSU, and tCO. In other competing architectures, the user may be able to fit the design into the CPLD,
but is not sure whether system timing requirements can be
met until after the design has been fit into the device. This is
because the timing models of competing architectures are
very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model.
tPD_PAL = COMBINATORIAL PAL ONLY
tPD_PLA = COMBINATORIAL PAL + PLA
INPUT PIN
INPUT PIN
Xilinx is the first to offer a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 5 and Table 1 showing the ICC vs.
Frequency of Xilinx’ XCR5128 TotalCMOS CPLD (data
taken w/eight up/down, loadable 16 bit counters at 5V,
25°C.
REGISTERED
tSU_PAL = PAL ONLY
tSU_PLA = PAL + PLA
D
GLOBAL CLOCK PIN
Q
REGISTERED
tCO
OUTPUT PIN
OUTPUT PIN
SP00441
Figure 4: CoolRunner Timing Model
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XCR5128: 128 Macrocell CPLD
120
100
80
ICC
(mA)
60
40
20
0
0
20
40
60
80
100
120
FREQUENCY (MHz)
SP00465
Figure 5: ICC vs. Frequency at VCC = 5V, 25°C
Table 1: ICC vs. Frequency (VCC = 5V, 25°C)
Frequency (MHz)
Typical ICC (mA)
0
0.5
1
1
20
20
JTAG Testing Capability
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JTAG is the commonly-used acronym for the Boundary
Scan Test (BST) feature defined for integrated circuits by
IEEE Standard 1149.1. This standard defines input/output
pins, logic control functions, and commands which facilitate
both board and device level testing without the use of specialized test equipment. BST provides the ability to test the
external connections of a device, test the internal logic of
the device, and capture data from the device during normal
operation. BST provides a number of benefits in each of the
following areas:
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Testability
- Allows testing of an unlimited number of
interconnects on the printed circuit board
- Testability is designed in at the component level
- Enables desired signal levels to be set at specific
pins (Preload)
- Data from pin or core logic signals can be examined
during normal operation
Reliability
- Eliminates physical contacts common to existing test
fixtures (e.g., "bed-of-nails")
- Degradation of test equipment is no longer a
concern
- Facilitates the handling of smaller, surface-mount
components
- Allows for testing when components exist on both
sides of the printed circuit board
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60
80
80
100
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120
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Cost
- Reduces/eliminates the need for expensive test
equipment
- Reduces test preparation time
- Reduces spare board inventories
The Xilinx XCR5128's JTAG interface includes a TAP Port
and a TAP Controller, both of which are defined by the IEEE
1149.1 JTAG Specification. As implemented in the Xilinx
XCR5128, the TAP Port includes four of the five pins (refer
to Table 2) described in the JTAG specification: TCK, TMS,
TDI, and TDO. The fifth signal defined by the JTAG specification is TRST* (Test Reset). TRST* is considered an
optional signal, since it is not actually required to perform
BST or ISP. The Xilinx XCR5128 saves an I/O pin for general purpose use by not implementing the optional TRST*
signal in the JTAG interface. Instead, the Xilinx XCR5128
supports the test reset functionality through the use of its
power up reset circuit, which is included in all Xilinx CPLDs.
The pins associated with the power up reset circuit should
connect to an external pull-up resistor to keep the JTAG
signals from floating when they are not being used.
In the Xilinx XCR5128, the four mandatory JTAG pins each
require a unique, dedicated pin on the device. However, if
JTAG and ISP are not desired in the end-application, these
pins may instead be used as additional general I/O pins.
The decision as to whether these pins are used for
JTAG/ISP or as general I/O is made when the JEDEC file is
generated. If the use of JTAG/ISP is selected, the dedi-
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XCR5128: 128 Macrocell CPLD
cated pins are not available for general purpose use. However, unlike competing CPLD’s, the Xilinx XCR5128 does
allow the macrocell logic associated with these dedicated
pins to be used as buried logic even when JTAG/ISP is
selected. Table 3 defines the dedicated pins used by the
four mandatory JTAG signals for each of the XCR5128
package types.
JTAG specifications define two sets of commands to support boundary-scan testing: high-level commands and
low-level commands. High-level commands are executed
via board test software on an a user test station such as
automated test equipment, a PC, or an engineering workstation (EWS). Each high-level command comprises a
sequence of low level commands. These low-level commands are executed within the component under test, and
therefore must be implemented as part of the TAP Controller design. The set of low-level boundary-scan commands
implemented in the Xilinx XCR5128 is defined in Table 4.
By supporting this set of low-level commands, the
XCR5128 allows execution of all high-level boundary-scan
commands.
Table 2: JTAG Pin Description
Pin
TCK
Name
Test Clock Output
TMS
Test Mode Select
TDI
Test Data Input
TDO
Test Data Output
Description
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins,
respectively. TCK is also used to clock the TAP Controller state machine.
Serial input pin selects the JTAG instruction mode. TMS should be driven high
during user mode operation.
Serial input pin for instructions and test data. Data is shifted in on the rising edge of
TCK.
Serial output pin for instructions and test data. Data is shifted out on the falling edge
of TCK. The signal is tri-stated if data is not being shifted out of the device.
Table 3: XCR5128 JTAG Pinout by Package Type
(Pin Number / Macrocell #)
Device
PZ5128
TCK
62 / 96 (F15)
64 / 96 (F15)
62 / 96 (F15)
82 / 96 (F15)
99 / 96 (F15)
84-pin PLCC
100-pin PQFP
100-pin VQFP
128-pin TQFP
160-pin PQFP
TMS
23 / 48 (C15)
17 / 48 (C15)
15 / 48 (C15)
21 / 48 (C15)
22 / 48 (C15)
TDI
14 / 32 (B15)
6 / 32 (B15)
4 / 32 (B15)
8 / 32 (B15)
9 / 32 (B15)
TDO
71 / 112 (G15)
75 / 112 (G15)
73 / 112 (G15)
95 / 112 (G15)
112/ 112 (G15)
Table 4: XCR5128 Low-Level JTAG Boundary-Scan Commands
Instruction
(Instruction Code)
Register Used
Sample/Preload
(0010)
Boundary-Scan Register
Extest
(0000)
Boundary-Scan Register
Bypass
(1111)
Bypass Register
Description
The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal operation
of the component to be taken and examined. It also allows data values to be loaded onto the
latched parallel outputs of the Boundary-Scan Shift-Register prior to selection of the other
boundary-scan test instructions.
The mandatory EXTEST instruction allows testing of off-chip circuitry and board level
interconnections. Data would typically be loaded onto the latched parallel outputs of
Boundary-Scan Shift-Register using the Sample/Preload instruction prior to selection of the
EXTEST instruction.
Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through the selected device to adjacent devices during normal device
operation. The Bypass instruction can be entered by holding TDI at a constant high value
and completing an Instruction-Scan cycle.
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XCR5128: 128 Macrocell CPLD
Table 4: XCR5128 Low-Level JTAG Boundary-Scan Commands
Idcode
(0001)
Boundary-Scan Register
HighZ
(0101)
Bypass Register
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to
be serially shifted out of TDO. The IDCODE instruction permits blind interrogation of the
components assembled onto a printed circuit board. Thus, in circumstances where the
component population may vary, it is possible to determine what components exist in a
product.
The HIGHZ instruction places the component in a state in which all of its system logic outputs
are placed in an inactive drive state (e.g., high impedance). In this state, an in-circuit test
system may drive signals onto the connections normally driven by a component output
without incurring the risk of damage to the component. The HighZ instruction also forces the
Bypass Register between TDI and TDO.
5V, In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit board, or complete electronic system before, during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
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Design
- Faster time-to-market
- Debug partitioning and simplified prototyping
- Printed circuit board reconfiguration during debug
- Better device and board level testing
Manufacturing
- Multi-Functional hardware
- Reconfigurability for Test
- Eliminates handling of "fine lead-pitch" components
for programming
- Reduced Inventory and manufacturing costs
- Improved quality and reliability
Field Support
- Easy remote upgrades and repair
- Support for field configuration, re-configuration, and
customization
The Xilinx XCR5128 allows for 5V, in-system programming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally-provided supervoltages, so that the XCR5128
may be easily programmed on the circuit board using only
the 5V supply required by the device for normal operation.
A set of low-level ISP basic commands implemented in the
XCR5128 enable this feature. The ISP commands implemented in the Xilinx XCR5128 are specified in Table 6.
Please note that an ENABLE command must precede all
ISP commands unless an ENABLE command has already
been given for a preceding ISP command and the device
9
has not gone through a Test-Logic/Rest TAP Controller
State.
Terminations
The CoolRunner XCR5128 CPLDs are TotalCMOS
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the voltage to be in the linear
region of the CMOS input structures, which can increase
the power consumption of the device. The XCR5128
CPLDs have programmable on-chip pull-down resistors on
each I/O pin. These pull-downs are automatically activated
by the fitter software for all unused I/O pins. Note that an I/O
macrocell used as buried logic that does not have the I/O
pin used for input is considered to be unused, and the
pull-down resistors will be turned on. We recommend that
any unused I/O pins on the XCR5128 device be left unconnected.
There are no on-chip pull-down structures associated with
the dedicated input pins. Xilinx recommends that any
unused dedicated inputs be terminated with external 10kΩ
pull-up resistors. These pins can be directly connected to
VCC or GND, but using the external pull-up resistors maintains maximum design flexibility should one of the unused
dedicated inputs be needed due to future design changes.
When using the JTAG/ISP functions, it is also recommended that 10kΩ pull-up resistors be used on each of the
pins associated with the four mandatory JTAG signals. Letting these signals float can cause the voltage on TMS to
come close to ground, which could cause the device to
enter JTAG/ISP mode at unspecified times. See the application notes JTAG and ISP Overview for Xilinx XPLA1 and
XPLA2 CPLDs and Terminating Unused I/O Pins in Xilinx
XPLA1 and XPLA2 CoolRunner CPLDs for more information.
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XCR5128: 128 Macrocell CPLD
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLD’s and other integrated circuits. The Xilinx XCR5128 supports the following methods:
•
•
•
•
PC parallel port
Workstation or PC serial port
Embedded processor
Automated test equipment
•
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Third party programmers
High-End JTAG and ISP tools
A Boundary-Scan Description Language (BSDL) description of the XCR5128 is also available from Xilinx for use in
test program development. For more details on JTAG and
ISP for the XCR5128, refer to the related application note:
JTAG and ISP in Xilinx CPLDs.
Table 5: Low Level ISP Commands
Instruction
(Register Used)
Enable
(ISP Shift Register)
Instruction
Code
1001
Erase
(ISP Shift Register)
Program
(ISP Shift Register)
1010
Verify
(ISP Shift Register)
1011
1100
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Description
Enables the Erase, Program, and Verify commands. Using the ENABLE instruction
before the Erase, Program, and Verify instructions allows the user to specify the
outputs the device using the JTAG Boundary-Scan SAMPLE/PRELOAD
command.
Erases the entire EEPROM array. The outputs during this operation can be defined
by user by using the JTAG SAMPLE/PRELOAD command.
Programs the data in the ISP Shift Register into the addressed EEPROM row. The
outputs during this operation can be defined by user by using the JTAG
SAMPLE/PRELOAD command.
Transfers the data from the addressed row to the ISP Shift Register. The data can
then be shifted out and compared with the JEDEC file. The outputs during this
operation can be defined by user by using the JTAG SAMPLE/PRELOAD
command.
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XCR5128: 128 Macrocell CPLD
Programming Specifications
Symbol
Parameter
DC Parameters
VCCP
VCC supply program/verify
ICCP
ICC limit program/verify
VIH
Input voltage (High)
VIL
Input voltage (Low)
VSOL
Output voltage (Low)
VSOH
Output voltage (High)
TDO_IOL Output current (Low)
TDO_IOH Output current (High)
AC Parameters
fMAX
CLK maximum frequency
PWE
Pulse width erase
PWP
Pulse width program
PWV
Pulse width verify
INIT
Initialization time
TMS_SU TMS setup time before TCK ↑
TDI_SU
TDI setup time before TCK ↑
TMS_H
TMS hold time after TCK ↑
TDI_H
TDI hold time after TCK ↑
TDO_CO TDO valid after TCK ↓
Min.
Max.
Unit
4.5
5.5
200
V
mA
V
V
V
V
mA
mA
2.0
0.8
0.5
2.4
12
-12
10
100
10
10
100
10
10
20
20
30
MHz
ms
ms
µs
µs
ns
ns
ns
ns
ns
Max.
7.0
VCC +0.5
VCC +0.5
30
100
150
150
Unit
V
V
V
mA
mA
5C
5C
Absolute Maximum Ratings1
Symbol
VCC
VI
VOUT
IIN
IOUT
TJ
Tstr
Parameter
Supply voltage2
Input voltage
Output voltage
Input current
Output current
Maximum junction temperature
Storage temperature
Min.
-0.5
-1.2
-0.5
-30
-100
-40
-65
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only.
Functional operation at these or any other condition above those indicated in the operational and programming specification
is not implied.
2. The chip supply voltage must rise monotonically.
Operating Range
Product Grade
Commercial
Industrial
11
Temperature
0 to +70°C
-40 to +85°C
Voltage
5.0V +5%
5.0V +10%
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XCR5128: 128 Macrocell CPLD
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 4.75V ≤ VCC ≤ 5.25V
Symbol
VIL
VIH
VI
VOL
VOH
II
IOZ
ICCQ
ICCD2
Parameter
Input voltage low
Input voltage high
Input clamp voltage
Output voltage low
Output voltage high
Input leakage current
3-stated output leakage current
Standby current
Dynamic current
IOS
Short circuit output current3
CIN
CCLK
CI/O
Input pin capacitance3
Clock input capacitance3
I/O pin capacitance3
Test Conditions
VCC = 4.75V
VCC = 5.25V
VCC = 4.75V, IIN = -18mA
VCC = 4.75V, IOL = 12mA
VCC = 4.75V, IOH = -12mA
VIN = 0 to VCC
VIN = 0 to VCC
V CC = 5.25V, TAMB = 0°C
VCC = 5.25V, TAMB = 0°C at 1 MHz
VCC = 5.25V, TAMB = 0°C at 50 MHz
One pin at a time for no longer than 1
second
T AMB = 25°C, f = 1 MHz
T AMB = 25°C, f = 1 MHz
T AMB = 25°C, f = 1 MHz
Min.
Max.
0.8
10
10
100
5
75
-200
Unit
V
V
V
V
V
µA
µA
µA
mA
mA
mA
8
12
10
pF
pF
pF
2.0
-1.2
0.5
2.4
-10
-10
-50
5
Notes:
1. See Table 1 on page 7 for typical values.
2. his parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and
unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. Typical values, not tested.
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XCR5128: 128 Macrocell CPLD
AC Electrical Characteristics1 For Commercial Grade Devices
Commercial: 0°C ≤ TAMB ≤ +70°C; 4.75V ≤ VCC ≤ 5.25V
Symbol
tPD_PAL
7
10
12
Min/ Max. Min. Max. Min. Max.
Parameter
Unit
tCO
Propagation delay time, input (or feedback node) to output
through PAL
Propagation delay time, input (or feedback node) to output
through
PAL + PLA
Clock to out (global synchronous clock from pin)
tSU_PAL
Setup time (from input or feedback node) through PAL
4.5
7
8
ns
tSU_PLA
Setup time (from input or feedback node) through PAL + PLA
6.5
9
10.5
ns
tH
Hold time
tCH
Clock High time
3
4
4
ns
tCL
Clock Low time
3
4
4
ns
tR
Input Rise time
20
20
20
ns
tF
Input Fall time
20
20
20
ns
fMAX1
Maximum FF toggle rate2 1/(tCH + tCL )
167
125
125
MHz
fMAX2
Maximum internal frequency2 1/(tSUPAL + tCF)
111
80
69
MHz
fMAX3
Maximum external frequency2 1/(tSUPAL + t CO)
95
71
63
MHz
tBUF
Output buffer delay time
tPDF_PA L
tCF
Input (or feedback node) to internal feedback node delay time
through PAL
Input (or feedback node) to internal feedback node delay time
through PAL+ PLA
Clock to internal feedback node delay time
4.5
5.5
6.5
ns
tINIT
Delay from valid VCC to valid reset
50
50
50
µs
tER
Input to output disable2, 3
9
12
15
ns
tEA
Input to output valid2
9
12
15
ns
tRP
Input to register preset2
11
12.5
15
ns
tRR
Input to register reset2
11
12.5
15
ns
tPD_PLA
tPDF_PL A
2
7.5
2
10
2
12
ns
3
9.5
3
12
3
14.5
ns
2
6
2
7
2
8
ns
0
0
1.5
0
1.5
ns
1.5
ns
2
6
2
8.5
2
10.5
ns
3
8
3
10.5
3
13
ns
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output cl = 5 pf.
13
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XCR5128: 128 Macrocell CPLD
DC Electrical Characteristics For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 4.5V ≤ VCC ≤ 5.5V
Symbol
VIL
VIH
VI
VOL
VOH
II
IOZ
ICCQ1
ICCD1, 2
Parameter
Input voltage low
Input voltage high
Input clamp voltage
Output voltage low
Output voltage high
Input leakage current
3-stated output leakage current
Standby current
Dynamic current
IOS
Short circuit output current3
CIN
CCLK
CI/O
Input pin capacitance3
Clock input capacitance3
I/O pin capacitance3
Test Conditions
VCC = 4.5V
VCC = 5.5V
VCC = 4.5V, IIN = -18 mA
VCC = 4.5V, IOL = 12 mA
VCC = 4.5V, IOH = -12 mA
VIN = 0 to VCC
VIN = 0 to VCC
V CC = 5.5V, TAMB = -40°C
VCC = 5.5V, TAMB = -40°C at 1 MHz
VCC = 5.5V, TAMB = -40°C at 50 MHz
One pin at a time for no longer than 1
second
T AMB = 25°C, f = 1 MHz
T AMB = 25°C, f = 1 MHz
T AMB = 25°C, f = 1 MHz
Min.
Max.
0.8
10
10
125
6
90
-230
Unit
V
V
V
V
V
µA
µA
µA
mA
mA
mA
8
12
10
pF
pF
pF
2.0
-1.2
0.5
2.4
-10
-10
-50
5
Notes:
1. See Table 1 on page 7 for typical values.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled
and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
3. Typical values, not tested.
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R
XCR5128: 128 Macrocell CPLD
AC Electrical Characteristics For Industrial Grade Devices
Industrial: -40°C ≤ TAMB ≤ +85°C; 4.5V ≤ VCC ≤ 5.5V
Symbol
tPD_PAL
tPD_PLA
tCO
tSU_PAL
tSU_PLA
tH
tCH
tCL
tR
tF
fMAX1
fMAX2
fMAX3
tBUF
tPDF_PAL
tPDF_PLA
tCF
tINIT
tER
tEA
tRP
tRR
Parameter
Min.
Propagation delay time, input (or feedback node) to output through PAL
2
Propagation delay time, input (or feedback node) to output through PAL
3
& PLA
Clock to out (global synchronous clock from pin)
2
Setup time (from input or feedback node) through PAL
8
Setup time (from input or feedback node) through PAL + PLA
10
Hold time
Clock High time
5
Clock Low time
5
Input Rise time
Input Fall time
Maximum FF toggle rate2 1/(tCH + tCL)
100
Maximum internal frequency2 1/(tSUPAL + tCF)
71
2
Maximum external frequency 1/(tSUPAL + tCO)
66
Output buffer delay time
Input (or feedback node) to internal feedback node delay time
2
through PAL
Input (or feedback node) to internal feedback node delay time through
3
PAL+ PLA
Clock to internal feedback node delay time
Delay from valid VCC to valid reset
Input to output disable2, 3
Input to output valid2
Input to register preset2
Input to register reset2
10
15
Max.
10
12
Min.
2
3
Max.
15
17.5
7
2
8
10.5
8
2
1.5
13.5
3
16
ns
6.5
50
15
15
17
17
ns
µs
ns
ns
ns
ns
0
5
5
20
20
20
20
100
69
63
10.5
6
50
15
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
0
1.5
8.5
Unit
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
15
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XCR5128: 128 Macrocell CPLD
Switching Characteristics
VCC
S1
R1
COMPONENT
VALUES
R1
470Ω
R2
250Ω
C1
35 pF
VIN
VOUT
R2
C1
S2
MEASUREMENT
S1
S2
tPZH
Open
Closed
tPZL
Closed
Open
tP
Closed
Closed
Note: For tPHZ and tPLZ C = 5 pF.
SP00458A
Voltage Waveform
VDD = 5V, 25°C
8.4
+3.0V
8.0
90%
10%
7.6
0V
tPD_PAL
(ns)
tF
tR
1.5ns
1.5ns
7.2
SP00368
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
6.8
Input Pulses
6.4
6.0
1
2
4
8
12
16
NUMBER OF OUTPUTS SWITCHING
SP00472
Figure 6: tPD_PAL vs. Outputs Switching
DS041 (v1.4) January 19, 2001
Table 6: tPD_PAL vs. Number of Outputs Switching
(VCC = 5V)
Number Of
Outputs
Typical (ns)
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2
4
8
12
16
6.6
6.8
7.0
7.2
7.4
7.6
16
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R
XCR5128: 128 Macrocell CPLD
Pin Function and Layout
XCR5128 I/O Pins
FuncMacrotion
cell
Block
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PC84 PQ100 VQ100 TQ128 PQ160 Notes
12
11
10
9
8
6
5
4
22
21
20
18
17
16
15
14
31
30
29
28
27
25
24
4
3
2
1
100
99
98
96
95
94
16
15
14
12
11
10
9
8
7
6
27
26
25
24
23
22
54
19
18
2
1
100
99
98
97
96
94
93
92
14
13
12
10
9
8
7
6
5
4
25
24
23
22
21
20
19
17
16
3
2
1
128
127
126
125
124
122
121
120
119
20
19
18
17
15
14
13
12
11
10
9
8
36
32
31
30
29
28
27
26
24
23
22
160
159
158
153
152
151
150
149
147
146
145
144
21
20
19
18
16
15
14
13
12
11
10
9
41
33
32
31
30
29
28
27
25
24
23
(1)
FuncMacrotion
cell
Block
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
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15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
PC84 PQ100 VQ100 TQ128 PQ160 Notes
23
41
40
39
37
36
35
34
33
44
45
46
48
49
50
51
52
54
55
56
57
58
60
17
39
38
37
35
34
33
32
31
30
29
42
43
44
46
47
48
49
50
51
52
54
55
56
57
58
59
60
62
15
37
36
35
33
32
31
30
29
28
27
40
41
42
44
45
46
47
48
49
50
52
53
54
55
56
57
58
60
21
50
49
48
47
45
44
43
42
41
40
39
38
53
54
55
56
58
59
60
61
62
63
64
65
67
71
72
73
74
75
76
77
79
80
22
59
58
57
56
54
53
52
51
50
49
48
43
62
63
64
65
67
68
69
70
71
72
73
78
80
88
89
90
91
92
93
94
96
97
(1)
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R
XCR5128: 128 Macrocell CPLD
FuncMacrotion
cell
Block
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PC84 PQ100 VQ100 TQ128 PQ160 Notes
61
62
63
64
65
67
68
69
70
71
73
74
75
76
77
79
80
81
63
64
65
66
67
69
70
71
72
73
74
75
77
78
79
80
81
82
83
85
86
87
61
62
63
64
65
67
68
69
70
71
72
73
75
76
77
78
79
80
81
83
84
85
81
82
83
84
85
86
88
89
90
91
92
93
94
95
100
101
102
103
104
105
106
107
109
110
111
112
98
99
100
101
102
103
104
105
106
107
109
110
111
112
121
122
123
128
129
130
131
132
134
135
136
137
(1)
(1)
XCR5128 Global, JTAG, Power, Ground, and
No connect Pins
Pin Type PC84 PQ100
IN0
83
89
IN1
1
91
IN2
84
90
IN3
2
92
gtsn
84
90
CLK0
83
89
CLK1
44
42
CLK2
41
39
CLK3
4
94
TCK
62
64
TDI
14
6
TDO
71
75
TMS
23
17
Vcc
3, 13, 5, 20,
26, 38, 36, 41,
43, 53, 53, 68,
66, 78 84, 93
VQ100
87
89
88
90
88
87
40
37
92
62
4
73
15
3, 18,
34, 39,
51, 66,
82, 91
GND
7, 19,
32, 42,
47, 59,
72, 82
13, 28,
40, 45,
61, 76,
88, 97
11, 26,
38, 43,
59, 74,
86, 95
No
Connects
-
-
-
(1) JTAG pins
TQ128
114
116
115
117
115
114
53
50
119
82
8
95
21
7, 25,
46, 52,
66, 87,
108,
118
16, 37,
51, 57,
78, 96,
113,
123
4, 5, 6,
33, 34,
35, 68,
69, 70,
97, 98,
99
PQ160 Notes
139
141
140
143
140
(1)
139
62
59
144
99
9
112
22
8, 26, 55,
61, 79,
104,
133, 143
17, 42,
60, 66,
95, 113,
138, 148
1, 2, 3, 4,
5, 6, 7,
34, 35,
36, 37,
38, 39,
40, 44,
45, 46,
47, 74,
75, 76,
77, 81,
82, 83,
84, 85,
86, 87,
114,
115,
116,
117,
118,
119,
120,
124,
125,
126,
127,
154,
155,
156, 157
(1) Global 3-State pin facilitates bed of nails testing without
using logic resources.
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R
XCR5128: 128 Macrocell CPLD
84-pin PLCC
128-pin TQFP
11
1
12
103
128
75
102
1
74
PLCC
TQFP
LQFP
32
54
65
38
33
53
64
39
SP00467A
SP00469B
100-pin PQFP
160-Pin PQFP
100
81
160
121
80
1
1
120
QFP
PQFP
40
30
81
51
41
31
80
50
SP00470B
SP00468A
100-pin VQFP
100
76
75
1
TQFP
25
51
26
50
SP00485A
19
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R
XCR5128: 128 Macrocell CPLD
Ordering Information
Example: XCR5128 -7 PC 84 C
Temperature Range
Device Type
Number of Pins
Speed Options
Package Type
Temperature Range
C = Commercial, TA = 0°C to +70°C
I = Industrial, TA = –40°C to +85°C
Speed Options
-15: 15 ns pin-to-pin delay
-12: 12 ns pin-to-pin delay
-10: 10 ns pin-to-pin delay
-7: 7.5 ns pin-to-pin delay
Packaging Options
PC84: 84-pin PLCC
PQ100: 100-pin PQFP
VQ100: 100-pin VQFP
TQ128: 128-pin TQFP
PQ160: 160-pin PQFP
Component Availability
Pins
Type
Code
XCR5128
-15
-12
-10
-7
84
Plastic PLCC
PC84
I
C
C, I
C
100
Plastic PQFP
PQ100
I
C
C, I
C
Plastic VQFP
VQ100
I
C
C, I
C
128
Plastic TQFP
TQ128
I
C
C, I
C
160
Plastic PQFP
PQ160
I
C
C, I
C
Revision History
Date
9/16/99
2/10/00
8/10/00
10/09/00
01/19/01
Version #
1.0
1.1
1.2
1.3
1.4
Revision
Initial Xilinx release.
Coverted to Xilinx format and updated.
Updated features and pinout tables.
Added Discontinuation Notice.
Added pin descriptions to PC84 package to VCC and GND.
DS041 (v1.4) January 19, 2001
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