a High Performance DSP-Based Motor Controller ADMC300 TARGET APPLICATIONS Industrial Drives, Servo Drives, Variable Speed Drives, Electric Vehicles FEATURES 25 MIPS Fixed-Point DSP Core Single Cycle Instruction Execution (40 ns) ADSP-2100 Family Code Compatible Independent Computational Units ALU Multiplier/Accumulator Barrel Shifter Multifunction Instructions Single Cycle Context Switch Powerful Program Sequencer Zero Overhead Looping Conditional Instruction Execution Two Independent Data Address Generators Memory Configuration 4K 24-Bit Program Memory RAM 2K 24-Bit Program Memory ROM 1K 16-Bit Data Memory RAM High-Resolution Multichannel ADC System Five Independent 16-Bit Sigma-Delta ADCs 76 dB SNR Typical (ENOB > 12 Bits) Arranged in Two Independently Clocked Banks Differential or Single-Ended Inputs Programmable Sample Frequency to 32.5 kHz Flexible Synchronization of ADC and PWM Subsystems Independent Offset Calibration for Each Channel Two Dedicated ADC Interrupts Internal 2.5 V Reference Three Multiplexer Control Pins for External Expansion Hardware or Software Convert Start Individual Power-Down for Each Bank Three-Phase PWM Generation Subsystem 16-Bit Dedicated PWM Generator Edge Resolution to 40 ns Programmable Dead Time Programmable Minimum Pulsewidth Double Update Mode Allows Duty Cycle Adjustment on Half Cycle Boundaries Special Features for Brushless DC Motors Hardwired Polarity Control External Dedicated Asynchronous Shutdown Pin (PWMTRIP) Additional Shutdown Pins in I/O System Individual Enable/Disable of Each Output High Frequency Chopping Mode Transparent Transition to Overmodulation Range with Duty Cycles of 100% Programmable Interrupt Controller Manages Priority and Masking of 11 Peripheral Interrupts (Continued on Page 7) FUNCTIONAL BLOCK DIAGRAM ADSP-2100 BASE ARCHITECTURE DATA ADDRESS GENERATORS DAG 1 DAG 2 PROGRAM SEQUENCER MOTOR CONTROL PERIPHERALS PROGRAM ROM 2K 24 MEMORY PROGRAM RAM 4K 24 DATA RAM 1K 16 3 WATCHDOG TIMER PROGRAM INTERRUPT CONTROLLER 2 ENCODER INTERFACE EVENT CAPTURE TIMERS 12 DIGITAL I/O PROGRAM MEMORY ADDRESS BUS DATA MEMORY ADDRESS BUS PROGRAM MEMORY DATA BUS DATA MEMORY DATA BUS ARITHMETIC UNITS ALU MAC SHIFTER SERIAL PORTS SPORT 0 5 SPORT 1 INTERVAL TIMER AUXILIARY PWM SIGMA-DELTA ADCs PWM GENERATION 6 2 10 7 REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 ADMC300–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (VDD = AVDD = 5 V 10%, GND = AGND = 0 V, TAMB = –40C to +85C, CLKIN = 12.5 MHz, unless otherwise noted) B Grade Parameter VDD AVDD TAMB Digital Supply Voltage Analog Supply Voltage Ambient Operating Temperature Min Max Units 4.50 4.50 –40 5.50 5.50 +85 V V °C ELECTRICAL CHARACTERISTICS Parameter VIH VIL VOH 1, 2 Hi-Level Input Voltage Lo-Level Input Voltage1, 2 Hi-Level Output Voltage1, 3 VOL Lo-Level Output Voltage1, 3 IIH Hi-Level Input Current4 IIH Hi-Level PWMTRIP, PIO0–PIO11 Current IIH Hi-Level PWMPOL Current IIL Lo-Level Input Current4 IIL Lo-Level PWMTRIP, PIO0–PIO11 Current IIL Lo-Level PWMPOL Current IOZH Hi-Level Three-State Leakage Current5 IOZL Lo-Level Three-State Leakage Current5 IDD IDD IDD IDD IDD IDD Digital Power Supply Current (Dynamic)6, 7 Analog Power Supply Current (Disabled)8 Analog Power Supply Current (Ref Only) Analog Power Supply Current (Ref + BankA) Analog Power Supply Current (Ref + BankB) Analog Power Supply Current (Ref + BankA/B) Test Conditions Min Max Unit @ VDD = Max @ VDD = Min @ VDD = Min, IOH = –1.0 mA @ VDD = Min, IOH = –0.1 mA @ VDD = Min, IOL = 2.0 mA @ VDD = Max, VIN = VDD Max @ VDD = Max, VIN = VDD Max @ VDD = Max, VIN = VDD Max @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = VDD Max @ VDD = Max, VIN = 0 V @ VDD = Max @ AVDD = VDD = Max @ AVDD = VDD = Max @ AVDD = VDD = Max @ AVDD = VDD = Max @ AVDD = VDD = Max 2.0 0.8 2.4 V V V VDD – 0.3 V 0.4 V 10 µA 100 µA 10 µA 10 µA 10 µA 100 µA 10 µA 10 µA 100 100 6.5 11.0 13.0 18.0 mA µA mA mA mA mA NOTES 1 Bidirectional pins: PIO0–PIO11, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1. 2 Input only pins: PWMTRIP, PWMPOL, RESET, EIA, EIB, EIZP, DR1A, DR1B, DR0, CLKIN. 3 Output pins: PWMSYNC, CL, CH, BL, BH, AL, AH, MUX0–MUX2, AUX0, AUX1, CLKOUT, DT0, DT1. 4 Input only pins: RESET, EIA, EIB, EIZP, DR1A, DR1B, DR0, CLKIN. 5 Three-stateable pins: DT0, DT1, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1. 6 Current reflects device operating with no output loads. 7 Dynamic condition refers to continuous operation of the DSP core, ADC banks and PWM generation in single update mode with PWMTM = 0x0480, ADCDIVA = ADCDIVB = 0x180. The encoder inputs are quiescent. 8 Disabled refers to powering down both ADC banks and the internal reference generation circuit by setting Bits 10, 11 and 12 of the ADCCTRL register. Current is total current from AV DD supply. Specifications subject to change without notice. –2– REV. B ADMC300 (VDD = AVDD = 5 V 10%, GND = AGND = 0 V, VREFIN = 2.50 V, TAMB = –40C to +85C, ANALOG-TO-DIGITAL CONVERTER CLKIN = 12.5 MHz, unless otherwise noted) Parameter Test Conditions Min Typ Signal-to-Noise Ratio1 (SNR) Total Harmonic Distortion1 (THD) Common-Mode Rejection Ratio2 (CMRR) Channel-Channel Crosstalk3 Gain Error Gain VIN Analog Input Range4 Analog Input Voltage (Differential)4 VDIFF VOFFSET DC Offset Voltage5 fMOD, MAX Maximum Sigma-Delta Modulator Rate @VDD = 5.0 V, @ fS = 32.55 kHz, @ fIN = 1.017 kHz, ADCDIVn = 0x180, V1–V5 = 4.0 V p-p V1N–V5N = VREFIN = 2.5 V 72 76 fS, MAX Maximum ADC Sample Rate6 VREFIN RIN Reference Input Voltage7 Equivalent Input Resistance8 Max VDD VDD/2 55 2.08 dB dB dB dB % LSB/V V V mV MHz 32.55 kHz 2.6 V kΩ –70 –82 –76 5 10,600 0 ADCDIVA = 0x180 ADCDIVB = 0x180 ADCDIVA = 0x180 ADCDIVB = 0x180 2.4 2.5 25 Unit NOTES 1 SNR measured with ADC channel configured in single-ended mode. SNR measurement does not include harmonic distortion, THD includes first six harmonics. The effective number of bits (ENOB) is related to the SNR by SNR = 6.02 (ENOB) +1.76 dB. Input signal filtered at 1.5 kHz. 2 Input signal applied to both pins of input differential pair of ADC channel. 3 Input signal applied to four ADC channels, dc applied to fifth, measurement taken at fifth ADC channel. 4 Peak-peak input voltage in differential input configuration is half that in single-ended mode. 5 This offset may be corrected for, using the ADC calibration feature. 6 At maximum sigma-delta modulator rate of 2.08 MHz. 7 Input reference pins: REFINA, REFINB. 8 Analog signal input pins: V1–V5, V1N–V5N. Specifications subject to change without notice. (VDD = AVDD = 5 V 10%, GND = AGND = 0 V, TAMB = –40C to +85C, CLKIN = 12.5 MHz, unless otherwise VOLTAGE REFERENCE noted) Parameter Test Conditions Voltage Level Source Current Power Supply Rejection Ratio (PSRR) Min Typ 2.25 VREF –5 Max Unit 2.75 –100 5 V µA mV/V Specifications subject to change without notice. (VDD = AVDD = 5 V 10%, GND = AGND = 0 V, TAMB = –40C to +85C, CLKIN = 12.5 MHz, unless PULSEWIDTH MODULATOR otherwise noted) Parameter Test Conditions Min Typ 1 TD TMIN fPWM TSYNC fCHOP Counter Resolution Edge Resolution Programmable Dead Time Programmable Dead Time Increments Programmable Pulse Deletion Programmable Deletion Increments PWM Frequency Range1 PWMSYNC Pulsewidth Gate Drive Chop Frequency Double Update Mode Max Unit 16 Bits ns µs ns µs ns Hz µs MHz 40 0 81.84 80 0 40.92 40 191 0.04 0.0244 10.24 6.25 NOTES 1 Resolution varies with PWM switching frequency, 191 Hz = 16 bits, 3.05 kHz = 12 bits, 48.8 kHz = 8 bits (12.5 MHz CLKIN) in single update mode. Specifications subject to change without notice. REV. B –3– ADMC300–SPECIFICATIONS (VDD = AVDD = 5 V 10%, GND = AGND = 0 V, TAMB = –40C to +85C, CLKIN = 12.5 MHz, unless ENCODER INTERFACE UNIT otherwise noted) Parameter fENC, MAX Test Conditions Min Typ 1 Maximum Encoder Pulse Rate Max Unit 3.1 MHz NOTES 1 Assumes perfect quadrature encoder signals. Specifications subject to change without notice. AUXILIARY PWM OUTPUTS (VDD = AVDD = 5 V 10%, GND = AGND = 0 V, TAMB = –40C to +85C, CLKIN = 12.5 MHz, unless otherwise noted) Parameter fAUXPWM Test Conditions Min Resolution Switching Frequency Typ Max 8 48.8 Unit Bits kHz Specifications subject to change without notice. TIMING PARAMETERS Parameter Min Max Unit Timing Requirements: tCKI CLKIN Period CLKIN Width Low tCKIL tCKIH CLKIN Width High 80 20 20 150 ns ns ns Switching Characteristics: tCKL CLKOUT Width Low tCKH CLKOUT Width High tCKOH CLKIN High to CLKOUT High 0.5 tCK – 10 0.5 tCK – 10 0 Control Signals Timing Requirement: tRSP RESET Width Low 5 tCK1 ns PWM Shutdown Signals Timing Requirements: tPWMTPW PWMTRIP Width Low tPIOPWM PIO Width Low 3 tCK 3 tCK ns ns Clock Signals tCK is defined as 0.5 tCKI. The ADMC300 uses an input clock with a frequency equal to half the instruction rate; a 12.5 MHz input clock (which is equivalent to 80 ns) yields a 40 ns processor cycle (equivalent to 25 MHz). tCK values within the range of 0.5 tCKI period should be substituted for all relevant timing parameters to obtain specification value. Example: tCKH = 0.5 tCK – 10 ns = 0.5 (40 ns) – 10 ns = 10 ns. 20 ns ns ns NOTES 1 Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). Specifications subject to change without notice. tCKI tCKIH CLKIN tCKIL tCKOH tCKH CLKOUT tCKL Figure 1. Clock Signals –4– REV. B ADMC300 Parameter Min Serial Ports Timing Requirements: SCLK Period tSCK tSCS DR/TFS/RFS Setup before SCLK Low tSCH DR/TFS/RFS Hold after SCLK Low SCLKIN Width tSCP 50 5 10 20 Switching Characteristics: CLKOUT High to SCLKOUT tCC tSCDE SCLK High to DT Enable tSCDV SCLK High to DT Valid tRH TFS/RFSOUT Hold after SCLK High tRD TFS/RFSOUT Delay from SCLK High tSCDH DT Hold after SCLK High tSCDD SCLK High to DT Disable Max Unit ns ns ns ns 0.25 tCK 0 0.25 tCK + 15 20 0 20 0 20 ns ns ns ns ns ns ns Specifications subject to change without notice. CLKOUT tCC tCC tSCK SCLK tSCP tSCS tSCH tSCP DR RFSIN TFSIN tRD tRH RFSOUT TFSOUT tSCDD tSCDV tSCDH tSCDE DT Figure 2. Serial Ports Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . +280°C ABSOLUTE MAXIMUM RATINGS* Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V Supply Voltage (AVDD) . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Output Voltage Swing . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range (Ambient) . . . – 40°C to +85°C *Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model ADMC300BST ADMC300-ADVEVALKIT ADMC300-PB Temperature Range Instruction Rate Package Description Package Option –40°C to +85°C 25 MHz 80-Lead Plastic Thin Quad Flatpack (TQFP) Development Tool Kit Evaluation/Processor Board ST-80 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMC300 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– WARNING! ESD SENSITIVE DEVICE ADMC300 PIN FUNCTION DESCRIPTIONS Pin No. Pin Type Pin Name Pin Pin No. Type Pin Name Pin No. Pin Type Pin Name Pin No. Pin Type Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND I O I/O I/O I/O SUP GND I O O O O GND SUP O O O O O GND DR0 DT0 RFS0 TFS0 SCLK0 VDD GND PWMTRIP PWMSYNC CL CH BL GND VDD BH AL AH MUX0 MUX1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MUX2 GND VDD AUX0 AUX1 PIO0 PIO1 PIO2 PIO3 PIO4 GND VDD PIO5 PIO6 PIO7 PIO8 PIO9/CONVST PIO10/ETU0 PIO11/ETU1 AGND 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 SUP I I I I I I SUP GND GND SUP I I O I I I I SUP GND AVDD V5N V5 V4N V4 V3N V3 AVDD AGND AGND AVDD REFINB REFINA VREF V2N V2 V1N V1 AVDD AGND 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GND GND I I I I I GND I O O GND SUP I I O I/O I/O I/O SUP GND GND EIZP EIA EIB RESET PWMPOL GND CLKIN XTAL CLKOUT GND VDD DR1A DR1B DT1 RFS1/SROM TFS1 SCLK1 VDD O GND SUP O O I/O I/O I/O I/O I/O GND SUP I/O I/O I/O I/O I/O I/O I/O GND 41 AVDD 42 V5N 43 V5 44 V4N 46 V3N 45 V4 48 AVDD 47 V3 49 AGND 50 AGND 51 AVDD 52 REFINB 53 REFINA 54 VREF 56 V2 55 V2N 57 V1N 59 AVDD 58 V1 60 AGND PIN CONFIGURATION 80-Lead Plastic Thin Quad Flatpack (TQFP) (ST-80) GND 61 40 AGND GND 62 39 PIO11/ETU1 EIZP 63 38 PIO10/ETU0 EIA 64 37 PIO9/CONVST EIB 65 36 PIO8 RESET 66 PWMPOL 67 35 PIO7 34 PIO6 GND 68 33 PIO5 CLKIN 69 XTAL 70 CLKOUT 71 GND 72 ADMC300 32 VDD TOP VIEW (Not to Scale) 31 GND 30 PIO4 29 PIO3 VDD 73 DR1A 74 28 PIO2 DR1B 75 DT1 76 26 PIO0 RFS1/SROM 77 TFS1 78 SCLK1 79 25 AUX1 24 AUX0 23 VDD PIN 1 IDENTIFIER 22 GND 80 –6– MUX1 20 MUX0 19 AL 17 AH 18 BH 16 VDD 15 GND 14 BL 13 CH 12 CL 11 PWMSYNC 10 9 PWMTRIP 6 SCLK0 8 5 TFS0 7 4 RFS0 VDD 3 DT0 GND 2 DR0 21 MUX2 GND 1 VDD 27 PIO1 REV. B ADMC300 (Continued from Page 1) GENERAL DESCRIPTION The ADMC300 is a single-chip DSP-based controller, suitable for high performance control of ac induction motors, permanent magnet synchronous motors and brushless dc motors. The ADMC300 integrates a 25 MIPS, fixed-point DSP core with a complete set of motor control peripherals that permits fast, efficient development of servo motor controllers. Flexible Encoder Interface Subsystem Incremental Encoder Interface Dedicated Three Pin Interface (EIA, EIB, EIZP) 16-Bit Quadrature Counter Input Encoder Signals to 3.1 MHz Optional Use of Zero Marker to Reset Counter Single North Marker Mode—Permits Single Reset of Counter On Only First Zero Marker Status Bits to Read Encoder Inputs Companion Encoder Event System for Accuracy Enhancements at Low Speeds Associated EIU Loop Timer Permits Regular, Programmable Updating of All Encoder and Event Timer Registers EIU Timer Can Also Be Used as General Purpose Timer If Not Linked to EIU Block Peripheral I/O (PIO) Subsystem 12-Pin Digital I/O Port Bit Configurable as Input or Output Each Pin Configurable as Rising Edge, Falling Edge, High Level or Low Level Interrupt Four Dedicated PIO Interrupts for PIO0 to PIO3 One Combined Interrupt for PIO4 to PIO11 Each I/O Line Configurable as PWM Trip Source Two 8-Bit Auxiliary PWM Outputs Synthesized Analog Output Fixed 48.8 kHz Operation 0 to 99.6% Duty Cycle Event Timer Unit Two Event Timer Channels with Dedicated Event Capture Blocks Permits Timing of Duty-Cycle, Period and Frequency Configurable Event Definition Dedicated Event Timer Interrupt Event Timer Readable On-the-Fly 16-Bit Watchdog Timer Programmable 16-Bit Interval Timer with Prescaler Two Double Buffered Synchronous Serial Ports Four Boot Load Protocols via SPORT1 E2PROM/SROM Booting UART Booting (SCI Compatible) with Autobaud Feature Synchronous Master Booting with Autobaud Feature Synchronous Slave Booting with Autobaud Feature Debugger Interface via SPORT1 with Autobaud (UART and Synchronous Supported) ROM Utilities Full Debugger for Program Development Preprogrammed Math Functions Preprogrammed Motor Control Functions—Vector Transformations 80-Lead TQFP Package Industrial Temperature Range –40C to +85C REV. B The DSP core of the ADMC300 is the ADSP-2171, which is completely code compatible with the ADSP-2100 DSP family and combines three computational units, data address generators and a program sequencer. The computational units comprise an ALU, a multiplier/accumulator (MAC) and a barrel shifter. The ADSP-2171 adds new instructions for bit manipulation, multiplication (X squared), biased rounding and global interrupt masking. In addition, two flexible, double-buffered, bidirectional, synchronous serial ports are included in the ADMC300. The ADMC300 provides 4K × 24-bit program memory RAM, 2K × 24-bit program memory ROM and 1K × 16-bit data memory RAM. The program and data memory RAM can be boot loaded through the serial port from either a serial SROM/ E2PROM, asynchronous (UART) connection, or synchronous connection. The program memory ROM includes a monitor that adds software debugging features through the serial port. In addition, a number of pre-programmed mathematical and motor control functions are included in the program memory ROM. The motor control peripherals of the ADMC300 comprise a high performance, five channel ADC system that uses sigmadelta conversion technology offering a typical signal-to-noise ratio (SNR) of 76 dB, equivalent to 12 bits. In addition, a 16-bit center-based PWM generation unit can be used to produce high accuracy PWM signals with minimal processor overhead. The ADMC300 also contains a flexible encoder interface unit for position sensor feedback, two auxiliary PWM outputs, twelve lines of digital I/O, a two-channel event capture system, a 16-bit watchdog timer, a 16-bit interval timer and a programmable interrupt controller that manages all peripheral interrupts. –7– ADMC300 INSTRUCTION REGISTER DATA ADDRESS GENERATOR #1 DATA ADDRESS GENERATOR #2 PM ROM 2K 24 DM RAM 1K 16 PM RAM 4K 24 PROGRAM SEQUENCER 14 PMA BUS 14 DMA BUS 24 PMD BUS BUS EXCHANGE DMD BUS 16 INPUT REGS ALU OUTPUT REGS INPUT REGS INPUT REGS MAC SHIFTER OUTPUT REGS OUTPUT REGS COMPANDING CIRCUITRY CONTROL LOGIC 16 R BUS TIMER TRANSMIT REG TRANSMIT REG RECEIVE REG RECEIVE REG SERIAL PORT 0 SERIAL PORT 1 5 6 Figure 3. DSP Core Block Diagram The processor contains three independent computational units: the arithmetic and logic unit (ALU), the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, multiply/ subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control including floatingpoint representations. DSP CORE ARCHITECTURE OVERVIEW Figure 3 is an overall block diagram of the DSP core of the ADMC300, which is based on the fixed-point ADSP-2171. The ADSP-2171 flexible architecture and comprehensive instruction set allows the processor to perform multiple operations in parallel. In one processor cycle (40 ns with a 12.5 MHz CLKIN) the DSP core can: • • • • • Generate the next program address. Fetch the next instruction. Perform one or two data moves. Update one or two data address pointers. Perform a computational operation. This all takes place while the processor continues to: • • • • • • Receive and transmit through the serial ports. Decrement the interval timer. Generate PWM signals. Convert the ADC input signals. Operate the encoder interface unit. Operate all other peripherals including the auxiliary PWM and event timer subsystem. –8– The internal result (R) bus directly connects the computational units so that the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps and subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADMC300 executes looped code with zero overhead; no explicit jump instructions are required to maintain the loop. REV. B ADMC300 Serial Ports Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from data memory and program memory. Each DAG maintains and updates four address pointers (I registers). Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value in one of four modify (M) registers. A length value may be associated with each pointer (L registers) to implement automatic modulo addressing for circular buffers. The circular buffering feature is also used by the serial ports for automatic data transfers to and from on-chip memory. DAG1 generates only data memory address but provides an optional bit-reversal capability. DAG2 may generate either program or data memory addresses, but has no bit-reversal capability. The ADMC300 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communication and multiprocessor communication. Following is a brief list of capabilities of the ADMC300 SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for further details. • SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section. • SPORTs can use an external serial clock or generate their own serial clock internally. • SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame synchronization signals are active high or inverted, with either of two pulsewidths and timings. • SPORTs support serial data word lengths from 3 bits to 16 bits and provide optional A-law and µ-law companding according to ITU (formerly CCITT) recommendation G.711. • SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. • SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. • SPORT0 has a multichannel interface to selectively receive and transmit a 24-word or 32-word, time-division multiplexed, serial bitstream. • SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1), and the Flag In and Flag Out signals. The internally generated serial clock may still be used in this configuration. • SPORT1 is the default input for program and data memory boot loading. The RFS1 pin can be configured internal to the ADMC300 as an SROM/E2PROM reset signal. • SPORT1 has two data receive pins (DR1A and DR1B). The DR1A pin is intended for synchronous boot loading from the external SROM/E2PROM. The DR1B pin can be used as the data receive pin for boot loading from an external UART (SCI compatible) or synchronous connection, as the data receive pin for the debugger communicating over the debugger interface, or as the data receive pin for a general purpose SPORT after booting. These two pins are internally multiplexed onto the one DR1 port of the SPORT. The particular data receive pin selected is determined by a bit in the MODECTRL register. Efficient data transfer is achieved with the use of five internal buses: • Program Memory Address (PMA) Bus • Program Memory Data (PMD) Bus • Data Memory Address (DMA) Bus • Data Memory Data (DMD) Bus • Result (R) Bus Program memory can store both instructions and data, permitting the ADMC300 to fetch two operands in a single cycle— one from program memory and one from data memory. The ADMC300 can fetch an operand from on-chip program memory and the next instruction in the same cycle. The ADMC300 writes data from its 16-bit registers to the 24-bit program memory using the PX register to provide the lower eight bits. When it reads data (not instructions) from 24-bit program memory to a 16-bit data register, the lower eight bits are placed in the PX register. The ADMC300 can respond to a number of distinct DSP core and peripheral interrupts. The DSP core interrupts include serial port receive and transmit interrupts, timer interrupts, software interrupts and external interrupts. The motor control peripherals also produce interrupts to the DSP core. The two serial ports (SPORTs) provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed and unframed data transmit and receive modes of operation. Each SPORT can generate an internal programmable serial clock or accept an external serial clock. Boot loading of both the program and data memory RAM of the ADMC300 is through the serial port SPORT1. A programmable interval counter is also included in the DSP core and can be used to generate periodic interrupts. A 16-bit count register (TCOUNT) is decremented every n processor cycles, where n–1 is a scaling value stored in the 8-bit TSCALE register. When the value of the counter reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). The ADMC300 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Each instruction is executed in a single 40 ns processor cycle (for a 12.5 MHz CLKIN). The ADMC300 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools support program development. For further information on the DSP core, refer to the ADSP-2100 Family User’s Manual, Third Edition, with particular reference to the ADSP-2171. REV. B –9– ADMC300 PIN FUNCTION DESCRIPTION Memory Map The ADMC300 is available in an 80-lead TQFP package. Table I contains the pin descriptions. The ADMC300 has two distinct memory types; program memory and data memory. In general, program memory contains user code and coefficients, while the data memory is used to store variables and data during program execution. Both program memory RAM and ROM is provided on the ADMC300. Program memory RAM is arranged in two noncontiguous 2K × 24-bit blocks, one starting at address 0x0000 and the other at 0x1800. Program memory ROM is located at address 0x0800. Data memory is arranged as a 1K × 16-bit block starting at address 0x3800. The motor control peripherals are memory mapped into a region of the data memory space starting at 0x2000. The complete program and data memory maps are given in Tables II and III respectively. Table I. Pin List Pin Group Name # of Input/ Pins Output RESET SPORT0 1 5 I I/O SPORT1 6 I/O CLKOUT CLKIN, XTAL 1 2 O I, O PIO0–PIO11 12 I/O AUX0–AUX1 AH–CL PWMTRIP PWMPOL PWMSYNC V1–V5 2 6 1 1 1 5 O O I I O I V1N–V5N 5 I REFINA– REFINB VREF MUX0–MUX2 EIA, EIB, EIZP AVDD AGND VDD GND 2 I 1 3 3 4 4 6 9 O O I Function Processor Reset Input. Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0). Serial Port 1 Pins (TFS1, RFS1, DT1, DR1A, DR1B, SCLK1). Processor Clock Output. External Clock or Quartz Crystal Connection Point. Digital I/O Port, External Convert Start and Event Timer Pins. Auxiliary PWM Outputs. PWM Outputs. PWM Trip Signal. PWM Polarity Pin. PWM Synchronization Pin. Noninverting Inputs of the Differential ADCs’ Input Amplifiers. Inverting Inputs of the Differential ADCs’ Input Amplifiers. Voltage reference inputs for ADCs. Voltage Reference Output. Multiplexer Control Lines. Encoder Interface Pins. Analog Power Supply. Analog Ground. Digital Power Supply. Digital Ground. Address Range Memory Type 0x0000–0x005F 0x0060–0x071F 0x0720–0x07DF 0x07E0–0x07FF 0x0800–0x0E20 0xE21–0xFD6 RAM RAM RAM RAM ROM ROM 0xFD7–0x0FFF 0x1000–0x17FF 0x1800–0x1FFF 0x2000–0x3FFF ROM RAM Function Interrupt Vector Table User Program Space Reserved by Debugger Reserved by Monitor ROM Monitor ROM Math and Motor Control Utilities Reserved Unused User Program Space Unused Table III. Data Memory Map Address Range 0x0000–0x1FFF 0x2000–0x20FF 0x2100–0x37FF 0x3800–0x3B5F 0x3B60–0x3BFF 0x3C00–0x3FFF Memory Type RAM RAM Function Unused Memory Mapped Registers Unused User Data Space Reserved by Monitor Memory Mapped Registers ROM Code INTERRUPT OVERVIEW The ADMC300 can respond to nineteen different interrupt sources, eight of which are internal DSP core interrupts and eleven interrupts from the motor control peripherals. The eight DSP core interrupts comprise the peripheral (IRQ2), SPORT0 receive, SPORT0 transmit, SPORT1 receive (or IRQ0), SPORT1 transmit (or IRQ1), two software and the interval timer interrupts. In addition, the motor control peripherals add eleven interrupts that include two ADC, two PWM, five peripheral I/O, one encoder interface and one event timer interrupt. The interrupts are internally prioritized and individually maskable. All peripheral interrupts are multiplexed into the DSP core through the peripheral IRQ2 interrupt. The programmable interrupt controller manages the masking and vector addressing of all eleven peripheral interrupts. A detailed description of the operation of the entire interrupt system of the ADMC300 is given later, after a more detailed description of the various peripheral systems. Windows is a registered trademark of Microsoft Corporation. Table II. Program Memory Map The 2K × 24-bit block of program memory ROM starting at address 0x0800 contains a monitor function that is used to download and execute user programs via the serial port. In addition, the monitor function supports an interactive mode in which commands are received and processed from a host. An example of such a host is the Windows®-based Motion Control Debugger that is part of the software development system for the ADMC300. In the interactive mode, the host can access both the internal DSP and peripheral motor control registers of the ADMC300, read and write to both program and data memory, implement breakpoints and perform single-step and run/halt operation as part of the program debugging cycle. In addition to the monitor function, the program memory ROM contains a number of useful mathematical and motor control utilities that can be called as subroutines from the user code. A complete list of these ROM functions is given in Table IV. The start address of the function in the program memory ROM is also given. Refer to the ADMC300 DSP Motor Controller Developer’s Reference Manual for more details of the ROM functions. –10– REV. B ADMC300 Table IV. ROM Utilities Utility Address Function PER_RST UMASK 0x07E4 0x0E21 PUT_VECTOR 0x0E28 SMASK 0x0E35 ADMC_COS ADMC_SIN ARCTAN RECIPROCAL SQRT LN LOG FLTONE 0x0E55 0x0E5C 0x0E72 0x0E94 0x0EAA 0x0EE4 0x0EE7 0x0F03 FIXONE 0x0F08 FPA FPS FPM FPD FPMACC 0x0F0C 0x0F1B 0x0F2B 0x0F34 0x0F55 PARK 0x0F77 Peripheral Reset. Limits Unsigned Value to Given Range. Facilitates User Setup of Vector Table. Limits Signed Value to Given Range. Cosine Function. Sine Function. Arctangent Function. Reciprocal (1/x) Function. Square Root Function. Natural Logarithm Function. Logarithm (Base 10) Function. Fixed Point to Floating Point Conversion. Floating Point to Fixed Point Conversion. Floating Point Addition. Floating Point Subtraction. Floating Point Multiplication. Floating Point Division. Floating Point Multiply and Accumulate. Forward and Reverse Park Transformation (Vector Rotation). Reverse Clark Transformation. Forward Clark Transformation. Unsigned Single Precision Division (Integer). Unsigned Single Precision Division (Fractional). Exit to Debugger after Running User Program. REV_CLARK FOR_CLARK SDIVQINT 0x0F8B 0x0FA1 0x0FAB SDIVQ 0x0FB4 EXIT 0x0FC6 SYSTEM INTERFACE Figure 4 shows a basic system configuration for the ADMC300 with an external crystal and serial E2PROM for boot loading of program and data memory RAM. 20pF XTAL CLKOUT 12.5 MHz 20pF DR1A RESET SCLK1 RFS1/ SROM DATA CLK SERIAL E2PROM RESET Figure 4. Basic System Configuration Clock Signals The ADMC300 can be clocked by either a crystal or a TTLcompatible clock signal. The CLKIN input cannot be halted, REV. B Because the ADMC300 includes an on-chip oscillator circuit, an external crystal may be used instead of a clock source, as shown in Figure 4. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors as shown in Figure 4. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. A clock output signal (CLKOUT) is generated by the processor at the processor’s cycle rate of twice the input frequency. Reset The RESET signal initiates a master reset of the ADMC300. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this power-up sequence, the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, tRSP. If an RC circuit is used to generate the RESET signal, the use of an external Schmitt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, initializes DSP core registers and performs a full reset of all of the motor control peripherals. When the RESET line is released, the first instruction is fetched from internal program memory ROM at location 0x0800. The internal monitor code at this location then commences the boot-loading sequence over the serial port, SPORT1. Boot Loading CLKIN ADMC300 changed during operation or operated below the specified minimum frequency during normal operation. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the CLKIN pin of the ADMC300. In this mode, with an external clock signal, the XTAL pin must be left unconnected. The ADMC300 uses an input clock with a frequency equal to half the instruction rate; a 12.5 MHz input clock yields a 40 ns processor cycle (which is equivalent to 25 MHz). Normally instructions are executed in a single processor cycle. All device timing is relative to the internal instruction rate, which is indicated by the CLKOUT signal. On power-up or reset, the ADMC300 is configured so that execution begins at the internal PM ROM at address 0x0800. This starts execution of the internal monitor function that first performs some initialization functions and copies a default interrupt vector table to addresses 0x0000–0x005F of program memory RAM. The monitor next attempts to boot load from an external SROM or E2PROM on SPORT1 using the three wire connection of Figure 4. The monitor program first toggles the RFS1/ SROM pin of the ADMC300 to reset the serial memory device. If an SROM or E2PROM is connected to SPORT1, data is clocked into the ADMC300 at a rate CLKOUT/26. Both –11– ADMC300 program and data memory RAM can be loaded from the SROM/ E2PROM. After the boot load is complete, program execution begins at address 0x0060. This is where the first instruction of the user code should be placed. If boot loading from an E2PROM is unsuccessful, the monitor code reconfigures SPORT1 as a UART and attempts to receive commands from an external device on this serial port. The monitor then waits for a byte to be received over SPORT1, locks onto the baud rate of the external device (autobaud feature) and takes in a header word that tells it with what type of device it is communicating. There are six alternatives: • A UART boot loader such as a Motorola 68HC11 SCI port. • A synchronous slave boot loader (the clock is external). • A synchronous master boot loader (the ADMC300 provides the clock). • A UART debugger interface. • A synchronous master debugger interface. • A synchronous slave debugger interface. With the debugger interface, the monitor enters interactive mode in which it processes commands received from the external device. DSP Control Registers The DSP core has a system control register, SYSCNTL, memory mapped at DM (0x3FFF). SPORT0 is enabled when Bit 12 is set, disabled when this bit is cleared. SPORT1 is enabled when Bit 11 is set, disabled when this bit is cleared. SPORT1 is configured as a serial port when Bit 10 is set, or as flags and interrupt lines when this bit is cleared. For proper operation of the ADMC300, all other bits in this register must be cleared (which is their default). The DSP core has a wait state control register, MEMWAIT, memory mapped at DM (0x3FFE). For proper operation of the ADMC300, this register must always contain the value 0x8000 (which is the default). The configuration of both the SYSCNTL and MEMWAIT registers of the ADMC300 is shown at the end of the data sheet. ANALOG-TO-DIGITAL CONVERSION SYSTEM A functional block diagram of the ADC system of the ADMC300 is shown in Figure 5. The ADC system provides the high performance conversion required for precision applications. It integrates five completely independent analog-to-digital converters based on sigma-delta conversion technology. Each ADC channel may REFINA REFINB ADC BANKA V1 V1N 16-BIT ADC1 (15…0) V2 V2N 16-BIT ADC2 (15…0) 16-BIT ADC3 (15…0) V4 V4N 16-BIT ADC4 (15…0) V5 V5N 16-BIT ADC5 (15…0) V3 V3N CALIBRATION MULTIPLEXER DSP DATA MEMORY BUS ADC BANKB ADCCAL (4…0) UPDATE ADC REGISTER UPDATE CONTROL CONVST(PIO9) ADCDIVA (11…6) ADCDIVB (11…6) ADCSYNC (6…0) MUX0 MUX1 MULTIPLEXER CONTROL ADCCTRL (15…0) INTERNAL VOLTAGE REFERENCE GENERATOR VREF MUX2 Figure 5. Functional Block Diagram of ADC System of ADMC300 –12– REV. B ADMC300 as the RC filter shown in Figure 6, which provides a more than 30 dB attenuation to signals above 1 MHz (3 dB at 34 kHz) is adequate. The additional antialiasing band limiting required by the Nyquist criterion for the 32.5 kHz sampling rate (a cutoff of 16.25 kHz) is supplied by the high order sinc filter in the digital domain. be configured as either a differential or single-ended input for maximum flexibility in interfacing to external sensors and inputs. The sigma-delta converter consists of two stages, a modulator and a sinc filter, that combine to produce a 16-bit conversion. For each channel, signal-to-noise ratios of 76 dB may be achieved, corresponding to greater than 12 bits of resolution from each converter. Input signals up to 16.27 kHz may be converted. For maximum flexibility, the five ADCs are arranged as two banks; ADC1 and ADC2 forming Bank A, and ADC3, ADC4 and ADC5 forming Bank B. The characteristics of each bank, such as sampling rate, internal or external conversion, synchronization to the PWM block, operating modes, may be controlled independently. The ADC registers of each bank may be loaded from an internal signal whose frequency may be programmed as a precise fraction of the CLKIN frequency. Alternatively, the ADCs may be updated by an external signal on the CONVST pin. There are two dedicated ADC interrupts; one for each bank of converters that can be used to signal that the ADCs of the particular bank have been updated. ADMC300 VIN + VREF 0.047F 100 Vx 0.0047F –VIN + VREF VxN 100 0.047F VREF The ADC system also contains a built-in calibration function that may be used to null any offsets within the ADC converters. Each ADC channel may be placed in the calibration state individually or in combination with other channels. In addition, the ADC system provides three multiplexer control pins that may be used in conjunction with an external multiplexer to permit external signal expansion. REFINA REFINB 0.1F Figure 6. Differential Configuration for ADC Input of ADMC300 ADMC300 There is a separate reference input for each bank of converters. However, the ADMC300 also provides a reference output that could be buffered and used as a reference source for either or both banks. VIN + VREF 100 Vx 0.047F Input Configuration The input to each ADC may be applied to the ADMC300 in either a single-ended or differential configuration. In many cases, a single-ended configuration is easier to provide but the differential connection permits the reduction of common-mode noise from the input signal. Each ADC input may be configured for single-ended or differential inputs as appropriate, completely independent of the other channels. Figure 6 illustrates a typical differential configuration for the inputs of one ADC channel of the ADMC300. The input signals are applied to pins Vx and VxN (for example V1 and V1N). For correct operation and maximum input dynamic range, the inputs signals should be centered on the reference voltage level, VREF. Therefore, the signal applied to the Vx pin should be VIN + VREF, where VIN is the analog input voltage. The corresponding signal applied to the inverting terminal of the differential input, VxN, is then –VIN + VREF so that the differential signal applied to the ADC input is actually 2 VIN. VxN VREF REFINB 0.1F Figure 7. Single-Ended Configuration for ADC Input of ADMC300 ADMC300 VREF VREF 0.1F The input RC combination of 100 Ω and 0.047 µF provides a first-order low-pass antialiasing filter with a cutoff frequency of 34 kHz. An advantage to sigma-delta ADCs is that the initial (analog) signal filtering required for antialiasing is much more modest than that required by other ADCs. With the sigma-delta ADC, the input filter needed for the analog signal only has to cut off at one-half of the modulator frequency, rather than the lower effective sampling frequency. For the ADMC300, the modulator runs 64 times faster than the sampling frequency. Thus for a 32.5 kHz sampling rate, the modulator frequency is 2.08 MHz, meaning the needed cutoff for the analog input signal is 1.04 MHz. Therefore, a simple first order filter, such REV. B REFINA VxN REFINA REFINB 0.1F Figure 8. Connection of Internal Voltage Reference of ADMC300 –13– ADMC300 for independent update rates, it is important that the REFINA and REFINB pins are driven by separate voltage reference sources to avoid excessive crosstalk between banks. The ADCDIVA and ADCDIVB registers are 6-bit registers aligned in Bits 6–11 and the value written to these registers is used to divide the CLKIN frequency to provide the ADC update rate. A 12-bit value is written to these registers, but since Bits 0–5 are ignored, the value should be an integer multiple of 64 or 0x040. The resultant ADC update rates for Banks A and B may be expressed as: f CLKIN f S, A = ADCDIVA The corresponding configuration for single-ended operation is shown in Figure 7, where the inverting input is now tied directly to the reference voltage level. The noninverting input is VIN + VREF. An antialiasing filter with a cutoff at 34 kHz is included on this input. Clearly, the differential input voltage swing in this configuration is half that of the differential configuration. Therefore, when operating in single-ended mode, the input voltage, VIN, may be twice as large as that when operating differentially. To ensure correct operation, a 0.1 µF, high-quality capacitor must be included at the reference input pins. A 0.1 µF capacitor should also be used at the VREF pin, even if external references are used. In both Figures 6 and 7, it is assumed that an external precision reference is used to provide the reference voltage level, VREF. For optimum operation, a high-performance 2.5 V reference such as the AD580 is recommended. This reference is applied directly to both input reference pins, REFINA and REFINB, and is also applied to any external bias circuitry used to produce the ADC input signals. For a lower cost solution, the ADMC300 also provides a reference output that may be used to provide the VREF signal. The reference output is available at the VREF pin. For correct operation, a 0.1 µF capacitor is required at this pin even if the internal reference is not used. In addition, it is recommended that the VREF signal be buffered in a unity-gain stage prior to use, as shown in Figure 8. Of course, since there are two separate reference inputs, pins REFINA and REFINB, the two banks of ADCs may be run differently, if required. ADC Register Update The sigma-delta converters of the ADMC300 operate at a highly oversampled rate. A number of control bits in the ADCCTRL register are used to control when and how data is latched into the ADC data registers of each bank. The data registers of each bank may be latched at a regular rate based on either an internal or an external convert start signal. Bits 0–1 of the ADCCTRL register determine whether the convert start signal is internal or external. Bit 0 controls the operation of Bank A and Bit 1 controls the operation of Bank B. If either of these bits is set to 1, the data registers of the corresponding ADC bank are latched within two CLKIN cycles of the occurrence of a rising edge on the CONVST pin (PIO9). Alternatively, if either bit is set to zero, internal mode is selected and the ADCs of the particular bank are updated at a regular rate, determined by the contents of the appropriate ADC sample frequency division register, ADCDIVA or ADCDIVB. f S, B = f CLKIN ADCDIVB where fCLKIN is the CLKIN frequency, equal to half the DSP instruction rate. Therefore, writing a value of 0x180 (= 384) gives an ADC update rate of 32.55 kHz with a CLKIN frequency of 12.5 MHz. The maximum value that can be written to these registers is 0xFC0, corresponding to an update rate of 3.1 kHz. Since the maximum update rate is limited to 32.55 kHz, the permissible range of ADC divide values is 0x180 to 0xFC0 in steps of 0x040. Each ADC channel contains an input modulator that oversamples the input signal at a high rate. The modulator sample frequency is automatically set by the internal ADC control to be exactly 64 times the ADC update rate determined by the ADC divide registers. This corresponds to an oversample ratio of 64. Therefore, in the case where ADCDIVA = 0x180, the input modulators of ADC Bank A sample the input signal at 2.08 MHz and the data registers ADC1 and ADC2 are updated at the 32.55 kHz rate. Synchronization of ADC and PWM Systems In motor control applications, it is advantageous to synchronize the operation of the ADC system to the PWM pulse generation. The ADMC300 permits separate control of such synchronization for each ADC bank and permits sophisticated definition of the particular way that the ADC and PWM systems are synchronized. Operation of Bank A of the ADC may be synchronized to the PWM by setting Bit 7 of the ADCCTRL register. Similarly, setting Bit 8 of the ADCCTRL register enables synchronization of Bank B to the PWM. At its simplest, the ADC and PWM systems may be programmed to operate at the same frequency and be synchronized to one another so that the ADC data registers are automatically updated at the start of each PWM period. This mode of operation is illustrated in Figure 9(a) and is enabled by writing identical values to the PWM period register, PWMTM, and the ADC divide register, ADCDIVA or ADCDIVB. Synchronization is subsequently enabled by setting Bit 7 (for Bank A) or Bit 8 (for Bank B) of the ADCCTRL register. Bits 2–3 of the ADCCTRL register can be used to place the ADC banks in an alternative read mode. The read mode is enabled by setting these bits to 1, effectively disabling the convert start mode. In the read mode, the ADC registers of the particular bank are continuously updated at a rate equal to half the DSP clock rate, so that data is effectively available on demand. Bit 2 of the ADCCTRL register is used to place ADC Bank A in read mode, while Bit 3 is used for Bank B. ADC Sample Rate Selection Internal convert start mode is selected by clearing Bits 0 and 2 of the ADCCTRL register for Bank A and Bits 1 and 3 for Bank B. In this mode, the ADC data registers are updated at a regular rate that is determined by the ADC clock divide registers, ADCDIVA and ADCDIVB. Therefore, each bank can be configured for independent update rates by writing different values to the two registers. When Bank A and Bank B are configured Additionally, a separate control register, ADCSYNC may be used to phase shift the update of the ADC registers to some suitably defined instant within the PWM period. In this mode, the frequencies of the PWM and ADC register updating are still the same but phase shifted relative to one another. This mode is illustrated in Figure 9 (b). Again, the PWM period register and ADC divide registers are loaded with the same value. However, the offset of the ADC update within the PWM period is programmed using the ADCSYNC register. The ADCSYNC –14– REV. B ADMC300 register is a 7-bit register so that the ADC sample period is effectively subdivided into 128 equal time slices. The value written to the ADCSYNC register is the number of such time slices before the PWMSYNC pulse that the CONVST pulse is active. In other words, the occurrence of the CONVST pulse lags the PWMSYNC pulse of Figure 9 (b) by a time, TOFFSET, that can be expressed as a fraction of the ADC update period: T OFFSET = phase shift between the ADC update and PWMSYNC pulses while operating at different frequencies, as illustrated by Figure 9 (d). The offset is defined by the ADCSYNC register as a fraction of the ADC update period in an identical manner to before. ADC Transfer Characteristics (128 − ADCSYNC ) ADCDIVn f 128 CLKIN Therefore, for the case where ADCDIVA is 0x180 and ADCSYNC is 0x060, the CONVST pulse will lag the PWMSYNC pulse by a quarter of the ADC update period, or 7.68 µs, with a 12.5 MHz CLKIN. The ability to phase shift the ADC update relative to the PWMSYNC pulse is available only in single update mode of the PWM. Each ADC converter of the ADMC300 consists of an input modulator stage and a decimation filter stage that produces the final conversion result. The output of the decimation filters are 16-bit, left-aligned, two’s complement representation of the input signal, VIN. The ideal ADC transfer characteristics for both single-ended and differential modes are shown in Figure 10. The transfer characteristics of the ADC when operated in the differential configuration are shown in Figure 10 (a) and for the single-ended configuration in Figure 10 (b). The peak-peak input voltage is 4 V. The output code of the ADCs is typically given by: It is also possible to operate the ADCs at a faster update rate than the PWM switching frequency and still maintain synchronism, as illustrated in Figure 9 (c). In this example, the value written to the ADCDIV registers is three times larger than the value written to the PWMTM register, so that the ADC update rate is three times faster than the PWM switching frequency. Synchronism is maintained by setting Bits 7 and 8 of the ADCCTRL register. In addition, it is possible to introduce a 2.5 Vx −VxN ADCx = 10,600 × V REFIN ( ) ANALOG INPUT 3.5 V V1 PWMSYNC PWMTM PWMCHA AH (a) V REF CONVST = 2.5 V V1N PWMSYNC PWMTM AH 1.5V ADC CODE PWMCHA (b) CONVST 0xAD30 TOFFSET 0x0000 0x52D0 (a) ANALOG INPUT PWMSYNC PWMTM AH PWMCHA (c) 4.5 V CONVST V1 PWMTM/3 V1N V PWMSYNC REF = 2.5 V PWMTM AH PWMCHA (d) CONVST 0.5V PWMTM/3 ADC CODE TOFFSET Figure 9. (a) Synchronization of ADC and PWM at Same Frequency with No Offset, (b) Synchronization of ADC and PWM at Same Frequency with Offset, (c) Synchronization of ADC and PWM with No Offset and ADC Update at Three Times the PWM Frequency (d) Synchronization of ADC and PWM at Different Frequencies with Offset (PWM Is Operating in Single Update Mode) REV. B 0xAD30 0x0000 0x52D0 (b) Figure 10. (a) Typical Transfer Characteristic of the ADC in Differential Input Configuration (b) Typical Transfer Characteristic of the ADC in Single-Ended –15– ADMC300 ADC Group Delay The digital filters of the ADCs carry out two important functions. First, they remove the out-of-band quantization noise, which has been suitably shaped by the noise-shaping circuits of the input modulator stages. The digital filters then decimate the high frequency bitstream from the modulators to a lower rate 16-bit word. The lower rate is set by the ADC divide registers for the respective ADC banks as described previously. The antialiasing decimation filter may be modeled by the Z-domain transfer function: 1 1− z −64 H SINC (Z ) = −1 64 1− z 3 Because of the finite impulse response of the decimation filters of the ADCs, it is usually only slower dynamic signals that are multiplexed into the ADCs. In a typical motor control system, such signals may comprise the dc link voltage, the output of various temperature sensors, reference inputs, etc. ADC Status Because of the dynamic characteristics of the decimation filters of the sigma-delta converters, it is necessary to allow the impulse response of the filters to decay before meaningful, accurate data is available. There is a one-bit status register, ADCSTAT, in the ADMC300 that indicates whether or not valid data is available from the ADC. Bit 0 of the ADCSTAT register is asserted while the decimation filters are settling to indicate that data is not yet valid. This BUSY bit can be programmed to represent the status of the decimation filters of either Bank A or Bank B by programming Bit 9 of the ADCCTRL register. The BUSY bit will go active for four ADC sample periods any time that ADCCTRL, ADCCAL or ADCSYNC are written to. If Bit 9 of the ADCCTRL register is cleared, the BUSY bit will go active any time ADCDIVA is written to, and the four ADC sample period width of the BUSY pulse will be four ADC Bank A sample periods. If Bit 9 of the ADCCTRL register is set, the BUSY bit will go active any time the ADCDIVB register is written to, and the four ADC sample period width of the BUSY pulse will be four ADC Bank B sample periods. It is still possible to read the ADC data registers while the BUSY signal is asserted. However, care must be taken in the interpretation of such data. Associated with the sinc filters is a group delay that may be approximated by: tφ = is directly controlled from the ADCCTRL register, using Bits 4–6. Bit 4 of the ADCCTRL register directly controls the MUX0 pin, so that setting this bit will place a HI level on the MUX0 pin. Similarly, Bit 5 directly controls the MUX1 pin and Bit 6 controls the MUX2 pin. 1.5 fS where fS is the update rate of the particular ADC channel. In order to minimize the impact of the group delay on the overall performance of the control system, it is advantageous to oversample the ADCs at a rate faster than the PWM frequency. ADC Calibration The ADC system of the ADMC300 has a calibration feature that may be used to null any offsets in the ADC channels. There is a 5-bit ADC calibration register, ADCCAL that has a dedicated bit for each ADC channel. Setting the appropriate bit of the ADCCAL register will place the respective ADC channel in the offset calibration state. Bit 0 controls ADC1, Bit 1 controls ADC2, etc. When the appropriate bit of the ADCCAL register is set, the two input pins associated with that ADC channel are effectively disconnected from the pins of the ADMC300 and connected internally to the reference voltage. After waiting for the settling time of the decimation filters, the resultant ADC code is a measure of the offset for that particular ADC channel. This number should be saved in memory and used to correct all further measurements from that channel. ADC Power-Down and Reset Features The ADC section of the ADMC300 has certain power-down features that may be used to reduce the overall power consumption of the part. Each bank of the ADC system may be individually powered down if all channels of that bank are not used in a particular application. Setting Bit 10 of the ADCCTRL register will power down the input modulators of both ADC channels of ADC Bank A. Similarly, setting Bit 11 of the ADCCTRL register will power down the three ADC channels of Bank B. Clearing these bits will enable the input modulators of the respective banks. On power-up, both Bits 10 and 11 of the ADCCTRL register are set by default, so that all five input modulator stages are disabled. To operate the required ADC channels, the appropriate bits in the ADCCTRL register must be cleared. ADC Interrupt Generation Two dedicated interrupts are associated with the ADC system of the ADMC300, one for each of the ADC banks. The interrupts are generated after the ADC data registers of the particular bank have been updated by either an internal or external CONVST pulse. Interrupts are not generated when the ADCs are in the read mode. There are separate interrupt vector locations associated with each of the interrupt sources. The ADC Bank A interrupt is the highest priority interrupt with its vector address at program memory location 0x0030. The Bank B interrupt is the third highest priority interrupt with a vector address of 0x0038. Each interrupt has a four word space in the vector table. The sequencing and masking of these interrupts is managed by the Programmable Interrupt Controller (PIC) block described later. In addition, setting Bit 12 of the ADCCTRL register will power down the internal reference circuitry. Further power reduction is possible if this reference circuitry is powered down. However, this bit has an effect only if both ADC banks are also powered down. Clearing Bit 12 of the ADCCTRL register will enable the internal reference circuitry. ADC Multiplexer Control The ADMC300 has three digital output pins, MUX2, MUX1 and MUX0, that can be used to drive an external multiplexer to feed additional analog inputs to the ADCs if required. Using these control lines, up to eight analog signals could be externally multiplexed into each ADC channel, allowing expansion up to 40 analog inputs. The state of the three multiplexer pins It is also possible to force a reset of all five input modulators of the ADC system by setting Bit 14 of the ADCCTRL register. Setting Bit 15 of the ADCCTRL register will force a reset of the decimation filters in all five ADC channels. In order to come out of input modulator reset or decimation filter reset, the respective bit must be cleared. On power-up, these bits are –16– REV. B ADMC300 cleared so that both the modulators and the decimation filters come up in the normal mode. It is recommended that prior to use, a full reset be performed. ADC Registers The composition of all the data registers associated with the ADC system of the ADMC300 is shown at the end of the data sheet. The reset values are shown for certain bits, where appropriate. THREE-PHASE PWM CONTROLLER The PWM generator block of the ADMC300 is a flexible, programmable, three-phase PWM waveform generator that can be programmed to generate the required switching patterns to drive a three-phase voltage source inverter for ac induction (ACIM) or permanent magnet synchronous (PMSM) motor control. In addition, the PWM block contains special functions that considerably simplify the generation of the required PWM switching patterns for control of the electronically commutated motor (ECM) or brushless dc motor (BDCM). The PWM generator produces three pairs of PWM signals on the six PWM output pins (AH, AL, BH, BL, CH and CL). The six PWM output signals consist of three high side drive signals (AH, BH and CH) and three low side drive signals (AL, BL and CL). The polarity of the generated PWM signals may be programmed by the PWMPOL pin, so that either active HI or active LO PWM patterns can be produced by the ADMC300. The switching frequency, dead time and minimum pulsewidths of the generated PWM patterns are programmable using respectively the PWMTM, PWMDT and PWMPD registers. In addition, three duty-cycle control registers (PWMCHA, PWMCHB and PWMCHC) directly control the duty cycles of the three pairs of PWM signals. Each of the six PWM output signals can be enabled or disabled by separate output enable bits of the PWMSEG register. In addition, three control bits of the PWMSEG register permit crossover of the two signals of a PWM pair for easy control of ECM or BDCM. In crossover mode, the PWM signal destined for the high side switch is diverted to the complementary lowside output and the signal destined for the low side switch is diverted to the corresponding high side output signal. In many applications, there is a need to provide an isolation barrier in the gate-drive circuits that turn on the power devices of the inverter. In general, there are two common isolation techniques, optical isolation using opto-couplers and transformer isolation using pulse transformers. The PWM controller of the ADMC300 permits mixing of the output PWM signals with a high frequency chopping signal to permit easy interface to such pulse transformers. The features of this gate-drive chopping mode can be controlled by the PWMGATE register. There is an 8-bit value within the PWMGATE register that directly controls the chopping frequency. In addition, high frequency chopping can be independently enabled for the high side and the low side outputs using separate control bits in the PWMGATE register. The PWM generator is capable of operating in two distinct modes, single update mode or double update mode. In single update mode the duty cycle values are programmable only once per PWM period, so that the resultant PWM patterns are symmetrical about the midpoint of the PWM period. In the double REV. B update mode, a second updating of the PWM duty cycle values is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns, that produce lower harmonic distortion in three-phase PWM inverters. This technique also permits closed loop controllers to change the average voltage applied to the machine windings at a faster rate and so permits faster closed loop bandwidths to be achieved. The operating mode of the PWM block (single or double update mode) is selected by a control bit in the MODECTRL register. The PWM generator of the ADMC300 also provides an output pulse on the PWMSYNC pin that is synchronized to the PWM switching frequency. In single update mode a PWMSYNC pulse is produced at the start of each PWM period. In double update mode, an additional PWMSYNC pulse is produced at the midpoint of each PWM period. The width of the PWMSYNC pulse is programmable through the PWMSYNCWT register. The PWM signals produced by the ADMC300 can be shut off in a number of different ways. First, there is a dedicated asynchronous PWM shutdown pin, PWMTRIP, that, when brought LO, instantaneously places all six PWM outputs in the OFF state (as determined by the state of the PWMPOL pin). In addition, each of the PIO lines of the ADMC300 (PIO0 to PIO11) can be configured to act as an additional PWM shutdown. By setting the appropriate bit in the PIOPWM register, the corresponding PIO line acts as an asynchronous PWM shutdown source in a manner identical to the PWMTRIP pin. These two hardware shutdown mechanisms are asynchronous so that the associated PWM disable circuitry does not go through any clocked logic, thereby ensuring correct PWM shutdown even in the event of a loss of the DSP clock. In addition to the hardware shutdown features, the PWM system may be shut down in software by writing to the PWMSWT register. Status information about the PWM system of the ADMC300 is available to the user in the SYSSTAT register. In particular, the state of both the PWMTRIP and the PWMPOL pins is available, as well as a status bit that indicates whether operation is in the first half or the second half of the PWM period. A functional block diagram of the PWM controller is shown in Figure 11. The generation of the six output PWM signals on pins AH to CL is controlled by four important blocks: • The Three-Phase PWM Timing Unit, which is the core of the PWM controller, generates three pairs of complemented and dead-time-adjusted center-based PWM signals. • The Output Control Unit allows the redirection of the outputs of the Three-Phase Timing Unit for each channel to either the high side or the low side output. In addition, the Output Control Unit allows individual enabling/disabling of each of the six PWM output signals. • The Gate Drive Unit provides the correct polarity output PWM signals based on the state of the PWMPOL pin. The Gate Drive Unit also permits the generation of the high frequency chopping frequency and its subsequent mixing with the PWM signals. • The PWM Shutdown Controller takes care of the various PWM shutdown modes (via the PWMTRIP pin, the PIO lines or the PWMSWT register) and generates the correct RESET signal for the Timing Unit. –17– ADMC300 The PWM controller is driven by a clock at the same frequency as the DSP instruction rate, CLKOUT, and is capable of generating two interrupts to the DSP core. One interrupt is generated on the occurrence of a PWMSYNC pulse and the other is generated on the occurrence of any PWM shutdown action. PWM CONFIGURATION REGISTERS PWMTM (15…0) PWMDT (9…0) PWMPD(9…0) PWMSYNCWT(7…0) MODECTRL (6) Therefore, the PWM switching period, TS, can be written as: TS = 2 × tCK × PWMTM For example, for a 25 MHz CLKOUT and a desired PWM switching frequency of 10 kHz (TS = 100 µs), the correct value to load into the PWMTM register is: PWM DUTY CYCLE REGISTERS PWMTM = PWMCHA (15…0) PWMCHB (15…0) PWMCHC (15…0) PWMSEG (8…0) PWMGATE (8…0) The largest value that can be written to the 16-bit PWMTM register is 0xFFFF = 65,535, which corresponds to a minimum PWM switching frequency of: AH AL THREE-PHASE PWM TIMING UNIT CLK SYNC OUTPUT CONTROL UNIT RESET SYNC GATE DRIVE UNIT CLK POL 25 ×106 = 1250 2 ×10 ×10 3 f PWM, MIN = BH BL 25 ×106 = 190.74 Hz 2 × 65,535 for a CLKOUT frequency of 25 MHz. CH CL PWM Switching Dead Time, PWMDT Register The second important parameter that must be set up in the initial configuration of the PWM block is the switching dead time. This is a short delay time introduced between turning off one PWM signal (say, AH) and turning on the complementary signal, AL. This short time delay is introduced to permit the power switch being turned off (in this case, AH) to completely recover its blocking capability before the complementary switch is turned on. This time delay prevents a potentially destructive short-circuit condition from developing across the dc link capacitor of a typical voltage source inverter. CLKOUT PWMSYNC PWMSYNC TO INTERRUPT CONTROLLER PWMPOL PWMTRIP PWMTRIP OR PIO PWM DETECT PWMSWT (0) PIO0 : : PIO11 PIOPWM (11…0) PWM SHUTDOWN CONTROLLER Figure 11. PWM Controller Overview Three-Phase Timing Unit The 16-bit three-phase timing unit is the core of the PWM controller and produces three pairs of pulsewidth modulated signals with high resolution and minimal processor overhead. The outputs of this timing unit are active LO such that a low level is interpreted as a command to turn ON the associated power device. There are four main configuration registers (PWMTM, PWMDT, PWMPD and PWMSYNCWT) that determine the fundamental characteristics of the PWM outputs. In addition, the operating mode of the PWM (single or double update mode) is selected by Bit 6 of the MODECTRL register. These registers, in conjunction with the three 16-bit duty cycle registers (PWMCHA, PWMCHB and PWMCHC), control the output of the three-phase timing unit. PWM Switching Frequency, PWMTM Register The PWM switching frequency is controlled by the PWM period register, PWMTM. The fundamental timing unit of the PWM controller is tCK = 1/fCLKOUT where fCLKOUT is the CLKOUT frequency (DSP instruction rate). Therefore, for a 25 MHz CLKOUT, the fundamental time increment is 40 ns. The value written to the PWMTM register is effectively the number of tCK clock increments in half a PWM period. The required PWMTM value as a function of the desired PWM switching frequency (fPWM) and is given by: PWMTM = f CLKOUT f CLKIN = 2 × f PWM f PWM The dead time is controlled by the 10-bit, read/write PWMDT register. There is only one dead-time register that controls the dead time inserted into all three pairs of PWM output signals. The dead time, TD, is related to the value in the PWMDT register by: T D = PWMDT × 2 × tCK = 2 × PWMDT f CLKOUT Therefore, a PWMDT value of 0x00A (= 10), introduces an 800 ns delay between the turn-off on any PWM signal (say, AH) and the turn-on of its complementary signal (AL). The amount of the dead time can therefore be programmed in increments of 2tCK (or 80 ns for a 25 MHz CLKOUT). The PWMDT register is a 10-bit register so that its maximum value is 0x3FF (= 1023), corresponding to a maximum programmed dead time of: T D, MAX = 1023 × 2 × tCK = 1023 × 2 × 40 ×10 –9 = 81.84 µs for a CLKOUT rate of 25 MHz. Obviously, the dead time can be programmed to be zero by writing 0 to the PWMDT register. PWM Operating Mode, MODECTRL and SYSSTAT Registers The PWM controller of the ADMC300 can operate in two distinct modes; single update mode and double update mode. The operating mode of the PWM controller is determined by the state of Bit 6 of the MODECTRL register. If this bit is cleared the PWM operates in the single update mode. Setting Bit 6 places the PWM in the double update mode. By default, following either a peripheral reset or power-on, Bit 6 of the MODECTRL register is cleared so that the default operating mode is single update mode. –18– REV. B ADMC300 In single update mode, a single PWMSYNC pulse is produced in each PWM period. The rising edge of this signal marks the start of a new PWM cycle and is used to latch new values from the PWM configuration registers (PWMTM, PWMDT, PWMPD and PWMSYNCWT) and the PWM duty cycle registers (PWMCHA, PWMCHB and PWMCHC) into the three-phase timing unit. In addition, the PWMSEG register is also latched into the output control unit on the rising edge of the PWMSYNC pulse. In effect, this means that the characteristics and resultant duty cycles of the PWM signals can be updated only once per PWM period at the start of each cycle. The result is that PWM patterns that are symmetrical about the midpoint of the switching period are produced. In double update mode, there is an additional PWMSYNC pulse produced at the midpoint of each PWM period. The rising edge of this new PWMSYNC pulse is again used to latch new values of the PWM configuration registers, duty cycle registers and the PWMSEG register. As a result it is possible to alter both the characteristics (switching frequency, dead time, minimum pulsewidth and PWMSYNC pulsewidth) as well as the output duty cycles at the midpoint of each PWM cycle. Consequently, it is possible to produce PWM switching patterns that are no longer symmetrical about the midpoint of the period (asymmetrical PWM patterns). In double update mode, it may be necessary to know whether operation at any point in time is in either the first half or the second half of the PWM cycle. This information is provided by Bit 3 of the SYSSTAT register, which is cleared during operation in the first half of each PWM period (between the rising edge of the original PWMSYNC pulse and the rising edge of the new PWMSYNC pulse introduced in double update mode). Bit 3 of the SYSSTAT register is set during operation in the second half of each PWM period. This status bit allows the user to make a determination of the particular half-cycle during implementation of the PWMSYNC interrupt service routine, if required. The advantage of double update mode is that lower harmonic voltages can be produced by the PWM process and faster control bandwidths are possible. However, for a given PWM switching frequency, the PWMSYNC pulses occur at twice the rate in the double update mode. Since new duty cycle values must be computed in each PWMSYNC interrupt service routine, there is a larger computational burden on the DSP in double update mode. PWM Duty Cycles, PWMCHA, PWMCHB, PWMCHC Registers The duty cycles of the six PWM output signals on pins AH to CL are controlled by the three 16-bit read/write duty cycle registers, PWMCHA, PWMCHB and PWMCHC. The integer value in the register PWMCHA controls the duty cycle of the signals on AH and AL, PWMCHB controls the duty cycle of the signals on BH and BL and PWMCHC controls the duty cycle of the signals on CH and CL. The duty cycle registers are programmed in integer counts of the fundamental time unit, tCK, and define the desired on-time of the high-side PWM signal produced by the three-phase timing unit over half the PWM period. The switching signals produced by the three-phase timing unit are also adjusted to incorporate the programmed dead time value in the PWMDT register. The three-phase timing unit produces active LO signals so that a LO level corresponds to a command to turn on the associated power device. A typical pair of PWM outputs (in this case for AH and AL) from the timing unit are shown in Figure 12 for operation in single update mode. All illustrated time values indicate the integer value in the associated register and can be converted to time by simply multiplying by the fundamental time increment, tCK. First, it is noted that the switching patterns are perfectly symmetrical about the midpoint of the switching period in this single update mode since the same values of PWMCHA, PWMTM and PWMDT are used to define the signals in both half cycles of the period. It can be seen how the programmed duty cycles are adjusted to incorporate the desired dead time into the resultant pair of PWM signals. Clearly, the dead time is incorporated by moving the switching instants of both PWM signals (AH and AL) away from the instant set by the PWMCHA register. Both switching edges are moved by an equal amount (PWMDT × tCK) to preserve the symmetrical output patterns. Also shown is the PWMSYNC pulse whose width is set by the PWMSYNCWT register and Bit 3 of the SYSSTAT register that indicates whether operation is in the first or second half cycle of the PWM period. PWMCHA PWMCHA AH 2 PWMDT 2 PWMDT AL PWMSYNC PWMSYNCWT + 1 Width of the PWMSYNC Pulse, PWMSYNCWT Register The PWM controller of the ADMC300 produces an output PWM synchronization pulse at a rate equal to the PWM switching frequency in single update mode and at twice the PWM frequency in the double update mode. This pulse is available for external use at the PWMSYNC pin. The width of this PWMSYNC pulse is programmable by the 8-bit read/write PWMSYNCWT register. The width of the PWMSYNC pulse, TPWMSYNC, is given by: TPWMSYNC = tCK × (PWMSYNCWT + 1) so that the width of the pulse is programmable from tCK to 256tCK (corresponding to 40 ns to 10.24 µs for a CLKOUT rate of 25 MHz). Following a reset, the PWMSYNCWT register contains 0x27 (= 39) so that the default PWMSYNC width is 1.6 µs. REV. B SYSSTAT (3) PWMTM PWMTM Figure 12. Typical PWM Outputs of Three-Phase Timing Unit in Single Update Mode (Active LO Waveforms) The resultant on-times of the PWM signals in Figure 12 may be written as: TAH = 2 × (PWMCHA – PWMDT) × tCK TAL = 2 × (PWMTM – PWMCHA – PWMDT) × tCK and the corresponding duty cycles are: –19– d AH = T AH PWMCHA – PWMDT = PWMTM TS ADMC300 d AL = T AL PWMTM – PWMCHA – PWMDT = PWMTM TS The minimum permissible TAH and TAL values are zero, corresponding to a 0% duty cycle. In a similar fashion, the maximum value is TS, corresponding to a 100% duty cycle. The output signals from the timing unit for operation in double update mode are shown in Figure 13. This illustrates a completely general case where the switching frequency, dead time and duty cycle are all changed in the second half of the PWM period. Of course, the same value for any or all of these quantities could be used in both halves of the PWM cycle. However, it can be seen that there is no guarantee that symmetrical PWM signals will be produced by the timing unit in double update mode. Additionally, it is seen that the dead time is inserted into the PWM signals in the same way as in the single update mode. PWMCHA1 PWMCHA2 2 PWMDT2 AL PWMSYNCWT1 + 1 PWMSYNC PWMSYNCWT2 + 1 PWMTM1 PWMTM2 Table V. Achievable PWM Resolution in Single and Double Update Modes Figure 13. Typical PWM Outputs of Three-Phase Timing Unit in Double Update Mode (Active LO Waveforms) In general the on-times of the PWM signals in double update mode can be defined as: T AH = (PWMCHA1 + PWMCHA2 – PWMDT 1 – PWMDT 2 ) × tCK T AL = (PWMTM1 + PWMTM2 – PWMCHA1 – PWMCHA2 –PWMDT 1 – PWMDT 2 ) × tCK where the subscript 1 refers to the value of that register during the first half cycle and the subscript 2 refers to the value during the second half cycle. The corresponding duty cycles are: d AH = d AL = TS TAL TS = In single update mode, the same value of PWMCHA, PWMCHB and PWMCHC is used to define the on-times in both half cycles of the PWM period. As a result the effective resolution of the PWM generation process is 2tCK (or 80 ns for a 25 MHz CLKOUT), since incrementing one of the duty cycle registers by one changes the resultant on-time of the associated PWM signals by tCK in each half period (or 2tCK for the full period). The achievable PWM switching frequency at a given PWM resolution is tabulated in Table V. SYSSTAT (3) TAH Effective PWM Resolution In double update mode, improved resolution is possible since different values of the duty cycle registers are used to define the on-times in both the first and second halves of the PWM period. As a result, it is possible to adjust the on-time over the whole period in increments of tCK. This corresponds to an effective PWM resolution of tCK in double update mode (or 40 ns for a 25 MHz CLKOUT). AH 2 PWMDT1 have been written, internal counting of the timers in the three-phase timing unit is enabled. Writing to the PWMTM register starts the internal timing of the main PWM timer. Provided the PWMTM register is written prior to the PWMCHA, PWMCHB and PWMCHC registers in the initialization, the first PWMSYNC pulse and interrupt (if enabled) appear 1.5 × t CK × PWMTM seconds after the initial write to the PWMTM register in single update mode. In double update mode, the first PWMSYNC pulse appears after PWMTM × tCK seconds. = Single Update Mode PWM Frequency (kHz) Double Update Mode PWM Frequency (kHz) 8 9 10 11 12 48.8 24.4 12.2 6.1 3.05 97.6 48.8 24.4 12.2 6.1 Minimum Pulsewidth, PWMPD Register ( PWMCHA1 + PWMCHA2 – PWMDT1 – PWMDT2 ) ( PWMTM1 + PWMTM2 ) ( PWMTM1 + PWMTM2 – PWMCHA1 – PWMCHA2 – PWMDT1 – PWMDT2 ) ( PWMTM1 + PWMTM2 ) since for the completely general case in double update mode, the switching period is given by: T S = (PWMTM1 + PWMTM 2 )× tCK Again, the values of TAH and TAL are constrained to lie between zero and TS. PWM signals similar to those illustrated in Figure 12 and Figure 13 can be produced on the BH, BL, CH and CL outputs by programming the PWMCHB and PWMCHC registers in a manner identical to that described for PWMCHA. The PWM controller does not produce any PWM outputs until all of the PWMTM, PWMCHA, PWMCHB and PWMCHC registers have been written to at least once. Once these registers Resolution (Bits) In many power converter switching applications, it is desirable to eliminate PWM switching signals below a certain width. It takes a certain finite time to both turn on and turn off modern power semiconductor devices. Therefore, if the width of any of the PWM signals goes below some minimum value, it may be desirable to completely eliminate the PWM switching for that particular cycle. The allowable minimum on-time for any of the six PWM outputs over half a PWM period that can be produced by the PWM controller may be programmed using the PWMPD register. The minimum on-time is programmed in increments of tCK so that the minimum on-time that will be produced over any half PWM period, TMIN, is related to the value in the PWMPD register by: TMIN = PWMPD × tCK so that a PWMPD value of 0x002 defines a permissible minimum on-time of 80 ns for a 25 MHz CLKOUT. –20– REV. B ADMC300 In each half cycle of the PWM, the timing unit checks the ontime of each of the six PWM signals. If any of the times is found to be less than the value specified by the PWMPD register, the corresponding PWM signal is turned OFF for the entire half period and its complementary signal is turned completely ON. Consider the example where PWMTM = 200, PWMCHA = 5, PWMDT = 3, PWMPD = 10 with a CLKOUT of 25 MHz and operation in single update mode. In this case, the PWM switching frequency is 62.5 kHz and the dead time is 240 ns. The permissible on-time of any PWM signal over one-half of any period is 400 ns. Clearly, for this example, the dead-time adjusted on-time of the AH signal over half a PWM period is (5–3) × 40 ns = 80 ns. This is less than the permissible value, so the timing unit will output a completely OFF (0% duty cycle) signal on AH. Additionally, the AL signal will be turned ON for the entire half period (100% duty cycle). Output Control Unit, PWMSEG Register The operation of the Output Control Unit is controlled by the 9-bit read/write PWMSEG register. This register controls two distinct features of the Output Control Unit that are directly useful in the control of ECM or BDCM. In the control of an ECM only two inverter legs are switched at any time and often the high-side device in one leg must be switched ON at the same time as the low-side driver in a second leg. Therefore, by programming identical duty cycles values for two PWM channels (say PWMCHA = PWMCHB) and setting Bit 7 of the PWMSEG register to cross over the BH/BL pair of PWM signals, it is possible to turn ON the high-side switch of Phase A and the low-side switch of Phase B at the same time. In the control of ECM, it is usual that the third inverter leg (Phase C in this example) be disabled for a number of PWM cycles. This function is implemented by disabling both the CH and CL PWM outputs by setting Bits 0 and 1 of the PWMSEG register. This situation is illustrated in Figure 14, where it can be seen that both the AH and BL signals are identical, since PWMCHA = PWMCHB and the crossover bit for phase B is set. In addition, the other four signals (AL, BH, CH and CL) have been disabled by setting the appropriate enable/disable bits of the PWMSEG register. For the situation illustrated in Figure 14, the appropriate value for the PWMSEG register is 0x00A7. In normal ECM operation, each inverter leg is disabled for certain periods of time so that the PWMSEG register is changed based on the position of the rotor shaft (motor commutation). The PWMSEG register contains three crossover bits; one for each pair of PWM outputs. Setting Bit 8 of the PWMSEG register enables the crossover mode for the AH/AL pair of PWM signals, setting Bit 7 enables crossover on the BH/BL pair of PWM signals and setting Bit 6 enables crossover on the CH/CL pair of PWM signals. If crossover mode is enabled for any pair of PWM signals, the high-side PWM signal from the timing unit (AH, for example) is diverted to the associated lowside output of the Output Control Unit so that the signal will ultimately appear at the AL pin. Of course, the corresponding low-side output of the Timing Unit is also diverted to the complementary high-side output of the Output Control Unit so that the signal appears at the AH pin. Following a reset, the three crossover bits are cleared so that the crossover mode is disabled on all three pairs of PWM signals. PWMCHA = PWMCHB AH 2 PWMDT REV. B 2 PWMDT AL BH BL CH CL The PWMSEG register also contains six bits (Bits 0 to 5) that can be used to individually enable or disable each of the six PWM outputs. The PWM signal of the AL pin is enabled by setting Bit 5 of the PWMSEG register, while Bit 4 controls AH, Bit 3 controls BL, Bit 2 controls BH, Bit 1 controls CL, and Bit 0 controls the CH output. If the associated bit of the PWMSEG register is set, the corresponding PWM output is disabled irrespective of the value of the corresponding duty cycle register. This PWM output signal will remain in the OFF state as long as the corresponding enable/disable bit of the PWMSEG register is set. The implementation of this output enable function is implemented after the crossover function. Following a reset, all six enable bits of the PWMSEG register are cleared so that all PWM outputs are enabled by default. In a manner identical to the duty cycle registers, the PWMSEG is latched on the rising edge of the PWMSYNC signal so that changes to this register only become effective at the start of each PWM cycle in single update mode. In double update mode, the PWMSEG register can also be updated at the midpoint of the PWM cycle. PWMCHA = PWMCHB PWMTM PWMTM Figure 14. Example active LO PWM signals suitable for ECM control, PWMCHA = PWMCHB, crossover BH/BL pair and disable AL, BH, CH and CL outputs. Operation is in single update mode. Gate Drive Unit, PWMGATE Register The Gate Drive Unit of the PWM controller adds features that simplify the design of isolated gate drive circuits for PWM inverters. If a transformer-coupled power device gate drive amplifier is used then the active PWM signal must be chopped at a high frequency. The 10-bit read/write PWMGATE register allows the programming of this high frequency chopping mode. The chopped active PWM signals may be required for the highside drivers only, for the low-side drivers only or for both the high-side and low-side switches. Therefore, independent control of this mode for both high- and low-side switches is included with two separate control bits in the PWMGATE register. –21– ADMC300 Typical PWM output signals with high frequency chopping enabled on both high-side and low-side signals are shown in Figure 15. Chopping of the high side PWM outputs (AH, BH and CH) is enabled by setting Bit 8 of the PWMGATE register. Chopping of the low-side PWM outputs (AL, BL and CL) is enabled by setting Bit 9 of the PWMGATE register. The high frequency chopping frequency is controlled by the 8-bit word (GDCLK) placed in Bits 0 to 7 of the PWMGATE register. The period of this high frequency carrier is: [ ( )] TCHOP = 4 × GDCLK + 1 × tCK and the chopping frequency is therefore an integral subdivision of the CLKOUT frequency: f CHOP = [ f CLKOUT ] 4 ×(GDCLK +1) The GDCLK value may range from 0 to 255, corresponding to a programmable chopping frequency rate from 24.4 kHz to 6.25 MHz for a 25 MHz CLKOUT rate. The gate drive features must be programmed before operation of the PWM controller and typically are not changed during normal operation of the PWM controller. Following a reset, all bits of the PWMGATE register are cleared so that high frequency chopping is disabled, by default. PWMCHA 2 PWMDT AL [4 (GDCLK+1) tCK] PWMTM PWMTM Figure 15. Typical Active LO PWM Signals with High Frequency Gate Chopping Enabled on Both High Side and Low Side Switches (GDCLK is integer equivalent of value in Bits 0 to 7 of PWMGATE register.) The polarity of the PWM signals produced at the output pins AH to CL may be selected in hardware by the PWMPOL pin. Connecting the PWMPOL pin to GND selects active LO PWM outputs, such that a LO level is interpreted as a command to turn on the associated power device. Conversely, connecting VDD to the PWMPOL pin selects active HI PWM and the associated power devices are turned ON by a HI level at the PWM outputs. There is an internal pull-up on the PWMPOL pin, so that if this pin becomes disconnected (or is not connected), active HI PWM will be produced. The level on the PWMPOL pin may be read from Bit 2 of the SYSSTAT register, where a zero indicates a measured LO level at the PWMPOL pin. In the event of external fault conditions, it is essential that the PWM system be instantaneously shut down in a safe fashion. A low level on the PWMTRIP pin provides an instantaneous, asynchronous (independent of the DSP clock) shutdown of the PWM controller. All six PWM outputs are placed in the OFF state (as defined by the PWMPOL pin). In addition, it is possible to initiate a PWM shutdown in software by writing to the 1-bit read/write PWMSWT register. The act of writing to this register sets the bit in the PWMSWT register and generates a PWM shutdown command in a manner identical to the PWMTRIP or PIO pins. A hardware trip has no effect on the PWMSWT register. Following a PWM shutdown, it is possible to read the PWMSWT register to determine if the shutdown was generated by hardware or software. Reading the PWMSWT register automatically clears its contents. PWM Registers PWM Polarity Control, PWMPOL Pin PWM Shutdown The 12 PIO lines of the ADMC300 can also be configured to operate as PWM shutdown pins using the PIOPWM register. The 12-bit PIOPWM has a control bit for each PIO line (Bit 0 controls PIO0 etc.). Setting the control bit enables the corresponding PIO line as a PWM shutdown pin. A low level on the PIO line will then generate an instantaneous, asynchronous shutdown of the PWM system, in a manner identical to the PWMTRIP pin. On power-up, and following a reset, all PIO lines are configured as inputs, have pull-downs and are programmed as PWM shutdown pins (PIOPWM = 0x0FFF) so that the PWM is shut down. Correct operation of the PWM is not possible without first correctly configuring the PIO system. On the occurrence of a PWM shutdown command (either from the PWMTRIP pin, the PIO lines or the PWMSWT register), a PWMTRIP interrupt will be generated. In addition, internal timing of the three-phase timing unit of the PWM controller is stopped. Following a PWM shutdown, the PWM can only be re-enabled (in a PWMTRIP interrupt service routine, for example) by writing to all of the PWMTM, PWMCHA, PWMCHB and PWMCHC registers. Provided the external fault has been cleared and the PWMTRIP or appropriate PIO lines have returned to a HI level, internal timing of the three-phase timing unit resumes and new duty-cycle values are latched on the next PWMSYNC boundary. PWMCHA AH 2 PWMDT In addition, the PWMSYNC pulse is disabled. The PWMTRIP pin has an internal pull-down resistor so that if the pin becomes disconnected the PWM will be disabled. The state of the PWMTRIP pin can be read from Bit 0 of the SYSSTAT register. The configuration of all registers of the PWM system are shown at the end of the data sheet. ENCODER INTERFACE UNIT The ADMC300 incorporates a powerful encoder interface block to incremental shaft encoders, which are often used for position feedback in high performance motion control systems. The encoder interface unit (EIU) includes a 16-bit quadrature up/down counter and has three dedicated pins on the ADMC300. The quadrature encoder signals are applied at the EIA and EIB pins and the optional zero pulse may be applied at the EIZP pin. The encoder interface unit will operate correctly with input frequencies up to slightly less than a quarter of the CLKIN frequency (3.1 MHz for a 12.5 MHz CLKIN). The direction of counting of the quadrature counter is programmable. In addition, the actual direction of counting may be read from the EIU status register, EIUSTAT. The EIU may be programmed to use the zero pulse to reset the quadrature encoder, if required. Alternatively, the zero pulse can be ignored and the encoder quadrature counter is reset according to the contents of a maximum count register, –22– REV. B ADMC300 EIUMAXCNT. There is also a single north marker mode available in which the encoder quadrature counter is reset only on the first zero pulse. Both modes are enabled by dedicated control bits in the EIU control register, EIUCTRL. A status bit is set in the EIUSTAT register on the first occurrence of the zero pulse. The Encoder Interface Unit can also be made to implement some error checking functions. If the error checking mode is enabled, upon the occurrence of a zero pulse, the contents of the encoder counter register are compared with the expected value (0 or EIUMAXCNT depending on the direction of rotation). If an encoder count error is detected (say due to a disconnected encoder line), a status bit in the EIUSTAT register is set and an EIU interrupt is generated. An additional status bit is provided in the EIUSTAT register, which indicates the initialization state of the EIU. Until the EIUMAXCNT register is written to, the EIU is not initialized. Three status bits in the EIUSTAT register can also be read to read the state of the three EIU pins, EIA, EIB and EIZP. The Encoder Interface Unit of the ADMC300 contains a 16-bit loop timer that behaves in a manner similar to the programmable interval timer of the DSP core. The loop timer consist of a timer register, period register and scale register so that it can be programmed to time-out and reload at appropriate intervals. A control bit in the EIUCTRL register is used to enable/disable this loop timer. When this loop timer times out, an EIU interrupt is generated. This interrupt could be used to control the timing of speed and position control loops in high performance drives. The Encoder Interface Unit also includes a high performance Encoder Event Timer (EET) block that permits the accurate timing of successive events of the encoder inputs. The EET can be programmed to time the duration between up to 256 encoder pulses and can be used to enhance velocity estimation, particularly at low speeds of rotation. The information from the registers of the EET block can be latched in two ways. In one mode, both the contents of the EIU quadrature count register, EIUCNT and all relevant EET registers (EETT and EETDELTAT) are latched when the EIU loop timer times out. In the second mode, the act of reading the EIUCNT register also simultaneously latches the EET registers. The EET data latching mode is selected by a control bit in the EIUCTRL register. Encoder Loop Timer The EIU contains a 16-bit loop timer that is structured in a manner similar to the interval timer of the DSP core (TCOUNT, TPERIOD and TSCALE registers). The corresponding registers of the encoder loop timer are EIUTIMER, EIUPERIOD and EIUSCALE. The EIU loop timer is clocked at the CLKIN rate. The EIU loop timer can be used to generate periodic interrupts based on multiples of the CLKIN cycle times. The EIU loop timer is enabled by setting Bit 5 of the EIUCTRL register. When enabled, the 16-bit timer register (EIUTIMER) is decremented every N cycles, where N-1 is the scaling value stored in the 8-bit EIUSCALE register. When the value of the EIUTIMER register reaches zero an EIU interrupt is generated and the EIUTIMER register is reloaded with the 16-bit value in the EIUPERIOD register. REV. B The scaling feature of this timer, provided by the EIUSCALE register, allows the 16-bit timer to generate periodic interrupts over a wide range of periods. For a 12.5 MHz CLKIN rate (80 ns period), the timer can generate interrupts with periods of 80 ns up to 5.24 ms with a zero scale value (EIUSCALE = 0). When scaling is used, time periods can range up to 1.34 seconds. The EIU interrupt can be masked in the PICMASK register. Encoder Interface Structure and Operation The functional block diagram of the entire encoder interface system of the ADMC300 is shown in Figure 16. The encoder interface section consists of a 16-bit quadrature up/down counter, a 16-bit read/write EIUCNT register that allows the up/down counter to be read by the DSP. There is also a 16-bit read/ write EIUMAXCNT register that must be written to initialize the encoder system. Until the EIUMAXCNT register has been written to, the Encoder Interface Unit is not initialized and Bit 2 of the EIUSTAT register is set. The contents of the EIUMAXCNT register are used in certain operating modes to reset the quadrature counter. The contents of the EIUMAXCNT register are also used for error checking of the EIU. Operation of the encoder interface is controlled by the 6-bit read/write EIUCTRL register. Typical encoder waveforms are illustrated in Figure 17. The contents of the quadrature counter are updated on each edge of both encoder signals applied on the EIA and EIB pins. Prior to application to the quadrature counter, these signals are synchronized to the CLKIN rate in input synchronization buffers. This eliminates the asynchronous nature of real world encoder signals prior to use in the Encoder Interface Unit logic. Encoder Counter Direction The direction of quadrature counting is determined by the REV bit (Bit 0) of the EIUCTRL register. If the REV bit is cleared, the signal at the EIA pin is fed to the A input of the quadrature counter, and the EIB pin is fed to the B input. Thus, if the EIAencoder signal leads the EIB signal (and therefore the A signal leads the B signal), the quadrature counter is incremented on each edge, as shown in Figure 17. This (A signal leads the B signal) is defined as the forward direction of motion. Setting Bit 0 of the EIUCTRL register causes the signal at the EIA pin to be fed to the B input of the quadrature counter and the signal EIB becomes the A input of the quadrature counter. Therefore, if the EIA signal leads the EIB signal at the pins of the ADMC300, the A input to the quadrature counter will now lag the B input. This will be recognized as rotation in the reverse direction and the counter will be decremented on each quadrature pulse. Following a reset, the REV bit is cleared. As shown in Figure 16, the two encoder signals are used to derive a quadrature signal that is used, in conjunction with a direction bit, to increment or decrement the encoder counter and also the Encoder Event Timer. The status of the direction signal is indicated at Bit 1 of the EIUSTAT register. While the encoder counter is incrementing, Bit 1 is set. Alternatively, when the encoder counter is decrementing, Bit 1 of the EIUSTAT register is cleared. –23– ADMC300 Encoder Counter Reset The ZERO bit (Bit 1) of the EIUCTRL register determines if the encoder zero marker is used to reset the up/down counter of the encoder interface. When Bit 1 of the EIUCTRL register is set, the zero marker signal is used to reset the up/down counter to zero (if moving in the forward direction) or to the value in the EIUMAXCNT register (if moving in the reverse direction). The reset operation takes place on the next quadrature pulse after the zero marker has been recognized. In order to ensure correct encoder counting (no missing or spurious codes) the logic in the encoder counter latches the conditions (appropriate encoder edge) at which the first reset is performed. Thereafter, irrespective of operating conditions, the encoder reset operation is always aligned with the same encoder edge. For example, if the first reset operation occurs on the rising edge of B and the encoder is moving in the forward direction, then all subsequent reset operations are aligned with the rising edge of the B signal (while moving in the forward direction) and on the falling edge of B for rotation in the reverse direction. In order to account for zero marker signals of different widths, the zero marker will be recognized as the rising edge of the EIZP signal when moving in the forward direction. When moving in the reverse direction, the zero marker is recognized at the falling edge of the signal at the EIZP pin. When the ZERO bit of the EIUCTRL register is cleared, the zero marker is not used at all by the encoder interface circuitry. In this mode, the contents of the EIUMAXCNT register are used as the reset value for the up/down counter. For example, for an N-line incremental encoder, the appropriate value to write to the EIUMAXCNT register is 4N-1. Therefore, for a 1024 line encoder, a value of 0x0FFF (= 4095) would be written to the EIUMAXCNT register. However, since absolute position information is not available in this mode, due to the absence of the zero marker, the full 16-bit range of the quadrature counter may be employed by writing a value of 0xFFFF to the EIUMAXCNT register. Following a reset, the ZERO bit is cleared. expected value (zero or EIUMAXCNT depending on direction) when the zero marker is detected. If a value other than the expected value is detected, an error condition is generated by setting Bit 0 of the EIUSTAT register and triggering an EIU interrupt. Since the EIU interrupt can be initiated by both this error checking function and the time-out of the encoder loop timer, this status bit must be read to determine the source of the interrupt if both are possible. Obviously if the encoder loop timer is disabled, the EIU interrupt can only be generated by this error-checking function. This EIU interrupt is also managed and may be masked by the programmable interrupt controller (PIC) block. The encoder continues to count encoder edges after an error has been detected. Bit 0 of the EIUSTAT register is cleared on the occurrence of the next zero marker provided the error condition no longer exists and the EIUCNT register again matches the expected value. Following a reset, the MON bit is cleared. Encoder Pin Status Three additional status bits are provided in the EIUSTAT register that provide a measure of the state of the three EIU pins (EIA, EIB and EIZP) following the synchronization buffers. Bit 3 indicates the state of the EIA pin, Bit 4 indicates the state of the EIB pin and Bit 5 gives the state of the EIZP pin. The value of these status bits read is not affected by any of the control bits in the EIUCTRL register. ENCODER EVENT TIMER BLOCK CLKIN CLOCK DIVIDER EETSTAT(0) CLK EIUSCALE (7…0) TIMEOUT EIUTIMER (15…0) EETDIV(15…0) ENCODER EVENT TIMER EETT(15…0) EETDELTAT(15…0) EIUPERIOD (15…0) PULSE DECIMATOR ENCODER LOOP TIMER EETN(7…0) QUADRATURE SIGNAL DIRECTION EETCNT(15…0) The value written to the EIUMAXCNT register must be in the form 4N-1, where N is any integer. A EIA Single North Marker Mode A further reset mode is available in the Encoder Interface Unit called Single North Marker Mode. This mode is enabled by setting Bit 2 (SNM) of the EIUCTRL register. For this mode to operate, the ZERO bit (Bit 1) of the EIUCTRL register must also be set. In this mode the EIUCNT register is reset (to zero or EIUMAXCNT depending on direction) only on the first occurrence of the zero marker. Subsequently, the EIUCNT register is reset by the natural roll-over to zero or the value in the EIUMAXCNT register. Following a reset, this SNM bit is cleared. Bit 6 of the EIUSTAT register is used to signal the first occurrence of a zero marker. When the first zero marker has been recognized by the EIU, Bit 6 of the EIUSTAT register is set. EIB B SYNCHRONIZATION BUFFERS EIZP ZP EIUSTAT(5…3) ENCODER INTERFACE BLOCK 16-BIT QUADRATURE UP/DOWN COUNTER ENCODER COUNTER ERROR CHECKING ZERO MON SNM REV EIUCNT(15…0) EIUMAXCNT(15…0) EIUSTAT(2…0) EIU INTERRUPT OR EIUCTRL(5…0) DSP DATA MEMORY BUS Figure 16. Configuration of Encoder Interface System of ADMC300 Encoder Error Checking Error checking in the EIU is enabled by setting Bit 3 (MON) of the EIUCTRL register. The ZERO bit of the EIUCTRL register must also be set for error checking to be enabled. In this mode, the contents of the EIUCNT register are compared with the –24– REV. B ADMC300 EIA EIB QUADRATURE SIGNAL EIUCNT VELOCITY EVENTS EETDELTAT ENCODER EVENT TIMER VALUE EETT EIUCNT READ Figure 17. Operation of Encoder Interface Unit and Encoder Event Timer of ADMC300 in forward direction with EETN = 2. Encoder Event Timer The Encoder Event Timer block forms an integral part of the EIU of the ADMC300. The EET accurately times the duration between encoder events. The information provided by the EET may be used to make allowances for the asynchronous timing of encoder and DSP-reading events. As a result, more accurate computations of the position and velocity of the motor shaft may be performed. The EET consists of a 16-bit encoder event timer, an encoder pulse decimator and a clock divider as shown in Figure 16. The EET clock frequency is selected by the 16-bit read/write EETDIV clock divide register, whose value divides the CLKIN frequency. The contents of the encoder event timer are incremented on each rising edge of the divided clock signal. An EETDIV value of zero gives the maximum divide value of 0x10000 (= 65,536), so that the clock frequency to the encoder event timer is at its minimum possible value. The quadrature signal from the Encoder Interface Unit is decimated at a rate determined by the 8-bit read/write EETN register. For example, writing a value of 2 to EETN, produces a pulse decimator output train at half the quadrature signal frequency, as shown in Figure 17. The rising edge of this decimated signal is termed a velocity event. Therefore, for an EETN value of 2, a velocity event occurs every two encoder edges, or on each edge of one of the encoder signals. An EETN value of zero gives an effective pulse decimation value of 256. On the occurrence of a velocity event, the contents of the encoder event timer are stored in an intermediate Interval Time register. Under normal operation, this register stores the elapsed time between successive velocity events. After, the timer value has been latched at the velocity event, the contents of the encoder event timer are reset to one. Latching Data from the EET When using the data from the Encoder Event Timer, it is important to latch a triplet set of data at the same instant in time. The three pieces of data are the contents of the encoder quadrature up/down counter, the stored value in the Interval Time register (giving the precise measured time between the last two velocity events) and the present value of the encoder event timer (giving an indication of how much time has passed since the last velocity event). The data from the EET can be latched on the occurrence of either of two different events. The particular event is REV. B selected by Bit 4 (EETLATCH) of the EIUCTRL register. Setting this EETLATCH bit causes the data to be latched on the time-out of the encoder loop timer (EIUTIMER). At that time, the contents of the encoder quadrature counter (EIUCNT) are latched to a 16-bit, read-only register EETCNT. In addition, the contents of the intermediate Interval Time register are latched to the EETT register and the contents of the encoder event timer are latched to the EETDELTAT register. The three registers, EETCNT, EETT and EETDELTAT then contain the desired triplet of position/time data required for the control algorithm. In addition, if the time-out of the EIUTIMER is used to generate an interrupt, the required data is automatically latched and waiting for execution of the interrupt service routine (which may be some time after the time-out instant if there are multiple interrupts in the system). By latching the EIUCNT register to the EETCNT, the user does not have to worry about changes in the EIUCNT register (due to additional encoder edges) prior to servicing of the EIU interrupt. The other EET latch event is chosen by clearing the EETLATCH bit of the EIUCTRL register. In this mode, whenever the EIUCNT register is read by the DSP, the current value of the intermediate Interval Time register is latched to the EETT register and the current value of the encoder event timer is latched to the EETDELTAT register. The three registers, EIUCNT, EETT and EETDELTAT now contain the desired triplet of position/speed data required for the control algorithm. Note the difference from before in that the encoder count value is now available in the EIUCNT register. It is important to realize that the EETT and EETDELTAT registers are only updated by either the time-out of the EIUTIMER register (if EETLATCH bit is set) or the act of reading the EIUCNT register (if the EETLATCH bit is cleared). Therefore, if the EETLATCH bit is set, the act of reading the EIUCNT register will not update the EETT and EETDELTAT registers. Following a reset, Bit 4 of the EIUCTRL is cleared. EET Status Register There is a 1-bit EETSTAT register that indicates whether or not an overflow of the EET has occurred. If the time between successive velocity events is sufficiently long, it is possible that the encoder event timer will overflow. When this condition is detected, Bit 0 of the EETSTAT register is set and the EETT register is fixed at 0xFFFF. Reading the EETSTAT register clears the overflow bit and permits the EETT register to be updated at the next velocity event. If an encoder direction reversal is detected by the EIU, the encoder event timer is set to zero and the EETT register is set to its maximum 0xFFFF value. Subsequent velocity events will cause the EETT register to be updated with the correct value. If a value of 0xFFFF is read from the EETT register, Bit 0 of the EETSTAT register can be read to determine whether an overflow or direction reversal condition exists. In the case of a direction reversal, the contents of the EETDELTAT register is valid, representing the time from the direction reversal to the instant at which the EIUCNT register is read. On reset the EETN, EETDIV, EETDELTAT and EETT registers are all cleared to zero. Whenever either the EETN or EETDIV registers are written to, the encoder event timer is reset to zero and the EETT register is set to zero. –25– ADMC300 EIU/EET Registers The EIU and EET registers are summarized at the end of the data sheet. PROGRAMMABLE INPUT/OUTPUT The ADMC300 has 12 programmable digital input/output pins called PIO0 to PIO11. Each pin may be individually configured as either an input or an output. An associated data register may be used to read data from pins configured as inputs and write data to pins configured as outputs. In addition, each I/O line may be configured as an interrupt source. Both edge (rising and falling) and level (high and low) interrupts may be detected. Four of the PIO lines (PIO0 to PIO3) have dedicated vector addresses in the interrupt table. The remaining eight interrupts (PIO4 to PIO11) are multiplexed into a single additional interrupt vector location. The PIOFLAG register is used to determine which line caused the interrupt. In addition, all PIO lines may be alternatively configured as PWM trip sources. The PIOPWM register has dedicated bits that may be used to enable this function on each PIO line. In this mode, a low level on any pin configured as a PWM trip source shuts down the PWM in a manner identical to the PWMTRIP pin. PIO Configuration Each of the 12 programmable input/output lines may be configured as either an input or an output by programming the appropriate bits of the PIODIR register. This 12-bit read/write register has one bit associated with each I/O line; Bit 0 corresponds to PIO0, etc. Clearing a bit in the PIODIR register will configure the corresponding pin as an input pin. Conversely, setting a bit configures the pin as an output pin. On reset, bits of the PIODIR register are cleared so that all 12 PIO pins are configured as inputs. In addition, all PIO lines are internally pulled down in the ADMC300 so that unconnected lines are seen as low level inputs. Three of the PIO lines also serve alternate functions. PIO9 is multiplexed as the external convert start signal for the ADC system. Signals on this pin can be used to trigger updating of the ADC data registers, if required. Also, PIO10 and PIO11 may be used as inputs to the Event Timer Unit (ETU) to accurately time the period, frequency or duty cycle of external signals. If these functions are not required, the three pins may be used as general purpose I/O lines. PIO Data Reading/Writing Associated with the PIO system is a data register, PIODATA, that also has a bit associated with each I/O line. Data written to the PIODATA register will appear on those pins configured as outputs. In addition, reading the PIODATA register will read the data from those pins configured as inputs. PIO Interrupt Generation Each of the twelve PIO lines may be configured as an interrupt source. Four of the PIO lines, PIO0 to PIO3, have dedicated interrupt vector locations while the remaining eight are multiplexed into an additional interrupt vector. The PIOINTEN enable function is used to enable or disable interrupts on the PIO4 to PIO11 lines. The PICMASK register of the programmable interrupt controller is used to enable interrupts on the four dedicated PIO lines, PIO0 to PIO3. Interrupts may be generated on either edge (rising or falling) or level (high or low) events by programming the appropriate bits of both the PIOMODE and PIOLEVEL registers. Both registers have a dedicated bit for each of the twelve PIO lines. Setting the appropriate bit of the PIOMODE register configures the interrupt as level-sensitive, while clearing the bit configures the corresponding PIO to be edge sensitive. In level-sensitive mode (PIOMODE bit is 1), setting the corresponding bit in the PIOLEVEL register configures the interrupt as active high, while clearing the bit in the PIOLEVEL register configures it for active low. In edge-sensitive mode (PIOMODE bit is 0), setting the corresponding bit of the PIOLEVEL register configures the interrupt for rising edge, while clearing the bit configures the interrupt for falling edge. On reset, all PIO interrupts are disabled. The appropriate register settings for correct PIO interrupt configuration is shown in Table VI. Table VI. PIO Interrupt Configuration PIOMODE 1 PIOLEVEL 0 0 1 Falling Edge Rising Edge Active Low Active High The four dedicated PIO interrupts from PIO0 to PIO3 have interrupt vector addresses at program memory addresses 0x0048 for PIO0, 0x004C for PIO1, 0x0050 for PIO2 and 0x0054 for PIO3. In the event of an interrupt on PIO4 to PIO11, the corresponding bit of the PIOFLAG register is set and the general PIO interrupt is activated. This interrupt has a dedicated vector address at location 0x003C. In the interrupt service routine for this interrupt, the user must poll the PIOFLAG register to determine which of the PIO4 to PIO11 lines, that have interrupts enabled, caused the interrupt. Of course, if only one of the PIO4 to PIO11 lines have interrupts enabled, no polling is necessary. Reading the PIOFLAG register clears all bits of the register. PIO lines that are configured as outputs may also be used to generate interrupts. If, for example, one of the PIO lines is configured simultaneously as an output and as an interrupt source, writing the appropriate data to the PIODATA register will trigger an interrupt. PIO as PWM Trip Sources By setting the appropriate bits of the PIOPWM register, each of the twelve PIO lines can be configured as a PWM trip source. In this mode, a low level on the PIO pin will cause a PWM trip that will disable all six PWM outputs on AH to CL. The disabling of the PWM is independent of the DSP clock, so that the PWM stage can be fully protected even in the event of a loss of clock signal to the DSP. A PWMTRIP interrupt will be generated when the PWM is reset (whether the PWM is reset via a PIO configured as a trip source, or via the PWMTRIP pin). It is also possible to generate the normal PIO interrupts on the occurrence of a falling-edge on the PIO line. The advantage of this highly flexible structure for PWM shutdown is that multiple fault signals could be applied to the ADMC300 at different PIO lines. The occurrence of a falling-edge on any of them will instantaneously shut down the PWM. However, based on the particular PIO interrupt that is flagged, the user can easily determine the source of the trip. This permits the action of the interrupt service routines following a PWM trip to be tailored to the particular fault that occurred. On reset, all PIO lines are configured as PWM trip sources. Because all PIO lines are also configured as inputs and have –26– REV. B ADMC300 (shorter than the programmed WDTIMER period value). On all but the first write to WDTIMER, the particular value written to the register is unimportant since writing to WDTIMER simply reloads the first value written to this register. internal pull-down resistors, any unconnected PIO lines will cause a PWM trip. Therefore, prior to using the PWM unit of the ADMC300, it is imperative that the PIO state be correctly configured for the particular application. PIO Registers The configuration of all registers associated with the PIO system are shown at the end of the data sheet. Each of the registers has a bit directly associated with one of the PIO lines. For example, Bit 0 of all registers affects only the PIO0 line of the ADMC300. AUXILIARY PWM OUTPUTS The ADMC300 provides two auxiliary, fixed-frequency, variable duty cycle PWM outputs that may be used to drive auxiliary switching circuits in the motor control system. Alternatively, by adding appropriate filtering at the output, these signals can be used to provide a simple digital-to-analog converter. These output signals appear on the AUX0 and AUX1 pins and are controlled by the duty cycle registers, AUXTIM0 and AUXTIM1. The auxiliary PWM outputs operate at a fixed frequency that is fCLKIN/256. This gives an auxiliary PWM switching frequency of 48.8 kHz for a 12.5 MHz CLKIN. The output duty cycle at the auxiliary PWM output pin is controlled by comparing the 8-bit auxiliary PWM duty-cycle registers, AUXTIM0 and AUXTIM1 with the contents of a timer. The value written to these registers may range from 0 to 255 so that duty cycles from 0 to 99.6% may be produced at the output pins. A simple filter at the output could then be used to produce a corresponding analog output from 0 to 0.996 VDD. WATCHDOG TIMER The ADMC300 incorporates a watchdog timer that can perform a full reset of the DSP and motor control peripherals in the event of software error. The watchdog timer is enabled by writing a timeout value to the 16-bit WDTIMER register. The timeout value represents the number of CLKIN cycles required for the watchdog timer to count down to zero. When the watchdog timer reaches zero, a full DSP core and motor control peripheral reset is performed. In addition, Bit 1 of the SYSSTAT register is set so that after reset the ADMC300 can determine that the reset was due to the time out of the watchdog timer and not a power-on reset. Following a reset, Bit 1 of the SYSSTAT register may be cleared by writing zero to the WDTIMER register. This clears the status bit but does not enable the watchdog timer. REV. B The ADMC300 contains a dual channel Event Timer Unit (ETU) that may be used to accurately measure the elapsed time between defined events on a particular channel. The ETU uses two input pins, ETU0 and ETU1, that are multiplexed with the PIO10 and PIO11 pins. The ETU system contains a set of 16-bit data registers that are used to store the value of the dedicated ETU timer on the occurrence of the defined events on the input pins. A configuration register is used to define the nature of the events on each of the input pins. In addition, a control register is used to initiate event capture on the inputs. A status register may be read to determine the state of the two capture channels. A dedicated ETU interrupt may be generated upon completion of a capture sequence on either the ETU0 or ETU1 channel. The ETU timer is a free running counter whose contents may be read from the 16-bit ETUTIME read only register. An event may be defined as either a rising or falling edge on the associated ETU0 and ETU1 inputs pins. Therefore, the ETU system can be used to compute the frequency, period, duty cycle or on-time of signals applied at the inputs. A functional block diagram of the ETU system of the ADMC300 is shown in Figure 18. ETU Event Definition The ETU system of the ADMC300 contains a dedicated 16-bit timer whose clock frequency may be programmed using the ETUDIVIDE register. This register divides the CLKIN frequency to provide the clock signal for the ETU timer. The clock frequency of the ETU timer may be expressed as fCLKIN/ ETUDIVIDE and is common to both channels. The outputs of the two auxiliary PWM timer circuits are synchronized on their rising edges. When the auxiliary timer registers are written to, the value becomes effective immediately. Therefore, if the value is smaller than the present timer value, the outputs go low immediately. The correct duty cycle appears for the subsequent auxiliary PWM period. On reset, the AUXTIM0 and AUXTIM1 registers are cleared so that no auxiliary PWM signals are produced and the AUX0 and AUX1 pins are low until these registers are programmed. The format of the AUXTIM0 and AUXTIM1 registers is shown at the end of the data sheet. On reset, the watchdog timer is disabled and is only enabled when the first timeout value is written to the WDTIMER register. To prevent the watchdog timer from timing out, the user must write to the WDTIMER register at regular intervals EVENT TIMER UNIT Two events are used to trigger the ETU, termed Event A and Event B. By setting the appropriate bits of the ETUCONFIG register, it is possible to define both Events A and B as either rising or falling edges on the appropriate pin. For example, setting Bit 0 of the ETUCONFIG register defines Event A of the ETU0 channel as a rising edge on the ETU0 pin. Similarly, setting Bit 4 of the ETUCONFIG register defines Event A of the ETU1 channel as a rising edge on the ETU1 pin. Event A defines the start of the event capture sequence. Associated with each ETU channel are three data registers, ETUA0, ETUB0 and ETUAA0 for ETU Channel 0 and ETUA1, ETUB1 and ETUAA1 for ETU Channel 1. These data registers store the ETU timer value on the occurrence of the first A Event, the first B Event and the second A Event respectively. For example, for ETU Channel 0, ETUA0 stores the timer value on the first occurrence of Event A on the ETU0 pin, ETUB0 stores the timer value on the first occurrence of Event B on the ETU0 pin and ETUAA0 stores the timer value on the second occurrence of Event A on the ETU0 pin. Registers ETUA1, ETUB1 and ETUAA1 perform the same function for events on ETU Channel 1. Because the ETU0 and ETU1 pins are multiplexed with the PIO10 and PIO11 pins, it is possible to configure these lines as –27– ADMC300 digital outputs using the PIODIR register. In this mode, writing suitable patterns to the PIODATA register will trigger the corresponding event capture on the ETU channels. ETU Interrupt Generation The completion of the event capture sequence can be defined as either the occurrence of Event B or the second occurrence of Event A by setting the appropriate bits of the ETUCONFIG register. At the end of the capture sequence, the ETU generates an interrupt. For example, if Bit 2 of the ETUCONFIG register is set, ETU Channel 0 will generate an ETU interrupt on the occurrence of Event B on the ETU0 pin. On the other hand, if Bit 6 of the ETUCONFIG register is cleared, ETU Channel 1 will generate an ETU interrupt on the occurrence of the second Event A on the ETU1 pin. Both ETU channels generate the same interrupt to the DSP when capture is complete. If both ETU channels are used simultaneously, the ETUSTAT register can be polled to determine which caused the interrupt. If capture on ETU Channel 0 is complete, Bit 0 of the ETUSTAT register is set; if capture on ETU Channel 1 is complete, Bit 1 is set. Reading the ETUSTAT register automatically clears all bits of the register. ETUA0 (15…0) ETU0 EVENT DETECTOR ETUB0 (15…0) INTERRUPT CONTROL Operation and control of the various interrupt sources is managed by a combination of the internal interrupt controller of the DSP core and a dedicated Programmable Interrupt Controller (PIC) that manages all interrupts from the motor control peripherals. Eight internal DSP core interrupts comprise the peripheral (IRQ2), SPORT0 transmit and receive, two software, SPORT1 transmit and receive (or alternatively IRQ1 and IRQ0), and the timer interrupts. The ADMC300 includes eleven additional interrupts that are interfaced to the DSP core through the IRQ2 interrupt. The eleven peripheral interrupts include two ADC interrupts (one per bank), the PWMSYNC interrupt, the five PIO interrupts (four dedicated to PIO0 to PIO3 and the combined PIO4 to PIO11 interrupt), the EIU interrupt, the ETU interrupt and the PWMTRIP interrupt. Each of the nineteen interrupts of the ADMC300 has a dedicated four word section in the interrupt vector table. The start address in the interrupt vector table for each of the nineteen ADMC300 interrupt sources is tabulated in Table VII. The interrupts are listed from the highest priority to the lowest priority. The entire interrupt control system of the ADMC300 is configured and controlled by the IFC, IMASK and ICNTL registers of the DSP core and the PICMASK and PICVECTOR registers of the PIC block. Table VII. Interrupt Vector Addresses ETUAA0 (15…0) CLKIN ETU Timer ETU INTERRUPT ETUTIME (15…0) ETUA1 (15…0) ETU1 EVENT DETECTOR Interrupt Source Interrupt Vector Address Peripheral Interrupt (IRQ2) ADC Bank A Update PWMSYNC ADC Bank B Update PIO Interrupt (PIO4 to PIO11) Encoder Interface Interrupt Event Timer Unit Interrupt PIO0 Interrupt PIO1 Interrupt PIO2 Interrupt PIO3 Interrupt PWMTRIP Interrupt SPORT0 Transmit Interrupt SPORT0 Receive Interrupt Software Interrupt 1 Software Interrupt 0 SPORT1 Transmit Interrupt or IRQ1 SPORT1 Receive Interrupt or IRQ0 Timer 0x0004 (Highest Priority) 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 (Lowest Priority) ETUDIVIDE (15…0) ETUB1 (15…0) ETUAA1 (15…0) ETUCONFIG (7)…0 ETUCTRL (1…0) ETUSTAT (1…0) Figure 18. Functional Block Diagram of Event Timer Unit ETU Operating Modes The ETU channels of the ADMC300 can operate in two distinct modes; single shot and free-running. The particular mode may be selected for ETU Channel 0 by programming Bit 3 of the ETUCONFIG register and for ETU channel 1 by programming Bit 7 of the ETUCONFIG register. Setting these bits puts the respective ETU channel in free-running mode while clearing the bits enables the single-shot mode. In single-shot mode, upon completion of the capture sequence, further event capture is disabled until the appropriate bit of the ETUCTRL register has been set. Setting Bit 0 of the ETUCTRL register restarts the capture for ETU Channel 0, while Bit 1 restarts capture for Channel 1. In the free-running mode, the bits of the ETUCTRL register remain set and the ETU channel continues to capture following the generation of the interrupt. ETU Registers The configuration of the ETU registers is shown at the end of the data sheet. Interrupt Masking Interrupt masking (or disabling) is controlled by the IMASK register of the DSP core and the PICMASK register. These registers contain individual bits that must be set to enable the various interrupt sources. It is important to remember that if any peripheral interrupt is to be enabled both the IRQ2 interrupt enable bit (Bit 9) of the IMASK register and the appropriate bit of the PICMASK register must be set. The configuration of both the IMASK and PICMASK registers of the ADMC300 is shown at the end of the data sheet. –28– REV. B ADMC300 Interrupt Configuration The IFC and ICNTL registers of the DSP core control and configure the interrupt controller of the DSP core. The IFC register is a 16-bit register that may be used to force and/or clear any of the eight DSP interrupts. Bits 0 to 7 of the IFC register may be used to clear the DSP interrupts while Bits 8 to 15 can be used to force a corresponding interrupt. Writing to Bits 11 and 12 in IFC is the only way to create the two software interrupts. The ICNTL register is used to configure the sensitivity (edge or level) of the IRQ0, IRQ1 and IRQ2 interrupts and to enable/ disable interrupt nesting. Setting Bit 0 of ICNTL configures the IRQ0 as edge sensitive while clearing the bit configures it for level sensitive. Bit 1 is used to configure the IRQ1 interrupt and Bit 2 is used to configure the IRQ2 interrupt. It is recommended that the IRQ2 interrupt be always configured for level sensitive as this ensures that no peripheral interrupts are lost. Setting Bit 4 of the ICNTL register enables interrupt nesting. The configuration of both IFC and ICNTL registers is shown at the end of the data sheet. Interrupt Operation Following a reset, the ROM code monitor of the ADMC300 copies a default interrupt vector table into program memory RAM from address 0x0000 to 0x005F. Since each interrupt source has a dedicated four word space in this vector table, it is possible to code short interrupt service routines (ISR) in place. Alternatively, it may be required to insert a JUMP instruction to the appropriate start address of the interrupt service routine if more memory is required for the ISR. ISR. The PUT_VECTOR ROM subroutine can be used to replace the RTI with the JUMP. The PIC block manages the sequencing of the eleven motor control peripheral interrupts. In the case of multiple simultaneous interrupts, the PIC will load the PICVECTOR register with the vector address of the highest priority pending interrupt. The contents of the PICVECTOR register will remain fixed until read by the DSP. This action is performed by the default DSP code at location 0x0004. The PIC block only asserts a new interrupt after the PICVECTOR register has been read. SYSTEM CONTROLLER The system controller block of the ADMC300 performs a number of distinct functions: 1. Manages the interface and data transfer between the DSP core and the motor control peripherals. 2. Controls the multiplexing of the SPORT1 pins to select either the DR1A or DR1B data receive pins. It also allows configuration of SPORT1 as a UART interface. 3. Manages the software flags of the DSP core. 4. Contains a status register (SYSSTAT) that indicates the state of the PWMTRIP, PWMPOL pins and the watchdog timer. 5. Performs a reset of the motor control peripherals and control registers following a hardware, software or watchdog initiated reset. DT1 On the occurrence of an interrupt, the program sequencer ensures that there is no latency (beyond synchronization delay) when processing unmasked interrupts. In the case of the timer, SPORT0, SPORT1 and software interrupts, the interrupt controller automatically jumps to the appropriate location in the interrupt vector table. At this point, a JUMP instruction to the appropriate ISR is required. DR1A DR1 ADMC300 DR1B DSP CORE SPORT1 0x0004: DM (I4_SAVE) = I4; I4 = DM (PICVECTOR); JUMP (I4); The default code for each of the motor control peripherals is: I4 = DM (I4_SAVE); RTI; RFS1/SROM SCLK1 SCLK1 FL1 UARTEN DR1SEL MODECTRL (5…4) Figure 19. Internal Multiplexing of SPORT1 Pins SPORT1 Control The ADMC300 uses SPORT1 as the default serial port for boot loading and as the interface to the development environment. There are two data receive pins, DR1A and DR1B, on the ADMC300. This permits DR1A to be used as the data receive pin when interfacing to serial ROM or E2PROM for boot loading. Alternatively, if connecting through another external device for either boot loading or interface to the development environment, the DR1B pin can be used. Both data receive pins are multiplexed internally into the single data receive input of Note that this default restores I4 to its value before the interrupt. The user should replace the RTI with a JUMP to their REV. B TFS1 TFS1 RFS1 In the event of a motor control peripheral interrupt, the operation is slightly different. For any of the eleven peripheral interrupts, the interrupt controller automatically jumps to location 0x0004 in the interrupt vector table. In addition, the required vector address (between 0x0030 and 0x0058) associated with the particular interrupt source is placed in the PICVECTOR register of the PIC block. Code loaded at location 0x0004 by the monitor on reset subsequently performs a JUMP from location 0x0004 to the address specified in the PICVECTOR register. This operation with the PICVECTOR register results in a slightly longer latency associated with processing any of the peripheral interrupts, as compared with the latency of the internal DSP core interrupts. The code located at location 0x0004 by the monitor on reset is as follows: DT1 –29– ADMC300 SPORT1. Two control bits in the MODECTRL register control the state of the SPORT1 pins by manipulating internal multiplexers in the ADMC300. The configuration of SPORT1 is illustrated in Figure 19. The ADMC300 also contains two software flags, FL1 and FL2. These flags may be controlled in software and perform specific functions on the ADMC300. The FL1 pin has already been described and is used to perform a reset of the external memory device via the RFS1/SROM pin. The FL2 flag is used specifically to perform a full peripheral reset of the chip (including the watchdog timer). This is accomplished by toggling the FL2 flag in software using the following code segment: Bit 4 of the MODECTRL register (DR1SEL) selects between the two data receive pins. Setting Bit 4 of MODECTRL connects the DR1B pin to the internal data receive port DR1 of SPORT1. Clearing Bit 4 connects DR1A to DR1. PRESET: Setting Bit 5 of the MODECTRL register (UARTEN) configures the serial port for UART mode. In this mode, the DR1 and RFS1 pins of the internal serial port are connected together. Additionally, setting the UARTEN bit connects the FL1 flag of the DSP to the external RFS1/SROM pin. In this mode, this pin is intended to be used to reset the external serial ROM device. SET FL2: TOGGLE FL2; TOGGLE FL2; RTS; System Control Registers The monitor code in ROM automatically configures the SPORT1 pins during the boot sequence. Initially, the DR1SEL bit is cleared and the UARTEN bit is set so that the ADMC300 first attempts to perform a reset of the external memory device using the RFS1/SROM pin. This is accomplished by toggling the FL1 flag using the following code segment: SROMRESET: SET FL1; TOGGLE FL1; TOGGLE FL1; RTS; If successful, data will be clocked from the external device in a continuous stream. The start of the data stream is detected by the serial port on the RFS1 pin, which is connected internally to the DR1 pin in this mode. If the serial load is successful, code is downloaded and execution begins at the start of user program memory (address 0x0060). Following a synchronous boot load, SPORT1 could be configured for normal synchronous serial mode by setting the DR1SEL pin to select the DR1B data receive pin and by clearing the UARTEN bit to return to SPORT mode. The system controller includes two registers, the MODECTRL register used to control the multiplexing of the SPORT1 pins and PWM operating mode, and the SYSSTAT register that displays various status information. The format of these registers is shown at the end of the data sheet. Bit 0 of the SYSSTAT register indicates the state of the PWMTRIP pin. If this bit is set, the PWMTRIP pin is high and no PWM trip is occurring. If this bit is cleared, then the PWM is shut down. Bit 1 of the SYSSTAT register is set following a watchdog timeout. This bit is cleared in normal operation. Finally, Bit 2 indicates the status of the PWMPOL pin. If this bit is set, the PWMPOL pin is high and active high PWM outputs will be produced. Bit 3 indicates the half cycle in which the PWM is operating. Register Memory Map The address, name, used bits and function of all motor control peripheral registers of the ADMC300 are tabulated in Table VIII. In addition, the relevant DSP core registers are tabulated in Table IX. Full details of the DSP core registers can be obtained by referring to the ADSP-2171 sections of the ADSP-2100 Family User’s Manual, Third Edition. Development Kit Failing a synchronous boot load, the ADMC300 monitor automatically sets the DR1SEL bit to select the DR1B pin and remains in UARTEN mode. The monitor code then waits for a header byte that tells it with which of the other interfaces it is to communicate. Obviously, if a debugger interface is required on SPORT1, it is not possible to use SPORT1 as a general purpose synchronous serial port. If such a serial port is required, it is recommended that SPORT0 be used. To facilitate device evaluation and programming, an evaluation kit (ADMC300-ADVEVALKIT) is available from Analog Devices. The evaluation kit consists of an evaluation board and the Motion Control Debugger software. The evaluation kit contains latest programming and device information. It is recommended that the evaluation kit be used for initial program development. Flag Pins The ADMC300 provides flag pins. The alternate configuration of SPORT1 includes a Flag In (FI) and Flag Out (FO) pin. This alternate configuration of SPORT1 is selected by Bit 10 of the DSP system control register, SYSCNTL at data memory address, 0x3FFF. In the alternate configuration, the DR1 pin (either DR1A or DR1B depending on the state of the DR1SEL bit) becomes the FI pin and the DT1 pin becomes the FO pin. Additionally, RFS1 is configured as the IRQ0 interrupt input and TFS1 is configured as the IRQ1 interrupt. The serial port clock, SCLK1, is still available in the alternate configuration. Following boot loading from a serial memory device, it is possible to reconfigure the SPORT1 to this alternate configuration. However, if a debugger interface is used, this configuration is not possible as the normal serial port pins are required for debugger communications. –30– REV. B ADMC300 Table VIII. Peripheral Register Map of ADMC300 Address 0x2000–0x2007 0x2008 0x2009 0x200A 0x200B 0x200C 0x200D 0x200E 0x200F 0x2010 0x2011 0x2012–0x2014 0x2015 0x2016 0x2017 0x2018 0x2019–0x201B 0x201C 0x201D 0x201E-0x201F 0x2020 0x2021 0x2022 0x2023 0x2024 0x2025 0x2026 0x2027 0x2028 0x2029 0x202A 0x202B 0x202C 0x202D–0x202F 0x2030 0x2031 0x2032 0x2033 0x2034 0x2035 0x2036 0x2037 0x2038 0x2039 0x203A 0x203B 0x203C–0x203F 0x2040 0x2041 0x2042 0x2043 0x2044 0x2045 0x2046 0x2047 0x2048–0x204F 0x2050 REV. B Name Bits PWMTM PWMDT PWMPD PWMGATE PWMCHA PWMCHB PWMCHC PWMSEG AUXTIM0 AUXTIM1 [15 . . . 0] [9 . . . 0] [9 . . . 0] [9 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [8 . . . 0] [7 . . . 0] [7 . . . 0] MODECTRL SYSSTAT [6 . . . 4] [3 . . . 0] WDTIMER [15 . . . 0] PICVECTOR PICMASK [15 . . . 0] [10 . . . 0] EIUCNT EIUMAXCNT EIUSTAT EIUCTRL EIUPERIOD EIUSCALE EIUTIMER EETCNT EETN EETDIV EETDELTAT EETT EETSTAT [15 . . . 0] [15 . . . 0] [6 . . . 0] [5 . . . 0] [15 . . . 0] [7 . . . 0] [15 . . . 0] [15 . . . 0] [7 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [0] ADC1 ADC2 ADC3 ADC4 ADC5 [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] ADCCTRL ADCSTAT ADCSYNC ADCDIVA ADCDIVB ADCCAL [15 . . . 0] [0] [6 . . . 0] [11 . . . 6] [11 . . . 6] [4 . . . 0] PIOLEVEL PIOMODE PIOPWM [11 . . . 0] [11 . . . 0] [11 . . . 0] PIODIR PIODATA PIOINTEN PIOFLAG [11 . . . 0] [11 . . . 0] [11 . . . 4] [11 . . . 4] ETUA0 [15 . . . 0] –31– Function Reserved PWM Period Register PWM Deadtime Register PWM Pulse Deletion Register PWM Gate Drive Configuration PWM Channel A Duty Cycle PWM Channel B Duty Cycle PWM Channel C Duty Cycle PWM Segment Select Register Aux. PWM Channel 0 Duty Cycle Aux. PWM Channel 1 Duty Cycle Reserved Mode Control Register System Status Register Reserved Watchdog Timer Register Reserved Peripheral Interrupt Vector Address Peripheral Interrupt Mask Register Reserved Encoder Count Register Encoder Maximum Count Register Encoder Interface Status Register Encoder Interface Control Register Encoder Loop Timer Period Register Encoder Loop Timer Scale Register Encoder Loop Timer Latched Value of EIUCNT Register Encoder Event Timer Pulse Decimator Encoder Event Timer Clock Divide Encoder Event Timer Delta Time Encoder Event Timer Period Register Encoder Event Timer Status Register Reserved ADC Channel 1 Data Register ADC Channel 2 Data Register ADC Channel 3 Data Register ADC Channel 4 Data Register ADC Channel 5 Data Register Reserved ADC Control Register ADC Status Register ADC Synchronization Register ADC Bank A Clock Divide Register ADC Bank B Clock Divide Register ADC Calibration Register Reserved PIO Interrupt Configuration PIO Interrupt Mode Control PIO PWM Trip Control Reserved PIO Direction Control PIO Data Register PIO Interrupt Enable Register PIO Interrupt Flag Register Reserved Event Timer Event A—Channel 0 ADMC300 Table VIII. Peripheral Register Map of ADMC300 (Continued) Address Name Bits Function 0x2051 0x2052 0x2053 0x2054 0x2055 0x2056 0x2057–0x205B 0x205C 0x205D 0x205E 0x205F 0x2060 0x2061 0x2062-0x20FF ETUB0 ETUAA0 ETUA1 ETUB1 ETUAA1 ETUTIME [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] ETUCONFIG ETUDIVIDE ETUSTAT ETUCTRL PWMSYNCWT PWMSWT [7 . . . 0] [15 . . . 0] [1 . . . 0] [1 . . . 0] [7 . . . 0] [0] Event Timer Event B—Channel 0 Event Timer Event AA—Channel 0 Event Timer A—Channnel 1 Event Timer Event B—Channel 1 Event Timer Event AA—Channel 1 ETU Timer Register Reserved Event Timer Configuration Event Timer Clock Divide Register Event Timer Status Register Event Timer Control Register PWMSYNC Pulsewidth Control Register PWM Software Trip Register Reserved Table IX. DSP Core Registers Address Name Bits Function 0x3FFF 0x3FFE 0x3FFD 0x3FFC 0x3FFB 0x3FFA 0x3FF9 0x3FF8 0x3FF7 0x3FF6 0x3FF5 0x3FF4 0x3FF3 0x3FF2 0x3FF1 0x3FF0 0x3FEF SYSCNTL MEMWAIT TPERIOD TCOUNT TSCALE SPORT0_RX_WORDS1 SPORT0_RX_WORDS0 SPORT0_TX_WORDS1 SPORT0_TX_WORDS0 SPORT0_CTRL_REG SPORT0_SCLKDIV SPORT0_RFSDIV SPORT0_AUTOBUF_CTRL SPORT1_CTRL_REG SPORT1_SCLKDIV SPORT1_RFSDIV SPORT1_AUTOBUF_CTRL [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [7 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] [15 . . . 0] System Control Register Memory Wait State Control Register Interval Timer Period Register Interval Timer Count Register Interval Timer Scale Register SPORT0 Multichannel Word 1 Receive SPORT0 Multichannel Word 0 Receive SPORT0 Multichannel Word 1 Transmit SPORT0 Multichannel Word 0 Transmit SPORT0 Control Register SPORT0 Clock Divide Register SPORT0 Receive Frame Sync Divide SPORT0 Autobuffer Control Register SPORT1 Control Register SPORT1 Clock Divide Register SPORT1 Receive Frame Sync Divide SPORT1 Autobuffer Control Register –32– REV. B ADMC300 ADC1 (R) ADC2 (R) ADC3 (R) ADC4 (R) ADC5 (R) 15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 0 0 1 1 1 1 0 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 DM (0x2030) DM (0x2031) DM (0x2032) DM (0x2033) DM (0x2034) ADCCTRL (R/W) 0 = NORMAL 1 = RESET 0 = NORMAL 1 = RESET FILTER MODE DM (0x2036) BANK A CONVERT START BANK B CONVERT START 0 = INTERNAL 1 = EXTERNAL MODULATOR MODE BANK A MODE 0 = CONVST 1 = READ RESERVED (SET TO 1) BANK B MODE 0 = POWER-ON 1 = POWER-DOWN REFERENCE POWER-DOWN MUX0 CONTROL 0 = LOW 1 = HIGH MUX1 CONTROL 0 = POWER-ON 1 = POWER-DOWN 0 = BANK A 1 = BANK B BANK B POWER-DOWN MUX2 CONTROL BANK A POWER-DOWN BANK A SYNCHRONIZATION BANK B SYNCHRONIZATION 0 = DISABLE 1 = ENABLE BUSY SIGNAL ADCSTAT (R) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2037) BUSY SIGNAL 0 = NORMAL 1 = FILTERS BUSY SETTLING ADCSYNC (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2038) RELATIVE PHASE OF PWMSYNC TO ADC CONVST Figure 20. Configuration of ADMC300 Registers Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a gray field – these bits should always be written as shown. REV. B –33– ADMC300 ADCDIVA (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 DM (0x2039) ADC BANK A DIVIDE VALUE ADCDIVB (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 DM (0x203A) ADC BANK B DIVIDE VALUE ADCCAL (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x203B) ADC1 CALIBRATION ADC2 CALIBRATION ADC3 CALIBRATION 0 = DISABLE 1 = ENABLE ADC4 CALIBRATION ADC5 CALIBRATION Figure 21. Configuration of ADMC300 Registers Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a gray field – these bits should always be written as shown. –34– REV. B ADMC300 PWMTM (R/W) PWMCHA (R/W) PWMCHB (R/W) PWMCHC (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM (0x2008) DM (0x200C) DM (0x200D) DM (0x200E) PWMDT (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 DM (0x2009) PWMPD (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 DM (0x200A) PWMGATE (R/W) 15 1 = ENABLE 0 = DISABLE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 DM (0x200B) LOW-SIDE CHOPPING GDCLK HIGH-SIDE CHOPPING PWMSEG (R/W) 15 1 = ENABLE 0 = DISABLE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 DM (0x200F) AH/AL CROSSOVER CH ENABLE BH/BL CROSSOVER CL ENABLE CH/CL CROSSOVER BH ENABLE BL ENABLE 1 = DISABLE 0 = ENABLE AH ENABLE AL ENABLE PWMSYNCWT (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 1 6 5 4 3 2 1 0 DM (0x2060) PWMSWT (R/W) 15 14 13 12 11 10 9 8 7 0 DM (0x2061) Figure 22. Configuration of ADMC300 Registers Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a gray field – these bits should always be written as shown. REV. B –35– ADMC300 EIUMAXCNT (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 EIUCNT (R/W) EIUPERIOD (R/W) EIUTIMER (R/W) EETCNT (R) 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 EIUSCALE (R/W) 9 8 7 6 5 4 3 2 1 0 DM (0x2021) DM (0x2020) DM (0x2024) DM (0x2026) DM (0x2027) DM (0x2025) EIUSTAT (R) 1 = RECEIVED 0 = NOT RECEIVED 15 14 13 12 11 10 9 8 7 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 DM (0x2022) FIRST ZERO MARKER EIZP STATE 1 = HI 0 = LO EIB STATE EIU COUNT ERROR 1 = ERROR 0 = NO ERROR EIU COUNT DIRECTION 1 = UP 0 = DOWN EIU STATE EIA STATE 1 = NOT INITIALIZED 0 = INITIALIZED EIUCTRL (R/W) 15 14 1 = ENABLE 0 = DISABLE 1 = EIUTIMER TIMEOUT 0 = EIUCNT READ 1 = ENABLE 0 = DISABLE 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 DM (0x2023) ENABLE EIU LOOP TIMER DIRECTION REVERSE EET LATCH DEFINITION ZERO MARKER EIU ERROR MONITORING SINGLE NORTH MARKER MODE 1 = SWAP EIA AND EIB 0 = DO NOT SWAP EIA/EIB 1 = USE FOR RESET 0 = DO NOT USE 1 = ENABLE 0 = DISABLE Figure 23. Configuration of ADMC300 Registers Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a gray field – these bits should always be written as shown. –36– REV. B ADMC300 EETN (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2028) EETDIV (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 DM (0x2029) EETDELTAT (R) 15 14 13 12 11 10 9 8 7 DM (0x202A) EETT (R) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM (0x202B) EETSTAT(R) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x202C) ENCODER EVENT TIMER OVERFLOW 0 = NO OVERFLOW 1 = OVERFLOW Figure 24. Configuration of ADMC300 Registers Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a gray field – these bits should always be written as shown. REV. B –37– ADMC300 PIOLEVEL (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2040) 0 = FALLING EDGE (PIOMODE = 0) = ACTIVE LOW (PIOMODE = 1) 1 = RISING EDGE (PIOMODE = 0) = ACTIVE HIGH (PIOMODE = 1) PIOMODE (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2041) 0 = EDGE SENSITIVE 1 = LEVEL SENSITIVE PIOPWM (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 DM (0x2042) 0 = PWM TRIP DISABLE 1 = PWM TRIP ENABLE PIODIR (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2044) 0 = INPUT 1 = OUTPUT PIODATA (R/W) 15 14 13 12 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 DM (0x2045) 0 = LOW LEVEL 1 = HIGH LEVEL PIOINTEN (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2046) 0 = INTERRUPT DISABLE 1 = INTERRUPT ENABLE PIOFLAG (R) 15 14 13 12 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 DM (0x2047) 0 = NO INTERRUPT 1 = INTERRUPT FLAGGED Figure 25. Configuration of ADMC300 Registers Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a gray field – these bits should always be written as shown. –38– REV. B ADMC300 AUXTIM0 (W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x2010) AUX0 DUTY CYCLE = AUXTIM0/256 15 14 13 12 11 10 9 0 0 0 0 0 0 0 AUXTIM1 (W) 8 7 6 0 0 0 5 4 3 2 1 0 0 0 0 0 0 0 DM (0x2011) AUX1 DUTY CYCLE = AUXTIM1/256 ETUA0 (R) ETUB0 (R) ETUAA0 (R) ETUA1 (R) ETUB1 (R) ETUAA1 (R) ETUTIME (R) 15 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 DM (0x2050) DM (0x2051) DM (0x2052) DM (0x2053) DM (0x2054) DM (0x2055) DM (0x2056) ETUCONFIG (R/W) 0 = SINGLE-SHOT 1 = FREE-RUNNING DM (0x205C) ETU0 EVENT A 0 = FALLING EDGE 1 = RISING EDGE ETU0 EVENT B 0 = FALLING EDGE 1 = RISING EDGE ETU0 INTERRUPT 0 = NEXT EVENT A 1 = EVENT B ETU0 MODE 0 = SINGLE-SHOT 1 = FREE-RUNNING ETU1 MODE 0 = NEXT EVENT A 1 = EVENT B ETU1 INTERRUPT 0 = FALLING EDGE 1 = RISING EDGE ETU1 EVENT B 0 = FALLING EDGE 1 = RISING EDGE ETU1 EVENT A ETUDIVIDE (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x205D) ETUSTAT (R) 0 = NOT CAPTURED 1 = SEQUENCE CAPTURED 1 0 DM (0x205E) ETU1 ETU0 0 = NOT CAPTURED 1 = SEQUENCE CAPTURED ETUCTRL (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = DO NOT CAPTURE 1 = START CAPTURE ETU1 DM (0x205F) ETU0 0 = DO NOT START 1 = START CAPTURE Figure 26. Configuration of ADMC300 Registers Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a gray field – these bits should always be written as shown. REV. B –39– ADMC300 IMASK (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 DSP REGISTER TIMER PERIPHERAL (OR IRQ2) SPORT1 RECEIVE (OR IRQ0) RESERVED (SET TO 0) 0 = DISABLE (MASK) 1 = ENABLE SPORT0 TRANSMIT SPORT1 TRANSMIT (OR IRQ1) 0 = DISABLE (MASK) 1 = ENABLE SPORT0 RECEIVE SOFTWARE 1 SOFTWARE 0 PICMASK (R/W) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM (0x201D) PWMTRIP 0 = DISABLE (MASK) 1 = ENABLE ADC BANK A PIO3 PWMSYNC PIO2 ADC BANK B PIO1 PIO (PIO4 TO PIO11) PIO0 ENCODER INTERFACE 0 = DISABLE (MASK) 1 = ENABLE EVENT TIMER 0 = DISABLE 1 = ENABLE 4 3 0 0 ICNTL 2 1 0 1 0 1 DSP REGISTER IRQ0 SENSITIVITY INTERRUPT NESTING 0 = LEVEL 1 = EDGE IRQ1 SENSITIVITY IRQ2 SENSITIVITY IFC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP REGISTER INTERRUPT FORCE INTERRUPT CLEAR IRQ2 TIMER SPORT0 TRANSMIT SPORT1 RECEIVE OR IRQ0 SPORT0 RECEIVE SPORT1 TRANSMIT OR IRQ1 SOFTWARE 1 SOFTWARE 0 SOFTWARE 0 SOFTWARE 1 SPORT1 TRANSMIT OR IRQ1 SPORT0 RECEIVE SPORT1 RECEIVE OR IRQ0 SPORT0 TRANSMIT TIMER IRQ2 Figure 27. Configuration of ADMC300 Registers Default bit values are shown; if no value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a gray field – these bits should always be written as shown. –40– REV. B ADMC300 15 14 13 12 11 10 MODECTRL (R/W) 9 8 7 6 5 4 0 0 0 3 2 1 0 DM (0x2015) DATA RECEIVE SELECT PWM MODE 1 = DOUBLE UPDATE 0 = SINGLE UPDATE 1 = DR1B 0 = DR1A SPORT1 MODE 1 = UART MODE 0 = SPORT MODE SYSSTAT (R) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM (0x2016) 1 = SECOND HALF CYCLE 0 = FIRST HALF CYCLE 15 14 13 12 11 10 0 0 0 0 1 1 0 = DISABLED 1 = ENABLED SPORT0 ENABLE 0 = DISABLED 1 = ENABLED SPORT1 ENABLE PWM PHASE FLAG SYSCNTL (R/W) 9 8 7 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 14 13 12 11 10 1 0 0 0 0 0 MEMWAIT (R/W) 9 8 7 6 0 0 0 0 1 = HI 0 = LO WATCHDOG FLAG 1 = WATCHDOG TRIP 0 = NO WATCHDOG TRIP PWMPOL PIN STATE 1 = HI = > ACTIVE HI 0 = LO = > ACTIVE LO DM (0x3FFF) 0 = FI, FO, IRQ0, IRQ1, SCLK 1 = SERIAL PORT SPORT1 CONFIGURE 15 PWMTRIP PIN STATE 5 4 3 2 1 0 0 0 0 0 0 0 DM (0x3FFE) Figure 28. Configuration of ADMC300 Registers Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field – these bits should always be written as shown. REV. B –41– ADMC300 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead TQFP (ST-80) 0.063 (1.60) MAX 0.030 (0.75) 0.020 (0.50) 41 40 60 61 0.486 (12.35) TYP 0.553 (14.05) 0.549 (13.95 0.640 (16.25) 0.620 (15.75) SEATING PLANE TOP VIEW (PINS DOWN) 0.057 (1.45) 0.053 (1.35) 80 21 20 1 0.029 (0.73) 0.022 (0.57) 0.014 (0.35) 0.010 (0.25) PRINTED IN U.S.A. 0.004 (0.10) MAX 0.006 (0.15) 0.002 (0.05) C3205b–5–6/00 (rev. B) 00103 0.640 (16.25) 0.620 (15.75) 0.553 (14.05) 0.549 (13.95) 0.486 (12.35) TYP –42– REV. B