CYPRESS CY7C343-35JC

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CY7C343
64-Macrocell MAX® EPLD
Features
Functional Description
• 64 MAX® macrocells in four LABs
The CY7C343 is a high-performance, high-density erasable
programmable logic device, available in 44-pin PLCC and
HLCC packages.
• Eightdedicated inputs, 24 bidirectional I/O pins
• Programmable interconnect array
The CY7C343 contains 64 highly flexible macrocells and 128
expander product terms. These resources are divided into four
Logic Array Blocks (LABs) connected through the Programmable Inter-connect Array (PIA). There are eight input pins,
one that doubles as a clock pin when needed. The CY7C343
also has 28 I/O pins, each connected to a macrocell (six for
LABs A and C, and eight for LABs B and D). The remaining 36
macrocells are used for embedded logic.
• 0.8-micron double-metal CMOS EPROM technology
• Available in 44-pin HLCC, PLCC
• Lowest power MAX device
The CY7C343 is excellent for a wide range of both
synchronous and asynchronous applications.
Logic Block Diagram 9 INPUT
INPUT 35
11 INPUT
INPUT/CLK 34
12 INPUT
INPUT 33
13 INPUT
INPUT 31
DEDICATED INPUTS
SYSTEM CLOCK
LAB A
I/O PINS
2
4
5
6
7
8
LAB D
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELL 56
MACROCELL 55
MACROCELL 54
MACROCELL 53
MACROCELL 52
MACROCELL 51
MACROCELL 50
MACROCELL 49
MACROCELLS 7–16
P
I
A
LAB B
I/O PINS
15
16
17
18
19
20
22
23
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22
MACROCELL 23
MACROCELL 24
1
44
42
41
40
39
38
37
I/O PINS
30
29
28
27
26
24
I/O PINS
MACROCELLS 57–64
LAB C
MACROCELL 38
MACROCELL 37
MACROCELL 36
MACROCELL 35
MACROCELL 34
MACROCELL 33
MACROCELLS 39–48
MACROCELLS 25–32
(3, 14, 25, 36)
(10, 21, 32, 43)
VCC
GND
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
Cypress Semiconductor Corporation
Document #: 38-03015 Rev. *B
Commercial
Military
Industrial
Commercial
Military
Industrial
•
7C343-20
20
135
225
225
125
200
200
3901 North First Street
7C343-25
25
135
225
225
125
200
200
•
7C343-30
30
135
225
225
125
200
200
7C343-35
35
135
225
225
125
200
200
Unit
ns
mA
mA
San Jose, CA 95134
•
408-943-2600
Revised April 22, 2004
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CY7C343
Pin Configuration
I/O
I/O
1
2
I/O
3
I/O
4
GND
I/O
5
I/O
I/O
6
V
CC
I/O
I/O
HLCC, PLCC
Top View
44 43 42 41 40
I/O
7
39
I/O
I/O
8
38
I/O
INPUT
9
37
I/O
GND
10
36
VCC
INPUT
11
35
INPUT
INPUT
12
34
INPUT/CLK
INPUT
13
33
INPUT
VCC
14
32
GND
I/O
15
31
INPUT
I/O
I/O
7C343
I/O
16
30
I/O
17
29
Document #: 38-03015 Rev. *B
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
GND
I/O
I/O
I/O
18 19 20 21 22 23 24 25 26 27 28
Page 2 of 19
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CY7C343
Programmable Interconnect Array
Timing Considerations
The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay tEXP to the overall delay. Similarly, there is an
additional tPIA delay for an input from an I/O pin when
compared to a signal from a straight input pin.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals, which
may cause glitches in internal or external logic. The fixed
delay, regardless of programmable interconnect array configuration, simplifies design by ensuring that internal signal
skews or races are avoided. The result is simpler design implementation, often in a single pass, without the multiple internal
logic placement and routing iterations required for a programmable gate array to achieve design timing objectives.
When calculating synchronous frequencies, use tS1 if all inputs
are on the input pins. tS2 should be used if data is applied at
an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting
frequency in the data path mode unless 1/(tWH + tWL) is less
than 1/tS2.
Timing Delays
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on dedicated input pins. If any data is
applied to an I/O pin, tAS2 must be used as the required set-up
time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH)
becomes the limiting frequency in the data path mode unless
1/(tAWH + tAH) is less than 1/(tAS2 + tAH).
Timing delays within the CY7C343 may be easily determined
using Warp®, Warp Professional™, or Warp Enterprise™
software. The CY7C343 has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this data sheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect
device reliability. The CY7C343 contains circuitry to protect
device pins from high static voltages or electric fields;
however, normal precautions should be taken to avoid
applying any voltage higher than maximum rated voltages.
For proper operation, input and output pins must be
constrained to the range GND < (VIN or VOUT) < VCC. Unused
inputs must always be tied to an appropriate logic level (either
VCC or GND). Each set of VCC and GND pins must be
connected together directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled to GND, directly
at the device. Decoupling capacitors should have good
frequency response, such as monolithic ceramic types.
Document #: 38-03015 Rev. *B
When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which
of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest
frequency. The lowest of these frequencies is the maximum
data path frequency for the synchronous configuration.
When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine
which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous configuration.
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same synchronous
clock. If tOH is greater than the minimum required input hold
time of the subsequent synchronous logic, then the devices
are guaranteed to function properly with a common
synchronous clock under worst-case environmental and
supply voltage conditions.
The parameter tAOH indicates the system compatibility of this
device when driving subsequent registered logic with a
positive hold time and using the same clock as the CY7C343.
In general, if tAOH is greater than the minimum required input
hold time of the subsequent logic (synchronous or
asynchronous), then the devices are guaranteed to function
properly under worst-case environmental and supply voltage
conditions, provided the clock signal source is the same. This
also applies if expander logic is used in the clock signal path
of the driving device, but not for the driven device. This is due
to the expander logic in the second device’s clock signal path
adding an additional delay (tEXP), causing the output data from
the preceding device to change prior to the arrival of the clock
signal at the following device’s register.
Page 3 of 19
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EXPANDER
DELAY
tEXP
LOGIC ARRAY
CONTROL DELAY
tLAC
INPUT
INPUT
DELAY
tIN
LOGIC ARRAY
DELAY
tLAD
CY7C343
REGISTER
OUTPUT
DELAY
tCLR
tPRE
tRSU
tRH
tRD
tCOMB
tLATCH
INPUT/
OUTPUT
tOD
tXZ
tZX
SYSTEM CLOCK DELAY tICS
PIA
DELAY
tPIA
CLOCK
DELAY
tIC
FEEDBACK
DELAY
tFD
I/O DELAY
tIO
Figure 1. CY7C343 Internal Timing Model
Document #: 38-03015 Rev. *B
Page 4 of 19
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Maximum Ratings
CY7C343
DC Output Current, per Pin ......................–25 mA to +25 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................ –65°C to +150°C
Ambient Temperature with
Power Applied.................................................. 0°C to +70°C
Maximum Junction Temperature
(Under Bias)................................................................. 150°C
Supply Voltage to Ground Potential ............... –2.0V to +7.0V
Maximum Power Dissipation...................................2500 mW
DC Input Voltage[1] .........................................–3.0V to +7.0V
DC Program Voltage..................................................... 13.0V
Static Discharge Voltage........................................... > 1100V
(per MIL–STD–883, method 3015)
Operating Range[2]
Range
Commercial
Industrial
Military
Ambient Temperature
0°C to +70°C
–40°C to +85°C
–55°C to +125°C (Case)
VCC
5V ±5%
5V ±10%
5V ±10%
DC VCC or GND Current ............................................500 mA
Electrical Characteristics Over the Operating Range[3]
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8 mA
Min.
Max.
2.4
Unit
V
0.45
V
VIH
Input HIGH Level
2.2
VCC + 0.3
V
VIL
Input LOW Level
–0.3
0.8
V
IIX
Input Current
GND < VIN < VCC
–10
+10
µA
IOZ
Output Leakage Current
VO = VCC or GND
–40
+40
µA
–30
0.5V[4, 5]
IOS
Output Short Circuit Current
VCC = Max., VOUT =
–90
mA
ICC1
Power Supply Current (Standby)
VI = VCC or GND
(No Load)
Commercial
125
mA
Military/Industrial
200
mA
ICC2
Power Supply Current[6]
VI = VCC or GND (No
Load) f = 1.0 MHz[5, 6]
Commercial
135
mA
Military/Industrial
225
mA
tR
Recommended Input Rise Time
100
ns
tF
Recommended Input Fall Time
100
ns
Capacitance[7]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
VIN = 2V, f = 1.0 MHz
VOUT = 2.0V, f = 1.0 MHz
Max.
10
10
Unit
pF
pF
AC Test Loads and Waveforms[7]
R1 464 Ω
R1 464Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
250Ω
50 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
3.0V
INCLUDING
JIG AND
SCOPE
(a)
R2
250Ω
5 pF
10%
GND
< 6 ns
90%
90%
10%
< 6 ns
(b)
THÉVENIN EQUIVALENT (commercial/military)
163 Ω
OUTPUT
1.75V
Notes:
1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns.
2. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
3. Typical values are for TA = 25°C and VCC = 5V.
4. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid
test problems caused by tester ground degradation.
5. Guaranteed but not 100% tested.
6. Measured with device programmed as a 16-bit counter in each LAB. This parameter is tested periodically by sampling production material.
7. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external
timing parameters are measured referenced to external pins of the device.
Document #: 38-03015 Rev. *B
Page 5 of 19
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CY7C343
External Synchronous Switching Characteristics Over Operating Range [7]
7C343-20
Parameter
Description
Min.
Max.
7C343-25
Min.
Max.
Unit
25
ns
tPD1
Dedicated Input to Combinatorial Output Delay[8]
tPD2
I/O Input to Combinatorial Output Delay[9]
32
39
tPD3
Dedicated Input to Combinatorial Output Delay with Expander Com’l/Ind
Delay[10]
Mil
30
37
30
37
tPD4
I/O Input to Combinatorial Output Delay with Expander Delay[5, Com’l/Ind
42
51
42
51
tEA
Input to Output Enable Delay[5, 8]
20
25
tER
Input to Output Disable Delay[5, 8]
Mil
20
25
tCO1
Synchronous Clock Input to Output Delay
Com’l/Ind
12
14
Mil
12
14
tCO2
Synchronous Clock to Local Feedback to Combinatorial
Output[5, 12]
Com’l/Ind
25
30
tS1
Dedicated Input or Feedback Set-Up Time to Synchronous
Clock Input[8]
Com’l/Ind
tS2
I/O Input Set-Up Time to Synchronous Clock Input[8, 13]
tH
Input Hold Time from Synchronous Clock Input[8]
tWH
Synchronous Clock Input HIGH Time
tWL
Synchronous Clock Input LOW Time
Mil
6
8
tRW
Asynchronous Clear Width[5, 8]
Com’l/Ind
20
25
Mil
20
25
tRR
Asynchronous Clear Recovery Time[5, 8]
Com’l/Ind
20
25
Mil
20
tRO
Asynchronous Clear to Registered Output Delay[8]
Com’l/Ind
20
Mil
20
25
Com’l/Ind
32
39
Mil
11]
Com’l/Ind
Mil
20
25
Com’l/Ind
20
25
Mil
ns
ns
ns
ns
ns
ns
ns
30
12
15
Com’l/Ind
24
30
Mil
24
30
Com’l/Ind
0
0
Mil
0
0
Com’l/Ind
6
8
Mil
6
8
Com’l/Ind
6
8
Mil
ns
15
ns
ns
ns
ns
ns
ns
25
Com’l/Ind
20
25
Mil
20
25
ns
Notes:
8. This specification is a measure of the delay from input signal applied to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13, 31, 33, 34, or 35) to combinatorial
output on any output pin. This delay assumes no expander terms are used to form the logic function. When this note is applied to any parameter specification it
indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path
(either clock or data) employs expander logic. If an input signal is applied to an I/O pin, an additional delay equal to tPIA should be added to the comparable delay
for a dedicated input. If expanders are used, add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders.
9. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
10. This specification is a measure of the delay from an input signal applied to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13, 31, 33, 34, or 35) to combinatorial
output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass
through the expander logic. This parameter is tested periodically by sampling production material.
11. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to
form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling
production material.
12. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array
and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This
parameter is tested periodically by sampling production material.
13. If data is applied to an I/O input for capture by a macrocell register, the I/O pin set-up time minimums should be observed. These parameters are tS2 for synchronous
operation and tAS2 for asynchronous operation..
Document #: 38-03015 Rev. *B
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CY7C343
External Synchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-20
Parameter
tPR
tPO
tCF
tP
fMAX1
fMAX2
fMAX3
fMAX4
tOH
tPW
Description
Asynchronous Preset Recovery Time
[5, 8]
Asynchronous Preset to Registered Output Delay[8]
Synchronous Clock to Local Feedback Input[5, 14]
External Synchronous Clock Period (1/fMAX3)[5]
External Maximum Frequency (1/(tCO1 + tS1))[5, 15]
Min.
Max.
7C343-25
Min.
Com’l/Ind
20
25
Mil
20
25
20
25
Mil
20
25
Com’l/Ind
3
3
Mil
3
3
Com’l/Ind
12
16
Mil
12
16
Com’l/Ind
41.6
34
Mil
41.6
34
66.6
55
66.6
55
Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS1 + tH), Com’l/Ind
or (1/tCO1)[5, 17]
Mil
83.3
62.5
83.3
62.5
Maximum Register Toggle Frequency (1/(tWL+tWH))[5, 18]
Com’l/Ind
83.3
62.5
Mil
83.3
62.5
Com’l/Ind
3
3
Mil
3
3
Com’l/Ind
20
25
Mil
20
25
Asynchronous Preset Width[5, 8]
Unit
ns
Com’l/Ind
Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 Com’l/Ind
+ tCF)) or (1/tCO1)[5, 16]
Mil
Output Data Stable Time from Synchronous Clock Input[5, 19]
Max.
ns
ns
ns
MHz
MHz
MHz
MHz
ns
ns
Notes:
14. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array input.
This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same
LAB. This parameter is tested periodically by sampling production material.
15. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can operate.
It is assumed that all data inputs and feedback signals are applied to dedicated inputs.
16. This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can operate. If register output states must
also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. All feedback is assumed to be local, originating within
the same LAB..
17. This frequency indicates the maximum frequency at which the device may operate in data path mode. This delay assumes data input signals are applied to
dedicated inputs and no expander logic is used.
18. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled.
19. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
Document #: 38-03015 Rev. *B
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CY7C343
External Synchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-30
Parameter
Description
7C343-35
Min. Max. Min. Max. Unit
tPD1
Dedicated Input to Combinatorial Output Delay[8]
tPD2
I/O Input to Combinatorial Output Delay[9]
tPD3
Dedicated Input to Combinatorial Output Delay with Expander
Delay[10]
tPD4
I/O Input to Combinatorial Output Delay with Expander Delay[5, 11] Com’l/Ind
tEA
Input to Output Enable Delay[5, 8]
Mil
30
35
tER
Input to Output Disable Delay[5, 8]
Com’l/Ind
30
35
Mil
30
35
tCO1
Synchronous Clock Input to Output Delay
Com’l/Ind
16
20
tCO2
Synchronous Clock to Local Feedback to Combinatorial Output[5, 12] Com’l/Ind
tS1
Dedicated Input or Feedback Set-Up Time to Synchronous Clock Com’l/Ind
Input[8]
Mil
20
20
25
tS2
I/O Input Set-Up Time to Synchronous Clock Input[8, 13]
Com’l/Ind
35
42
Mil
35
42
tH
Input Hold Time from Synchronous Clock Input[8]
Com’l/Ind
0
0
Mil
0
0
tWH
Synchronous Clock Input HIGH Time
Com’l/Ind
10
12.5
Mil
10
12.5
tWL
Synchronous Clock Input LOW Time
Com’l/Ind
10
12.5
Mil
10
12.5
tRW
Asynchronous Clear Width[5, 8]
Com’l/Ind
30
35
tRR
Asynchronous Clear Recovery Time[5, 8]
tRO
Asynchronous Clear to Registered Output Delay[8]
tPR
Asynchronous Preset Recovery Time[5, 8]
tPO
Asynchronous Preset to Registered Output Delay[8]
tCF
Synchronous Clock to Local Feedback Input[5, 14]
tP
External Synchronous Clock Period (1/fMAX3)[5]
fMAX1
External Maximum Frequency (1/(tCO1 + tS1))[5, 15]
Com’l/Ind
30
Mil
30
35
Com’l/Ind
44
53
Mil
44
53
Com’l/Ind
44
55
Mil
44
55
58
73
Mil
58
73
Com’l/Ind
30
35
Mil
Mil
16
20
35
42
35
30
35
Com’l/Ind
30
35
Mil
30
Com’l/Ind
Mil
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
35
ns
35
Com’l/Ind
30
35
Mil
30
35
Com’l/Ind
3
5
Mil
ns
ns
35
30
30
ns
35
30
Com’l/Ind
ns
42
25
Mil
Mil
Document #: 38-03015 Rev. *B
35
3
ns
ns
5
Com’l/Ind
20
25
Mil
20
25
Com’l/Ind
27
22.2
Mil
27
22.2
ns
MHz
Page 8 of 19
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CY7C343
External Synchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-30
Parameter
fMAX2
fMAX3
fMAX4
tOH
tPW
Description
7C343-35
Min. Max. Min. Max. Unit
Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + Com’l/Ind
tCF)) or (1/tCO1)[5, 16]
Mil
43
33
43
33
Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS1 + tH), Com’l/Ind
or (1/tCO1)[5, 17]
Mil
50
40
50
40
Maximum Register Toggle Frequency (1/(tWL+tWH))[5, 18]
Com’l/Ind
50
40
Mil
50
40
Com’l/Ind
3
3
Mil
3
3
Com’l/Ind
30
35
Mil
30
35
Output Data Stable Time from Synchronous Clock Input[5, 19]
Asynchronous Preset Width[5, 8]
MHz
MHz
MHz
ns
ns
External Asynchronous Switching Characteristics Over Operating Range [7]
7C343-20
Parameter
tACO1
tACO2
tAS1
tAS2
tAH
tAWH
tAWL
tACF
tAP
fMAXA1
Description
Asynchronous Clock Input to Output
Delay[8]
Min.
Min.
Com’l/Ind
20
12
Mil
20
Asynchronous Clock Input to Local Feedback to Combinatorial Com’l/Ind
Output[20]
Mil
Dedicated Input or Feedback Set-Up Time to Asynchronous
Clock Input[8]
I/O Input Set-Up Time to Asynchronous Clock Input[8]
Input Hold Time from Asynchronous Clock Input[8]
Asynchronous Clock Input HIGH Time[8]
Asynchronous Clock Input LOW Time[8, 21]
Asynchronous Clock to Local Feedback Input[5, 22]
External Asynchronous Clock Period (1/fMAXA4)[5]
7C343-25
Max.
Max.
ns
32
25
32
25
Com’l/Ind
4
40
Mil
4
40
Com’l/Ind
15
5
Mil
15
5
Com’l/Ind
5
20
Mil
5
20
Com’l/Ind
9
6
Mil
9
6
Com’l/Ind
7
11
Mil
7
11
Com’l/Ind
13
9
Mil
13
9
ns
ns
ns
16
15
16
15
20
41.6
20
ns
ns
Com’l/Ind
41.6
ns
ns
Mil
External Maximum Frequency in Asynchronous Mode 1/(tACO1 Com’l/Ind
+ tAS1)[5, 23]
Mil
Unit
ns
MHz
Notes:
20. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB
logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input.
The clock signal is applied to a dedicated input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material.
21. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped. If a
given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL.
22. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay
plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback
within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin. This parameter is tested periodically
by sampling production material.
23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can
operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no expander logic is employed in the clock
signal path or data path.
Document #: 38-03015 Rev. *B
Page 9 of 19
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CY7C343
External Asynchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-20
Parameter
fMAXA2
fMAXA3
fMAXA4
tAOH
Min.
Description
[5, 24]
Maximum Internal Asynchronous Frequency
Data Path Maximum Frequency in Asynchronous Mode[5, 25]
Max.
7C343-25
Min.
Max.
Unit
Com’l/Ind
58.8
33
Mil
58.8
50
Com’l/Ind
50
50
MHz
Mil
50
MHz
Maximum Asynchronous Register Toggle Frequency 1/(tAWH + Com’l/Ind
tAWL)[5, 26]
Mil
62.5
40
62.5
40
Output Data Stable Time from Asynchronous Clock Input[5, 27] Com’l/Ind
12
15
12
15
Mil
MHz
ns
External Asynchronous Switching Characteristics Over Operating Range [7]
7C343-30
Parameter
tACO1
tACO2
tAS1
tAS2
tAH
tAWH
tAWL
tACF
tAP
fMAXA1
fMAXA2
fMAXA3
fMAXA4
Description
Asynchronous Clock Input to Output
Delay[8]
Min.
Max.
7C343-35
Min.
Com’l/Ind
30
35
Mil
30
35
46
55
46
55
Asynchronous Clock Input to Local Feedback to Combinatorial Com’l/Ind
Output[20]
Mil
Dedicated Input or Feedback Set-Up Time to Asynchronous
Clock Input[8]
Com’l/Ind
6
8
Mil
6
8
I/O Input Set-Up Time to Asynchronous Clock Input[8]
Com’l/Ind
25
30
Mil
25
30
Com’l/Ind
8
10
Mil
8
10
Com’l/Ind
14
16
Mil
14
16
Com’l/Ind
11
14
Mil
11
14
Input Hold Time from Asynchronous Clock Input[8]
Asynchronous Clock Input HIGH Time[8]
Asynchronous Clock Input LOW Time[8, 21]
Asynchronous Clock to Local Feedback Input[5, 22]
External Asynchronous Clock Period (1/fMAXA4)[5]
ns
ns
ns
18
22
18
22
25
30
25
30
External Maximum Frequency in Asynchronous Mode 1/(tACO1 Com’l/Ind
+ tAS1)[5, 23]
Mil
27
23
27
23
Maximum Internal Asynchronous Frequency[5, 24]
Com’l/Ind
40
33
Mil
40
33
Com’l/Ind
33
28
Mil
33
28
40
33
40
33
Maximum Asynchronous Register Toggle Frequency 1/(tAWH + Com’l/Ind
tAWL)[5, 26]
Mil
ns
ns
Com’l/Ind
Mil
ns
ns
Mil
Com’l/Ind
Data Path Maximum Frequency in Asynchronous Mode[5, 25]
Max. Unit
ns
ns
MHz
MHz
MHz
MHz
Notes:
24. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate.
This parameter is determined by the lesser of (1/tACF + tAS1)) or (1/(tAWH +tAWL)). If register output states must also control external points, this frequency can still be observed
as long as this frequency is less than 1/tACO1.
25. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by
the least of 1/(tAWH + tAWL), 1/(tAS1 + tAH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used.
26. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode
by a clock signal applied to an external dedicated input pin.
27. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input.
Document #: 38-03015 Rev. *B
Page 10 of 19
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CY7C343
External Asynchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-30
Parameter
tAOH
Description
Min.
[5, 27]
Output Data Stable Time from Asynchronous Clock Input
Max.
7C343-35
Max. Unit
Min.
Com’l/Ind
15
15
Mil
15
15
ns
Internal Switching Characteristics Over Operating Range [7]
7C343-20
Parameter
tIN
tIO
tEXP
tLAD
tLAC
tOD
tZX
tXZ
tRSU
tRH
tLATCH
tRD
tCOMB
tCH
tCL
tIC
tICS
Description
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay[28]
Output Buffer Disable Delay
Min.
Max.
7C343-25
Min.
4
5
4
5
Com’l/Ind
4
5
Mil
4
5
Com’l/Ind
10
12
Mil
10
12
Com’l/Ind
10
12
Mil
10
12
Com’l/Ind
8
10
Mil
8
10
Com’l/Ind
4
5
Mil
4
5
Com’l/Ind
8
10
Mil
8
10
Com’l/Ind
8
10
Mil
8
10
6
4
6
Register Hold Time Relative to Clock Signal at Com’l/Ind
Register
Mil
4
6
4
6
Transparent Mode Delay[29]
Clock HIGH Time
Clock LOW Time
Asynchronous Clock Logic Delay
Synchronous Clock Delay
ns
Com’l/Ind
4
Register Delay
Unit
Mil
Register Set-Up Time Relative to Clock Signal Com’l/Ind
at Register
Mil
Flow-Through Latch Delay
Max.
2
3
2
3
Com’l/ Ind
1
1
Mil
1
1
Com’l/Ind
2
3
Mil
2
3
6
8
6
8
Com’l/Ind
6
8
Mil
6
8
ns
ns
ns
ns
ns
ns
Com’l/Ind
Com’l/Ind
ns
ns
Mil
Mil
ns
ns
ns
ns
ns
ns
Com’l/Ind
12
14
Mil
12
14
Com’l/Ind
2
2
Mil
2
2
ns
ns
Notes:
28. Sample tested only for an output change of 500 mV.
29. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial
operation.
Document #: 38-03015 Rev. *B
Page 11 of 19
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CY7C343
Internal Switching Characteristics Over Operating Range (continued)[7]
7C343-20
Parameter
tFD
tPRE
tCLR
tPCW
tPCR
tPIA
Description
Feedback Delay
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Min.
7C343-25
Min.
Max.
Unit
ns
Com’l/Ind
1
1
Mil
1
1
Com’l/Ind
4
5
Mil
4
5
Com’l/Ind
4
5
Mil
4
5
Asynchronous Preset and Clear Pulse Width Com’l /Ind
Asynchronous Preset and Clear Recovery
Time
Max.
4
5
Mil
4
5
Com’l/Ind
4
5
Mil
4
5
Programmable Interconnect Array Delay Time Com’l/Ind
Mil
ns
ns
ns
ns
12
14
12
14
ns
Internal Switching Characteristics Over Operating Range [7]
7C343-30
Parameter
tIN
tIO
tEXP
tLAD
tLAC
tOD
tZX
tXZ
tRSU
tRH
tLATCH
tRD
tCOMB
Description
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay[28]
Output Buffer Disable Delay
Min.
Max.
7C343-35
Min.
7
9
7
9
Com’l/Ind
5
7
Mil
5
7
Com’l/Ind
14
20
Mil
14
20
Com’l/Ind
14
16
Mil
14
16
Com’l/Ind
12
13
Mil
12
13
Com’l/Ind
5
6
Mil
5
6
Com’l/Ind
11
13
Mil
11
13
Com’l/Ind
11
13
Mil
11
13
10
8
10
Register Hold Time Relative to Clock Signal at Com’l/Ind
Register
Mil
8
12
8
12
Transparent Mode Delay[29]
Document #: 38-03015 Rev. *B
ns
Com’l/Ind
8
Register Delay
Unit
Mil
Register Set-Up Time Relative to Clock Signal Com’l/Ind
at Register
Mil
Flow-Through Latch Delay
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
Com’l/Ind
4
4
Mil
4
4
Com’l/Ind
2
2
Mil
2
2
Com’l/Ind
4
4
Mil
4
4
ns
ns
ns
Page 12 of 19
USE ULTRA37000™ FOR
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CY7C343
Internal Switching Characteristics Over Operating Range (continued)[7]
7C343-30
Parameter
tCH
tCL
tIC
tICS
tFD
tPRE
tCLR
tPCW
tPCR
tPIA
Description
Clock HIGH Time
Clock LOW Time
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Min.
7C343-35
Min.
Com’l/Ind
10
12.5
Mil
10
12.5
Com’l/Ind
10
12.5
Mil
10
12.5
Max.
ns
16
18
Mil
16
18
Com’l/Ind
2
3
Mil
2
3
Com’l/Ind
1
2
Mil
1
2
Com’l/Ind
6
7
Mil
6
7
Com’l/Ind
6
7
Mil
6
7
6
7
Mil
6
7
Com’l/Ind
6
7
Mil
6
7
Programmable Interconnect Array Delay Time Com’l/Ind
Mil
Unit
ns
Com’l/Ind
Asynchronous Preset and Clear Pulse Width Com’l/Ind
Asynchronous Preset and Clear Recovery
Time
Max.
ns
ns
ns
ns
ns
ns
ns
16
20
16
20
ns
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
t PD1 /tPD2
COMBINATORIAL
OUTPUT
t ER
COMBINATORIAL OR
REGISTERED OUTPUT
HIGH-IMPEDANCE
THREE–STATE
t ER
HIGH-IMPEDANCE
THREE-STATE
Document #: 38-03015 Rev. *B
VALID OUTPUT
Page 13 of 19
USE ULTRA37000™ FOR
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CY7C343
Switching Waveforms (continued)
External Synchronous
DEDICATED INPUTS OR
[8]
REGISTERED FEEDBACK
tS1
tH
t WH
tWL
SYNCHRONOUS
CLOCK
tCO1
ASYNCHRONOUS
CLEAR/PRESET[8]
tRW /tPW
tRR /tPR
tOH
tRO/tPO
REGISTERED
OUTPUTS
tCO2
COMBINATORIAL OUTPUT FROM
REGISTERED FEEDBACK [12]
External Asynchronous
DEDICATEDINPUTSOR
REGISTERED
FEEDBACK [8 ]
tAH
tAS1
ASYNCHRONOUS
CLOCK INPUT
ASYNCHRONOUS
CLEAR/PRESET [8 ]
tACO1
tAWH
tRW/tPW
tAWL
tRR/tPR
tAOH
tRO/tPO
ASYNCHRONOUS REGISTERED
OUTPUTS
tACO2
COMBINATORIAL OUTPUT FROM
ASYNCH. REGISTERED FEEDBACK
Internal Combinatorial
tIN
INPUT PIN
tIO
tPIA
I/O PIN
tEXP
EXPANDER
ARRAY DELAY
tLAC, tLAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
Document #: 38-03015 Rev. *B
Page 14 of 19
USE ULTRA37000™ FOR
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CY7C343
Switching Waveforms (continued)
Internal Asynchronous
tAWH
tIOtR
tAWL
tF
CLOCK PIN
tIN
CLOCK INTO
LOGIC ARRAY
tIC
CLOCK FROM
LOGIC ARRAY
tRSU
tRH
DATA FROM
LOGIC ARRAY
tRD,tLATCH
tFD
tCLR,tPRE
tFD
REGISTER OUTPUT
TO LOCAL LAB
Internal Synchronous
tCH
tCL
SYSTEM CLOCK PIN
tIN
tICS
tRSU
tRH
SYSTEM CLOCK
AT REGISTER
DATA FROM
LOGIC ARRAY
Output Mode
CLOCK FROM
LOGIC ARRAY
tRD
tOD
DATA FROM
LOGIC ARRAY
tXZ
OUTPUT PIN
tZX
HIGH IMPEDANCE
STATE
Information
Speed
(ns)
Ordering Code
Package
Name
Operating
Range
Package Type
20
CY7C343-20JC/JI
J67
44-Lead Plastic Leaded Chip Carrier
Commercial/Industrial
25
CY7C343-25HC/HI
H67
44-Pin Windowed Leaded Chip Carrier
Commercial/Industrial
30
35
CY7C343-25JC/JI
J67
44-Lead Plastic Leaded Chip Carrier
CY7C343-30HC/HI
H67
44-Pin Windowed Leaded Chip Carrier
Commercial/Industrial
CY7C343-30JC/JI
J67
44-Lead Plastic Leaded Chip Carrier
CY7C343-30HMB
H67
44-Pin Windowed Leaded Chip Carrier
Military
Commercial/Industrial
CY7C343-35HC/HI
H67
44-Pin Windowed Leaded Chip Carrier
CY7C343-35JC
J67
44-Lead Plastic Leaded Chip Carrier
CY7C343-35HMB
H67
44-Pin Windowed Leaded Chip Carrier
Document #: 38-03015 Rev. *B
Military
Page 15 of 19
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CY7C343
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
tPD1
7, 8, 9, 10, 11
tPD2
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Parameters
Parameters
Subgroups
Subgroups
VOH
1, 2, 3
tPD3
VOL
1, 2, 3
tCO1
7, 8, 9, 10, 11
VIH
1, 2, 3
tS
7, 8, 9, 10, 11
VIL
1, 2, 3
tH
7, 8, 9, 10, 11
IIX
1, 2, 3
tACO1
7, 8, 9, 10, 11
IOZ
1, 2, 3
tACO2
7, 8, 9, 10, 11
1, 2, 3
tAS
7, 8, 9, 10, 11
tAH
7, 8, 9, 10, 11
ICC1
Document #: 38-03015 Rev. *B
Page 16 of 19
USE ULTRA37000™ FOR
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CY7C343
Package Diagrams
44-Pin Windowed Leaded Chip Carrier H67
51-80079-**
Document #: 38-03015 Rev. *B
Page 17 of 19
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C343
Package Diagrams (continued)
44-Lead Plastic Leaded Chip Carrier J67
51-85003-*A
Warp is a registered trademark, and Ultra37000, Warp Professional and Warp Enterprise are trademarks, of Cypress Semiconductor Corporation.
Document #: 38-03015 Rev. *B
Page 18 of 19
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C343
Document History Page
Document Title: CY7C343 64-Macrocell MAX® EPLD
Document Number: 38-03015
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
106315
04/24/01
SZV
Change from Spec number: to 38-03015
*A
122226
12/28/02
RBI
Power up requirements added to Operating Range Information
*B
213375
See ECN
FSG
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03015 Rev. *B
Page 19 of 19