CYPRESS CY62136VLL-55ZI

CY62136V MoBL™
128K x 16 Static RAM
Features
• Low voltage range:
— CY62136V: 2.7V-3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62136V is a high-performance CMOS static RAM organized as 131,072 words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling.
The device can also be put into standby mode when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
Truth Table at the back of this data sheet for a complete description of read and write modes.
The CY62136V is available in 48-ball FBGA and standard
44-pin TSOP Type II (forward pinout) packaging.
Logic Block Diagram
Pin Configurations
TSOP II (Forward)
Top View
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A3
A2
A1
A0
SENSE AMPS
A8
A7
A6
A5
A4
ROW DECODER
DATA IN DRIVERS
128K x 16
RAM Array
1024 X 2048
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
A9
A10
A11
A12
A13
A14
A15
A16
BHE
WE
CE
OE
BLE
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
Document #: 38-05087 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 5, 2000
CY62136V MoBL™
Pin Configurations (continued)
FBGA
Top View
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
NC
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Maximum Ratings
DC Voltage Applied to Outputs
in High Z State[1]....................................–0.5V to VCC + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Storage Temperature ..................................–65°C to +150°C
Output Current into Outputs (LOW)..............................20 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Supply Voltage to Ground Potential................–0.5V to +4.6V
Latch-Up Current.....................................................>200 mA
Operating Range
Device
Range
CY62136V
Industrial
Ambient Temperature
VCC
−40°C to +85°C
2.7V to 3.6V
Product Portfolio
Power Dissipation (Industrial)
VCC Range
Product
CY62136V
VCC(min.)
2.7V
VCC(typ.)
3.0V
[2]
Operating (ICC)
VCC(max.)
Power
3.6V
LL
[2]
Typ.
7 mA
Maximum
15 mA
Standby (ISB2)
[2]
Typ.
1 µA
Maximum
15 µA
Notes:
1. VIL(min) = –2.0V for pulse durations less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25°C.
Document #: 38-05087 Rev. **
Page 2 of 12
CY62136V MoBL™
Electrical Characteristics Over the Operating Range
CY62136V
Parameter
Description
Test Conditions
Min.
Typ.[2]
Max.
Unit
VOH
Output HIGH Voltage
IOH = −1.0 mA
VCC = 2.7V
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 2.7V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
IIX
Input Load Current
GND < VI < VCC
−1
+1
+1
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
−1
+1
+1
µA
ICC
VCC Operating Supply
Current
IOUT = 0 mA,
f = fMAX = 1/tRC,
CMOS levels
7
15
mA
1
2
mA
100
µA
15
µA
2.4
VCC = 3.6V
2.2
VCC = 2.7V
−0.5
VCC = 3.6V
IOUT = 0 mA,
f = 1 MHz,
CMOS Levels
ISB1
Automatic CE
Power-Down Current—
CMOS Inputs
CE > VCC−0.3V,
VIN > VCC−0.3V or
VIN < 0.3V, f = fMAX
ISB2
Automatic CE
Power-Down Current—
CMOS Inputs
CE > VCC−0.3V
VIN > VCC−0.3V
or VIN < 0.3V, f = 0
VCC =
3.6V
LL
V
1
0.4
V
VCC + 0.5V
V
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
6
pF
8
pF
TA = 25°C, f = 1 MHz,
VCC= VCC(typ)
Thermal Resistance
Description
Thermal Resistance
(Junction to Ambient)[3]
Test Conditions
Symbol
BGA
TSOPII
Unit
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer
printed circuit board
ΘJA
55
60
°C/W
ΘJC
16
22
°C/W
Thermal Resistance
(Junction to Case)[3]
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05087 Rev. **
Page 3 of 12
CY62136V MoBL™
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
R1
VCC
VCC
OUTPUT
VCC Typ
OUTPUT
10%
90%
10%
90%
GND
R2
30 pF
5 pF
INCLUDING
JIG AND
SCOPE
Rise Time:
1 V/ns
INCLUDING
JIG AND
SCOPE
Fall Time:
1 V/ns
(b)
(c)
3.0V
UNIT
R1
1105
Ohms
R2
1550
Ohms
RTH
645
Ohms
VTH
1.75V
Volts
(a)
Equivalent to:
R2
THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
Data Retention Characteristics (Over the Operating Range)
Parameter
Conditions[5]
Description
Min.
Typ.[2]
1.0
Max.
Unit
3.6
V
7.5
µA
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[3]
Chip Deselect to Data
Retention Time
0
ns
tR[4]
Operation Recovery Time
70
ns
VCC = 1.0V
CE > VCC − 0.3V,
VIN > VCC − 0.3V or
VIN < 0.3V
No input may exceed
VCC+0.3V
LL
0.5
Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min.)
tCDR
VDR > 1.0 V
VCC(min.)
tR
CE
Notes:
4. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 ms or stable at VCC(min) > 100 ms.
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC typ., and output loading of the specified
IOL/IOH and 30-pF load capacitance.
Document #: 38-05087 Rev. **
Page 4 of 12
CY62136V MoBL™
Switching Characteristics Over the Operating Range[5]
55 ns
Parameter
Description
Min.
70 ns
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
55
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
55
[6]
tLZOE
OE LOW to Low Z
10
OE HIGH to High Z
tLZCE
CE LOW to Low Z[6]
70
25
ns
25
10
ns
ns
tHZCE
CE HIGH to High Z
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
55
70
ns
tDBE
BLE / BHE LOW to Data Valid
25
35
ns
tLZBE
BLE / BHE LOW to Low Z
tHZBE
25
ns
ns
5
10
[6, 7]
ns
10
5
[6, 7]
tHZOE
70
0
[6, 7]
BLE / BHE HIGH to High Z
0
5
[8]
25
ns
5
25
ns
ns
25
ns
[8, 9]
WRITE CYCLE
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
45
60
ns
tAW
Address Set-Up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
50
ns
tBW
BLE / BHE LOW to Write End
50
60
ns
tSD
Data Set-Up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
tLZWE
WE LOW to High Z
[6, 7]
20
[6]
WE HIGH to Low Z
5
25
10
ns
ns
Switching Waveforms
Read Cycle No. 1 [10, 11]
tRC
ADDRESS
tOHA
DATA OUT
PREVIOUS DATA VALID
tAA
DATA VALID
Notes:
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
Document #: 38-05087 Rev. **
Page 5 of 12
CY62136V MoBL™
Switching Waveforms (continued)
Read Cycle No. 2 [11, 12]
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
BHE/BLE
tLZOE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
ICC
50%
50%
ISB
[8, 13, 14]
Write Cycle No. 1 (WE Controlled)
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tSD
DATA I/O
NOTE 15
tHD
DATAIN VALID
tHZOE
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high impedance if OE = VIH.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
15. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05087 Rev. **
Page 6 of 12
CY62136V MoBL™
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
[8, 13, 14]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tBW
BHE/BLE
tPWE
WE
tSD
DATA I/O
tHD
DATAIN VALID
Write Cycle No. 3 (WE Controlled, OE LOW)
[9, 14]
tWC
ADDRESS
CE
tAW
tBW
BHE/BLE
WE
tHA
tSA
tSD
DATA I/O
NOTE 15
tHZWE
Document #: 38-05087 Rev. **
tHD
DATAIN VALID
tLZWE
Page 7 of 12
CY62136V MoBL™
Switching Waveforms (continued)
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
[15]
tWC
ADDRESS
CE
tAW
tHA
tBW
BHE/BLE
tSA
WE
tSD
DATA I/O
DATAIN VALID
NOTE 15
tHZWE
Document #: 38-05087 Rev. **
tHD
tLZWE
Page 8 of 12
CY62136V MoBL™
Typical DC and AC Characteristics
Normalized Operating Current
vs. Supply Voltage
1.4
Standby Current vs. Supply Voltage
35
MoBL
30
1.2
MoBL
0.8
ICC
25
ISB (µA)
1.0
0.6
20
15
10
0.4
5
0.2
0
0.0
1.7
2.2
2.7
3.2
SUPPLY VOLTAGE (V)
3.7
1.0
2.7 2.8
3.7
1.9
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
80
MoBL
70
60
TAA (ns)
50
40
30
20
10
1.0
3.7
2.7 2.8
1.9
SUPPLY VOLTAGE (V)
Truth Table
CE
WE
OE
BHE
BLE
H
X
X
X
X
High Z
Deselect/Power-Down
Standby (ISB)
L
H
L
L
L
Data Out (I/OO–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
H
L
H
H
High Z
Deselect/Output Disabled
Active (ICC)
L
H
H
L
L
High Z
Deselect/Output Disabled
Active (ICC)
L
H
H
H
L
High Z
Deselect/Output Disabled
Active (ICC)
L
H
H
L
H
High Z
Deselect/Output Disabled
Active (ICC)
L
L
X
L
L
Data In (I/OO–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0 –I/O7 in High Z
Write
Active (ICC)
Document #: 38-05087 Rev. **
Inputs/Outputs
Mode
Power
Page 9 of 12
CY62136V MoBL™
Ordering Information
Speed
(ns)
Ordering Code
55
CY62136VLL-55ZI
70
CY62136VLL-70ZI
CY62136VLL-55BAI
CY62136VLL-70BAI
Package
Name
Z44
BA48
Z44
BA48
Operating
Range
Package Type
44-Pin TSOP II
Industrial
48-Ball Fine Pitch BGA
44-Pin TSOP II
48-Ball Fine Pitch BGA
Package Diagrams
48-Ball (7.00 mm x 7.00 mm) FBGA BA48
51-85096-D
Document #: 38-05087 Rev. **
Page 10 of 12
62136V: 8/2000
Revision: February 2, 2001
CY62136V MoBL™
Package Diagrams (continued)
44-Pin TSOP II Z44
51-85087-A
Document #: 38-05087 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62136V MoBL™
Document Title: CY62136V MoBL™ 128K x 16 Static RAM
Document Number: 38-05087
REV.
ECN NO.
Issue Date
Oreg. of Change
Description of Change
**
107347
05/25/01
SZV
Change from Spec #: 38-00728 to 38-05087
Document #: 38-05087 Rev. **
Page 12 of 12